Sort memory requests based on access efficiency

Abstract

The present invention discloses an apparatus, and an embodiment thereof includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine whether the memory request includes a read request or a write request. The received read request may be scheduled for execution, and the received write request may be stored in the write request queue. The memory controller circuit may reorder the scheduled memory requests based on achieving a specified memory access efficiency and based on the number of write requests stored in the write request queue.

Description

Technical Field

[0001] Embodiments described herein relate to the field of computing systems, and more particularly, to the management of memory requests by a memory controller in a computing system. Background Art

[0002] Computer systems including systems on a chip (SoCs) include a processor and a plurality of memory circuits that store software programs or applications and data operated on by the processor. Such memories may vary in storage capacity and access time. In some computing systems, some memory circuits are coupled to the processor via memory controller circuits that communicate with the processor via a communication link or other communication network.

[0003] During operation, a processor, which may include a processor core, a graphics processor, etc., transmits a request to access the memory controller via a communication link. The memory controller receives the request and arbitrates access to the memory circuit for the request. When relaying a particular request from the processor to the memory circuit, the memory controller circuit waits until the memory circuit implements the particular request. To implement the particular request, the memory circuit may send the requested data or an acknowledgement signal to the memory controller circuit, which in turn relays the data or signal to the requesting processor. Summary of the invention

[0004] Broadly speaking, the present disclosure contemplates a system, an apparatus, and a method, wherein the apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine whether the memory request includes a read request or a write request. The received read request may be scheduled for execution, and the received write request may be stored in the write request queue. The memory controller circuit may reorder the scheduled memory requests based on achieving a specified memory access efficiency and based on the number of write requests stored in the write request queue.

[0005] In some implementations, the memory controller circuitry may be configured to determine a current memory access efficiency in response to completion of a read sequence and a write sequence. The read sequence may correspond to execution of a plurality of read requests, and the write sequence may correspond to execution of a plurality of write requests. The current memory access efficiency may be determined based on a ratio of clock cycles used to process memory requests to a total clock cycle that occurred during the completed read sequence and write sequence.

[0006] In certain implementations, the memory controller circuitry may be configured to modify the number of memory requests to be executed in subsequent read sequences and write sequences based on a comparison of the current memory access efficiency with the specified memory access efficiency. In various embodiments, the memory controller circuitry may be configured to schedule at least one partial write memory request to be executed between a read sequence and a write sequence.

[0007] In some embodiments, the memory controller circuitry may be configured to schedule a subset of the write requests included in the write request queue in response to determining that the number of write requests in the write request queue meets a threshold number of requests. In a particular implementation, the memory controller circuitry may be configured to prioritize read requests over write requests by scheduling the plurality of write requests to be executed after executing a plurality of read requests. In various embodiments, the memory controller circuitry may be configured to prioritize a particular write request over a different write request in response to determining that an amount of data to be stored by a particular write request is greater than an amount of data to be stored by a different write request. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0009] Figure 1 A block diagram of an embodiment of a memory system including a memory controller circuit and a memory circuit is shown.

[0010] Figure 2 A block diagram of an embodiment of a memory controller circuit and a memory circuit is shown, where the memory circuit includes a plurality of memory devices.

[0011] Figure 3 An embodiment of a scheduled request buffer is depicted along with a diagram representing a timeline for executing buffered memory requests.

[0012] Figure 4 Three tables representing different states of the scheduled request buffer are presented.

[0013] Figure 5 Another embodiment of a scheduled request buffer is shown, along with a corresponding diagram depicting a timeline for executing buffered memory requests.

[0014] Figure 6 A flow chart of an embodiment of a method for scheduling memory requests by a memory controller circuit is shown.

[0015] Figure 7 A flow chart of an embodiment of a method for determining an efficiency value corresponding to execution of a memory request is presented.

[0016] Figure 8 A block diagram of an embodiment of a computer system is depicted.

[0017] Fig. 9 A block diagram depicting an exemplary computer-readable medium is shown, according to some embodiments.

[0018] Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and specific embodiments are not intended to limit the present disclosure to the specific forms illustrated, but on the contrary, their purpose is to cover all modifications, equivalents and alternative forms that fall within the essence and scope of the present disclosure defined by the appended claims. As used throughout this patent application, the word "may" is used in a permissive sense (i.e., meaning with possibility) rather than a mandatory sense (i.e., meaning must). Similarly, the word "includes" means including but not limited to.

[0019] Various units, circuits or other components may be described as being "configured to" perform one or more tasks. In such contexts, "configured to" is a broad statement of a structure that generally means "having" a "circuit" that performs one or more tasks during operation. In this way, even when the unit / circuit / component is not currently connected, the unit / circuit / component may be configured to perform a task. Typically, the circuit that forms the structure corresponding to "configured to" may include a hardware circuit. Similarly, for convenience in description, various units / circuits / components may be described as performing one or more tasks. Such descriptions should be interpreted as including the phrase "configured to". The statement that the unit / circuit / component configured to perform one or more tasks is explicitly intended to not invoke the interpretation of paragraph f of 35 U.S.C. §112 for the unit / circuit / component. More generally, the statement of any element is explicitly intended not to invoke the interpretation of paragraph f of 35 U.S.C. §112 for the element, unless the language of "device for..." or "step for..." is specifically stated.

[0020] As used herein, the term "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, the determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. The phrase "based on" is therefore synonymous with the phrase "based at least in part on." DETAILED DESCRIPTION

[0021] In a computer system, a hierarchical structure of memory circuits is used to store program instructions and data for use by functional circuit blocks within the computer system. Such functional circuit blocks may include processors, processor cores, graphics cores, audio processing circuits, network processing circuits, etc. Some of the memory circuits (such as cache memory circuits) may be directly coupled to the functional circuit blocks to provide low-density fast access dedicated storage devices for the functional blocks. Other memory circuits are shared between multiple functional circuit blocks to allow the functional circuit blocks to access a larger amount of storage space. In order to facilitate such sharing of memory circuits, a memory controller circuit may be used to manage access to the memory circuits.

[0022] The memory controller circuit receives requests from functional circuit blocks to access the memory circuit. Such requests may include requests to retrieve previously stored data from the memory circuit (commonly referred to as "read requests") and requests to store data in the memory circuit (commonly referred to as "write requests"). In some cases, read requests and write requests may be combined to form a "read-modify-write" request.

[0023] When the memory controller circuit receives requests to access the memory circuit, each request is placed in an execution order relative to other received requests in a process known as scheduling. The memory controller circuit may determine the execution order based on various criteria. For example, certain types of requests to access memory may have a higher priority and therefore be placed before requests with lower priority in the execution order. In some cases, scheduling according to various criteria may result in time periods during which the memory circuit is not fully utilized, thereby reducing the efficiency of the memory subsystem. As described and used herein, memory subsystem "efficiency" refers to any measurement of the utilization of the memory subsystem. A common measure of efficiency is the ratio of active (i.e., non-idle) memory cycles to the total possible memory cycles that occur in a given amount of time.

[0024] Inefficient use of memory circuits in a computer system can adversely affect the performance of the computer system. For example, retrieving video data from memory in an inefficient manner can result in incorrectly displayed video. In addition, inefficient memory access can cause software or program instructions to not be used in a timely manner for a processor or processor core, resulting in a pause or slowdown in computer system performance. The embodiments shown in the accompanying drawings and described below can provide a technique for scheduling memory access requests while maintaining a desired efficiency, thereby improving computer system performance.

[0025] exist Figure 11 is a block diagram of an embodiment of a memory system including a memory controller circuit and a memory circuit. As shown, the memory system 100 includes a memory controller circuit 110 coupled to a memory circuit 120 via a communication bus 180. The memory controller circuit 110 also includes a scheduled request buffer 130 and a write request queue 140. In various embodiments, the memory controller circuit 110 and the memory circuit 120 may be included on the same integrated circuit or may be implemented in separate integrated circuits. The memory controller circuit 110 may be a specific embodiment of a state machine or other sequential logic circuit, and the memory circuit 120 may be any suitable type of memory circuit, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), etc.

[0026] As shown, the memory controller circuit 110 is configured to receive a memory request to access the memory circuit and determine whether the memory request includes a read request or a write request. The memory controller circuit 110 is further configured to schedule the received read request for execution or store the received write request in the write request queue 140. In addition, the memory controller circuit 110 is configured to reorder the scheduled memory requests based on achieving a specified memory access efficiency 160 and further based on the number of write requests stored in the write request queue 140.

[0027] As shown, the memory controller circuit 110 may generate one or more memory commands to be sent to the memory circuit 120 via the communication bus 180 based on the read request. Such commands may be placed in the scheduled request buffer 130. In various embodiments, the scheduled request buffer 130 may be a specific embodiment of a register file or other suitable storage circuit configured to store commands 134-136. In some cases, the memory controller circuit 110 may place the read request or a command associated with the read request in the next available entry in the scheduled request buffer 130. In other cases, the memory controller circuit 110 may compare the address included in the memory request 150 and schedule the read request to be executed with other read requests that access information on the same memory page referenced by the included address.

[0028] With respect to write requests, the memory controller circuit 110 may continue to store received write requests into the write request queue 140 until the number of queued write requests reaches a threshold number, as indicated by threshold 141. During this time, the memory controller circuit 110 may continue to schedule and execute read requests. After the number of queued write requests reaches threshold 141, one or more of the queued write requests (such as write requests 144-146) are scheduled by placing the write requests into the scheduled request buffer 130 for execution in the scheduled order.

[0029] As described in more detail below, in some embodiments, the memory controller circuit 110 may determine a current memory access efficiency 170 on the communication bus 180 after completing a "read sequence" (a series of read memory accesses that does not include a write) and a "write sequence" (a series of write memory accesses). When the current memory access efficiency is calculated (after completing a single read sequence and a single write sequence, or otherwise), the efficiency may then be compared to a specified memory access efficiency 160 as part of the reordering process. In various embodiments, the specified memory access efficiency 160 may be specified as part of the design of the memory system 100, may be determined by hardware based on current processing requirements, or may even be set by software.

[0030] As described above, the memory controller circuit 110 is coupled to the memory circuit 120 via the communication bus 180. In various embodiments, the communication bus 180 may include a local clock signal, as well as dedicated lines for commands, addresses, and data. Such data lines may be bidirectional, thereby allowing the memory controller circuit 110 or the memory circuit 120 to drive data onto the data lines. It should be noted that the memory controller circuit 100 and the memory circuit 120 cannot drive the data lines at the same time. Each time a read operation is changed to a write operation (or vice versa), multiple cycles may be required to allow the data lines included in the communication bus 180 to reach a state where the new device may drive the data lines. For example, when switching from a read operation to a write operation, the memory controller circuit 110 must wait to start sending the data to be written until the memory circuit 120 has completed sending the data associated with the read operation.

[0031] Please note that Figure 1 The memory controller circuit 110 shown is only an example. Figure 1 The illustration is simplified to highlight the features relevant to the present disclosure. In other embodiments, the memory controller circuit 110 may include additional circuit blocks, such as interface circuits configured to send and receive data via, for example, the communication bus 180.

[0032] like Figure 1As depicted, write requests may be stored in a write request queue. Figure 2 , shows an embodiment of a memory controller utilizing a write request queue. The memory controller circuit 210 includes a system interface 211, an arbitration circuit 212, an instruction queue 230, and a write request queue 240. The memory controller circuit 210 is coupled to the memory circuit 220 via a data bus 280 and a bus clock 282. The memory circuit 220 includes memory devices 225a-225d, which in turn include a corresponding plurality of memory groups 227 and memory pages 229 (shown only for memory device 225a for clarity). In some embodiments, the memory controller circuit 210, the instruction queue 230, the write request queue 240, and the memory circuit 220 may correspond to Figure 1 The memory controller circuit 110, the scheduled request buffer 130, the write request queue 140, and the memory circuit 120 in FIG.

[0033] As shown, the memory circuit 220 includes four memory devices 225a-225d (collectively referred to as memory devices 225). Each of the memory devices 225 includes a plurality of memory groups 227 (for clarity, the memory groups 227 and memory pages 229 are shown only for the memory device 225A). In various embodiments, the number of memory groups may be the same or may vary between the memory devices 225. For a given memory device in the memory devices 227, different memory groups may be able to implement memory requests simultaneously or in overlapping order. However, each memory device 227 may be limited to sending or receiving commands, addresses, and data for a single memory request at a time. Each of the memory groups 227 includes a plurality of memory pages 229. It should be noted that a "memory page" (also referred to herein as a "page") corresponds to the amount of data that can be accessed from a single memory group 227 using a single read command or write command. In some embodiments, a memory page may correspond to one or more physical rows of memory cells in a memory array. In other embodiments, a memory page may correspond to a different physical or logical organization of memory cells, such as one or more columns of memory cells, or a plurality of memory cells addressable with a portion of a memory address value.

[0034] Similar to the memory controller circuit 110, the memory controller circuit 210 includes a circuit for receiving, decoding, scheduling and executing the received memory request. As shown, the system interface 211 receives a memory request for accessing the memory circuit 220 from a processing circuit included in a computing system including the memory controller 210. The arbitration circuit 212 receives the memory request from the system interface 211 and determines whether the memory request includes a read request or a write request. The arbitration circuit 212 places the received read request in the instruction queue 230. In some embodiments, the arbitration circuit 212 can schedule the read request using other read requests with similar memory addresses. For example, read requests with storage addresses corresponding to the same memory page 229 can be scheduled together, thereby allowing a number of read requests to be implemented by a single activation of the common memory page 229. For example, in an embodiment in which the memory controller circuit 210 can send concurrent requests to different memory groups or devices, read requests with addresses to different memory groups 227 or to different memory devices 225 can be scheduled together.

[0035] It should be noted that as used herein, the terms "concurrent" and "parallel" are used to refer to events that may occur during overlapping time points. The use of "concurrent" or "parallel" is not intended to imply that events start and end at the same time, but does not exclude such occurrences.

[0036] Arbitration circuit 212 places the received write request into write request queue 240. In a computing system in which memory controller circuit 210 may be used, read requests may be executed in priority over write requests. Read requests may be issued for data that will be used by an active application or process, and therefore, the amount of time used to retrieve the data and fulfill the request may affect the performance of the application or process. In contrast, a write request may include data that was previously used by an application or process for use at a later time. In addition, data included in a write request may currently be stored in cache memory and therefore available to the application or process even if the write request has not yet been fulfilled.

[0037] As shown, the communication bus 280 is a combined input / output (I / O) bus for transmitting both read and write data. When switching from a read command to a write command, the data associated with the read command is sent from the memory circuit 220 to the memory controller circuit 210. The data is received by the memory controller circuit 210 before the I / O bus is reconfigured to transmit data in the opposite direction for a write command. The opposite is true for switching from a write command to a read command, e.g., the data associated with the write command is sent via the I / O bus before any read data can be sent by the memory circuit 220.

[0038] Thus, switching the communication bus 280 back and forth between read requests and write requests generates cycles of the bus clock 282 that may not be used for the next memory command due to waiting for the completion of the data transfer. These unused clock cycles may result in a reduction in the efficiency of the memory controller circuit 210. In order to achieve the desired efficiency goals, the memory controller circuit 210 may adjust the number of read requests processed during a single read sequence and the number of write requests processed during a single write sequence. It should be noted that a given read sequence or write sequence may include any suitable number of corresponding memory requests, including zero requests in some cases.

[0039] As described above, the number of read requests and write requests scheduled for the corresponding read sequence and write sequence is determined based on the current memory access efficiency. After the read sequence and the subsequent write sequence have been completed, the memory controller circuit 210 determines the value of the current memory access efficiency based on the ratio of the number of cycles of the bus clock 282 used to process the memory request and the total number of cycles of the bus clock 282 that occurred during the completed read sequence and write sequence. The memory controller circuit 210 can then compare the current memory access efficiency with the specified memory access efficiency to determine the current increment relative to the specified efficiency. The memory controller circuit 210 then reorders the scheduled memory requests based on achieving the specified memory access efficiency.

[0040] In addition to adjusting the number of requests processed during a given sequence, the memory controller circuit 210 may also employ one or more request ordering techniques to achieve a specified memory access efficiency. For example, the memory controller circuit 210 may modify the number of memory requests to be executed in a subsequent read sequence and write sequence. The memory controller circuit 210 may schedule at least one partial write memory request (i.e., a read-modify-write request) to be executed between the read sequence and the write sequence. Another technique includes prioritizing a particular write request over a different write request in response to determining that the amount of data to be stored by a particular write request is greater than the amount of data to be stored by a different write request. These techniques will be described in more detail below.

[0041] By prioritizing read requests over write requests, the memory controller circuit 210 may store received write requests in the write request queue 240, thereby freeing up available entries in the instruction queue 230 for the received read requests. Thus, under some conditions, a set of read sequences and write sequences may include all read requests but no write requests. Thus, such prioritization of read requests may improve the performance of an active application or process by reducing the amount of time between issuing a read request and subsequently fulfilling the read request.

[0042] As shown, arbitration circuit 212 stores received write requests 244-258 in write request queue 240. Once the number of queued write requests reaches a threshold number (as indicated by write request 258 and threshold 241), arbitration circuit 212 schedules a subset of the queued write requests by placing the subset into instruction queue 230. Figure 2 As shown, the subset includes write requests 244-246. However, in other embodiments, any suitable number of write requests may be included in the subset, including all write requests in write request queue 240. In order to prioritize the read requests, arbitration circuit 212 schedules read requests 232-237 to be executed before write requests 244-246. Read requests 232-237 form a read sequence, while write requests 244-246 form a write sequence. The read sequence and the write sequence together form a set of read sequences and write sequences, also referred to herein as a memory request sequence.

[0043] The value of threshold 241 may be set during the design of memory controller circuit 210, or by software, such as an operating system executing in a computer system including memory controller circuit 210. In some embodiments, the threshold may be adjusted based on a comparison of a current memory access efficiency to a specified memory access efficiency.

[0044] Arbitration circuit 212 may prioritize a particular write request over a different write request in response to determining that the amount of data to be stored by a particular write request is greater than the amount of data to be stored by a different write request. As shown in instruction queue 230, write requests are scheduled in the order of 246, 244, and then 245. For example, write request 246 may be a request to store 128 bytes of data in one of memory devices 225. However, write requests 244 and 245 may each be a request to store 32 bytes of data, so arbitration circuit 212 schedules these requests after write request 246. Since write requests 244 and 245 are for the same amount of data, arbitration circuit 212 may use other criteria to select the order of the two requests. For example, write request 244 may address a location in memory device 225 that is different from memory request 246, and therefore may be scheduled to be executed simultaneously with write request 246. In addition, arbitration circuit 212 may schedule write request 244 before write request 245 based on the order in which the memory controller circuit 210 receives the two requests.

[0045] To execute the memory request, the memory controller circuit 210 sends one or more memory commands corresponding to each request to the memory circuit 220. The memory circuit 220 executes the memory commands corresponding to the scheduled read requests and write requests. The memory controller circuit 210 sends the memory commands to the memory circuit 220 via the communication bus 280 and the bus clock 282. The memory controller circuit 210 uses the bus clock 282 to control the flow of memory commands to the memory circuit 220. Multiple cycles of the bus clock 228 (referred to herein as "clock cycles" for simplicity) occur between the time when the execution of a specific memory request is initiated and the time when the generated memory command implements the memory request. The execution of some memory requests may include idle clock cycles between separate memory commands for implementing a specific memory request. Depending on the memory requests waiting in the instruction queue 230, other memory commands may be executed during some or all of these otherwise idle clock cycles. The efficiency of the memory controller circuit 210 can be determined based on the ratio or percentage of clock cycles actively used to execute memory commands relative to the total number of clock cycles occurring within a specific amount of time.

[0046] Please note that Figure 2 The embodiments are merely examples for demonstrating the disclosed concepts. For clarity, the number of read requests and write requests shown is selected. In other embodiments, any suitable number of read requests and write requests may be included in the instruction queue and the write request queue.

[0047] Re-reference Figure 1 , the memory controller circuit determines a value representing the efficiency of the memory controller. In some embodiments, the efficiency can be determined by the number of memory commands executed within a specific amount of time.

[0048] Go to Figure 3 , in an example for determining efficiency, shows an implementation of a scheduled request buffer and a graph depicting memory command execution versus time. In various implementations, the scheduled request buffer 330 may correspond to Figure 1 The scheduled request buffer 130 in Figure 2 2. As shown, the scheduled request buffer 330 includes eight entries currently filled with eight corresponding memory requests 331-338. Each of the memory requests 331-338 is a read request (indicated by the letter "R") or a write request (indicated by the letter "W"). In addition, a memory page indicator is included, which indicates which memory page of the plurality of memory pages (p1-p5) the corresponding request accesses. For example, memory request 333 is a read request for information at a location in memory page 2.

[0049] As shown, chart 300 depicts a timeline for executing memory commands corresponding to memory requests 331-338. Clock signal 315 corresponds to Figure 1 1-338 and provides a timing reference to a memory controller (e.g., memory controller circuit 110) that executes memory requests 331-338. Execution signal 317 indicates activity in a command interface between memory controller circuit 110 and a memory circuit (such as memory circuit 120). A high signal indicates when a memory command is actively executed, and a low signal indicates when the command interface is idle. Note that when the command interface is idle, circuits in the memory controller and memory circuits may actively execute or otherwise process various memory requests and commands. Several letters are used with execution signal 317 to indicate the type of memory command being executed. "a" indicates an activation command for preparing a corresponding memory page for one or more subsequent read commands or write commands. "r" indicates a read command for reading one or more bytes of information from an activated memory page. Similarly, "w" indicates a write command for writing one or more bytes of information to an activated page.

[0050] As previously described, a memory controller executes a memory request by issuing one or more memory commands to a memory circuit, which then executes the individual memory commands, thereby fulfilling the corresponding memory request. Figure 3 , at time t1, memory request 331 is initiated by executing a page activate command for memory page 1. As shown, the memory circuit utilizes several cycles of clock signal 315 until time t2, at which time information from page 1 can be read and sent to the memory controller. Memory request 331 is implemented by executing a read command at time t2. In addition, a second read command is executed to implement memory request 332 to access information on the same memory page. By time t3, memory requests 333 and 334 have been implemented. For the sake of brevity, the description of the memory commands used to implement memory requests 333 and 334 is omitted. At time t3, memory request 335 is initiated by executing an activate command for page 4, and then the information is read for several cycles of clock signal 315.

[0051] As shown, the memory circuit 120 is configured to a read state for a read command or to a write state for a write command, and several cycles of the clock signal 315 are used to reconfigure the memory circuit 120 from the read state to the write state. During this transition, no memory read, write, and activate commands are issued to the memory circuit 120. Between time t4 and time t5, a transition from the read state to the write state is performed. The read-to-write transition can end the read sequence including the memory requests 331-335 and prepare the memory circuit 120 for the write sequence including the memory requests 336-338.

[0052] At time t5, memory circuit 120 is in a write state and performs a memory page activation to prepare page 3 for a write command. After several cycles of clock signal 315, at time t6, page 3 is ready to receive data as part of memory request 336. As shown, the write command of memory circuit 120 may be different from the read command. While the read command may read a subset of memory locations on the activated page, in some embodiments, the write command may write to all locations on the activated page. Therefore, since more information is sent from memory controller circuit 110 to memory circuit 120, the write command may take more time to complete.

[0053] After request 336 is completed, memory controller circuit 110 and memory circuit 120 may continue to implement memory requests 337 and 338. Memory controller circuit 110 may determine a current memory access efficiency in response to the completion of the read sequence and the write sequence. The current memory access efficiency is determined based on the ratio of clock cycles used to process memory requests to the total clock cycles that occur during the completed read sequence and the write sequence. For example, a particular read sequence may include 48 read requests and a subsequent write sequence may include 16 write requests. Implementing these 64 memory requests may take 150 cycles of clock signal 315. During these 150 cycles, execution signal 317 may indicate activity that lasted for 45 cycles, resulting in a ratio of 0.30% or a current memory access efficiency of 30%. Memory controller circuit 110 may include a specified memory access efficiency that is set during the design of memory controller circuit 110 or set by software (such as an operating system executed in a computer system including memory controller circuit 110). The current memory access efficiency value of 30% is compared to the specified memory access efficiency value (e.g., 90%), thereby determining that the memory controller circuit 110 is operating at the specified target. Based on the comparison, the memory controller circuit 110 may modify one or more techniques for future memory request sequences. For example, the memory controller circuit 110 may modify the number of memory requests included in a subsequent memory request sequence. Additional details are provided later in this disclosure.

[0054] Please note that Figure 3 The implementation scheme of is an example. Figure 3 The memory commands may be simplified to clearly disclose the features of the embodiments. In other embodiments, additional commands may be executed to implement a read request or a write request. In some embodiments, the order of the memory commands may be different. The number of clock cycles used to complete a particular memory command may be different from Figure 3 Quantity shown.

[0055] exist Figure 3 In the description of , a memory controller is disclosed to adjust the number of memory requests included in a subsequent memory request sequence in response to a comparison of a current memory access efficiency with a specified memory access efficiency. Figure 4 , several tables representing scheduled request buffers are used to illustrate examples of such adjustments. Scheduled request buffers 430a depict a scheduled request buffer (such as Figure 1 The states of the scheduled request buffers 130 in FIG. 4A and 430B illustrate possible states of the scheduled request buffers at a later point in time in response to two different values ​​431B and 431C of the current memory access efficiency.

[0056] Scheduled request buffer 430a depicts the state of a scheduled request buffer having a read sequence and a write sequence, each of which has 32 corresponding memory requests. Once the scheduled requests are executed at the end of the read sequence and the write sequence, the memory controller circuit (such as Figure 1 The memory controller circuit 110 in the memory controller circuit 110 determines the current memory access efficiency, as described above. The memory controller circuit 110 can modify the number of memory requests to be executed in subsequent read sequences and write sequences based on the comparison of the current memory access efficiency with the specified memory access efficiency.

[0057] As a first example, the memory controller circuit 110 determines a value of 60% for the current memory access efficiency 431b. If the specified memory access efficiency is 85%, the memory controller circuit 110 may adjust the number of memory requests included in subsequent read sequences and write sequences. This may occur if the read requests are accessing different memory pages on one or two memory groups on a single memory device, thereby limiting the number of read requests that can be executed simultaneously. In contrast, queued write requests may span various memory devices, thereby enabling concurrent execution of multiple write requests. As shown in the scheduled request buffer 430b, the memory controller circuit 110 reduces the number of read requests in the read sequence to 20 and increases the number of write requests in the write sequence to 40. Note that in addition to modifying the number of requests in each of the read sequence and the write sequence, the total number of memory requests is also modified for the combined memory request sequence.

[0058] In a second example, the memory controller circuit 110 determines a value of 95% for the current memory access efficiency 431c. Assuming the same specified memory access efficiency of 85%, the memory controller circuit 110 may again adjust the number of memory requests in each of the read sequence and the write sequence. Assuming a similar combination of read requests and write requests as previously described, the memory controller circuit 110 increases the number of read requests in the read sequence to 48 and decreases the number of write requests in the write sequence to 16. Due to the higher value of the memory access efficiency 431c, the memory controller circuit 110 has margin to execute some of the read requests that have a limited chance of being executed simultaneously. By tracking the current memory access efficiency and comparing to the specified memory access efficiency, the memory controller circuit may modify the number of memory requests in the read sequence and the write sequence to obtain the specified efficiency.

[0059] Please note that Figure 4 The depiction in is merely an example. In other embodiments, different numbers of memory requests may be included in the read sequence and the write sequence. Although only read requests and write requests are shown, in other embodiments, other types of memory requests may be included, such as partial read requests.

[0060] Now go to Figure 5 , shows an example of scheduling read-modify-write memory requests. The scheduled request buffer 530 may correspond to Figure 1 The scheduled request buffer 130 in Figure 2230 in the instruction queue. Scheduled request buffer 530 is shown as having three entries currently populated with three respective memory requests 531-533. Memory request 531 is a read request (R) for memory page 1 (p1). Memory request 533 is a write request (W) for memory page 4 (p4). In addition, memory request 532 is a partial read (i.e., read-modify-write) request (RMW) for page 3 (p3). Common Reference Figure 1 and scheduled request buffer 530 , execute three memory requests 531 - 533 according to the timeline of diagram 500 .

[0061] As shown, chart 500 depicts a timeline for executing memory commands corresponding to three memory requests 531-533. Clock signal 515 corresponds to clock signal 115 and provides a timing reference to memory controller circuit 110. Execution signal 517 indicates activity in the command interface between memory controller circuit 110 and memory circuit 120. The high portion of the signal indicates when a memory command is actively being executed, and the low portion of the signal indicates when the command interface is idle. Similar to Figure 3 In the diagram 300 in FIG. 1 , several letters are used with the execute signal 317 to indicate the type of memory command being executed. "a" indicates an activate command for preparing a corresponding memory page for one or more subsequent read commands or write commands. "r" indicates a read command for reading one or more bytes of information from an activated memory page. Similarly, "w" indicates a write command for writing one or more bytes of information to an activated page.

[0062] As shown, read request 531 is the last read request in the read sequence, and write request 533 is the first write request in the subsequent write sequence. The memory controller circuit 110 schedules a partial write request 532 to be executed between the end of the read sequence and the beginning of the write sequence. A partial write request is a type of read-modify-write request that includes reading information from a specified page, modifying some or all data from the specified page (if necessary), and then writing the modified data back to the specified page. Since both a read command and a write command are executed to implement this type of memory request, a read-to-write transition is performed between the read command and the write command. As described below, scheduling a read-modify-write request between a read sequence and a write sequence allows the memory circuit 120 to avoid performing a read-to-write transition specifically for a read-modify-write request.

[0063] Between times t1 and t2, two memory commands, a page activation command and a read command, are executed to implement the read request 531. Between times t2 and t3, the page activation command and the read command are executed to implement the read portion of the memory request 532, resulting in the specified page 3 being read by the memory controller circuit 110. After reading the data from page 3, the memory controller circuit 110 initiates a read-to-write transition of the memory circuit 120 from time t3 to time t4. During the transition time, the memory controller circuit 110 may make any necessary changes to the data from page 3, as specified in the memory request 532. After the memory circuit 120 is in the write state, the write portion of the memory request 532 is implemented between times t4 and t5. Since the memory circuit 120 is now in the write state, the write request 533 may begin at time t5 without requiring an additional state transition.

[0064] Note that if a read-modify-write request 532 is scheduled during a read sequence, a write-to-read transition will be required after the request 532 is fulfilled, returning the memory circuit 120 to the read state to complete the read sequence. Likewise, if a read-modify-write request 532 is scheduled during a write sequence, a write-to-read transition will be required before the request 532 begins, placing the memory circuit 120 in the read state for the first read portion of the request.

[0065] Also note that Figure 5 500 is an example for demonstrating the disclosed concepts. For clarity, the timeline in diagram 500 is simplified. In other embodiments, any suitable number of clock cycles may occur during and between the activities shown.

[0066] Circuits and diagrams related to scheduling and execution of memory requests have been presented above. Two methods for operating such circuits are now presented.

[0067] Now turn to Figure 6 , a flow chart of an embodiment of a method for managing memory requests in a memory controller is shown. The method 600 may be applied to a memory controller circuit such as Figure 1 The memory controller circuit 110 or Figure 2 The memory controller circuit 210 in FIG. Figure 1 and Figure 6 , the method may start in block 601.

[0068] A memory controller receives a memory request to access a memory circuit (block 602). A memory controller (e.g., memory controller circuit 110) receives a memory request from one or more processing circuits within a computing system that includes memory controller circuit 110 and memory circuit 120. A processing circuit may issue a memory request to retrieve information from memory circuit 120, such as instructions or operands of program code of an application or other software process currently executing in a processing circuit in the computing system. In other cases, a processing circuit may issue a memory request to store information in memory circuit 120 for later use. Figure 1 As shown, the memory controller 110 includes a write request queue and a scheduled request buffer.

[0069] The memory controller processes the memory request according to whether the memory request is a read request or a write request (block 604). The memory controller circuit 110 determines whether the memory request includes a read request or a write request. In some embodiments, additional types of memory requests may be received, such as read-modify-write commands. Memory access may take several cycles of a clock signal (e.g., clock signal 115), and therefore, the memory controller circuit 110 may be configured to schedule the received memory request in such a manner so as to implement the memory request at an effective rate. Since a read request may include a request for an instruction or operand of an application program, the speed at which such a read request is implemented may have a direct impact on the computing system performance perceived by a user of the computing system. Therefore, scheduling a read request may take precedence over scheduling a write request. The received read request may be scheduled as part of a read sequence within a group of other read requests within the scheduled request buffer 130. A write request may have a lower priority than a read request because the write request may not be in the critical path of code execution. Therefore, the memory controller circuit 110 may store the received write request in a write request queue 140.

[0070] The memory controller determines an efficiency value representing the current efficiency of the memory controller in executing the memory request (block 606). After executing the plurality of memory requests, the memory controller circuit 110 determines a value of the current memory access efficiency associated with the execution of the memory commands included in the most recent read sequence and write sequence. The efficiency value may be determined based on a ratio of active clock cycles to total clock cycles of the bus clock 282 (e.g., Figure 2 2, during a completed read sequence and a completed write sequence). An active clock cycle refers to a cycle of the bus clock 282 used to process a memory request. A total number of cycles refers to the number of cycles of the bus clock 282 that occur from the start of execution of the first request of a read sequence to the completion of the last request of a write sequence. In other embodiments, the efficiency value may be based on the number of memory requests in a read sequence and a write sequence divided by the total number of cycles.

[0071] The memory controller schedules the memory request based on the efficiency value and based on the number of write requests stored in the write request queue (block 608). The memory controller circuit 110 compares the determined value of the current memory access efficiency with the specified memory access efficiency value. The specified value may be set during the design of the memory controller circuit 110, or may be sent to the memory controller circuit 110 by the operating system or other software running on the computing system. The memory controller circuit 110 schedules the memory request within the appropriate upcoming read sequence or write sequence. For the upcoming read sequence and write sequence, the memory controller circuit 110 may also adjust the number of read requests and / or the number of write requests to be included in the subsequent read sequence and write sequence. For example, if the number of write requests in the write request queue 140 is less than the threshold 141, the received write request is stored in the write request queue 140 instead of being scheduled for processing. In addition, if the number of requests in the write request queue 140 reaches the threshold 141, one or more write requests currently stored in the write request queue 140 may be scheduled for execution in the upcoming write sequence.

[0072] The memory circuit executes the scheduled read and write requests (block 610). To execute the scheduled memory requests, the memory controller circuit 110 sends one or more memory commands corresponding to each request to the memory circuit 120. The memory circuit 120 executes the memory commands corresponding to the scheduled read and write requests. The method ends in block 614.

[0073] Please note that Figure 6 The method shown is an example for demonstrating the disclosed concept. In other embodiments, the operations can be performed in a different order. Additional operations may also be included, such as comparing the current queue number of write requests with a threshold number.

[0074] Now go to Figure 7 , a flow chart is shown that illustrates an embodiment of a method for determining and utilizing an efficiency value by a memory controller. Similar to the method 600 described above, the method 700 may be applied to a memory controller circuit, such as Figure 1 The memory controller circuit 110 or Figure 2 The operations disclosed in method 700 may be performed in conjunction with or as part of method 600. Figure 1 and Figure 7 , the method may start in block 701.

[0075] The memory controller completes a read sequence by executing a scheduled number of consecutive read requests (block 702). As described above, the memory controller circuit 110 creates a set of received read requests to form a read sequence. The requests of the read sequence are executed in a specific order, and no write request is executed until the last read request of the read sequence has been completed. The specific order may include executing some read requests serially, while some read requests may be executed simultaneously, such as executing two read requests addressing different memory banks or different memory devices in parallel.

[0076] The memory controller completes the write sequence by executing the scheduled number of consecutive write requests (block 704). Similar to block 702, as described above, the memory controller circuit 110 uses the write requests queued to the write request queue 140 to create a set of write requests to form a write sequence. As with the requests of the read sequence, the requests of the write sequence may be executed in a specific order, and the read request is not executed until the last write request of the write sequence is completed. The specific order of the write requests may also include executing some write requests serially, while executing some write requests simultaneously, where appropriate.

[0077] In response to completing the read sequence and the write sequence, the memory controller determines an efficiency value based on the amount of time the memory controller was executing memory requests during the read sequence and the write sequence (block 706). After executing the memory requests of the read sequence and the subsequent write sequence, the memory controller circuit 110 determines a current memory access efficiency value. For example, the efficiency value may be based on a percentage of cycles of the clock signal 115 that occurred during execution of the memory commands associated with the memory requests in the read sequence and the write sequence out of a total number of cycles that occurred from the start of execution of the first request of the read sequence to the completion of the last request of the write sequence.

[0078] The memory controller adjusts the number of memory requests to be executed in the subsequent read sequence and write sequence based on the determined value (block 708). The memory controller circuit 110 compares the determined current memory access efficiency value with the specified memory access efficiency value. Based on the comparison, the memory controller circuit 110 may adjust the number of read requests and / or write requests scheduled in the subsequent read sequence and write sequence. In some cases, the number of read requests in the read sequence or the number of write requests in the write sequence (but not both) may be zero. The method ends in block 710.

[0079] Note that method 700 is an example involving managing memory requests. In other embodiments, operations may be performed in a different order. Some embodiments may include additional operations, such as including a read-to-write transition between a read sequence and a write sequence.

[0080] exist Figure 8 A block diagram of an embodiment of a computer system such as a system on a chip (SoC) is shown in . Computer system 800 may represent a system that includes memory controller circuits and memory circuits and utilizes the concepts disclosed above. In various embodiments, computer system 800 may be a system implemented on one or more circuit boards including multiple integrated circuits, or may be an SoC integrated onto a single computer chip, or may be implemented as a combination thereof. Computer system 800 includes several processing cores (including core 801), a graphics processor 802, and system peripherals 803, all of which are coupled to a memory cache controller 805. Memory cache controller 805 is coupled to cache memory 806 and memory controller circuit 808. Memory controller circuit 808 is coupled to memories 810a-810c. Memory controller 808 and memories 810a-810c together form a memory system 820, which, in some embodiments, corresponds to Figure 1 A memory system 100 in FIG.

[0081] In the illustrated embodiment, core 801 represents a general-purpose processing core that performs computing operations. Although a single processing core (i.e., core 801) is shown, in some embodiments, core 801 may correspond to a core complex that includes any suitable number of processing cores. In various embodiments, core 801 may implement any suitable instruction set architecture (ISA), such as ARM TM , The kernel 801 may execute instructions and utilize data stored in memory external to the computer system 800, such as memory 810a-810c, by issuing memory transactions to obtain the instructions and data to be utilized. Data and instructions obtained from memory 810a-810c may be cached in cache memory 806. In some embodiments, the kernel 801 may include one or more cache memories in addition to cache memory 806.

[0082] In the illustrated embodiment, the graphics processor 802 includes circuitry for processing images or videos to be sent to a display screen (not shown). In some embodiments, images and / or videos to be processed by the graphics processor 802 may be stored in memories 810a-810c. The memories 810a-810c may also store graphics processing instructions used by the graphics processor 802 to generate images. The graphics processor 802 may correspond to a processing core capable of issuing memory transactions to retrieve graphics data and instructions. Data retrieved from the memories 810a-810c may be cached in the cache memory 806.

[0083] In the embodiments identified, the system peripherals 803 include one or more circuit blocks for performing any number of suitable tasks. For example, in various embodiments, the system peripherals 803 may include any one or more of a communication peripheral (e.g., a universal serial bus (USB), Ethernet), an encryption engine, an audio processor, a direct memory access module, or any other peripheral that can generate memory transactions to retrieve data or commands from the memories 810a-810c. The system peripherals 803 may include one or more processing cores within various functional circuits that are capable of issuing memory transactions to the memory cache controller 805.

[0084] In the illustrated embodiment, the memory cache controller 805 includes circuitry for managing memory transactions issued by the core 801, the graphics processor 802, and the system peripherals 803. In the illustrated embodiment, the memory cache controller 805 decodes the memory transaction, translates the address, and determines whether the valid content corresponding to the addressed location is currently in the cache memory 806, or whether the data is to be obtained from the memory 810a-810c or elsewhere. If the valid content is not currently cached in the cache memory 806, the memory cache controller 805 may send the transaction to the memory controller circuit 808 to obtain the requested data. In some embodiments, the computer system 800 may include more than one cache memory 806, and therefore may include a corresponding memory cache controller 805 for each cache memory 806.

[0085] In some embodiments, the memory controller circuit 808 may correspond to Figure 1 806. The memory controller circuit 808 may include one or more memory controller circuits for implementing memory transactions from each of the memories 810a-c. For example, one memory controller circuit may be included for each of the memories 810a-810c. In the illustrated embodiment, the memory controller circuit 808 includes circuits for reading and writing data to each of the memories 810a-810c. If valid content corresponding to the transaction address is not currently stored in the cache memory 806, the memory controller circuit 808 receives the memory transaction from the memory cache controller 805.

[0086] The memories 810a-810c are storage devices that together form at least a portion of a memory hierarchy that stores data and instructions for the computer system 800. More specifically, the memories 810a-810c may correspond to volatile memories that have an access time that is less than the access time of non-volatile memory devices. Thus, the memories 810a-810c may be used to store instructions and data corresponding to an operating system and one or more application programs that are read from non-volatile memory after system startup of the computer system 800. The memories 810a-810c may represent memory devices in the dynamic random access memory (DRAM) family of memory devices or in the static random access memory (SRAM) family of memory devices, or in some embodiments, a combination thereof.

[0087] Also note that to improve clarity and aid in demonstrating the concepts disclosed, Figure 8 The block diagram of computer system 800 shown has been simplified. In other embodiments, different and / or additional circuit blocks and different configurations of these circuit blocks are possible and contemplated.

[0088] Fig. 9 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. Fig. 9 Embodiments of the present invention may be used in designing and manufacturing integrated circuits such as, for example, including Figure 8 The semiconductor manufacturing system 920 is used in the process of manufacturing an IC of the computer system 800. In the illustrated embodiment, the semiconductor manufacturing system 920 is configured to process the design information 915 stored on the non-transitory computer-readable storage medium 910 and manufacture the integrated circuit 930 based on the design information 915.

[0089] The non-transitory computer-readable storage medium 910 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 910 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 910 may also include other types of non-transitory memories or combinations thereof. The non-transitory computer-readable storage medium 910 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0090] The design information 915 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 915 may be capable of being used by the semiconductor manufacturing system 920 to manufacture at least a portion of the integrated circuit 930. The format of the design information 915 may be recognizable by at least one semiconductor manufacturing system, such as the semiconductor manufacturing system 920. In some embodiments, the design information 915 may include a netlist specifying the elements of the cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in the integrated circuit 930 may also be included in the design information 915. Such cell libraries may include information indicating a device or transistor level netlist, mask design data, characterization data, etc. of the cells included in the cell library.

[0091] In various embodiments, the integrated circuit 930 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, the design information 915 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, the mask design data may be formatted according to a graphic data system (GDS) or any other suitable format.

[0092] Semiconductor manufacturing system 920 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 920 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0093] In various embodiments, the integrated circuit 930 is configured to operate according to the circuit design specified by the design information 915, which may include performing any of the functionality described herein. For example, the integrated circuit 930 may include any of the various elements shown or described herein. In addition, the integrated circuit 930 may be configured to perform the various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0094] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0095] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even when only a single embodiment is described with respect to specific features. The feature examples provided in this disclosure are intended to be illustrative, not limiting, unless otherwise stated. The above description is intended to cover such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the effective effects of the present disclosure.

[0096] The scope of the present disclosure includes any feature or combination of features disclosed herein (explicitly or implicitly) or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from the corresponding independent claims may be combined in any appropriate manner and not just by the specific combinations listed in the appended claims.

Claims

1. A device comprising: Memory circuit; and A memory controller circuit comprising a write request queue configured to: receiving a memory request to access the memory circuit, and determining whether the memory request comprises a read request or a write request; scheduling the received read request for execution; storing the received write request in the write request queue; determining a current memory access efficiency using a ratio of a number of active clock cycles used to execute memory requests included in a recent read sequence and a write sequence to a number of total clock cycles; as well as Based on the current memory access efficiency and the specified memory access efficiency, scheduled memory requests are reordered, wherein the particular write request is prioritized over a different write request based on a determination that an amount of data to be stored by the particular write request is greater than an amount of data to be stored by the different write request.

2. The apparatus of claim 1 , wherein a read sequence corresponds to execution of a plurality of read requests and a write sequence corresponds to execution of a plurality of write requests, and wherein the active clock cycles correspond to cycles used to process memory requests included in the most recent read and write sequences and the total clock cycles correspond to the number of cycles that occur from the start of execution of a first request in the read sequence to the completion of a last request in the write sequence.

3. The apparatus of claim 2, wherein the memory controller circuit is further configured to modify a number of memory requests to be executed in subsequent read sequences and write sequences based on a comparison of the current memory access efficiency with the specified memory access efficiency. 4 . The apparatus of claim 2 , wherein the memory controller circuit is further configured to schedule at least one partial write memory request to be executed between a read sequence and a write sequence. 5 . The apparatus of claim 1 , wherein the memory controller circuit is further configured to schedule a subset of the write requests included in the write request queue in response to determining that the number of write requests in the write request queue satisfies a threshold number of requests. 6 . The apparatus of claim 5 , wherein the memory controller circuit is further configured to prioritize read requests over write requests by scheduling a subset of the write requests to be executed after executing a plurality of read requests.

7. A method comprising: receiving, by a memory controller, a memory request to access a memory circuit, wherein the memory controller includes a write request queue and a scheduled request buffer; Processing, by the memory controller, the memory request according to whether the memory request is a read request or a write request; determining an efficiency value based on activity of a communication bus during execution of a plurality of read requests and a plurality of write requests, wherein the communication bus is coupled between the memory controller and at least one memory circuit, and the efficiency value is determined using a ratio of a number of active bus clock cycles used to process the memory requests to a total number of bus clock cycles; scheduling the memory requests based on the efficiency value and based on a number of write requests stored in the write request queue, wherein the scheduling includes prioritizing a particular write request over a different write request based on a determination that an amount of data to be stored by the particular write request is greater than an amount of data to be stored by the different write request; as well as The scheduled read requests and write requests are executed by the memory circuit.

8. The method of claim 7, wherein the processing comprises adding to the write request queue in response to the memory request being a write request.

9. The method of claim 8, further comprising scheduling a plurality of write requests from the write request queue for execution in response to determining that the number of write requests in the write request queue is greater than a threshold number.

10. The method of claim 7, wherein the processing comprises scheduling the memory request for execution in response to the memory request being a read request.

11. The method according to claim 7, further comprising: Complete the read sequence by executing the scheduled number of consecutive read requests; Complete the write sequence by executing the scheduled number of consecutive write requests; as well as The efficiency value is determined in response to completing a read sequence and a write sequence. 12 . The method of claim 11 , further comprising adjusting a number of memory requests to be performed in subsequent read and write sequences based on the determined efficiency value.

13. An apparatus comprising: a system interface coupled to at least one processor; an instruction queue configured to store one or more memory requests prior to execution; Write request queue; and An arbitration circuit, wherein the arbitration circuit is configured to: receiving a memory request from the system interface and determining whether the memory request comprises a read request or a write request; placing the received read request into the instruction queue; placing the received write request into the write request queue; determining a current level of memory access efficiency using a ratio of a number of active bus clock cycles used to execute memory requests included in a recent read sequence and a write sequence to a total number of bus clock cycles; as well as Memory requests placed in the instruction queue are reordered based on the current level of memory access efficiency and a specified level of memory access efficiency, wherein the particular write request is prioritized over the different write request based on a determination that an amount of data to be stored by the particular write request is greater than an amount of data to be stored by the different write request.

14. The apparatus of claim 13 , wherein a read sequence corresponds to execution of a plurality of read requests and a write sequence corresponds to execution of a plurality of write requests, and wherein the active bus clock cycles correspond to cycles used to process memory requests included in the most recent read and write sequences and the number of total bus clock cycles corresponds to the number of cycles occurring from the start of execution of a first request in the read sequence to the completion of a last request in the write sequence.

15. The apparatus of claim 14, wherein the arbitration circuit is further configured to adjust a number of memory requests to be executed in subsequent read sequences and write sequences based on a comparison of the current level with the specified level. 16 . The apparatus of claim 14 , wherein the arbitration circuit is further configured to place at least one partial write memory request in the instruction queue to be executed between a read sequence and a write sequence.

17. The apparatus of claim 13, wherein the arbitration circuit is further configured to place a subset of the write requests included in the write request queue in the instruction queue in response to determining that the number of write requests in the write request queue satisfies a threshold number of requests, wherein the scheduled read request is executed in priority to the subset of write requests.

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