Low-Speed Bus Timestamping Method and Circuit

Abstract

Methods and circuits for low-speed bus timestamping and triggering are presented in this disclosure. A master device and a slave device can be interfaced via a communication link including data lines and a clock line. The master device generates and controls a clock signal on the clock line and sends a synchronization command to the slave device on the data line. In response to the synchronization command, the master device receives timestamp information of events detected at each slave device. The master device tracks transitions and frequencies of the clock signal and determines the time of events based on the timestamp information, the tracked transitions and frequencies. The master device can also send delay setting information to each slave device for generating a trigger signal at the slave device based on transitions of the clock signal, the synchronization command, and the delay setting information.

Description

[0001] Division Explanation

[0002] This application is a divisional application of the Chinese patent application with application number 201680043146.1, titled "Low-Speed Bus Timestamping Method and Circuit", filed on July 18, 2016. Technical Field

[0003] The present disclosure generally relates to low-speed bus message protocols, and more particularly to methods and circuits for low-speed bus timestamping and triggering. Background Art

[0004] Internal integrated circuit (I2C) interfaces are commonly used to attach lower-speed peripheral integrated circuits (ICs) to higher-speed processors and microcontrollers. The lower-speed peripheral ICs are typically referred to as slave devices, while the higher-speed processors or microcontrollers are typically referred to as master devices. Generally, the slave devices can be coupled to peripheral devices such as sensors, gyroscopes, compasses, microphones, etc. The slave devices can be configured to monitor and / or control the operation of the peripheral devices coupled to the slave devices.

[0005] In the I2C message protocol, simultaneous operations by two or more slave devices can utilize a common trigger signal (e.g., generated by the master device) that is independent of the I2C low-speed serial bus. Similarly, to determine when an event occurs (e.g., a measurement performed by a peripheral device coupled to a slave device), each slave device uses a dedicated line fed back to the master device to signal to the master device the time when the event occurs. For each slave device, the master device can capture the state of the actual time clock (i.e., the time of the event or the timestamp of the event) when the master device receives the event marker signal from the slave device. The disadvantage of this method is the many additional communication lines (i.e., board traces) between the master device and the slave devices and the required additional signal pins. Summary of the Invention

[0006] Certain embodiments of the present disclosure provide a system for low-speed bus triggering, the system including: a master device, coupled to a communication link, the master device configured to: transmit a clock signal and a synchronization command via the communication link, and transmit delay setting information via the communication link, the delay setting information indicating the number of selected transitions of the clock signal to occur between the synchronization command and the generation of a trigger signal at one or more slave devices coupled to the communication link; a slave device, coupled to the communication link, the slave device configured to: receive the synchronization command and first delay setting information via the communication link, and track the number of selected transitions of the clock signal after the synchronization command, and generate a trigger signal in response to the number of selected transitions reaching the delay setting indicated by the first delay setting information.

[0007] Certain embodiments of the present disclosure provide a slave device, including: an interface for coupling to a communication link carrying a clock signal, the interface being configured to receive a synchronization command and first delay setting information via the communication link, and a control circuit configured to track the number of selected transitions of the clock signal after the synchronization command and generate a trigger signal in response to the number of selected transitions reaching a delay setting indicated by the first delay setting information.

[0008] Certain embodiments of the present disclosure provide a master device, including: an interface circuit for coupling to a communication link, the interface circuit being configured to: transmit a clock signal and a synchronization command via the communication link; and receive delay setting information via the communication link, the delay setting information indicating the number of selected transitions of the clock signal to occur between the synchronization command and the generation of a trigger signal at one or more slave devices coupled to the communication link.

[0009] Certain embodiments of the present disclosure provide a method for low-speed bus triggering, the method including: receiving a synchronization command and first delay setting information via a communication link carrying a clock signal; tracking the number of selected transitions of the clock signal after the synchronization command; and generating a trigger signal in response to the number of selected transitions reaching a delay setting indicated by the first delay setting information. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram illustrating an I3C master device interfacing with multiple slave devices via an I3C-based communication link according to an embodiment of the present disclosure.

[0011] Figure 2 is a schematic diagram of a system for implementing timestamping and delay triggering including a master device interfacing with a slave device via an I3C-based communication link according to an embodiment of the present disclosure.

[0012] Figure 3 illustrates an example timestamp synchronization command and waveforms of signals driving an I3C serial bus with respect to the timestamp synchronization command according to an embodiment of the present disclosure.

[0013] Figure 4 is an example schematic diagram of a circuit for implementing time synchronization at a slave device according to an embodiment of the present disclosure.

[0014] Figure 5 is an example schematic diagram of an oscillator circuit for improving the resolution of time synchronization that can be implemented at a slave device according to an embodiment of the present disclosure.

[0015] Figure 6 is an example schematic diagram of a circuit for implementing timestamping that can be implemented at a slave device according to an embodiment of the present disclosure.

[0016] Figure 7 An example diagram of the time for a master device to capture and read events from multiple slave devices according to an embodiment of the present disclosure.

[0017] Figure 8 An example diagram of the time for a master device and / or a monitoring device to capture and read events from multiple slave devices according to an embodiment of the present disclosure.

[0018] Figure 9 An example schematic diagram of a circuit for implementing timestamping at a slave device without an oscillator circuit (e.g., an oscillator circuit from Figure 5 ).

[0019] Figure 10 An example schematic diagram of a circuit for implementing a delayed trigger at a slave device according to an embodiment of the present disclosure.

[0020] Figure 11 An example diagram of a master device controlling the time of events at multiple slave devices according to an embodiment of the present disclosure.

[0021] Figure 12 An example schematic diagram of a circuit that can be implemented at a master device to support timestamping according to an embodiment of the present disclosure.

[0022] Figure 13 A diagram illustrating a method for timestamping changes in a reference clock signal executed at a master device according to an embodiment of the present disclosure.

[0023] Figure 14 A flowchart illustrating a method for timestamping that can be executed at a master device according to an embodiment of the present disclosure.

[0024] Figure 15 A flowchart illustrating a method for delayed trigger that can be executed at a slave device according to an embodiment of the present disclosure.

[0025] Figure 16 A flowchart illustrating a method for delayed trigger that can be executed at a master device according to an embodiment of the present disclosure.

[0026] The accompanying drawings depict embodiments of the present disclosure for illustrative purposes only. Those skilled in the art will readily appreciate from the following description that alternative embodiments of the structures and methods illustrated herein can be employed without departing from the principles of the disclosure described herein or the benefits advocated. Detailed Description

[0027] Embodiments of the present disclosure relate to synchronizing multiple slave devices operating in conjunction with a master device according to a messaging protocol, such as the I3C messaging protocol, which is an enhanced version of the Inter-Integrated Circuit (I2C) messaging protocol. Synchronization of the multiple slave devices presented herein can provide accurate timestamping of events detected at the slave devices, as well as efficient initiation of delayed trigger events at the multiple slave devices.

[0028] Certain embodiments of the present disclosure support initiating simultaneous read / operations on peripherals coupled to slave devices. For example, the methods and circuits presented herein can synchronize measurements between a gyroscope and a magnetic compass (coupled to a pair of slave devices), while both the gyroscope and the magnetic compass are positioned on a rotating object. The methods and circuits presented in the present disclosure can also initiate delayed trigger events on multiple slave devices, which can be useful for tomography.

[0029] According to embodiments of the present disclosure, as discussed in more detail below, multiple slave devices can initiate simultaneous operations (e.g., measurements) via an I3C time synchronization trigger. In this way, the need for side channels for synchronizing events can be eliminated. There is no concern for time units or local clock signals, since all slave devices can be triggered simultaneously. More generally, embodiments of the present disclosure support the use of time synchronization commands that initiate a timer at each slave device, which triggers an event at the end of a predetermined time period. The time delay for triggering an event at each slave device can be set by a steering command, which can precede the time synchronization command.

[0030] In an illustrative embodiment of the present disclosure, cellular phone-based tomography can be considered. Each slave device can drive one transducer in a transducer array (e.g., located on the back of a cellular phone), where the transducer generates an acoustic pulse (e.g., to control the phase for beamforming) at the end of each of the aforementioned time delay intervals (e.g., based on a trigger signal from the slave device). Soon after, each transducer can receive a reflected waveform, where each feature of the reflected waveform (e.g., as defined by an earlier command, which is within a preset time aperture and within current amplitude / derivative / second derivative bounds) can be timestamped and recorded in a register at the slave device. Then, the master device can poll each slave device and read back the stored timestamped data. For example, after a certain number of trigger / timestamp operations, there is sufficient data to create an image of the interior of the abdomen (or some other internal organ).

[0031] According to embodiments of the present disclosure, independent clock signals and counter circuits in different slave devices can be synchronized for timestamping their readings. In this way, events from different sensors can be accurately time-correlated. For example, multiple measurements generated by an I3C microphone array can be correlated to determine the direction from which a sound (e.g., "applause") originated, where each microphone in the array can have its own clock signal.

[0032] Embodiments of the present disclosure support the use of new common command code (CCC) serial bus commands, namely, the "Time Sync" command for time synchronization. In some embodiments, the master device can issue a time sync CCC to synchronize all slave devices to a specific transition (e.g., falling edge) of the clock signal driving the serial clock line (SCL) bus. Each slave device can be configured to count all transitions of the SCL signal after detecting the time sync CCC, and can use the transitions of the SCL clock signal as time markers for timestamping events. The master device can count all transitions of the SCL clock signal after detecting the time sync CCC, while also monitoring the period of the transitions of the SCL clock signal for a (stable) time basis. The master device can also monitor the bus traffic for timestamped data, collect the timestamped data, and perform calculations to determine the timing of events (e.g., sensor measurements) detected at the slave devices for the time basis. In other embodiments, a monitoring device separate from the master device can perform the counting of SCL transitions and the collection of timestamped data.

[0033] Embodiments of the present disclosure facilitate accurate timestamping and triggering. In one or more embodiments, for timestamping, the slave device can monitor the sensor and record the time (count) at which the sensed event occurred. In one or more other embodiments, for triggering, the master device can issue a command for all slave devices in a group to start certain operations at an exact time (count). It should be noted that this can be for a delayed start, after which the action occurs, where the time delay can be preset to different delay values on a per-slave-device basis.

[0034] Figure 1 FIG. 100 is a schematic diagram illustrating a master device 102 interfaced with multiple slave devices 104 according to embodiments of the present disclosure. In one or more embodiments, each slave device 104 can be a low-speed peripheral integrated circuit (IC), while the master device 102 can be a higher-speed processor or microcontroller. In one embodiment, the master device 102 can be coupled to a real-time clock source 106 that generates a clock signal 108 for the master device 102. In another embodiment, the master device 102 can include an internal clock signal source for generating a clock signal.

[0035] As Figure 1 shown, the master device 102 may interface with the slave device 104 via the communication link 110. In some embodiments, the communication link 110 is a dual-wire communication link including a serial data line (SDA) bus 112 and an SCL bus 114. The SDA bus 112 is a single-wire bus that may be used to carry commands and / or data between the master device 102 and the slave device 104 using single-ended signals according to a communication protocol such as I3C. The SCL bus 114 is a single-wire bus that may be used to carry a single-ended clock signal (e.g., clock signal 108) that may be generated and / or controlled by the master device 102. The clock signal 108 is used as a timing reference for sending and receiving commands and / or data on the SDA bus 112. Each slave device 104 may be coupled to a peripheral device (e.g., a transducer, a microphone, a sensor, etc.) controlled by the slave device 104.

[0036] For some embodiments discussed in more detail below, the master device 102 may issue a time synchronization command via the SDA bus 112 to synchronize the local counts of the transitions (e.g., the falling edges of the clock signals) of the clock signals in different slave devices 104, so as to accurately timestamp readings (events) from devices (e.g., sensors) coupled to the slave devices 104. The timestamped events locally stored at each slave device 104 may be provided (e.g., via the SDA bus 112) to the master device 102 to calculate the actual occurrence time of each event, where the global actual time may be accurately tracked by the master device 102 based on the transitions of the clock signal 108 (e.g., the signal carried by the SCL bus 114). In this way, events (e.g., measurements) from different sensors coupled to different slave devices 104 may be accurately time-correlated at the master device 102.

[0037] For some other embodiments discussed in more detail below, multiple slave devices 104 may initiate a synchronization operation (e.g., a measurement) via a time synchronization trigger controlled by the master device 102 (e.g., by sending an appropriate command via the SDA bus 112). Thus, the need for a side communication channel between the master device 102 and the slave devices 104 for synchronizing operations (events) may be eliminated.

[0038] Figure 2 is a schematic diagram of a system 200 that may implement timestamping and delayed triggering and includes a master device 202 that interfaces with a slave device 204 via a communication link 205. For some embodiments, the master device 202 may correspond to Figure 1 the master device 102 shown in Figure 1Any of the slave devices in slave device 104 shown. Although one slave device 204 is illustrated in Figure 2 Figure 2 , embodiments of the present disclosure support interfacing multiple slave devices 204 to a master device 202. As Figure 2 shown, communication link 205 may include an SDA bus 206 and an SCL bus 208. As Figure 2 further shown, both the master device 202 and the slave device 204 may drive the SDA bus 206, while only the master device 202 may provide and control a clock signal (hereinafter referred to as the SCL clock signal 208) that may be carried by the SCL bus 208. The slave device 204 may communicate with the master device 202 via the SDA bus 206, and the slave device 204 may utilize the SCL clock signal 208 for timestamping events detected by the slave device 204 and / or synchronizing delay triggers (as discussed in more detail below).

[0039] In some embodiments, the master device 204 may broadcast single data rate (SDR) commands 210 to the slave devices 204 via the SDA bus 206. In one or more embodiments, the SDR commands 210 may include time synchronization CCCs. After the SDR commands 210 are decoded (e.g., by decoding logic 212), the slave devices 204 may operate according to the decoded SDR commands 210. In one embodiment, the time synchronization CCC may be detected at a time tracking / trigger control circuit 214. Based on the detected time synchronization CCC, a time synchronization mark (not shown) may be generated by the time tracking / trigger control circuit 214 to begin time synchronization and time tracking until an event occurs and is detected (as discussed in more detail below). As Figure 2 shown, the slave device 204 may be coupled to a sensor 216 that generates a sensor output signal 218 indicative of a measurement of an environmental characteristic. An event detector circuit 220 detects the occurrence of an event based on the sensor output signal 218 and generates an event detection signal 222 that switches from a low logic level to a high logic level when the event is detected.

[0040] In some embodiments, the time tracking / trigger control circuit 214 may be configured to timestamp the occurrence of an event (e.g., a sensor measurement) 222 with reference to the start of time synchronization, which may be indicated by a time synchronization mark (not shown). As discussed in more detail below, the time tracking / trigger control circuit 214 may perform the timestamping of the event 222 based at least in part on a selected transition of the SCL clock signal 208 (i.e., the reference clock signal) that may be generated and controlled by the master device 202. The time tracking / trigger control circuit 214 may store the timestamp 224 of the event 222. As Figure 2As shown and discussed in more detail below, communication logic 226 can read the value of timestamp 224 and provide the timestamp value 224 to SDA bus 206 (e.g., when SDA bus 206 has no other traffic). As Figure 2 As further shown, communication logic 226 and decoding logic 212 represent an interface 228 that couples slave device 204 to SDA bus 206.

[0041] In some embodiments, prior to broadcasting SDR command 210 with a time synchronization CCC, master device 202 can communicate (e.g., via SDA bus 206) other SDR commands with delay setting information to slave device 204, the delay setting information determining a time delay for generating a trigger signal by slave device 204. As Figure 2 As shown, trigger delay setting circuit 230 generates delay setting information 232 that indicates a trigger delay in the form of a number of selected transitions of SCL clock signal 208 that are to occur between SDR command 210 with a time synchronization CCC and the generation of a trigger signal at slave device 204. In one embodiment, trigger delay setting circuit 230 generates delay setting information 232 based on an expected frequency change of SCL clock signal 208 that is to occur after SDR command 210 with a time synchronization CCC. Information about the expected frequency change of SCL clock signal 208 is known at master device 202. Encoder 234 of master device communication interface 236 encodes delay setting information 232 within SDR command 210. SDR command 210 with encoded delay setting information 232 is then broadcast via SDA bus 206 to one or more slave devices 204 to initiate a delayed trigger. As Figure 2 As further shown, once decoding logic 212 of slave device 204 decodes the delay setting information (e.g., a coarse delay setting and a fine delay setting) provided by master device 202 within SDR command 210 and then detects a time synchronization CCC encoded within another SDR command 210, time tracking / trigger control circuit 214 can be configured to generate a delayed trigger signal 238 at a time delay determined based on the provided delay setting information (as discussed in more detail below). In one embodiment, delayed trigger signal 238 can initiate an operation (e.g., a measurement) of a peripheral device coupled to slave device 204, e.g., an operation of output transducer 240 coupled to slave device 204.

[0042] In some embodiments, Figure 2The time tracking circuit 242 of the master device 202 illustrated in the figure may be configured to track the actual time starting from the time synchronization tag generated after the synchronization signal 244. The encoder 234 encodes the synchronization signal 244 to generate an SDR command 210 with the time synchronization CCC, and the SDR command 210 may then be broadcast via the SDA bus 206 to one or more slave devices 204 to initiate time synchronization. The synchronization CCC broadcast 246 (i.e., the time synchronization CCC) may also be detected within the time tracking circuit 242, and the time tracking circuit 242 may then generate a time synchronization tag that indicates the start of tracking the system reference time at the master device 202 based on the number of selected transitions of the tracked SLC clock signal 208.

[0043] In some embodiments, the counter circuit 248 within the time tracking circuit 242 may be configured to keep track of the number of selected transitions (e.g., falling edges) of the SCL clock signal 208. For each frequency of the SCL clock signal 208, the number of selected transitions of the SCL signal 208 (e.g., denoted as SCL count C0 in Figure 2 the figure) may be saved into a latch 250, and the latch 250 may be controlled by a change of frequency (COF) signal 252. As discussed in more detail below, the SCL count C0 may represent the number of selected transitions of the SCL clock signal 208 between the time synchronization tag and the last selected transition (e.g., falling edge) of the SCL clock signal 208 before the change of frequency of the SCL clock signal 208. After each change of frequency of the SCL clock signal 208, the updated SCL count C0 may be stored in the latch 250 controlled by the COF signal 252. The updated SCL count C0 may indicate the number of selected transitions of the SCL clock signal 208 between the time synchronization tag and the last selected transition before the change of frequency of the SCL clock signal 208. After each change of frequency of the SCL clock signal 208 and based on the corresponding COF signal 252, the previous (old) value of the SCL count C0 may also be saved in a register file (e.g., look-up table) 254. Thus, the register file 254 may include different values (e.g., values CNT_1, CNT_2,..., CNT_N) of the SCL count C0 corresponding to N different frequencies of the SCL clock signal 208. Each value CNT_i stored in the register file 254 may also be associated with a value Ti representing the period of each frequency encoding the SCL clock signal 208. Therefore, the values of CNT_i and Ti (i = 1,..., N) stored in the register file 254 may provide information about the system reference time from the time synchronization tag.

[0044] In some embodiments, the master device 202 may receive information about a timestamp 224 of an event 222 detected at the slave device 204 via the SDA bus 206. The master device 202 may use the information about the system reference time of the start trace of the slave time synchronization mark stored in the register file 254 to correlate it with the timestamp 224 (e.g., at the actual time calculation circuit 256) to determine the exact global (system) time 258 at which the event 222 occurred. The calculated time 258 represents the global time measured based on the selected transition of the SCL clock signal 208 starting from the start of the time synchronization mark at the master device 202. In one embodiment, the SCL clock signal 208 may be generated at the master device 202 by an adjustable clock generator 260, and the adjustable clock generator 260 may provide the frequency of the SCL clock signal 208 based on an indication 262 of the desired period of the SCL clock signal 208 (e.g., indicating Ti).

[0045] As discussed above, embodiments of the present disclosure support adding a new timestamp synchronization CCC broadcast command to the message protocol. The master device 202 may issue a timestamp synchronization command via the SDA bus 206 to synchronize one or more slave devices 204 coupled to the SDA bus 206 to a specific selected transition (e.g., falling edge) of the clock signal driving the SCL bus. Figure 3 Illustrated is a waveform of an example timestamp synchronization command 300 according to an embodiment of the present disclosure and signals driving the SDA and SCL buses in relation to the timestamp synchronization command 300. The timestamp synchronization command 300 may be initiated by the master device 202 and broadcast to one or more slave devices 204 via the SDA bus 206. As Figure 3 shown, a start portion 302 of the timestamp synchronization command 300 may be followed by a broadcast portion 304 indicated with the value 0x7E. Toward the end of the broadcast portion 304, the master device may send a write operation (‘W’) signal to the slave device, where at least one slave device may respond to the write operation (‘W’) with an acknowledgement (ACK) on the SDA bus to confirm receipt of the broadcast portion 304 of the timestamp synchronization command 300.

[0046] As Figure 3As shown, the CCC part 306 of the SDR command of the timestamp synchronization command 300 may follow the broadcast part 304. The command code 0x28 corresponds to the timestamp synchronization command. The part 308 (e.g., the 'T' bit) may be associated with a specific signal waveform 310 on the SDA bus. During the 'T' bit of the timestamp synchronization command 300, after the first selected transition (e.g., rising edge) of the SCL clock signal, the slave device 204 may detect the time synchronization CCC 312. The next selected transition (e.g., falling edge) of the SCL clock signal may represent the time synchronization mark 314, which is also detected at the slave device 204. As discussed in more detail below, the time synchronization mark 314 may represent the moment when the synchronization of one or more slave devices 204 with the system reference time base generated by the master device 202 starts. As Figure 3 As further shown, the timestamp synchronization command 300 may end at the part 316 that starts reading data from the slave device 204 via the SDA bus.

[0047] In some embodiments, as discussed in more detail below, the time synchronization mark 314 provides a way for multiple slave devices to synchronize for timestamping events. The time synchronization mark 314 also allows multiple slave devices to start simultaneous operations (e.g., measurements) via the time synchronization trigger. As a result, the need for a side channel between the master device and the slave device for synchronizing events can be eliminated. It should be noted that in the trigger case, the time unit or the local clock is not concerned because all slave devices are triggered simultaneously.

[0048] In some other embodiments, the timestamping of events detected at the slave device may be supported based on the time synchronization mark 314. As discussed in more detail below, the control circuit in the slave device may be initialized based on the time synchronization mark 314 and may be configured to track the number of selected transitions of the SCL clock signal. Once an event is detected, the number of selected transitions of the SCL clock signal followed may be saved in the local memory of the slave device to be read back by the master device at a later time. The master device that generates and controls the SCL clock signal may also keep track of the number of selected transitions of the SCL clock signal and may correlate its count with the saved timestamp count read back from the slave device to determine the global system time when the event occurred.

[0049] Figure 4 is an example schematic diagram of a circuit 400 for implementing time synchronization at a slave device such as the slave device 204. In some embodiments, the circuit 400 may be Figure 2Part of the time tracking / trigger control circuit 214 illustrated in the figure. The flip-flop 420 outputs a synchronization pulse 402 to the reset line 404 when detecting a (time) synchronization CCC (i.e., when detecting the rising edge of the pulse 406). Refer back to Figure 2 , the pulse 406 detected by the synchronization CCC can be generated by the decoding logic 212 of the slave device 204 after detecting the time synchronization command 210. The selected transition of the synchronization pulse 402 (which is the falling edge 408 as Figure 4 shown) can represent a time synchronization mark. Refer back to Figure 3 , the time synchronization mark 314 can be aligned with the selected transition of the SCL clock signal during the 'T' bit of the timestamp synchronization command 300 after detecting the time synchronization CCC. Thus, as Figure 4 shown, the time synchronization mark can be aligned with the selected transition 410 of the SCL clock signal 412 after the rising edge of the pulse 406 indicating the detection of the synchronization CCC.

[0050] In some embodiments, the synchronization pulse 402 present at the reset line 404 can reset the counter 414 to all zeros, as shown by the waveform 416 at the output of the counter 414. After being reset to all zeros, the counter 414 increments after each selected transition of the SCL clock signal 412 (e.g., after each falling edge). It can be noted that the method presented herein and Figure 4 illustrated in Figure 4 provides a uniform time reference across all slave devices including the circuit 400 shown in

[0051] based on the synchronization pulse 402 and the time synchronization mark aligned with the selected transitions of the SCL clock signal (which can be controlled by the master device). Figure 5 is an example schematic diagram of an oscillator circuit 500 that can be implemented at the slave device 204 to improve the resolution of timestamping and delayed triggering according to an embodiment of the present disclosure. In one or more embodiments, the oscillator circuit 500 can be Figure 2 part of the time tracking / trigger control circuit 214 of the slave device 204 shown in

[0052] As Figure 5As shown, the oscillator circuit 500 may include a burst oscillator 502 and a counter 504. The burst oscillator 502 includes a number of serially-connected inverters that generate a high-speed clock signal 506 when the enable signal 508 is at a high logic level. The frequency of the high-speed clock signal 506 is higher than the frequency of the SCL clock signal. After being started by a reset signal 510, the counter 504 begins to count the selected transitions of the high-speed clock signal 506. The output F(0) of the burst oscillator 502 and the m-bit output F(1:m) of the counter 504 form the output 512 of the oscillator circuit 500. In one or more embodiments, the burst oscillator 502 may be configured to operate for a limited amount of time sufficient to perform a specific number of measurements (e.g., one or two measurements) after detecting an event. Accordingly, the burst oscillator 502 consumes a limited amount of power.

[0053] In one embodiment, a certain type of sensor (e.g., accelerometer, gyroscope) coupled to a slave device inherently has a relatively stable time basis and can use this time basis to provide a clock signal that can be used to improve the resolution of timestamping and delayed triggering. Other sensors may not have a stable time basis and need to employ a local oscillator for generating a local clock signal. In one embodiment, the local oscillator at the slave device may be based on a phase-locked loop (PLL) device that uses the SCL clock signal as a reference clock to generate a synchronous and stable local clock having a higher frequency than the SCL clock signal. However, this method has the disadvantages of consuming continuous power and a large silicon area.

[0054] Figure 6 is an example schematic diagram of a circuit 600 for implementing timestamping at a slave device 204 according to an embodiment of the present disclosure. The circuit 600 may be Figure 2 part of the time tracking / trigger control circuit 214 of the slave device 204 shown in Figure 6 As shown, the circuit 600 may include the circuit 400 from Figure 4 and the oscillator circuit 500 from Figure 5 In some embodiments, the circuit 600 may be configured to implement timestamping at the slave device 204, and the oscillator circuit 500 is used to improve the resolution of timestamping when compared to timestamping using only the counting of the selected transitions of the SCL clock signal.

[0055] As discussed above with reference to the circuit 400 illustrated in Figure 4 a synchronous pulse (e.g., the synchronous pulse 402 shown in Figure 4 ) present at the reset line 602 may be generated upon detecting (time) synchronization CCC, i.e., upon detecting at the input 604 Figure 4is generated at the rising edge of the pulse 406 shown in. A falling edge of a synchronization pulse (e.g., the synchronization pulse 402 shown in Figure 4 ) can represent a time synchronization marker that aligns with a selection transition (e.g., the falling edge 410 shown in Figure 2 ) of the SCL clock signal 606 during the 'T' bit of a timestamp synchronization command (e.g., the SDR time synchronization command 210 broadcast by the master device 202 shown in Figure 3 , the timestamp synchronization command 300 shown in Figure 4 ) after detecting the synchronization CCC at the input 604. A synchronization pulse present at the reset line 602 can reset the counter 608 to all zeros. In one embodiment, the counter 608 can be the same counter 414 of the circuit 400 shown in Figure 4 . The counter 608 can be configured to increment at each selection transition (e.g., falling edge) of the SCL clock signal 606 and can provide a uniform time reference across all slave devices (e.g., the slave device 104 illustrated in Figure 1 , the multiple slave devices 204 shown in Figure 2 ), where the SCL clock signal 606 can be generated and controlled by a master device (e.g., the master device 102 illustrated in Figure 1 , the master device 202 shown in Figure 2 ).

[0056] In some embodiments, an event 610 can be timestamped at least in part based on the value 612 of the counter 608. After detecting the occurrence of the event 610, a value 612 representing the number of selection transitions of the SCL clock signal 606 between the time synchronization marker and the last selection transition 614 of the SCL clock signal 606 before detecting the event 610 can be stored in a latch 616 (e.g., the value C0 shown in Figure 6 can be stored in the latch 616).

[0057] In some embodiments, as discussed, the oscillator circuit 500 can be used in combination with the counter 608 to provide a finer resolution for timestamping. The oscillator circuit 500 including the burst oscillator 502 from Figure 5 can be configured to generate a periodic oscillator signal having a frequency higher than the frequency of the SCL clock signal 606. As shown in Figure 6As shown, after detecting event 610, trigger 618 generates an enable signal 620 that activates burst oscillator 502 within oscillator circuit 500. After activation based on enable signal 620, burst oscillator 502 of oscillator circuit 500 can generate a high-speed clock signal (oscillator signal) 506, and counter 504 of oscillator circuit 500 can keep track of the number of selected transitions (e.g., falling edges) of oscillator signal 506.

[0058] In one or more embodiments, the first selected transition 622 of SCL clock signal 606 immediately following the detection of event 610 causes the output of trigger 624 to go high, thereby initiating the storage of value 626 at the output of oscillator & counter circuit 500 in latch 628. This value is shown as C1. The value of C1 represents a delay in the form of the number of selected transitions of oscillator signal 506 between the detection of event 610 and the first selected transition 622 of SCL clock signal 606 after the detection of event 610.

[0059] The next selected transition 630 of SCL clock signal 606 after the first selected transition 622 causes the output of trigger 632 to go high. As a result, this initiates the storage of new value 626 at the output of oscillator & counter circuit 500 in latch 634. This value is shown as C2. The value of C2 represents a delay in the form of the number of selected transitions of oscillator signal 506 between the detection of event 610 and the second selected transition 630 of SCL clock signal 606 after the first selected transition 622.

[0060] In some embodiments, information regarding the elapsed time between the time synchronization mark and the detection of event 610 (i.e., the timestamp of event 610) can be based on the stored values C0, C1, and C2. In one or more embodiments, the Figure 2 timestamp 224 from Figure 6 can be calculated at slave device 204 by

[0061]

[0062] In equation (1), T0 represents timestamp 224. Information regarding the timestamp of event 610 can be communicated to master device 202 via interface 228 of slave device 204 when SDA bus 206 is available. In one embodiment, as Figure 6 shown, the timestamp value T0 defined by equation (1) can also be stored in delay register 638 before being communicated to master device 202. Delay register 638 can hold the timestamp value T0 until SDA bus 206 becomes available.

[0063] Figure 7 FIG. 700 is an example diagram of a master device 702 capturing and reading the times of events from multiple slave devices 704 and 706, according to an embodiment of the present disclosure. The master device 702 may correspond to Figure 2 the master device 202 shown in Figure 2 and each of the slave devices 704 and 706 may correspond to Figure 7 the slave device 204 shown in Figure 7 As shown, the master device 702 may broadcast a time synchronization CCC 708 to the slave devices 704, 706. The slave devices 704, 706 may track the time delays 710, 712 between a time synchronization tag ( Figure 7 not shown in Figure 7 FIG. 700) generated when the synchronization CCC 708 is detected at the slave devices 704, 706 and an event detected at each slave device. When an event 714 is detected at the slave device 704 and an event 716 is detected at the slave device 706, the time delays representing the number of selection transitions of an SCL clock signal ( Figure 6 not shown in

[0064] FIG. 700) tracked at each slave device are latched, i.e., the events are timestamped in each slave device and stored in a delay register. As Figure 2 shown, the slave device 704 may store the tracked delay 710 as a timestamp of the event 714 into a delay register 718; the slave device 706 may store the tracked delay 712 as a timestamp of the event 716 into a delay register 720. In one or more embodiments, the delay register 718 of the slave device 704 and the delay register 720 of the slave device 706 may correspond to Figure 2 the delay register 638 illustrated in Figure 7As shown, slave devices 704, 706 may need to wait until the traffic 722 on the SDA bus is completed. Then, slave device 706 can initiate an in-band interrupt (IBI) 724, which signals to master device 702 that the timestamp 712 of event 716 is available for reading by master device 702. After receiving the IBI 724, master device 702 can send a request 726 to slave device 706 via the SDA bus. Request 726 requests to read information about the timestamp 712 of event 716 stored in the latency register 720 of slave device 706. After receiving request 726, slave device 706 can read 728 the timestamp 712 from the latency register 720 and provide information about the timestamp 712 of event 716 to master device 702 via the SDA bus. After that, master device 702 can initiate another read 730 from the latency register 720 of slave device 704, which stores information about the timestamp 710 of event 714. Information about the timestamp 710 of event 714 can then be provided to master device 702 via the SDA bus.

[0065] In Figure 7 the illustrative embodiment shown, slave device 706 may have a higher priority than slave device 704. Although slave device 704 may also initiate an IBI, in this case slave device 704 does not get the chance to do so because master device 702 decides to automatically read the timestamp 710 of event 714 in response to the IBI 724 received from slave device 706. It should also be noted that due to the traffic 722 after the synchronous CCC 708, the SCL clock signal ( Figure 7 not shown in ) may switch continuously before and after the detected events 714, 716, thereby providing a continuous time basis for reference by slave devices 704, 706.

[0066] Figure 8 FIG. 800 is an example diagram of capturing and reading the times of events from multiple slave devices 804 and 806 by a master device 802 and a monitoring device 808 according to an embodiment of the present disclosure. In some embodiments, the monitoring device 808 may interface with the slave devices 804 and 806 via the SDA bus and the SCL bus. Different from the master device 802, the monitoring device 808 neither issues any commands nor generates / controls any clock signals. Instead, the monitoring device 808 may simply monitor the traffic on the SDA bus and collect the corresponding information communicated on the SDA bus by the master device 802 and / or the slave devices 804, 806. The master device 802 may correspond to the master device 202 from Figure 2 and each slave device 804, 806 may correspond to the slave device 204 from Figure 2 .

[0067] AsFigure 8 As shown, the master device 802 can broadcast the time synchronization CCC 810 to the slave devices 804, 806, and the slave devices 804, 806 can track the time synchronization marks generated when the synchronization CCC 810 is detected at the slave devices 804, 806 ( Figure 8 not shown in the figure) and the time delays 812 and 814 between the events detected at each slave device. The synchronization CCC 810 can also be detected by the monitoring device 808. When an event 816 is detected at the slave device 804 and an event 818 is detected at the slave device 806, the time delays tracked at each slave device are latched, that is, the events are timestamped in each slave device and stored in the delay register. As Figure 8 shown, the slave device 804 can store the tracked delay 812 between the time synchronization mark and the detected event 816 into the delay register 820; the slave device 806 can store the tracked delay 814 between the time synchronization mark and the event 818 into the delay register 822. In one or more embodiments, the delay register 820 of the slave device 804 and the delay register 822 of the slave device 806 can correspond to Figure 6 the delay register 638 illustrated in the figure.

[0068] As Figure 8 further shown, other services 824 can be provided by the master device 802 on the SDA bus. The same service 824 can also be monitored by the monitoring device 808. In some embodiments, each slave device may need to wait for the bus idle condition on the SDA bus before the slave device can initiate an interrupt to the master device. As Figure 8 shown, the slave devices 804, 806 may need to wait until the service 824 on the SDA bus is completed. Then, the slave device 806 can initiate an IBI, and the IBI signals via the SDA bus 826 that the timestamp 814 of the event 818 is available for being read. The same interrupt 826 sent via the SDA bus can be received by both the master device 802 and the monitoring device 808. After receiving the interrupt 826, the master device 802 can provide a request 828 with the address of the slave device 806 to the slave device 806, and the request 828 requests to read the information about the timestamp 814 of the event 818 stored in the delay register 822 of the slave device 806. The request 828 including the address of the slave device 806 can also be received by the monitoring device 808.

[0069] After receiving request 828, slave device 806 can read timestamp 814 from delay register 822 at 830 and provide information about timestamp 814 of event 818 to master device 802 via the SDA bus. At the same time, since the information about timestamp 814 of event 818 is available at the SDA bus, monitoring device 808 can also obtain timestamp 814 of event 818. After that, master device 802 can initiate another read 834 from delay register 820 by sending a request 832 with the address of slave device 804, and delay register 820 stores information about timestamp 812 of event 816. The address 832 of slave device 804 can also be received by monitoring device 808 that monitors all traffic on the SDA bus. The information about timestamp 812 of event 816 can then be provided to master device 802 and monitoring device 808 via the SDA bus. As discussed more fully herein with respect to Figure 2 and Figure 12 After receiving timestamp data 812 and 814 from slave devices 804 and 806, respectively, with reference to a global system reference clock signal (i.e., the SCL clock signal) generated and controlled by master device 802 (not shown in Figure 8 ), master device 802 calculates the times of events 816 and 818.

[0070] In some embodiments, master device 802 is not capable of processing timestamp data 812, 814, i.e., master device 802 does not support converting timestamp data 812, 814 into the actual times of events referenced to the global system reference clock signal. In such a case, monitoring device 808 can be configured to handle the processing of timestamp data 812, 814 received from slave devices 804, 806, thereby allowing the use of master devices that do not support timestamps. In this configuration, as discussed above, master device 802 can still control the SDA bus and the SCL bus, as well as handle read / write / interrupts to / from slave devices 804, 806. However, master device 802 does not handle the complexity of timestamps. Instead, monitoring device 808 is configured to convert the received timestamp data 812, 814 into the times of events 816, 818 referenced to the global system reference clock signal. As discussed more fully with respect to Figure 2 and Figure 12 , monitoring device 808 is configured to keep track of the selected transitions of the SCL clock signal and time the transitions of the SCL clock signal relative to its own accurate time base in the same manner that master device 802 would.

[0071] When the IBI 826 is initiated by the slave device 806 by pulling down the SDA bus during the bus idle state after the service 824 is completed, the master device 802 responds by toggling the SCL clock signal and initiates a read-back of the timestamp information 814 from the slave device by sending a request 828. However, the master device 802 may ignore the received timestamp information 814. Instead, the master device 802 may rely on the monitoring device 808, which is also used to read the same timestamp data 814 and use the timestamp 814 to calculate the actual time of the event 818 detected at the slave device 806. Similarly, the monitoring device 808 utilizes the timestamp 812 received from the slave device 804 and calculates the time of the event 816 detected at the slave device 804. At a later time, the monitoring device 808 may send information about the times of the events 816, 818 to the master device 802.

[0072] In Figure 8 the illustrative embodiment shown, the slave device 806 may have a higher priority than the slave device 804. Although the slave device 804 may also initiate an IBI, in this case the slave device 804 does not have the opportunity to do so because the master device 802 decides to automatically read the timestamp 812 of the event 816 in response to the IBI 826 received from the slave device 806. It should be noted that due to the service 824 after the synchronous CCC 810, the SCL clock signal ( Figure 8 not shown in ) may be toggled continuously before and after the detected events 816, 818, thereby providing a continuous time basis for reference by the slave devices 804, 806.

[0073] Figure 9 is an example schematic diagram of a circuit 900 for implementing a timestamp at a slave device (e.g., Figure 2 the slave device 204 shown in ), which does not have an oscillator circuit 500 from Figure 6 shown as part of the timestamp circuit 600 in Figure 5 . The circuit 900 may be part of the time tracking / trigger control circuit 214 of the slave device 204 shown in Figure 2 .

[0074] As discussed above with reference to Figure 4 the circuit 400 illustrated in, the synchronization pulse 402 present at the reset line 902 may be generated when a (time) synchronous CCC is detected, i.e., when the rising edge of the pulse 406 shown in Figure 4 is detected at the input 904. The falling edge of the synchronization pulse 402 may represent a time synchronization marker, which is associated with a timestamp synchronization command after detecting the synchronous CCC at the input 904 (e.g., fromFigure 2 the SDR time synchronization command 210 broadcast by the master device 202 shown in Figure 3 is aligned with the selection transition 410 of the SCL clock signal 906 during the 'T' bit of the timestamp synchronization command 300 shown in. A synchronization pulse present at the reset line 902 can reset the counter 908 to all zeros. The counter 908 can correspond to Figure 4 the counter 414 of the circuit 400 shown in. The counter 908 can be configured to increment with each selection transition of the SCL clock signal 906 and can provide a uniform time reference across all slave devices, while the SCL clock signal 906 can be generated and controlled by the master device.

[0075] In some embodiments, an event 910 can be timestamped at least in part based on the value 912 of the counter 908. After detecting the event 910, the value 912 can be stored in the latch 914, and the value 912 represents the number of selection transitions of the SCL clock signal 906 between the time synchronization mark and the last selection transition of the SCL clock signal 906 before detecting the event 910. As Figure 9 shown, the value C0 representing the number of selection transitions of the SCL clock signal 906 between the time synchronization mark and the detection of the event 910 is stored in the latch 914.

[0076] Since the oscillator circuit 500 including the burst oscillator 502 from Figure 5 is not included in the circuit 900 illustrated in Figure 9 , the values of C1 and C2 associated with a finer resolution of the timestamp are placeholders and are set to zero. After reading the timestamp data 224 associated with the time of the event 910 given by the value of C0 stored in the latch 914, Figure 2 the master device 202 illustrated in can convert the values of C0 + 1 and C0 + 2 into the system reference time for each value, i.e., into the actual times T1 and T2, respectively, by the actual time calculation unit 256. In some embodiments, the value of C0 + 1 represents the number of selection transitions of the SCL clock signal 906 between the time synchronization mark and the first selection transition of the SCL clock signal 906 after the event 910, and the value of C0 + 2 represents the number of selection transitions of the SCL clock signal 906 between the time synchronization mark and the second selection transition of the SCL clock signal 906 after the event 910. Then the master device 202 can determine the system reference (actual) time T of the event 910 together with T1 and T2. Thus,

[0077] where C2 > C1, otherwise T = T1. (2)

[0078] InFigure 9 In the illustrative embodiment shown, both the values of C1 and C2 are set to zero, and the actual time T of event 910 can be determined based solely on the value of C0 + 1, i.e., the actual time T of event 910 can be equal to T1.

[0079] According to an embodiment of the present disclosure, as discussed above, multiple slave devices can initiate simultaneous operations (e.g., measurements) based on a time synchronization trigger controlled by a master device via the SDA bus. Based on this method, an additional communication channel between the master device and the slave devices can be eliminated. Embodiments of the present disclosure support the use of a time synchronization command broadcast by the master device, which can start a timer at each slave device, and the timer triggers an event (e.g., measurement) at the end of a predetermined time period. In one or more embodiments, the time delay for triggering an event at each slave device can be set by a command communicated by the master device via the SDA bus, and this command can precede the time synchronization command.

[0080] Figure 10 is an example schematic diagram of a circuit 1000 for implementing a delayed trigger at the slave device 204 illustrated in Figure 2 . The circuit 1000 can be a part of the time tracking / trigger control circuit 214 of the slave device 204 shown in Figure 2 . In some embodiments, Figure 2 the master device 202 illustrated in

[0081] can control the exact time of the trigger generated at each slave device 204. When a (time) synchronization CCC is detected at the input 1004 (i.e., when a time synchronization command is detected), the trigger 1040 generates a synchronization pulse on the reset line 1002. The falling edge of the synchronization pulse can represent a time synchronization marker 1006, and the time synchronization marker 1006 is aligned with the selected transition of the SCL clock signal 1008 during the 'T' bit of the time synchronization command (e.g., the SDR time synchronization command 210 broadcast by the master device 202 shown in Figure 2 ) after the time synchronization command is detected at the input 1004. The synchronization pulse present at the reset line 1002 can reset the counter 1010 to all zeros. In one embodiment, the counter 1010 can correspond to the counter 414 of the circuit 400 shown in Figure 4 . The counter 1010 increments at each selected transition of the SCL clock signal 1010 and can provide a uniform time reference across all slave devices 204, where the SCL clock signal 1008 can be generated and controlled by the master device 202.

[0082] Figure 10The circuit 1000 illustrated in the figure can generally be configured to track the number of selected transitions of the SCL clock signal 1008 after detecting a time synchronization command, and be configured to generate a trigger signal in response to the number of selected transitions of the SCL clock signal 1008 reaching a delay setting indicated by delay setting information 1012, and the delay setting information 1012 can be provided by the master device 202 into the delay register 1014. In some embodiments, the delay setting information 1012 can include rough delay setting information 1016 and fine delay setting information 1018, which can be set by the master device 202 in a command communicated via the SDA bus before broadcasting the time synchronization command. The rough delay setting information 1016 indicates a trigger delay in the form of the number of selected transitions of the SCL clock signal 1008 to occur between the time synchronization mark 1006 and the generation of the trigger signal. As Figure 10 shown, the comparator 1020 can be configured to compare the rough delay setting information 1016 with the value 1022 of the counter 1010, and the value 1022 represents the number of selected transitions of the SCL clock signal 1008 occurring after the time synchronization mark 1006. When the value 1022 of the counter 1010 is equal to the rough delay setting information 1016 and the number of selected transitions of the SCL clock signal 1008 being tracked reaches the rough delay setting information 1016, the output of the comparator 1024 becomes logic '1'. As a result, the flip - flop 1050 causes the enable signal 1026 to become logic '1', and enables the operation of the oscillator and counter circuit 1028. The oscillator and counter circuit 1028 can be used in combination with the counter 1010 and the comparator 1024 to provide a finer resolution for the delay trigger.

[0083] For some embodiments, the oscillator and counter circuit 1028 can correspond to Figure 5 the oscillator circuit 500 illustrated in the figure, which includes a burst oscillator 502 and a counter 504. When enabled by the enable signal 1026, the oscillator and counter circuit 1028 internally generates a burst oscillator signal 1030 having a frequency higher than that of the SCL clock signal 1008. As Figure 10As shown, after activating the oscillator and counter circuit 1028 with the enable signal 1026, the burst oscillator within the oscillator and counter circuit 1028 can generate a burst oscillator signal 1030, and the counter within the oscillator and counter circuit 1028 can keep track of the number of selected transitions of the burst oscillator signal 1030. The fine delay setting information 1018 indicates a trigger delay in the form of the number of selected transitions of the burst oscillator signal 1030 to occur between the enable signal 1026 and the generation of the trigger signal. Once the number of selected transitions of the burst oscillator signal 1030 represented by the signal 1032 at the output of the oscillator and counter circuit 1028 reaches the fine delay setting 1018, the comparator 1034 causes the logic level of the trigger signal 1036 to become logic "1". At the exact moment controlled by the master device 202 based on the coarse delay setting information and the fine delay setting information, the trigger signal 1036 switches its logic state. The trigger signal 1036 generated by the circuit 1000 illustrated in Figure 10 can correspond to the delayed trigger signal 238 generated by the time tracking / trigger control circuit 214 of the slave device 204 shown in Figure 2 . At the exact moment controlled by the master device 202, the delayed trigger signal 238 can initiate the operation of the transducer 240 coupled to the slave device 204.

[0084] Figure 11 FIG. 1100 is an example diagram of controlling the time of events at multiple slave devices by a master device according to an embodiment of the present disclosure. As Figure 11 shown, the master device 1102 can provide delay setting information to the slave devices 1104 and 1106, that is, the delay setting information 1108 can be stored at the delay register 1110 of the slave device 1104, and the delay setting information 1112 can be stored at the delay register 1114 of the slave device 1106. The delay register 1110 of the slave device 1104 and the delay register 1114 of the slave device 1106 can correspond to the delay register 1014 shown in Figure 10 . In some embodiments, as discussed, the delay setting information 1108 and 1112 can be communicated to the slave devices 1104 and 1106 via the SDA bus via an SDR command sent from the master device 1102. The master device 1102 can correspond to the master device 202 from Figure 2 , and each slave device 1104, 1106 can correspond to the slave device 204 from Figure 2 .

[0085] As Figure 11Further shown, after communicating the delay setup information 1108 and 1112, the master device 1102 may broadcast a time synchronization command (Sync CCC 1116) via the SDA bus. After the Sync CCC 1116 is detected at the slave devices 1104 and 1106, a time synchronization mark ( Figure 11 not shown) may be generated at each slave device, i.e., the slave devices 1104 and 1106 may synchronize by clearing their respective counters. Starting from the time synchronization mark, the slave devices 1104 and 1106 may track a reference time, which may be provided by the master device 1102 via the SCL clock signal. When the time tracked at the slave device 1104 reaches the delay setup information 1108, the slave device 1104 may generate a trigger in the form of a trigger event 1118, which may be delayed a specific reference time 1120 from the time synchronization mark. Similarly, when the time tracked at the slave device 1106 reaches the delay setup information 1112, the slave device 1106 may generate a trigger in the form of a trigger event 1122, which may be delayed a specific reference time 1124 from the time synchronization mark.

[0086] In some embodiments, as discussed, Figure 2 the master device 202 illustrated in may start tracking the system reference time from the time synchronization mark indicated by the time synchronization command, so as to convert the timestamp of an event detected at the slave device 204 to the system (actual) time referenced to the global clock signal generated and controlled by the master device 202. Figure 12 is an example schematic diagram of a circuit 1200 implemented at the master device 202 according to an embodiment of the present disclosure for supporting timestamping. Figure 12 The circuit 1200 illustrated in may correspond to Figure 2 the time tracking circuit 234 of the master device 202 shown in.

[0087] When a Sync CCC broadcast is indicated by a signal with a high logic level at the input 1206, the flip-flop 1202 generates a synchronization pulse on the reset line 1204. The falling edge of the synchronization pulse may represent the time synchronization mark, which is aligned with the selected transition of the SCL clock signal 1208 during the 'T' bit of the time synchronization command detected at the input 1206. The synchronization pulse present at the reset line 1204 may reset the counter 1210 to all zeros. The counter 1210 may correspond to Figure 2The counter circuit 248 of the master device 202 shown in. The counter 1210 increments at each selected transition of the SCL clock signal 1208 and can provide a uniform time reference between the master device and all slave devices. In one embodiment, when the master device controls the SCL bus (e.g., as in SDR and double data rate (DDR) modes), the SCL clock signal 1208 can be derived from a reference clock by a clock generator 260 from Figure 2 and is controlled by the master device 202.

[0088] In some embodiments, the frequency change of the SCL clock signal 1208 can be stamped using the value 1212 of the counter 1210. Once the frequency change (COF) signal 1214 indicating the frequency change of the SCL clock signal 1208 becomes logic '1', the value 1212 of the counter 1210 can be stored in the latch 1216, which is Figure 12 indicated as value C0 in. In one embodiment, the value of C0 represents the number of selected transitions of the SCL clock signal 1208 between the time synchronization mark and the last selected transition of the SCL clock signal 1208 before the first frequency change of the SCL clock signal 1208. Referring back to Figure 2 , the Figure 12 value C0 stored in the latch 1216 in can correspond to the SCL count C0 stored in the latch 250 of the master device 202 when the COF signal 252 goes high.

[0089] In some embodiments, a register or lookup table 1218 can store information related to different periods associated with different frequencies of the SCL clock signal 1208. For example, as Figure 12As shown, bit T(1,0) can be encoded in the duration of a period when the frequency of the SCL clock signal 1208 is 12 MHz; bit T(0,1) can be encoded in the duration of a period when the frequency of the SCL clock signal 1208 is 1 MHz; and bit T(0,0) can be encoded in the duration of a period when the frequency of the SCL clock signal 1208 is 400 KHz. The value 1220 encoded by bits T(0:m) at the output of the register 1218 can be used in combination with the value of C0 stored in the latch 1216 to provide the relationship between the number of selected transitions of the SCL clock signal 1208 and the actual time reference. Once the COF signal 1214 indicating a change in the frequency of the SCL clock signal 1208 becomes logic '1', the value 1220 encoded by bits T(0:m) at the output of the register 1218 can be stored in the latch 1222 and indicated as the value C1. Thus, the value of C1 can represent the period of the SCL clock signal 1208 before the change in the frequency of the SCL clock signal 1208. The latched values of C0 and C1 can provide information about the system time reference between the time synchronization marker and the COF.

[0090] In some embodiments, as Figure 12 shown, when the value 1212 indicating the number of selected transitions of the SCL clock signal 1208 between the time synchronization marker and the change in the frequency of the SCL clock signal 1208 and the encoded period value 1220 representing the frequency of the SCL clock signal 1208 before the frequency change are respectively stored as the values C0 and C1, the next selected transition of the SCL clock signal 1208 can cause the flip - flop 1224 to generate an interrupt (INT) signal 1226, initiating the storage of the values C0 and C1 into a cache or register file. After that, a clear signal 1228 can be pulsed, which can reset the latches 1216 and 1222, i.e., the latched values of C0 and C1 are cleared after being stored into the cache or register file based on the INT signal 1226. Referring back to Figure 2 , the values of C0 and C1 stored in the cache or register file can correspond to the CNT_1 and T1 values stored in the register file 254 of the master device 202 shown in Figure 2 .

[0091] Referring back to Figure 12 , after resetting the latches 1216, 1222, the circuit 1200 can continue to track the number of selected transitions of the SCL clock signal 1208 after the first frequency change of the SCL clock signal 1208 until the next frequency change of the SCL clock signal 1208. Figure 12The latched values C0 and C1 therein can provide information about the reference time between the time synchronization marker and the next frequency change of the SCL clock signal 1208 indicated by the COF signal 1214. In this way, Figure 2 the master device 202 therein can track the reference time based on the SCL clock signal 1208 generated and controlled by the master device 202 starting at the time synchronization marker, and use this reference time information to correlate it with the timestamp of an event detected at the slave device 204 to calculate the actual time of the SCL clock signal 1208 at which the event detected at the slave device 204 occurred.

[0092] Starting from the synchronized time represented by the time synchronization marker, the master device 202 stores the time of the time synchronization marker and counts each selected transition of the SCL clock signal 1208 via the counter 1210. The master device 202 stores in the latches 1222 and 1216 a measure 1220 (i.e., the value C1) representing the frequency of the SCL clock signal 1208 and a count 1212 (i.e., the value C0) of the selected transitions of the SCL clock signal 1208 at which the frequency change of the SCL clock signal 1208 indicated by the COF signal 1214 occurs. After the INT 1226 is initiated by the COF signal 1214, the stored values of C0 and C1 can be transferred from the latches 1216, 1222 to a cache or register file. Referring back to Figure 2 , the values of C0 and C1 transferred to the cache or register file can respectively correspond to the CNT_i and Ti values, which are stored in the register file 254 of the master device 202 whenever the COF signal 252 goes high, providing reference time information. In some embodiments, as discussed, the master device 202 can receive the timestamp 224 of an event 222 detected at the slave device 204 via the SDA bus 206. The master device 202 can use the reference time information stored in the register file 254, i.e., the CNT_i and Ti values, to reconstruct the moment of any selected transition of the SCL clock signal without actually storing the time of each such transition. When the master device 202 receives the SCL clock signal count or the timestamp 224 of the event 222 detected at the slave device 204, the master device 202 correlates the timestamp 224 with the reference time information of the register file 254 at the actual time calculation unit 256 to determine the exact moment 258 of the event 222 relative to the system reference clock.

[0093] Figure 13 FIG. 1300 is a diagram illustrating a method for timestamping changes in an SCL clock signal performed at the master device 202 illustrated in Figure 2 in accordance with an embodiment of the present disclosure, and the method can be performed by the Figure 12 circuit 1200 inFigure 13 As shown, the SCL clock signal 1302 driving the SCL bus can change its frequency, which can be controlled by the master device 202. Additionally, for a certain period of time, the SCL clock signal 1302 can have no transitions, which corresponds to the bus idle condition. Thus, as Figure 13 shown, the SCL clock signal 1302 is not periodic for a specific period during the bus idle condition, and the SCL clock signal 1302 can become periodic again. As discussed above with respect to Figure 12 the circuit 1200 illustrated in Figure 13 shown, the master device 202 can timestamp the last selected transition of the SCL clock signal 1302 before the frequency change of the SCL clock signal 1302. As

[0094] shown, the selected last transition 1304 associated with the previous clock frequency 1306 of the SCL clock signal 1302 can be timestamped relative to a time synchronization marker (not shown). After that, the last selected transition of the SCL clock signal 1302 for the next clock frequency 1308 is also timestamped, i.e., the last high-to-low transition 1310 of the SCL clock signal 1302 before the bus idle condition 1312 is timestamped. The timestamp 1310 together with the timestamp 1304 indicates the time between two successive frequency changes of the SCL clock signal 1302. It should be noted that the bus idle condition 1312 when the SCL clock signal 1302 is not periodic can also be considered a frequency change of the SCL clock signal 1302, because the frequency of the SCL clock signal 1302 actually changes from a non-zero frequency 1308 to zero. Thus, the high-to-low transition 1314 of the SCL clock signal 1302 when transitioning from the bus idle condition 1312 to the new clock frequency 1316 is also timestamped. The timestamp 1314 together with the timestamp 1310 indicates the duration of the bus idle condition 1312. Figure 2 In some embodiments, as discussed,

[0095] Embodiments of the present disclosure relate to a method for converting a system time basis at a master device into a local time basis at a slave device for timestamping and delayed triggering. Referring back to Figure 2 , the master device 202 may be configured to generate a reference SCL clock signal 208 that is also available at one or more slave devices 204. In one or more embodiments, the reference SCL clock signal 208 may have a particular resolution and may be convertible to system time. The master device 202 may then provide a synchronization indication on the SDA bus 206 in the form of Figure 2 and Figure 3 the time synchronization commands 210 and 300 shown in. By providing the synchronization indication, the master device 202 may also set a reference point on the SDA bus 206, which may correspond to a selected transition of the reference SCL clock signal 208 during the time synchronization command. The reference point provided by the master device 202 may be received at each slave device 204 as a time synchronization marker aligned with the selected transition of the reference SCL clock signal 208. In some embodiments, as discussed, in response to receiving the reference point, each slave device 204 may track the amount of time that has elapsed with respect to a local time reference. In response to detecting an event at the slave device 204, an indication of the amount of local time that has elapsed when the event was detected may be loaded into a register and / or may be sent onto the SDA bus 206. Additionally, based on the reference point and the reference SCL clock signal 208 provided by the master device 202, each slave device 204 may generate a trigger signal at a moment directly controlled by the master device 202 and based on a system time basis reference.

[0096] Embodiments of the present disclosure also relate to a method for converting a local time basis at a slave device to a system time basis at a master device for timestamping. One or more slave devices 204 may monitor the occurrence of an event. As discussed, at each slave device 204, the occurrence of an event may be marked on a local time basis, and the timestamp of the event may be locked at the slave device 204. Before starting to monitor the occurrence of an event, each slave device 204 may receive from the master device 202 via the SDA bus 206 a reference point signal in the form of a time synchronization mark. The time synchronization mark may be based on a reference clock (such as the SCL clock signal 208) generated and controlled at the master device 202 and may thus be convertible to a system-wide time basis. At each slave device 204, a delay may be determined between the time when the time synchronization mark is received at that slave device 204 and the time when the occurrence of the event is detected on the local time basis. The delay corresponds to the time of the event in the local time basis and may be reported to the master device 202. In some embodiments, as discussed, the master device 202 may determine the corresponding time of occurrence of each event at the slave device 204 in the system-wide time basis.

[0097] Figure 14 is a flowchart of a method 1400 for timestamping that may be performed at the master device 202 illustrated in Figure 2 as illustrated in.

[0098] Operation of method 1400 may begin with the master device 202 generating 1402 a clock signal (such as the SCL clock signal 208) and a synchronization command (such as the time synchronization command 210).

[0099] The master device 202 transmits 1404 the clock signal and the synchronization command via a communication link (such as Figure 2 the communication link 205 including the SCL line 208 and the SDA line 206 illustrated in).

[0100] The master device 202 receives 1406 timestamp information (e.g., the timestamp 224) via the communication link, the timestamp information indicating the number of selected transitions of the clock signal elapsed between the synchronization command and the moment when an event is detected at the slave device (e.g., the event 222 is detected at the slave device 204).

[0101] More specifically shown as Figure 12 the time tracking circuit 234 of the master device 202, which is the circuit 1200 illustrated in, tracks 1408 the count of the selected transitions of the clock signal between the synchronization command and the frequency change of the clock signal occurring after the synchronization command.

[0102] The actual time calculation unit 256 of the master device 202 determines the time of the event detected at the slave device 1410 based on the timestamp information and the count of the selection transitions of the clock signal.

[0103] Figure 15 is a flowchart of a method 1500 for delayed triggering that can be performed at the slave device 204 illustrated in Figure 2 as illustrated in.

[0104] The operation of method 1500 can begin with the slave device 204 receiving 1502 a synchronization command (e.g., time synchronization command 210) and delay setting information via a communication link carrying a clock signal (e.g., SCL clock signal 208), where the delay setting information can be provided by an SDR command 210 generated by the master device 202 prior to the time synchronization command. In some embodiments, as discussed, the communication link can correspond to communication link 205 including SDA line 206 and SCL line 208.

[0105] Shown in more detail as Figure 10 the time tracking / trigger control circuit 214 of the slave device 202 in circuit 1000 in tracks 1504 the number of selection transitions (e.g., falling edge of the SCL clock signal 208) of the clock signal after the synchronization command.

[0106] In response to the number of selection transitions reaching the delay setting indicated by the delay setting information, the slave device 204 generates 1506 a trigger signal (such as a delayed trigger 238).

[0107] Figure 16 is a flowchart of a method 1600 for delayed triggering that can be performed at the master device 202 illustrated in Figure 2 as illustrated in.

[0108] The operation of method 1600 can begin with the master device 202 transmitting 1602 a clock signal (e.g., SCL clock signal 208) and a synchronization command (e.g., time synchronization command 210) via a communication link. In some embodiments, as discussed, the communication link can correspond to communication link 205 including SDA line 206 and SCL line 208.

[0109] The master device 202 transmits 1604 delay setting information that indicates the number of selected transitions of a clock signal to occur between a synchronization command and the generation of a trigger signal (e.g., delayed trigger 238) at one or more slave devices 204 coupled to a communication link. In some embodiments, as discussed, the delay setting information can include coarse delay setting information and fine delay setting information, which are located in the SDR command 210 generated by the master device 202 prior to the synchronization command.

[0110] The foregoing description of embodiments of the present disclosure has been presented for purposes of illustration; it is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above disclosure, as will be recognized by those of ordinary skill in the relevant art.

[0111] Some portions of this specification describe embodiments of the present disclosure in terms of algorithms and symbolic representations of operations on information. The description and representation of these algorithms are commonly used by those skilled in the data processing arts to effectively convey the substance of their work to others skilled in the art. These operations, when described functionally, computationally, or logically, are understood to be implemented by a computer program, an equivalent circuit, microcode, or the like. Additionally, it has proven convenient at times to refer to these arrangements of operations as modules, without loss of generality. The described operations and their associated modules can be implemented in software, firmware, hardware, or any combination thereof.

[0112] Any of the steps, operations, or processes described herein can be performed or implemented using one or more hardware or software modules, either alone or in combination with other devices. In one embodiment, a software module is implemented using a computer program product that includes a computer-readable medium containing computer program code that can be executed by a computer processor to perform any or all of the described steps, operations, or processes.

[0113] Embodiments of the present disclosure can also relate to an apparatus for performing the operations herein. The apparatus can be specially constructed for the required purposes, and / or it can include a general-purpose computing device selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a non-transitory tangible computer-readable storage medium or any type of medium suitable for storing electronic instructions that can be coupled to a computer system bus. Additionally, any computing system referred to in this specification can include a single processor or can be an architecture employing multiple processor designs for increased computing capabilities.

[0114] Finally, the language used in this specification has been chosen in principle for readability and guidance purposes and may not have been chosen to delimit or circumscribe the technical solution of the present invention. Accordingly, the scope of the present disclosure is not intended to be limited by this detailed description, but rather, is limited by any claims issued based on the application. Thus, the disclosure of the embodiments is intended to be illustrative and not limiting of the scope of the present disclosure, the scope of which is set forth in the appended claims.

Claims

1. A system for low-speed bus triggering, the system comprising: A master device, coupled to a dual-wire communication link, the master device being configured to: Generate a delay setting command with delay setting information, and Generate a time synchronization command to generate a trigger signal; And A slave device, coupled to the dual-wire communication link, the slave device being configured to: Receive, via a first single-wire bus of the dual-wire communication link, the delay setting command with the delay setting information transmitted from the master device, After receiving the delay setting command, receive, via the first single-wire bus of the dual-wire communication link, the time synchronization command transmitted from the master device, After receiving the time synchronization command, track the number of selected transitions of a clock signal, the clock signal being transmitted from the master device via a second single-wire bus of the dual-wire communication link, Generate the trigger signal in response to the number of the selected transitions reaching a delay setting indicated by the delay setting information, and In response to a poll from the master device, transmit, via the first single-wire bus of the dual-wire communication link, data received by the slave device and associated with the trigger signal to the master device.

2. The system according to claim 1, wherein the slave device comprises: A counter circuit having a value that is reset in response to detecting the time synchronization command and incremented at each selected transition of the clock signal; And A comparator circuit for comparing the value of the counter circuit with the delay setting information, the trigger signal being generated based on the comparison.

3. The system according to claim 1, wherein: The delay setting information is first delay setting information; The slave device is configured to: Receive second delay setting information via the communication link; Generate an oscillator signal having a frequency higher than that of the clock signal; Track the number of selected transitions of the oscillator signal that occur after the number of selected transitions of the clock signal reaches the delay setting indicated by the first delay setting information; and Generate the trigger signal in response to the number of selected transitions of the oscillator signal reaching a delay setting indicated by the second delay setting information.

4. The system according to claim 1, wherein the master device is configured to generate the delay setting information indicating the delay of the trigger signal, the delay of the trigger signal being represented as the number of selected transitions of the clock signal between a time synchronization mark of the time synchronization command and the generation of the trigger signal.

5. A slave device, comprising: An interface circuit for coupling to a dual-wire communication link, the interface circuit being configured to: Receive, from a master device via a first single-wire bus of the dual-wire communication link, a delay setting command with delay setting information, and After receiving the delay setting command, receive, from the master device via the first single-wire bus of the dual-wire communication link, a time synchronization command for generating a trigger signal; A control circuit configured to: After receiving the time synchronization command, tracking the number of selected transitions of a clock signal, where the clock signal is carried by a second single-wire bus of the dual-wire communication link, and generating a trigger signal in response to the number of selected transitions reaching a delay setting indicated by the delay setting information; and where the interface circuit is configured to transmit, in response to a poll from the master device, data received by the slave device and associated with the trigger signal to the master device via the first single-wire bus of the dual-wire communication link.

6. The slave device according to claim 5, wherein the control circuit further comprises: a counter circuit having a value that is reset in response to detecting the time synchronization command and incremented at each selected transition of the clock signal; and a comparator circuit for comparing the value of the counter circuit with the delay setting information, the trigger signal being generated based on the comparison.

7. The slave device according to claim 5, wherein the interface circuit is further configured to receive second delay setting information via the communication link, and the control circuit further comprises: an oscillator circuit for generating an oscillator signal having a frequency higher than the frequency of the clock signal; a counter circuit for tracking the number of selected transitions of the oscillator signal that occur after the number of selected transitions of the clock signal reaches the delay setting indicated by the delay setting information; and a comparator circuit for further generating the trigger signal in response to the number of selected transitions of the oscillator signal reaching a delay setting indicated by the second delay setting information.

8. The slave device according to claim 7, wherein the control circuit further comprises: another counter circuit having a value that is reset in response to detecting the time synchronization command and incremented at each selected transition of the clock signal; and another comparator circuit for: comparing the value of the another counter circuit with the delay setting information, and generating an enable signal that activates the oscillator circuit and the counter circuit.

9. The slave device according to claim 8, wherein the second delay setting information indicates a delay of the trigger signal, the delay of the trigger signal being represented as the number of selected transitions of the oscillator signal between the occurrence of the enable signal and the generation of the trigger signal.

10. The slave device according to claim 5, wherein the trigger signal triggers the operation of a transducer associated with the slave device.

11. The slave device according to claim 5, wherein the control circuit generates the trigger signal synchronously with one or more other trigger signals generated by one or more other slave devices.

12. A method for low-speed bus triggering, the method comprising: receiving, by a slave device from a master device via a first single-wire bus of a dual-wire communication link, a delay setting command having delay setting information; After receiving the delay setting command, the slave device receives, via the first single-wire bus of the dual-wire communication link, a time synchronization command from the master device for generating a trigger signal; After receiving the time synchronization command, the slave device tracks the number of selected transitions of a clock signal, where the clock signal is carried by the second single-wire bus of the dual-wire communication link; In response to the number of the selected transitions reaching a delay setting indicated by the delay setting information, the slave device generates the trigger signal; And In response to a poll from the master device, via the first single-wire bus of the dual-wire communication link, the slave device transmits data received by the slave device and associated with the trigger signal to the master device.

13. The method according to claim 12, further comprising: Resetting a value in response to detecting the time synchronization command; Incrementing the value at each selected transition of the clock signal; Comparing the value with the delay setting information; and Generating the trigger signal based on the comparison.

14. The method according to claim 12, further comprising: Where the delay setting information is first delay setting information; Receiving second delay setting information via the communication link; Generating an oscillator signal having a frequency higher than the frequency of the clock signal; Tracking the number of selected transitions of the oscillator signal that occur after the number of selected transitions of the clock signal reaches the delay setting indicated by the first delay setting information; and Also generating the trigger signal in response to the number of selected transitions of the oscillator signal reaching a delay setting indicated by the second delay setting information.

15. The method according to claim 14, further comprising: Resetting a value in response to detecting the time synchronization command; Incrementing the value at each selected transition of the clock signal; Comparing the value with the first delay setting information; Generating an enable signal based on the comparison; Generating an oscillator signal in response to generating the enable signal; And Tracking the number of selected transitions of the oscillator signal in response to generating the enable signal.

16. The method according to claim 15, where the second delay setting information indicates a delay of the trigger signal, and the delay of the trigger signal is represented as the number of selected transitions of the oscillator signal between the occurrence of the enable signal and the generation of the trigger signal.

17. The method according to claim 12, further comprising: Generating the trigger signal synchronously with the generation of one or more other trigger signals.

18. A master device, comprising: An interface circuit for coupling to a dual-wire communication link, the interface circuit configured to: Transmit a delay setting command with delay setting information to a slave device via the first single-wire bus of the dual-wire communication link, Transmit a time synchronization command from the master device to the slave device via the first single-wire bus of the dual-wire communication link to generate a trigger signal, A clock signal is transmitted from the master device to the slave device via a second single-wire bus of the dual-wire communication link, and in response to polling from the master device, data is received from the slave device via the first single-wire bus of the dual-wire communication link, where the data is received by the slave device and is associated with the trigger signal.

19. The master device according to claim 18, wherein the interface circuit is configured to transmit the delay setting command via the communication link before transmitting the time synchronization command.

20. The master device according to claim 18, wherein the delay setting information includes coarse delay setting information and fine delay setting information, the coarse delay setting information indicating a coarse time resolution for generating the trigger signal, and the fine delay setting information indicating a fine time resolution for generating the trigger signal.

21. The master device according to claim 18, wherein: the slave device is a first slave device; the trigger signal is a first trigger signal; the delay setting command is a first delay setting command; the delay setting information is first delay setting information indicating the number of selected transitions of the clock signal to occur between the time synchronization command and the generation of the first trigger signal at the first slave device, and a second delay setting command with second delay setting information is transmitted via the communication link, the second delay setting information indicating the number of selected transitions of the clock signal to occur between the time synchronization command and the generation of a second trigger signal at a second slave device.

22. The master device according to claim 18, further comprising a trigger delay setting circuit configured to generate the delay setting information based on an expected frequency change of the clock signal occurring after the time synchronization command.

23. The master device according to claim 18, further comprising a trigger delay setting circuit configured to generate the delay setting information indicating a delay of the trigger signal, the delay of the trigger signal being represented as the number of selected transitions of the clock signal between the time synchronization mark of the time synchronization command and the generation of the trigger signal.

24. The master device according to claim 18, further comprising an encoder configured to encode the delay setting information within the time synchronization command.

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