A unified compilation method and system for vendor libraries for heterogeneous multi-target platforms

Abstract

The present invention realizes a unified compilation method and system of PLC supplier libraries for heterogeneous multi-platforms, which can be used for unified compilation and generation of PLC supplier libraries for multiple different instruction platforms. The unified compilation method of PLC supplier libraries for heterogeneous multi-platforms is as follows: step 1: write a PLC supplier library program, compile and generate a linked instruction program, combine multiple unlinked library instruction programs in a single platform into a library segment, merge the library segments of multiple platforms to generate a library file with the suffix .SFBL; step 2: write a PLC operation logic program for actual operation, compile and generate unlinked target instructions for a specific target platform, load the .SFBL library file, search for the corresponding library segment of the target platform, link and relocate, and generate a target file running on the specific target platform. The method can provide unified compilation of PLC supplier libraries of multiple different instruction architectures, effectively reducing development and application costs.

Description

Technical Field

[0001] The present invention relates to the field of programming compilation, and in particular to a cross-compilation and unified compilation method for a multi-target heterogeneous system. The present invention provides a unified compilation method and system for a supplier library of a heterogeneous multi-target platform. Background Art

[0002] There are many types of PLCs at present, and the CPU chips used by each product are different according to functional requirements. When users use PLC controllers for programming, the PLC logic configuration software used also generates different target instructions according to different target platforms. Each additional platform requires a separate generation of the corresponding supplier library compilation file, which not only makes the development process lengthy and complicated, but also causes project compatibility issues due to version iteration. Therefore, the PLC logic configuration software of different manufacturers basically only supports their own PLC products. Some manufacturers who use third-party programming software such as CodeSys and OpenPCS also limit the functions and chip selection range of PLC products, or require a very complex secondary development process. The difficulty of developing the PLC logic configuration software supplier library, the long development cycle, and the complex update iteration have greatly restricted the development of domestic PLCs. The domestic industrial control market is heavily dependent on foreign PLC software and hardware products. Summary of the invention

[0003] In response to the above problems, the purpose of this embodiment is to provide a unified compilation method and system for supplier libraries for heterogeneous multi-target platforms to solve the problems of difficulty in developing PLC logic configuration software supplier libraries, long development cycle, and complex update iterations. The present invention can provide a good compatibility solution for the development of PLC programming compilation software, promote the development of domestic PLC programming compilation technology, and improve the quality of PLC logic configuration software.

[0004] A unified compilation method for a supplier library of a heterogeneous multi-target platform, characterized in that the method can be used to uniformly compile and generate PLC supplier libraries of multiple different instruction platforms. The unified compilation method for a PLC supplier library of a heterogeneous multi-platform is:

[0005] Step 1: Generate unlinked library target instruction program: Write the PLC supplier library program, compile and generate unlinked instruction program, load the platform description file, generate unlinked target instruction set library segment files for each platform, and merge the library segments of multiple platforms to generate a library file with the suffix .SFBL;

[0006] Step 2: Link with other programs to generate an executable target program: Write the PLC operation logic program for actual operation, compile and generate unlinked target instructions for a specific target platform, load the .SFBL library file, find the corresponding library segment of the target platform, link and relocate, and generate a target file that runs on a specific target platform.

[0007] This method can provide unified compilation of PLC supplier libraries with different instruction architectures, effectively reducing development and application costs.

[0008] Preferably, step 1 of generating an unlinked library target instruction program includes 6 steps:

[0009] S2-1: Lexical analysis: Analyze the variables, identifiers, and symbols of the supplier library logic program to generate a token stream;

[0010] S2-2: Syntax analysis: Perform syntax analysis based on the results of lexical analysis;

[0011] S2-3: Abstract syntax tree: Generate an abstract syntax tree structure and collect symbol information;

[0012] S2-4: Binary tree chain structure conversion: converting the abstract syntax tree structure into a rule-based intermediate code structure, wherein the rule-based intermediate code structure is a data structure combining a binary tree and a linked list;

[0013] S2-5: Multi-platform target description loading: Load the target platform description file, which adopts rule-based definition, including register description, stack description, byte alignment, parameter and return value description, and relocation method description;

[0014] S2-6: Multi-platform target instruction generation: traverse the intermediate code structure generated by S4, generate the unlinked target instruction set library segment files for each platform according to the platform description file generated by S5, and combine all library segment files to generate .SFBL file.

[0015] Preferably, the specific steps of step 2 linking with other programs to generate an executable target program are as follows:

[0016] S3-1: Compile the PLC running logic program, traverse the location of calling the supplier library, and generate the identification that needs to be relocated and linked;

[0017] S3-2: Load the .SFBL file and obtain the corresponding library segment according to the target platform;

[0018] S3-3: Link the PLC running logic target program and the corresponding library segment to generate a .o instruction file;

[0019] S3-4: Find the call relocation tag;

[0020] S3-5: Modify the offset of the call instruction and generate a .nbp file;

[0021] S3-6: Generate the running program of the target platform and generate a .prg file;

[0022] Preferably, the rule-based intermediate code structure is IRS-RTL, supporting X86, MIPS32, Arach64, SPARC V8, ARMV7M, and the rule description files include MD_RTL_X86.trg, MD_RTL_MIPS32.trg, MD_RTL_MIPS64.trg, MD_RTL_aarch64.trg, MD_RTL_SPARCV8.trg, MD_RTL_ARMV7M.trg;

[0023] Preferably, the unified compilation method of supplier libraries for heterogeneous multi-target platforms is implemented as a PLC logic configuration software, which can provide ST language, LD language, FBD language, IL language, and SFC language programming environment that complies with the IEC61131-3 standard, and provide a supplier library program editor, a PLC running logic program editor, a compiler, a linker, a debugger, a communication, a library manager, and a simulator.

[0024] Preferably, the PLC logic configuration software can generate target instruction programs for different platforms for operation, and is connected to the simulator and the actual PLC device through communication for engineering download and operation.

[0025] The embodiments of the present invention include the following advantages:

[0026] A PLC logic configuration software implemented by the supplier library unified compilation method for heterogeneous multi-target platforms can flexibly support PLC target platforms with different architectures, integrate supplier library development and PLC logic configuration programming, and support arbitrary platform expansion. PLC hardware manufacturers can choose suitable chips according to cost or functional requirements without the limitation of logic programming configuration software, which solves the problems of difficult development, long development cycle and complex update and iteration of PLC logic configuration software supplier library, and can effectively promote the development of domestic PLC and solve the current situation that the domestic industrial control market is heavily dependent on foreign PLC software and hardware products. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of the present application, and do not constitute a limitation of the present invention. In the drawings:

[0028] Figure 1 It is a flow chart of multi-target platform vendor library file generation and linking;

[0029] Figure 2 It is a PLC-oriented supplier library generation system block diagram;

[0030] Figure 3 It is a multi-platform vendor library compilation that generates an unlinked target instruction flow chart;

[0031] Figure 4 It is to link the target instructions and PLC logic program together to compile and generate a flow chart;

[0032] Figure 5 Rule-based intermediate code generation graph; DETAILED DESCRIPTION

[0033] In order to more clearly express the purpose, technical solutions and advantages of the present invention, the technical solutions in the embodiments of the present invention are clearly and completely described below in combination with the drawings in the implementation of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0034] Figure 1 The embodiment of the present invention provides a schematic diagram of a multi-target platform supplier library file generation and linking flow chart, see Figure 1 , the method comprising:

[0035] Step 1: Generate unlinked library target instruction program: Write the PLC supplier library program, compile and generate it into a linked instruction program, combine multiple unlinked library instruction programs in a single platform into a library segment, and merge the library segments of multiple platforms to generate a library file with the suffix .SFBL;

[0036] Step 2: Link with other programs to generate an executable target program: Write the PLC operation logic program for actual operation, compile and generate unlinked target instructions for a specific target platform, load the .SFBL library file, find the corresponding library segment of the target platform, link and relocate, and generate a target file that runs on a specific target platform.

[0037] This method can provide unified compilation of PLC supplier libraries with different instruction architectures, effectively reducing development and application costs.

[0038] Furthermore, the method is implemented as a PLC logic configuration software, which provides PLC supplier library programming and compilation functions, PLC logic configuration functions, communication and online, simulation and other functions to verify the feasibility of the method.

[0039] Further, the composition of the PLC logic configuration software is as follows: Figure 2As shown, it includes ST language, LD language, FBD language, IL language, and SFC language programming environments, and provides supplier library program editor, PLC operation logic program editor, compiler, linker, debugger, communication, library manager, and simulator.

[0040] Furthermore, the PLC logic configuration software can generate target instruction programs for different platforms for operation, and is connected to the simulator and the actual PLC device through communication for engineering download and operation.

[0041] Further, the step 1 of generating the unlinked library target instruction program includes 6 steps, such as Figure 3 As shown:

[0042] S2-1: Lexical analysis: Analyze the variables, identifiers, and symbols of the supplier library logic program to generate a token stream;

[0043] S2-2: Syntax analysis: Perform syntax analysis based on the results of lexical analysis;

[0044] S2-3: Abstract syntax tree: Generate an abstract syntax tree structure and collect symbol information;

[0045] S2-4: Binary tree chain structure conversion: converting the abstract syntax tree structure into a rule-based intermediate code structure, wherein the rule-based intermediate code structure is a data structure combining a binary tree and a linked list;

[0046] S2-5: Multi-platform target description loading: Load the target platform description file, which adopts rule-based definition, including register description, stack description, byte alignment, parameter and return value description, and relocation method description;

[0047] S2-6: Multi-platform target instruction generation: traverse the intermediate code structure generated by S4, generate the unlinked target instruction set library segment files for each platform according to the platform description file generated by S5, and combine all library segment files to generate .SFBL file.

[0048] Furthermore, the S2-1 uses a lex tool to perform lexical analysis, and the lexical analyzer is generated using the C++ interface of win_flex.

[0049] Furthermore, in the step S2-2, the yacc tool is used, and the syntax analyzer is generated using the C++ interface of win_bison.

[0050] Furthermore, the S2-3 step generates an abstract syntax tree, and the abstract syntax tree nodes mainly include statements and expressions. The abstract syntax tree nodes (AstNode) include two types of nodes: StmtNode and ExprNode. AstNode provides a Traverse interface for traversing the tree. When traversing, AstNodeVisitor is used for processing, where AstNodeVisitor can be a syntax checker or an intermediate code generator. Semantic checking refers to checking whether the abstract syntax tree that conforms to the syntax specification conforms to the semantic specification. Semantic checking is performed by traversing the abstract syntax tree formed after the syntax analysis is completed.

[0051] Furthermore, in the step S2-4, the intermediate code generation is also completed by traversing the abstract syntax tree.

[0052] Furthermore, in the step S2-5, the description of each platform adopts a file with a .trg suffix.

[0053] Furthermore, the specific steps of linking the step 2 with other programs to generate an executable target program include 6 steps, such as Figure 4 As shown:

[0054] S3-1: Compile the PLC running logic program, traverse the location of calling the supplier library, and generate the identification that needs to be relocated and linked;

[0055] S3-2: Load the .SFBL file and obtain the corresponding library segment according to the target platform;

[0056] S3-3: Link the PLC running logic target program and the corresponding library segment to generate a .o instruction file;

[0057] S3-4: Find the call relocation tag;

[0058] S3-5: Modify the offset of the call instruction and generate a .nbp file;

[0059] S3-6: Generate the running program of the target platform and generate a .prg file;

[0060] Furthermore, in S3-1, when using a supplier library, you must first add it to the project. When adding, the specified library file will be copied to the Lib folder, and the library information will be registered in the library manager. First check whether the file to be added is legal (CRC). For legal files: If there is a file with a duplicate library name, check the version. If the version is inconsistent, prompt the user to choose: add, replace or cancel; if the version is consistent and it is not the same file, prompt the user to choose: replace or cancel; if it is the same file, return directly and position the cursor on the original library. If the library name is not duplicated, add it directly.

[0061] Furthermore, when the .SFBL file is loaded in step S3-2, the integrity check of the file is performed, including verifying whether the file exists (under the project path), whether the GUID of the file is consistent with the registered information, and whether the CRC of the file is consistent with the registered information. If the correct file cannot be found under the project path, the installation path is searched. If it can be found under the installation path, the corresponding library under the installation path is copied to the project path. If it cannot be found under the installation path, the user is prompted and the corresponding library under the reference library list is set to disable state.

[0062] Further, in step S3-3, the PLC logic program is loaded and compiled to output the target program segment, including the defined symbols and undefined symbols of this module. The linker will create a global symbol table (Global Symbol Table), which contains the symbols defined by all modules, and connects the undefined symbols of each module to the defined symbols. After the global symbol table is generated, it is necessary to update the information related to each input file and symbol, which currently includes: relocation information, a relocation item includes the index of the symbol used during relocation in the local symbol table (i.e., the symbol table in the input file). After the global symbol table is generated, this item needs to be updated to the index of the symbol in the global symbol table.

[0063] Further, in step S3-4, the relocation information symbol table generated in S3-3 is searched, and the linker needs to complete the relocation of each segment

[0064] Furthermore, in step S3-5, in the input file, the relocation information of the segment is together with the core data of the segment. When merging similar segments, only the core data of the segment is merged, and the relocation information of the segment is saved separately. After the segment is merged into the segment of the output file, its relocation information is used to relocate the segment data in the output file.

[0065] Furthermore, in step S3-6, the linker merges the segments into one and then performs relocation and generates segment table entries. This process is the general processing process of the linker. This segment in the output file is called a common section. In addition to the general processing process mentioned above, some segments will have some processing of specific information of this segment. Different segments may have different problems and methods to be processed. For example, after the general processing process of the PROGRAM segment in the PRG file is completed, the CRC32 and Machine Code length of the PROGRAM segment and other information need to be backfilled. These segments are called special sections. Each linking process of the linker only generates one output file. The name of the output file is specified by the linker controller script.

[0066] Furthermore, if Figure 5 As shown, the rule-based intermediate code structure is IRS-RTL, which supports X86, MIPS32, Arach64, SPARC V8, and ARMV7M, and the rule description files include MD_RTL_X86.trg, MD_RTL_MIPS32.trg, MD_RTL_MIPS64.trg, MD_RTL_aarch64.trg, MD_RTL_SPARCV8.trg, and MD_RTL_ARMV7M.trg;

[0067] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

Claims

1. A unified compilation method for PLC vendor libraries for heterogeneous multi-platforms, characterized in that: The method can be used for unified compilation and generation of PLC vendor libraries for multiple different instruction platforms. The unified compilation method of PLC vendor libraries for heterogeneous multi-platforms is as follows: Step 1: Generate an unlinked library target instruction program: write a PLC vendor library program, compile and generate an unlinked instruction program, load a platform description file, generate an unlinked target instruction set library segment file for each platform, merge the library segments of multiple platforms to generate a library file with the suffix .SFBL; wherein, generating an unlinked library target instruction program includes 6 steps: S1-1: Lexical analysis: Analyze the variables, identifiers, and symbols of the supplier library logic program and generate a token stream; S1-2: Syntax analysis: Perform syntax analysis based on the results of lexical analysis; S1-3: Abstract syntax tree: Generate an abstract syntax tree structure and collect symbol information; S1-4: Binary tree chain structure conversion: converting the abstract syntax tree structure into a rule-based intermediate code structure, wherein the rule-based intermediate code structure is a data structure combining a binary tree and a linked list; S1-5: Multi-platform target description loading: Load the target platform description file, which adopts rule-based definition, including register description, stack description, byte alignment, parameter and return value description, and relocation method description; S1-6: Multi-platform target instruction generation: traverse the intermediate code structure generated by S4, generate the unlinked target instruction set library segment files of each platform according to the platform description file generated by S5, and combine all the library segment files to generate the .SFBL file; Step 2: Link with other programs to generate an executable target program: Write the PLC operation logic program for actual operation, compile and generate unlinked target instructions for a specific target platform, load the .SFBL library file, find the corresponding library segment of the target platform, link and relocate, and generate a target file that runs on a specific target platform. This method can provide unified compilation of PLC supplier libraries with multiple different instruction architectures, effectively reducing development and application costs.

2. According to the method of claim 1, the specific steps of step 2 linking with other programs to generate an executable target program are as follows: S2-1: Compile the PLC running logic program, traverse the location of calling the supplier library, and generate the identification that needs to be relocated and linked; S2-2: Load the .SFBL file and obtain the corresponding library segment according to the target platform; S2-3: Link the PLC running logic target program and the corresponding library segment to generate a .o instruction file; S2-4: Find the call relocation tag; S2-5: Modify the offset of the call instruction and generate a .nbp file; S2-6: Generate the running program for the target platform and generate a .prg file.

3. According to the method of claim 1, the rule-based intermediate code structure is IRS-RTL, supporting X86, MIPS32, Arach64, SPARC V8, ARMV7M, and the rule description files include MD_RTL_X86.trg, MD_RTL_MIPS32.trg, MD_RTL_ MIPS64.trg, MD_RTL_ aarch64.trg, MD_RTL_ SPARCV8.trg, MD_RTL_ARMV7M.trg.

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