Scan driver and display device

Abstract

A scan driver and a display device are provided, the scan driver comprising: a plurality of stages, each stage comprising: a logic circuit configured to transmit an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal in response to a voltage of the first node after bootstrapping, the carry signal being provided as an input signal for a next stage; and a mask controller configured to receive a mask signal and a carry signal, and to output the mask signal as a scan signal provided to a pixel row corresponding to each stage in response to the carry signal.

Description

Technical Field

[0001] An aspect of some example embodiments of the inventive concepts relates to a display device. Background Art

[0002] Reduction in power consumption may be beneficial in display devices employed in portable devices such as smartphones, tablet computers, etc. To reduce power consumption of a display device, a low-frequency driving technique may be utilized that drives or refreshes a display panel at a frequency lower than a normal driving frequency.

[0003] However, in a display device to which the low-frequency driving technology is applied, when a still image is not displayed in the entire area of ​​the display panel, or when a still image is displayed only in a partial area of ​​the display panel, the entire area of ​​the display panel is driven at a normal driving frequency. Therefore, in this case, the low-frequency driving is not performed, and the power consumption is not reduced.

[0004] The above information disclosed in this background technology section is only for enhancement of understanding of the background technology and therefore the information discussed in this background technology section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some example embodiments of the inventive concepts relate to a display device, and, for example, to a display device that performs multi-frequency driving (MFD).

[0006] Some example embodiments provide a scan driver capable of providing a plurality of scan signals to a plurality of pixel rows at different driving frequencies.

[0007] Some example embodiments provide a display device including a scan driver.

[0008] According to some example embodiments, the scan driver includes a plurality of stages. Each stage includes a logic circuit, a carry output unit, and a mask control unit, wherein the logic circuit is configured to transmit an input signal to a first node in response to a first clock signal and to bootstrap the first node in response to a second clock signal, the carry output unit is configured to output the second clock signal as a carry signal in response to a voltage of the first node after bootstrapping, the carry signal is provided as an input signal for a next stage, and the mask control unit is configured to receive the mask signal and the carry signal, and output the mask signal as a scan signal provided to a pixel row corresponding to each stage in response to the carry signal.

[0009] According to some example embodiments, the mask signal may have an on level or an off level according to a driving frequency of a panel area including a pixel row in a first effective period of the carry signal. The mask control unit may output a scan signal having an on level when the mask signal has an on level, and may output a scan signal having an off level when the mask signal has an off level.

[0010] According to some example embodiments, a second effective period of the mask signal, in which the mask signal has an on level, may at least partially overlap with a first effective period of the carry signal.

[0011] According to some example embodiments, an end time point of the second effective period of the mask signal may be before an end time point of the first effective period of the carry signal.

[0012] According to some example embodiments, the mask control unit may include a first transistor including a gate receiving the carry signal, a first terminal coupled to a scan output node at which the scan signal is output, and a second terminal receiving the mask signal.

[0013] According to some example embodiments, the mask control unit may include a second transistor including a gate coupled to the second node, a first terminal receiving a gate-off voltage, and a second terminal coupled to the scan output node.

[0014] According to some example embodiments, the carry output circuit may include a third transistor and a fourth transistor, the third transistor including a gate coupled to the first node, a first terminal coupled to a carry output node at which a carry signal is output, and a second terminal receiving a second clock signal, and the fourth transistor including a gate coupled to the second node, a first terminal receiving a gate-off voltage, and a second terminal coupled to the carry output node.

[0015] According to some example embodiments, a logic circuit may include an input unit, a stress relaxation unit, a bootstrap unit, a holding unit, and a stabilization unit, the input unit being configured to transmit the input signal to a third node in response to a first clock signal, the stress relaxation unit being located between the first node and the third node and being configured to transmit the input signal from the third node to the first node so that a voltage of the first node is changed to a first conduction level, the bootstrap unit being configured to change the voltage of the first node from the first conduction level to a second conduction level by bootstrapping the first node based on a second clock signal, the second conduction level having an absolute value greater than an absolute value of the first conduction level, the holding unit being configured to hold the second node at an off level while outputting a carry signal, and the stabilization unit being configured to periodically apply a gate-on voltage to the second node in response to the second clock signal after outputting the carry signal, and to periodically apply a gate-off voltage to the third node in response to the first clock signal.

[0016] According to some example embodiments, the input unit may include a fifth transistor including a gate receiving the first clock signal, a first terminal receiving the input signal, and a second terminal coupled to the third node.

[0017] According to some example embodiments, the stress relaxation unit may include a sixth transistor including a gate receiving a gate-on voltage, a first terminal coupled to the third node, and a second terminal coupled to the first node.

[0018] According to some example embodiments, the bootstrap unit may include a first capacitor including a first electrode coupled to a carry output node at which a carry signal is output and a second electrode coupled to the first node.

[0019] According to some example embodiments, the holding unit may include a seventh transistor including a gate coupled to the third node, a first terminal coupled to the second node, and a second terminal receiving the first clock signal.

[0020] According to some example embodiments, the stabilization unit may include an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor, the eighth transistor including a gate receiving a first clock signal, a first terminal coupled to a second node, and a second terminal receiving a gate-on voltage, the ninth transistor including a gate coupled to the second node, a first terminal receiving a gate-off voltage, and a second terminal, the tenth transistor including a gate receiving a second clock signal, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to a third node, and the second capacitor including a first electrode receiving the gate-off voltage and a second electrode coupled to the second node.

[0021] According to some example embodiments, the scan driver includes a plurality of stages. Each stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a second capacitor, the first transistor including a gate coupled to a carry output node, a first terminal coupled to the scan output node, and a second terminal receiving a mask signal, the second transistor including a gate coupled to the second node, a first terminal receiving a gate-off voltage, and a second terminal coupled to the scan output node, the third transistor including a gate coupled to the first node, a first terminal coupled to the carry output node, and a second terminal receiving a second clock signal, the fourth transistor including a gate coupled to the second node, a first terminal receiving a gate-off voltage, and a second terminal coupled to the carry output node, the fifth transistor including a gate receiving the first clock signal, a first terminal receiving an input signal, and a second terminal coupled to the third transistor. a second terminal of the node, the sixth transistor includes a gate receiving a gate-on voltage, a first terminal coupled to the third node, and a second terminal coupled to the first node, the first capacitor includes a first electrode coupled to the carry output node and a second electrode coupled to the first node, the seventh transistor includes a gate coupled to the third node, a first terminal coupled to the second node, and a second terminal receiving a first clock signal, the eighth transistor includes a gate receiving the first clock signal, a first terminal coupled to the second node, and a second terminal receiving the gate-on voltage, the ninth transistor includes a gate coupled to the second node, a first terminal receiving a gate-off voltage, and a second terminal, the tenth transistor includes a gate receiving the second clock signal, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the third node, and the second capacitor includes a first electrode receiving the gate-off voltage and a second electrode coupled to the second node.

[0022] According to some example embodiments, the first transistor may output the mask signal as a scan signal provided to the pixel row corresponding to each stage at the scan-output node in response to a carry signal output at the carry-output node.

[0023] According to some example embodiments, the mask signal may have an on level or an off level according to a driving frequency of a panel area including a pixel row in a first effective period of the carry signal. The first transistor may output a scan signal having an on level when the mask signal has an on level, and may output a scan signal having an off level when the mask signal has an off level.

[0024] According to some example embodiments, a display device includes a display panel, a data driver, a scan driver, and a controller, the display panel includes a plurality of pixel rows, the data driver is configured to provide a data signal to each of the plurality of pixel rows, the scan driver is configured to provide a plurality of scan signals to the plurality of pixel rows, respectively, and the controller is configured to control the data driver and the scan driver. The scan driver includes a plurality of stages. Each stage includes a logic circuit, a carry output unit, and a mask control unit, the logic circuit is configured to transmit an input signal to a first node in response to a first clock signal, and to bootstrap the first node in response to a second clock signal, the carry output unit is configured to output the second clock signal as a carry signal in response to a voltage of the first node after bootstrapping, the carry signal is provided as an input signal for a next stage, and the mask control unit is configured to receive a mask signal and a carry signal, and output a mask signal as a scan signal provided to a pixel row corresponding to each stage among the plurality of pixel rows in response to the carry signal.

[0025] According to some example embodiments, the controller may include a still image detection block, a driving frequency decision block, and a scan driver control block, wherein the still image detection block is configured to divide the input image data into a plurality of panel area data for a plurality of panel areas each including at least one pixel row among the plurality of pixel rows, and is configured to determine whether each of the plurality of panel area data represents a still image, the driving frequency decision block is configured to determine a plurality of driving frequencies for the plurality of panel areas based on whether each of the plurality of panel area data represents a still image, and the scan driver control block is configured to generate a masking signal based on the plurality of driving frequencies for the plurality of panel areas.

[0026] According to some example embodiments, the driving frequency decision block may determine a first driving frequency for a first panel area among the plurality of driving frequencies as a normal driving frequency when first panel area data for a first panel area among the plurality of panel area data represents a moving image, and may determine a second driving frequency for a second panel area among the plurality of driving frequencies as a low driving frequency lower than the normal driving frequency when second panel area data for a second panel area among the plurality of panel area data represents a still image. In order to output a first scanning signal among the plurality of scanning signals to a first pixel row included in a first panel area driven at the normal driving frequency among the plurality of pixel rows in all frame periods of the plurality of frame periods, the scanning driver control block may generate a masking signal having an on level in all valid periods of a carry signal generated by a first stage among the plurality of stages coupled to the first pixel row. In order to output a second scan signal among the multiple scan signals to a second pixel row among the multiple pixel rows included in a second panel area driven at a low driving frequency in a portion of the multiple frame periods, the scan driver control block can generate a mask signal having an on-level in a portion of an effective period of a carry signal generated by a second stage among the multiple stages coupled to the second pixel row and having an off-level in a remaining portion of the effective period of the carry signal generated by the second stage.

[0027] According to some example embodiments, the plurality of stages may include odd-numbered stages coupled in series with each other and even-numbered stages coupled in series with each other, the odd-numbered stages being configured to provide corresponding scan signals among the plurality of scan signals to odd-numbered pixel rows among the plurality of pixel rows, and the even-numbered stages being configured to provide corresponding scan signals among the plurality of scan signals to even-numbered pixel rows among the plurality of pixel rows.

[0028] As described above, in the scan driver and the display device according to some example embodiments, each stage may include a mask control unit that outputs a mask signal as a scan signal provided to a corresponding pixel row. Therefore, the scan driver according to some example embodiments may provide a plurality of scan signals to a plurality of pixel rows at different driving frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 is a circuit diagram illustrating each stage included in a scan driver according to some example embodiments.

[0031] Figure 2 Is used to describe Figure 1A timing diagram of an example of the operation of the stage.

[0032] Figures 3 to 7 Is used to describe Figure 1 A circuit diagram of an example of the operation of the stage.

[0033] Figure 8 is a block diagram illustrating a display device including a scan driver according to some example embodiments.

[0034] Fig. 9 is a circuit diagram illustrating an example of a pixel included in a display device according to some example embodiments.

[0035] Fig.10 is a block diagram illustrating an example of a scan driver included in a display device according to some example embodiments.

[0036] Fig.11 is a diagram illustrating an example of a display panel including a plurality of panel areas driven at different driving frequencies in a display device according to some example embodiments.

[0037] Fig.12 Is used to describe Fig.11 FIG. 1 is a timing diagram of an example of the operation of a scan driver providing a scan signal to a display panel.

[0038] Fig.13 It is used to describe the scanning driver in the first frame period Fig.11 FIG. 1 is a diagram showing an example of an operation of providing a scan signal to a display panel, Fig.14 It is used to describe the scanning driver in the second frame period Fig.11 FIG. 1 is a diagram of an example of an operation of providing a scan signal to a display panel.

[0039] Fig.15 is a block diagram illustrating another example of a scan driver included in a display device according to some example embodiments.

[0040] Fig.16 An electronic device including a display device according to some example embodiments. DETAILED DESCRIPTION

[0041] Hereinafter, aspects of some example embodiments of the inventive concept will be explained in more detail with reference to the accompanying drawings.

[0042] Figure 1 is a circuit diagram illustrating each stage included in a scan driver according to some example embodiments.

[0043] Reference Figure 1, a scan driver according to some example embodiments may include a plurality of stages, and each stage 100 may include a logic circuit 110, a carry output unit (or carry output or carry output circuit) 120, and a mask control unit (or mask controller or mask control circuit) 130. The plurality of stages may receive an input signal SIN, a first clock signal CLK1, a second clock signal CLK2, and a mask signal MS, may sequentially generate a plurality of carry signals CR based on the input signal SIN, the first clock signal CLK1, and the second clock signal CLK2, and selectively output corresponding scan signals SS according to the mask signal MS.

[0044] The logic circuit 110 may transmit the input signal SIN to the first node NQ in response to the first clock signal CLK1, and may bootstrap the first node NQ in response to the second clock signal CLK2. In some example embodiments, the first stage of the plurality of stages may receive the scan start signal FLM as the input signal SIN, and each of the remaining stages may receive the carry signal PCR of the previous stage as the input signal SIN. In addition, according to some example embodiments, Figure 1 As shown in , the logic circuit 110 of each odd-numbered stage in the plurality of stages may transmit the input signal SIN to the first node NQ in response to the first clock signal CLK1, and may bootstrap the first node NQ in response to the second clock signal CLK2. In addition, the logic circuit 110 of each even-numbered stage in the plurality of stages may transmit the input signal SIN to the first node NQ in response to the second clock signal CLK2, and may bootstrap the first node NQ in response to the first clock signal CLK1.

[0045] According to some example embodiments, Figure 1 As shown in the figure, the logic circuit 110 may include an input unit (or input or input circuit) 140, a stress relaxation unit (or stress relaxer or stress relaxation circuit) 150, a bootstrap unit (or bootstrap or bootstrap circuit) 160, a holding unit (or retainer or holding circuit) 170 and a stabilization unit (or stabilizer or stabilization circuit) 180.

[0046] The input unit 140 may transmit the input signal SIN to the third node NQ' in response to the first clock signal CLK1. In some example embodiments, the stress relaxation unit 150 may be located at the Q node, and thus the Q node may be divided into a first node NQ and a third node NQ' by the stress relaxation unit 150. Therefore, the stress relaxation unit 150 may be located between the first node NQ and the third node NQ' (e.g., such that when current passes through the stress relaxation unit 150, the first node NQ and the third node NQ' are electrically connected, e.g., to form a single node). The input unit 140 may be coupled to the third node NQ'. In some example embodiments, the input unit 140 may include a fifth transistor T5, the fifth transistor T5 including a gate receiving the first clock signal CLK1, a first terminal receiving the input signal SIN, and a second terminal coupled to the third node NQ'. In addition, in some example embodiments, as Figure 1 As shown in , the fifth transistor T5 may be implemented with a double transistor including two transistors connected in series, but is not limited to being implemented with a double transistor.

[0047] The stress relaxation unit 150 may be located between the first node NQ and the third node NQ', and may transmit the input signal SIN from the third node NQ' to the first node NQ. The voltage of the first node NQ may be changed to a first conduction level by the input signal SIN transmitted to the first node NQ. In some example embodiments, the stress relaxation unit 150 may include a sixth transistor T6 including a gate receiving a gate-on voltage VGL (e.g., a low gate voltage), a first terminal coupled to the third node NQ', and a second terminal coupled to the first node NQ.

[0048] The bootstrap unit 160 may change the voltage of the first node NQ from a first conduction level to a second conduction level by bootstrapping the first node NQ based on the second clock signal CLK2. The second conduction level may have an absolute value greater than the absolute value of the first conduction level. In some example embodiments, the first conduction level may be a first low level, and the second conduction level may be a second low level lower than the first low level. In addition, the voltage level difference between the first conduction level (e.g., the first low level) and the second conduction level (e.g., the second low level) may correspond to, but is not limited to, the voltage level difference between the cut-off level (e.g., the high level) and the first conduction level (e.g., the first low level). In some example embodiments, the bootstrap unit 160 may include a first capacitor C1, the first capacitor C1 including a first electrode coupled to a carry output node NCO at which a carry signal CR is output and a second electrode coupled to the first node NQ.

[0049] The holding unit 170 may hold the second node NQB at a cut-off level (e.g., a high level) while outputting the carry signal CR. In some example embodiments, the holding unit 170 may include a seventh transistor T7 including a gate coupled to the third node NQ', a first terminal coupled to the second node NQB, and a second terminal receiving the first clock signal CLK1.

[0050] After outputting the carry signal CR, the stabilization unit 180 may periodically apply the gate-on voltage VGL to the second node NQB in response to the second clock signal CLK2, and periodically apply the gate-off voltage VGH (e.g., a high gate voltage) to the third node NQ' in response to the first clock signal CLK1. The gate-off voltage VGH applied to the third node NQ' may be transmitted to the first node NQ via the sixth transistor T6, and thus the gate-off voltage VGH may also be periodically applied to the first node NQ.

[0051] In some example embodiments, the stabilization unit 180 may include an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a second capacitor C2, the eighth transistor T8 including a gate receiving the first clock signal CLK1, a first terminal coupled to the second node NQB, and a second terminal receiving the gate-on voltage VGL, the ninth transistor T9 including a gate coupled to the second node NQB, a first terminal receiving the gate-off voltage VGH, and a second terminal, the tenth transistor T10 including a gate receiving the second clock signal CLK2, a first terminal coupled to the second terminal of the ninth transistor T9, and a second terminal coupled to the third node NQ', and the second capacitor C2 including a first electrode receiving the gate-off voltage VGH and a second electrode coupled to the second node NQB.

[0052] The carry output unit 120 may output the second clock signal CLK2 as a carry signal CR in response to the voltage of the first node NQ after bootstrapping or the voltage of the first node NQ having the second conduction level, and the carry signal CR is provided as an input signal SIN for the next stage. In some example embodiments, the carry output unit 120 may include a third transistor T3 and a fourth transistor T4, the third transistor T3 including a gate coupled to the first node NQ, a first terminal coupled to a carry output node NCO at which the carry signal CR is output, and a second terminal receiving the second clock signal CLK2, and the fourth transistor T4 including a gate coupled to the second node NQB, a first terminal receiving a gate-off voltage VGH, and a second terminal coupled to the carry output node NCO.

[0053] The mask control unit 130 may receive the mask signal MS and the carry signal CR, and may output the mask signal MS as the scan signal SS provided to the pixel row corresponding to each stage 100 in response to the carry signal CR. In some example embodiments, the mask control unit 130 may include a first transistor T1 including a gate coupled to a carry output node NCO at which the carry signal CR is output, a first terminal coupled to a scan output node NSO at which the scan signal SS is output, and a second terminal receiving the mask signal MS, and a second transistor T2 including a gate coupled to a second node NQB, a first terminal receiving a gate-off voltage VGH, and a second terminal coupled to the scan output node NSO.

[0054] In some example embodiments, the scan driver may be included in a display device that performs a multi-frequency drive (MFD) that drives a plurality of panel regions each including at least one pixel row at a plurality of driving frequencies. The controller of the display device may provide a mask signal MS having an on level (e.g., a first on level) or an off level to each stage 100 according to the driving frequency of the panel region including the pixel row in the effective period of the carry signal CR. In addition, the mask control unit 130 may output a scan signal SS having an on level when the mask signal MS has an on level. In addition, the mask control unit 130 may output a scan signal SS having an off level when the mask signal MS has an off level, or may not output a scan signal SS having an on level. That is, each stage 100 may selectively output a scan signal SS (a scan signal SS having an on level) according to the mask signal MS in the effective period of the carry signal CR.

[0055] In the scan driver according to some example embodiments, each stage 100 may output the mask signal MS as the scan signal SS in response to the carry signal CR. Therefore, the plurality of stages 100 of the scan driver may sequentially generate a plurality of carry signals CR, and may selectively output the corresponding scan signals SS according to the mask signal MS in the effective periods of the plurality of carry signals CR. Therefore, the scan driver according to some example embodiments may provide the plurality of scan signals SS to the plurality of pixel rows at different driving frequencies.

[0056] In the following, reference will be made to Figures 1 to 7 An example of the operation of stage 100 is described in more detail.

[0057] Figure 2 Is used to describe Figure 1 A timing diagram of an example of the operation of the stage, Figures 3 to 7 Is used to describe Figure 1 A circuit diagram of an example of the operation of the stage.

[0058] Reference Figure 1 and Figure 2 , each stage 100 may receive an input signal SIN as well as a first clock signal CLK1, a second clock signal CLK2, and a mask signal MS. For a first stage among a plurality of stages included in the scan driver, the input signal SIN may be a scan start signal FLM, and for the remaining stages among the plurality of stages, the input signal SIN may be a carry signal PCR of a previous stage. In addition, the first clock signal CLK1 and the second clock signal CLK2 may have different phases (e.g., opposite phases).

[0059] The mask signal MS may have an on level 210 (e.g., a first low level L) or an off level 220 (e.g., a high level H) in the first effective period AP1 of the carry signal CR according to the driving frequency of the panel area including the pixel row corresponding to each stage 100. For example, in the case where the driving frequency of the panel area is a normal driving frequency (e.g., about 60 Hz or about 120 Hz), the mask signal MS may have the on level 210 in all first effective periods AP1 in a plurality of frame periods.

[0060] In another example, in the case where the driving frequency of the panel area is a low driving frequency lower than the normal driving frequency, the mask signal MS may have an on level 210 in a portion of the first effective period AP1 in the plurality of frame periods, and may have an off level 220 in the remaining portion of the first effective period AP1 in the plurality of frame periods. In addition, in some example embodiments, for each of the first clock signal CLK1 and the second clock signal CLK2, as Figure 2 As shown in , the effective period (or on-period) can be shorter than the ineffective period (or off-period).

[0061] For example, the duty cycle of each of the first clock signal CLK1 and the second clock signal CLK2 may be, but is not limited to, about 20% to about 40%. In other example embodiments, the active period of each of the first clock signal CLK1 and the second clock signal CLK2 may be longer than or equal to the inactive period of each of the first clock signal CLK1 and the second clock signal CLK2. Figures 1 to 7 , an example is shown in which the first transistor T1 to the tenth transistor T10 are PMOS transistors, the first on-level is a first low level L, the second on-level is a second low level 2L, the off-level is a high level H, the gate on-voltage is a low gate voltage VGL, and the gate off-voltage is a high gate voltage VGH.

[0062] In the period from the first time point TP1 to the second time point TP2, the input signal SIN having the first low level L may be applied, and the first clock signal CLK1 having the first low level L may be applied. In this case, Figure 3 As shown in , the fifth transistor T5 may be turned on in response to the first clock signal CLK1 having the first low level L, and the sixth transistor T6 may be turned on in response to the low gate voltage VGL having the first low level L.

[0063] The input signal SIN may be transmitted to the third node NQ′ via the turned-on fifth transistor T5, and thus the voltage V_NQ′ of the third node NQ′ may be changed from the high level H to the first low level L. In addition, the input signal SIN at the third node NQ′ may be transmitted to the first node NQ via the turned-on sixth transistor T6, and thus the voltage V_NQ of the first node NQ may be changed from the high level H to the first low level L.

[0064] The first clock signal CLK1 may be changed from the first low level L to the high level H at the second time point TP2, and the first clock signal CLK1 having the high level H may be applied in a period from the second time point TP2 to the third time point TP3. Figure 4 As shown in , the seventh transistor T7 may be turned on in response to the voltage V_NQ' of the third node NQ' having the first low level L. The first clock signal CLK1 having the high level H may be transmitted to the second node NQB via the turned-on seventh transistor T7, and the voltage V_NQB of the second node NQB may be changed from the first low level L to the high level H.

[0065] The second clock signal CLK2 may be changed from the high level H to the first low level L at the third time point TP3, and the second clock signal CLK2 having the first low level L may be applied in a period from the third time point TP3 to the fourth time point TP4. Figure 5 As shown in , the third transistor T3 may be turned on in response to the voltage V_NQ of the first node NQ, and the second clock signal CLK2 having the first low level L may be output as a carry signal CR having the first low level L at the carry output node NCO via the turned-on third transistor T3.

[0066] If the second clock signal CLK2 having the first low level L is applied to the carry output node NCO via the turned-on third transistor T3, the voltage of the carry output node NCO or the voltage of the first electrode of the first capacitor C1 may change from the high level H to the first low level L. If the voltage of the first electrode of the first capacitor C1 changes from the high level H to the first low level L, the voltage of the second electrode of the first capacitor C1 or the voltage V_NQ of the first node NQ may change from the first low level L to a second low level 2L lower than the first low level L.

[0067] In some example embodiments, the voltage level difference between the first low level L and the second low level 2L may correspond to, but is not limited to, a voltage level difference between the high level H and the first low level L. Here, the operation of changing the voltage V_NQ of the first node NQ from the first low level L to the second low level 2L may be referred to as a bootstrap operation, and the first capacitor C1 may be referred to as a bootstrap capacitor.

[0068] In the case where the stage 100 does not include the sixth transistor T6, or in the case where the first node NQ and the third node NQ' are the same node, if the voltage V_NQ of the first node NQ changes from the first low level L to the second low level 2L, the voltage V_NQ of the first node NQ having a high absolute value is applied to the transistors T5, T7, and T10 directly coupled to the third node NQ'. For example, because a voltage having a high level H is applied to the first terminals of the transistors T5, T7, and T10, and a voltage having a second low level 2L is applied to the second terminals of the transistors T5, T7, and T10, high voltage stress is applied to the transistors T5, T7, and T10. However, in the stage 100 of the scan driver according to some example embodiments, although the voltage V_NQ of the first node NQ has the second low level 2L, the low gate voltage VGL having the first low level L higher than the second low level 2L may be applied to the gate of the sixth transistor T6, and thus the voltage V_NQ of the first node NQ is not transmitted to the third node NQ'. Therefore, voltage stress applied to the transistors T5, T7, and T10 directly coupled to the third node NQ' may be reduced. Therefore, the sixth transistor T6 may be referred to as a stress relaxation transistor (or stress relief transistor).

[0069] While the carry signal CR is output, the voltage V_NQB of the second node NQB may be maintained or maintained at a high level H by the seventh transistor T7 having a gate receiving the voltage V_NQ' of the third node NQ'. Therefore, while the carry signal CR is output, the second transistor T2 and the fourth transistor T4 may not be turned on based on the voltage V_NQB of the second node NQB having a high level H.

[0070] In addition, while the carry signal CR is output, or in the first effective period AP1 of the carry signal CR, the first transistor T1 may be turned on in response to the carry signal CR output at the carry output node NCO, and the turned-on first transistor T1 may output the mask signal MS as the scan signal SS provided at the scan output node NSO to the pixel row corresponding to the stage 100. For example, in the first effective period AP1 of the carry signal CR, the mask signal MS may have an on level 210 (e.g., a first low level L) or an off level 220 (e.g., a high level H) according to the driving frequency of the panel area including the pixel row, the turned-on first transistor T1 may output the scan signal SS having an on level 230 when the mask signal MS has the on level 210, and the scan signal SS having an off level 240 may be output when the mask signal MS has the off level 220.

[0071] In some example embodiments, Figure 2 As shown in , the second effective period AP2 of the mask signal MS may at least partially overlap with the first effective period AP1 of the carry signal CR, and in the second effective period AP2 of the mask signal MS, the mask signal MS has a conduction level. Therefore, in the first effective period AP1 of the carry signal CR, the mask signal MS having the conduction level 210 may be output as the scan signal SS. In addition, in some example embodiments, as Figure 2 As shown in , the end time point of the second effective period AP2 of the mask signal MS or the rising edge RE2 of the mask signal MS may be before the end time point of the first effective period AP1 of the carry signal CR or the rising edge RE1 of the carry signal CR. Therefore, although the mask signal MS has the on level 210 in the first effective period AP1 of the carry signal CR, the mask signal MS may be changed from the on level 210 (e.g., the first low level L) to the off level 220 (e.g., the high level H) before the first effective period AP1 of the carry signal CR ends. Therefore, before the first effective period AP1 of the carry signal CR ends, the turned-on first transistor T1 may transmit the mask signal MS having the high level H to the scan output node NSO, and the voltage of the scan output node NSO may be changed to the high level H.

[0072] If the second clock signal CLK2 changes to the high level H at the fourth time point TP4, the carry signal CR at the carry output node NCO may change to the high level H. If the voltage of the carry output node NCO or the voltage of the first electrode of the first capacitor C1 changes from the first low level L to the high level H, the voltage of the second electrode of the first capacitor C1 or the voltage V_NQ of the first node NQ may change from the second low level 2L to the first low level L.

[0073] The first clock signal CLK1 may be changed from the high level H to the first low level L at the fifth time point TP5, and the first clock signal CLK1 having the first low level L may be applied in a period from the fifth time point TP5 to the sixth time point TP6. Figure 6 As shown in , the fifth transistor T5 and the eighth transistor T8 may be turned on in response to the first clock signal CLK1 having the first low level L, and the sixth transistor T6 may be turned on in response to the low gate voltage VGL having the first low level L.

[0074] The voltage V_NQ' of the third node NQ' may be changed from the first low level L to the high level H by the turned-on fifth transistor T5, and the voltage V_NQ of the first node NQ may be changed from the first low level L to the high level H by the turned-on sixth transistor T6. The voltage V_NQB of the second node NQB may be changed from the high level H to the first low level L by the turned-on eighth transistor T8, and further, the eighth transistor T8 may be turned on every time the first clock signal CLK1 has the first low level L, so that the low gate voltage VGL may be periodically applied to the second node NQB. The second transistor T2 and the fourth transistor T4 may be turned on in response to the voltage V_NQB of the second node NQB having the first low level L. The turned-on second transistor T2 may apply the high gate voltage VGH to the scan output node NSO, and the turned-on fourth transistor T4 may apply the high gate voltage VGH to the carry output node NCO.

[0075] The second clock signal CLK2 may be changed from the high level H to the first low level L at the seventh time point TP7, and the second clock signal CLK2 having the first low level L may be applied in a period from the seventh time point TP7 to the eighth time point TP8. Figure 7 As shown in , the ninth transistor T9 can be turned on in response to the voltage V_NQB of the second node NQB having the first low level L, the tenth transistor T10 can be turned on in response to the second clock signal CLK2 having the first low level L, and the sixth transistor T6 can be turned on in response to the low gate voltage VGL having the first low level L.

[0076] The turned-on ninth transistor T9 and the tenth transistor T10 may transmit the high gate voltage VGH to the third node NQ', and thus the voltage V_NQ' of the third node NQ' may be stabilized as a high level H. In addition, the voltage V_NQ of the first node NQ may be stabilized as a high level H by the turned-on sixth transistor T6. The tenth transistor T10 may be turned on each time the second clock signal CLK2 has the first low level L, and thus the high gate voltage VGH may be periodically applied to the first node NQ and the third node NQ'.

[0077] As described above, in the scan driver according to some example embodiments, each stage 100 may generate a carry signal CR and may output a mask signal MS as a scan signal SS in response to the carry signal CR. Therefore, each stage 100 may selectively output a scan signal SS having an on level 230 .

[0078] Figure 8 is a block diagram illustrating a display device including a scan driver according to some example embodiments, Fig. 9 is a circuit diagram illustrating an example of a pixel included in a display device according to some example embodiments, Fig.10 is a block diagram illustrating an example of a scan driver included in a display device according to some example embodiments, Fig.11 is a circuit diagram illustrating an example of a display panel including a plurality of panel areas driven at different driving frequencies in a display device according to some example embodiments, Fig.12 Is used to describe Fig.11 A timing diagram of an example of the operation of a scan driver providing a scan signal to a display panel, Fig.13 It is used to describe the scanning driver in the first frame period Fig.11 FIG. 1 is a diagram showing an example of an operation of providing a scan signal to a display panel, Fig.14 It is used to describe the scanning driver in the second frame period Fig.11 FIG. 1 is a diagram showing an example of an operation of providing a scan signal to a display panel, Fig.15 is a block diagram illustrating another example of a scan driver included in a display device according to some example embodiments.

[0079] Reference Figure 8 , a display device 300 according to some example embodiments may include a display panel 310 including a plurality of pixel rows, a data driver 320 providing a data signal DS to each of the plurality of pixel rows, a scan driver 330 providing a plurality of scan signals SS to the plurality of pixel rows, respectively, and a controller 350 controlling the data driver 320 and the scan driver 330. In some example embodiments, the display device 300 may further include an emission driver 340 providing an emission signal SEM to the plurality of pixel rows.

[0080] The display panel 310 may include a plurality of scan lines, a plurality of data lines, and a plurality of pixel rows respectively coupled to the plurality of scan lines. Here, each pixel row may refer to a row of pixels PX connected to a single scan line. In some example embodiments, each pixel PX may include at least one capacitor, at least two transistors, and an organic light emitting diode (OLED), and the display panel 310 may be an OLED display panel.

[0081] For example, Fig. 9As shown in , each pixel PX may include a driving transistor PXT1, a switching transistor PXT2, a compensation transistor PXT3, a storage capacitor CST, a first initialization transistor PXT4, a first emission transistor PXT5, a second emission transistor PXT6, a second initialization transistor PXT7 (or a bypass transistor), and an organic light emitting diode EL, the driving transistor PXT1 generating a driving current, the switching transistor PXT2 transmitting a data signal DS from a data driver 320 to a source electrode (source) of the driving transistor PXT1 in response to a scan signal SS from a scan driver 330, the compensation transistor PXT3 diode-connecting the driving transistor PXT1 in response to a scan signal SS from the scan driver 330, the storage capacitor CST storing the data signal DS transmitted via the switching transistor PXT2 and the diode-connected driving transistor PXT1, the first initialization transistor PXT4 transmitting a data signal DS from a data driver 320 to a source electrode (source) of the driving transistor PXT1, The initialization voltage VINIT is provided to the storage capacitor CST and the gate of the driving transistor PXT1 in response to the initialization signal SI of 0 (or the scan signal PRE_SS for the previous pixel row), the first emission transistor PXT5 connects the line of the first power supply voltage ELVDD to the source of the driving transistor PXT1 in response to the emission signal SEM from the emission driver 340, the second emission transistor PXT6 connects the drain of the driving transistor PXT1 to the organic light emitting diode EL in response to the emission signal SEM from the emission driver 340, the second initialization transistor PXT7 (or the bypass transistor) provides the initialization voltage VINIT to the organic light emitting diode EL in response to the bypass signal SB from the scan driver 330 (or the scan signal NEXT_SS for the next pixel row), and the organic light emitting diode EL emits light based on the driving current from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS.

[0082] In some example embodiments, each pixel PX may include: Fig. 9 In other example embodiments, each pixel PX may include an NMOS transistor.

[0083] In other example embodiments, each pixel PX may include different types of transistors suitable for low-frequency driving capable of reducing power consumption. For example, each pixel PX may include at least one low-temperature polysilicon (LTPS) PMOS transistor and at least one oxide NMOS transistor. For example, the compensation transistor PXT3 and the first initialization transistor PXT4 may be implemented with NMOS transistors, and the other transistors PXT1, PXT2, PXT5, PXT6, and PXT7 may be implemented with PMOS transistors. In addition, according to some example embodiments, without departing from the spirit and scope of the example embodiments, the pixel circuit of the pixel PX may include fewer or additional transistors, capacitors, and / or other circuit components.

[0084] In this case, since the transistors PXT3 and PXT4 directly coupled to the storage capacitor CST are implemented with NMOS transistors, leakage current from the storage capacitor CST can be reduced, and thus the pixel PX can be suitable for low-frequency driving. In other example embodiments, the display panel 310 may be a liquid crystal display (LCD) panel, etc.

[0085] The data driver 320 may generate a data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 350, and may provide the data signal DS to each of the plurality of pixel rows through a plurality of data lines. In some example embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some example embodiments, the data driver 320 and the controller 350 may be implemented with a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other example embodiments, the data driver 320 and the controller 350 may be implemented with separate integrated circuits.

[0086] The scan driver 330 may generate a plurality of scan signals SS based on a scan control signal received from the controller 350, and may provide the plurality of scan signals SS to a plurality of pixel rows through a plurality of scan lines, respectively. In some example embodiments, the scan control signal may include, but is not limited to, a scan start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a mask signal MS. In some example embodiments, the scan driver 330 may be integrated or formed in a peripheral portion of the display panel 310. In other example embodiments, the scan driver 330 may be implemented with one or more integrated circuits.

[0087] In some example embodiments, Fig.10As shown in , the scan driver 330a may include a plurality of stages 331a, 332a, 333a, 334a, 335a, 336a, ... that sequentially generate a plurality of carry signals CR1, CR2, CR3, CR4, CR5, CR6, ... and selectively generate corresponding scan signals SS1, SS2, SS3, SS4, SS5, SS6, ... according to the mask signal MS. In some example embodiments, each of the stages 331a, 332a, 333a, 334a, 335a, 336a, ... may have a Figure 1 The configuration of stage 100 is the same or a similar configuration.

[0088] The plurality of stages 331a, 332a, 333a, 334a, 335a, 336a, ... may receive a scan start signal FLM, may receive a first clock signal CLK1 and a second clock signal CLK2 having different phases (e.g., opposite phases), and may also receive a mask signal MS having an on level or an off level in an effective period of a corresponding carry signal CR1, CR2, CR3, CR4, CR5, CR6, ... A first stage (stage 1) 331a of the plurality of stages 331a, 332a, 333a, 334a, 335a, 336a, ... may receive the scan start signal FLM as an input signal, and the remaining stages (e.g., 332a) of the plurality of stages 331a, 332a, 333a, 334a, 335a, 336a, ... may receive a carry signal (e.g., CR1) from a previous stage (e.g., 331a) as an input signal.

[0089] In some example embodiments, odd-numbered stages 331a, 333a, 335a, ... among the plurality of stages 331a, 332a, 333a, 334a, 335a, 336a, ... may receive input signals in response to the first clock signal CLK1, and may generate carry signals CR1, CR3, CR5, ... in response to the second clock signal CLK2. In addition, even-numbered stages 332a, 334a, 336a, ... among the plurality of stages 331a, 332a, 333a, 334a, 335a, 336a, ... may receive input signals in response to the second clock signal CLK2, and may generate carry signals CR2, CR4, CR6, ... in response to the first clock signal CLK1. The corresponding stages 331a, 332a, 333a, 334a, 335a, 336a, ... may output the masking signal MS as the corresponding scan signal SS1, SS2, SS3, SS4, SS5, SS6, ... during the valid periods of the corresponding carry signals CR1, CR2, CR3, CR4, CR5, CR6, ...

[0090] Therefore, for example, while the first stage 331a outputs the first carry signal CR1, the first stage 331a may output the first scan signal SS1 when the mask signal MS has the on level, and may not output the first scan signal SS1 when the mask signal MS has the off level. Thereafter, while the second stage (stage 2) 332a outputs the second carry signal CR2, the second stage 332a may output the second scan signal SS2 when the mask signal MS has the on level, and may not output the second scan signal SS2 when the mask signal MS has the off level.

[0091] The emission driver 340 may generate an emission signal SEM based on an emission control signal EMCTRL received from the controller 350, and may provide the emission signal SEM to a plurality of pixel rows through a plurality of emission lines. In some example embodiments, the emission signal SEM may be provided sequentially to a plurality of pixel rows. In other example embodiments, the emission signal SEM may be a global signal provided to a plurality of pixel rows substantially simultaneously. In some example embodiments, the emission driver 340 may be integrated or formed in a peripheral portion of the display panel 310. In other example embodiments, the emission driver 340 may be implemented with one or more integrated circuits.

[0092] The controller (e.g., timing controller (TCON)) 350 may receive input image data IDAT and control signal CTRL from an external host (e.g., a graphics processing unit (GPU) or a graphics card). In some example embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 350 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, and an emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL.

[0093] The controller 350 may control the operation of the data driver 320 by providing the output image data ODAT and the data control signal DCTRL to the data driver 320 , may control the operation of the scan driver 330 by providing the scan control signal to the scan driver 330 , and may control the operation of the emission driver 340 by providing the emission control signal EMCTRL to the emission driver 340 .

[0094] The display device 300 according to some example embodiments may perform multi-frequency driving (MFD) to drive a plurality of panel regions of the display panel 310 at a plurality of driving frequencies (which may be different from each other). In order to perform the MFD, Figure 8As shown in the figure, the controller 350 may include a still image detection block (or a still image detector or a still image detection circuit) 360, a driving frequency determination block (or a driving frequency determiner or a driving frequency determiner or a driving frequency determination circuit) 370 and a scan driver control block (or a scan driver controller or a scan driver control circuit) 380.

[0095] The still image detection block 360 may divide the input image data IDAT into a plurality of panel area data for a plurality of panel areas each including at least one of a plurality of pixel rows, and may determine whether each of the plurality of panel area data represents a still image. In some example embodiments, each panel area may include only one pixel row, and the still image detection block 360 may divide the input image data IDAT into a plurality of panel area data each for one pixel row, and may determine whether each of the panel area data for one pixel row represents a still image.

[0096] In other example embodiments, each panel area may include two or more pixel rows, and the still image detection block 360 may divide the input image data IDAT into a plurality of panel area data each for the two or more pixel rows, and may determine whether each panel area data for the two or more pixel rows represents a still image.

[0097] For example, Fig.11 As shown in , the still image detection block 360 can divide the input image data IDAT for the display panel 310a into first panel area data, second panel area data, and third panel area data, the first panel area data is used for the first panel area PZ1 including the first pixel row and the second pixel row receiving the first scan signal SS1 and the second scan signal SS2, the second panel area data is used for the second panel area PZ2 including the third pixel row and the fourth pixel row receiving the third scan signal SS3 and the fourth scan signal SS4, and the third panel area data is used for the third panel area PZ3 including the fifth pixel row and the sixth pixel row receiving the fifth scan signal SS5 and the sixth scan signal SS6. Although Fig.11 An example of a display panel 310a including first to sixth pixel rows receiving first to sixth scan signals SS1 to SS6 is shown, but the number of pixel rows of the display panel 310 is not limited to Fig.11 In addition, although Fig.11 An example is shown in which the display panel 310a is divided into a first panel area PZ1, a second panel area PZ2, and a third panel area PZ3, but the number of the panel areas PZ1, PZ2, and PZ3 is not limited to Fig.11 .

[0098] In some example embodiments, for each panel area data, the still image detection block 360 may determine whether the panel area data represents a still image or a static image by comparing the panel area data in the previous frame period with the panel area data in the current frame period. For example, the still image detection block 360 may determine that the panel area data represents a still image when the panel area data in the current frame period is the same as the panel area data in the previous frame period, and may determine that the panel area data does not represent a still image or represents a moving image when the panel area data in the current frame period is different from the panel area data in the previous frame period.

[0099] In other example embodiments, for each panel area data, the still image detection block 360 may determine whether the panel area data represents a still image by comparing a previous representative value (e.g., an average value or a checksum) of the panel area data in the previous frame period with a current representative value of the panel area data in the current frame period. Fig.11 As shown in , the still image detection block 360 can determine that the first panel area data for the first panel area PZ1 represents a still image when the current representative value of the first panel area data is the same as the previous representative value of the first panel area data, can determine that the second panel area data for the second panel area PZ2 represents a moving image when the current representative value of the second panel area data is different from the previous representative value of the second panel area data, and can determine that the third panel area data for the third panel area PZ3 represents a still image when the current representative value of the third panel area data is the same as the previous representative value of the third panel area data.

[0100] The driving frequency decision block 370 may decide (or set or determine) a plurality of driving frequencies for a plurality of panel areas according to whether each of the plurality of panel area data represents a still image. In some example embodiments, when each panel area data represents a moving image, the driving frequency decision block 370 may decide (or set or determine) the driving frequency for the panel area corresponding to the panel area data as a normal driving frequency. Here, the normal driving frequency may be a driving frequency under normal driving of the display device 300.

[0101] For example, the normal driving frequency may be the same as the input frame frequency (e.g., about 60 Hz or about 120 Hz) of the input image data IDAT. In addition, in the case where each panel area data represents a still image, the driving frequency decision block 370 may decide (or set or determine) the driving frequency for the panel area corresponding to the panel area data to be a low driving frequency lower than the normal driving frequency. Here, the low driving frequency may be any frequency lower than the normal driving frequency.

[0102] In some example embodiments, in the case where each panel area data represents a still image, the driving frequency decision block 370 may determine a flicker value corresponding to the grayscale (or brightness) of the panel area data by using a flicker lookup table, and may decide (or set or determine) a driving frequency for the panel area corresponding to the panel area data based on the flicker value. For example, the flicker lookup table may store flicker values ​​corresponding to the grayscale of the image data (e.g., 256 grayscales from 0 grayscale to 255 grayscale), respectively. Here, the flicker value may represent the level of flicker perceived by the user.

[0103] According to some example embodiments, the determination of the flicker value and the driving frequency may be performed on a pixel-by-pixel basis, a segment-by-segment basis, or a panel region-by-panel region basis. For example, each panel region data may be divided into a plurality of segment data for a plurality of segments, a flicker value for each segment may be determined by using a flicker lookup table, a segment driving frequency for each segment may be determined, and the driving frequency for the panel region may be determined as the maximum segment driving frequency among the segment driving frequencies.

[0104] For example, Fig.11 As shown in, in the case where the second panel area data for the second panel area PZ2 represents a moving image, the driving frequency decision block 370 can decide (or set or determine) the second driving frequency DF2 for the second panel area PZ2 to be a normal driving frequency, for example, about 60Hz. In addition, in the case where each of the first panel area data and the third panel area data for the first panel area PZ1 and the third panel area PZ3 represents a still image, the driving frequency decision block 370 can decide (or set or determine) the first driving frequency DF1 and the third driving frequency DF3 for the first panel area PZ1 and the third panel area PZ3 to be a low driving frequency lower than the normal driving frequency. For example, the driving frequency decision block 370 can determine the flicker value according to the grayscale (or brightness) of the first panel area data, and can decide (or set or determine) the first driving frequency DF1 for the first panel area PZ1 to be about 15Hz lower than the normal driving frequency according to the flicker value. In addition, the driving frequency decision block 370 can determine the flicker value according to the grayscale (or brightness) of the third panel area data, and can decide (or set or determine) the third driving frequency DF3 for the third panel area PZ3 to be approximately 30 Hz lower than the normal driving frequency according to the flicker value.

[0105] The scan driver control block 380 may generate the mask signal MS based on the plurality of driving frequencies for the plurality of panel regions. In some example embodiments, in order to output the corresponding scan signal SS to the pixel rows included in the panel region driven at the normal driving frequency in all frame periods, the scan driver control block 380 may generate the mask signal MS having an on level in all valid periods of the carry signal CR generated by the stage coupled to the pixel row.

[0106] In addition, in order to output the corresponding scan signal SS to the pixel rows included in the panel area driven at a low driving frequency in a part of the frame period, the scan driver control block 380 can generate a mask signal MS, which has a turn-on level in a part of the effective period of the carry signal CR generated by the stage coupled to the pixel row and has an off level in the remaining part of the effective period of the carry signal CR generated by the stage coupled to the pixel row.

[0107] For example, Figures 10 to 12 As shown in , the plurality of stages 331a to 336a may sequentially generate a plurality of carry signals CR1 to CR6 in each frame period FP1 to FP4. According to the plurality of driving frequencies DF1, DF2, and DF3 for the plurality of panel regions PZ1, PZ2, and PZ3, the scan driver control block 380 may generate a masking signal MS having an on level or an off level in an effective period of the plurality of carry signals CR1 to CR6 in the plurality of frame periods FP1 to FP4. The plurality of stages 331a to 336a may selectively output a plurality of scan signals SS1 to SS6 according to the masking signal MS.

[0108] In the example, Fig.11 As shown in, in the case where the second driving frequency DF2 for the second panel area PZ2 is decided (or set or determined) to be a normal driving frequency (for example, about 60 Hz), the scan driver control block 380 can generate a masking signal MS with a turn-on level in all valid periods of the third carry signal CR3 and the fourth carry signal CR4 in the first frame period FP1, the second frame period FP2, the third frame period FP3 and the fourth frame period FP4, and the third stage (stage 3) 333a and the fourth stage (stage 4) 334a can output the third scan signal SS3 and the fourth scan signal SS4 in all of the first frame period FP1, the second frame period FP2, the third frame period FP3 and the fourth frame period FP4 in response to the masking signal MS.

[0109] In addition, the controller 350 may provide the output image data ODAT including the second panel area data PD2 to the data driver 320 in all of the first frame period FP1, the second frame period FP2, the third frame period FP3, and the fourth frame period FP4, and the data driver 320 may provide the data signal DS corresponding to the second panel area data PD2 to the second panel area PZ2 in all of the first frame period FP1, the second frame period FP2, the third frame period FP3, and the fourth frame period FP4. Therefore, the second panel area PZ2 may be driven at a normal driving frequency (e.g., about 60 Hz).

[0110] In addition, when the first driving frequency DF1 for the first panel area PZ1 is determined (or set) to a low driving frequency (for example, about 15 Hz), the scan driver control block 380 can generate a masking signal MS, which has a turn-on level in the effective period of the first carry signal CR1 and the second carry signal CR2 in the first frame period FP1, and has a cut-off level in the effective period of the first carry signal CR1 and the second carry signal CR2 in the second frame period FP2, the third frame period FP3 and the fourth frame period FP4.

[0111] In response to the mask signal MS, the first stage 331a and the second stage 332a may output the first scan signal SS1 and the second scan signal SS2 in the first frame period FP1, and may not output the first scan signal SS1 and the second scan signal SS2 in the second frame period FP2, the third frame period FP3, and the fourth frame period FP4. In addition, the controller 350 may provide the data driver 320 with the output image data ODAT including the first panel area data PD1 in the first frame period FP1, and may provide the data driver 320 with the output image data ODAT not including the first panel area data PD1 in the second frame period FP2, the third frame period FP3, and the fourth frame period FP4. The data driver 320 may provide the data signal DS corresponding to the first panel area data PD1 to the first panel area PZ1 in the first frame period FP1, and may not provide the data signal DS to the first panel area PZ1 in the second frame period FP2, the third frame period FP3, and the fourth frame period FP4. Therefore, the first panel area PZ1 may be driven at a low driving frequency (e.g., about 15 Hz).

[0112] In addition, in the case where the third driving frequency DF3 for the third panel area PZ3 is decided (or set or determined) to be a low driving frequency (e.g., about 30 Hz), the scan driver control block 380 may generate a mask signal MS having an on-level in the effective periods of the fifth carry signal CR5 and the sixth carry signal CR6 in the first frame period FP1 and the third frame period FP3, and having an off-level in the effective periods of the fifth carry signal CR5 and the sixth carry signal CR6 in the second frame period FP2 and the fourth frame period FP4. In response to the mask signal MS, the fifth stage (stage 5) 335a and the sixth stage (stage 6) 336a may output the fifth scan signal SS5 and the sixth scan signal SS6 in the first frame period FP1 and the third frame period FP3, and may not output the fifth scan signal SS5 and the sixth scan signal SS6 in the second frame period FP2 and the fourth frame period FP4.

[0113] In addition, the controller 350 may provide the data driver 320 with the output image data ODAT including the third panel area data PD3 in the first frame period FP1 and the third frame period FP3, and may provide the data driver 320 with the output image data ODAT not including the third panel area data PD3 in the second frame period FP2 and the fourth frame period FP4. The data driver 320 may provide the data signal DS corresponding to the third panel area data PD3 to the third panel area PZ3 in the first frame period FP1 and the third frame period FP3, and may not provide the data signal DS to the third panel area PZ3 in the second frame period FP2 and the fourth frame period FP4. Therefore, the third panel area PZ3 may be driven at a low driving frequency (e.g., about 30 Hz).

[0114] As described above, the scan driver control block 380 may generate the mask signal MS so that the scan signals SS3 and SS4 may be provided to the second panel area PZ2 displaying a moving image in all of the plurality of frame periods FP1, FP2, FP3, and FP4, and the scan signals SS1, SS2, SS5, and SS6 may be provided to the first panel area PZ1 and the third panel area PZ3 displaying a still image in a portion of the plurality of frame periods FP1, FP2, FP3, and FP4. For example, in the first frame period FP1, as shown in FIG. Fig.13 As shown in , the scan driver control block 380 can generate a masking signal MS having a turn-on level L in the effective period of the first carry signal CR1 to the sixth carry signal CR6, and the plurality of stages 331a to 336a can sequentially output the first scan signal SS1 to the sixth scan signal SS6 in response to the masking signal MS.

[0115] However, in the second frame period FP2, as Fig.14As shown in , the scan driver control block 380 may generate a mask signal MS having an on level L in the effective periods of the third carry signal CR3 and the fourth carry signal CR4, and having an off level H in the effective periods of the first carry signal CR1, the second carry signal CR2, the fifth carry signal CR5, and the sixth carry signal CR6. In response to the mask signal MS, the plurality of stages 331a to 336a may sequentially output the third scan signal SS3 and the fourth scan signal SS4, and may not output the first scan signal SS1, the second scan signal SS2, the fifth scan signal SS5, and the sixth scan signal SS6.

[0116] In other example embodiments, Fig.15 As shown in , the scan driver 330b may include odd-numbered stages 331b, 333b, 335b, ... coupled to each other in series and even-numbered stages 332b, 334b, 336b, ... coupled to each other in series. The odd-numbered stages 331b, 333b, 335b, ... may provide corresponding scan signals SS1, SS3, SS5, ... among a plurality of scan signals SS1, SS2, SS3, SS4, SS5, SS6, ... to the odd-numbered pixel rows of the display panel 310, and the even-numbered stages 332b, 334b, 336b, ... may provide corresponding scan signals SS2, SS4, SS6, ... among a plurality of scan signals SS1, SS2, SS3, SS4, SS5, SS6, ... to the even-numbered pixel rows of the display panel 310. The odd stages 331b, 333b, 335b, ... can perform scanning signals based on the odd scan start signal OFLM, the first odd clock signal OCLK1, the second odd clock signal OCLK2 and the odd masking signal OMS, and the even stages 332b, 334b, 336b, ... can perform scanning signals based on the even scan start signal EFLM, the first even clock signal ECLK1, the second even clock signal ECLK2 and the even masking signal EMS.

[0117] In the display device 300 according to some example embodiments, each stage of the scan driver 330 may output the mask signal MS as the scan signal SS in response to the carry signal CR. Therefore, the scan driver 330 may sequentially generate a plurality of carry signals CR1, CR2, CR3, CR4, CR5, CR6, ..., and may selectively output corresponding scan signals SS1, SS2, SS3, SS4, SS5, SS6, ... according to the mask signal MS in the effective periods of the plurality of carry signals CR1, CR2, CR3, CR4, CR5, CR6, .... Therefore, the scan driver 330 of the display device 300 may provide a plurality of scan signals SS1, SS2, SS3, SS4, SS5, SS6, ... to a plurality of pixel rows of the display panel 310 at different driving frequencies.

[0118] Fig.16 An electronic device including a display device according to some example embodiments.

[0119] Reference Fig.16 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electrical devices, and the like.

[0120] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, in some example embodiments, the processor 1110 may also be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0121] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0122] The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may be an input device (such as a keyboard, a keypad, a mouse, a touch screen, etc.) and an output device (such as a printer, a speaker, etc.). The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be coupled to other components via a bus or other communication links.

[0123] In the display device 1160, each stage of the scan driver may include a mask control unit that outputs a mask signal as a scan signal in response to a carry signal. Therefore, the scan driver may provide a plurality of scan signals to a plurality of pixel rows at different driving frequencies, and the display device 1160 may perform multi-frequency driving.

[0124] Aspects of the embodiments according to the inventive concept may be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, aspects of the embodiments according to the inventive concept may be applied to mobile phones, smart phones, wearable electronic devices, tablet computers, televisions (TVs), digital TVs, 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0125] The foregoing is an illustration of example embodiments and should not be construed as limiting the example embodiments. Although several example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are feasible in the example embodiments without substantially departing from the novel teachings and features of the embodiments conceived in accordance with the present invention. Therefore, all such modifications are intended to be included within the scope of the embodiments conceived in accordance with the present invention as defined in the claims and their equivalents. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A scanning driver, comprising: Multiple levels, each level includes: a logic circuit configured to transmit an input signal to a first node in response to a first clock signal and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal in response to the voltage of the first node after bootstrapping, the carry signal being provided as an input signal for a next stage; and a mask controller configured to receive a mask signal and the carry signal, and output the mask signal as a scan signal provided to a pixel row corresponding to each stage in response to the carry signal, wherein the mask signal has an on level or an off level in a first effective period of the carry signal according to a driving frequency of a panel region including the pixel row, and Wherein, the masking controller is configured to output a scanning signal with an on-level when the masking signal has an on-level, and to output a scanning signal with an off-level when the masking signal has an off-level, so that the scanning driver provides multiple scanning signals to multiple pixel rows at different driving frequencies.

2. The scan driver according to claim 1, wherein: A second effective period of the mask signal at least partially overlaps with the first effective period of the carry signal, and in the second effective period of the mask signal, the mask signal has an on level.

3. The scan driver according to claim 2, wherein: An end time point of the second effective period of the mask signal is before an end time point of the first effective period of the carry signal.

4. The scan driver according to claim 1, wherein: The masking controller comprises: A first transistor includes a gate configured to receive the carry signal, a first terminal coupled to a scan output node at which the scan signal is output, and a second terminal configured to receive the mask signal.

5. The scan driver according to claim 4, wherein: The masking controller further comprises: The second transistor includes a gate coupled to the second node, a first terminal configured to receive a gate-off voltage, and a second terminal coupled to the scan output node.

6. The scan driver according to claim 1, wherein: The carry output circuit comprises: a third transistor including a gate coupled to the first node, a first terminal coupled to a carry output node at which the carry signal is output, and a second terminal configured to receive the second clock signal; and A fourth transistor includes a gate coupled to the second node, a first terminal configured to receive a gate-off voltage, and a second terminal coupled to the carry output node.

7. The scan driver according to claim 1, wherein: The logic circuit comprises: an input circuit configured to transmit the input signal to a third node in response to the first clock signal; a stress relaxation circuit located between the first node and the third node and configured to transmit the input signal from the third node to the first node so that a voltage of the first node changes to a first conduction level; a bootstrap circuit configured to change a voltage of the first node from the first conduction level to a second conduction level having an absolute value greater than that of the first conduction level by bootstrapping the first node based on the second clock signal; a holding circuit configured to hold the second node at an off level while outputting the carry signal; and A stabilization circuit is configured to periodically apply a gate-on voltage to the second node in response to the second clock signal after outputting the carry signal, and to periodically apply a gate-off voltage to the third node in response to the first clock signal.

8. A scanning driver, comprising: Multiple levels, each level includes: a first transistor including a gate coupled to the carry-out node, a first terminal coupled to the scan-out node, and a second terminal configured to receive a mask signal; a second transistor including a gate coupled to the second node, a first terminal configured to receive a gate-off voltage, and a second terminal coupled to the scan-out node; a third transistor including a gate coupled to the first node, a first terminal coupled to the carry output node, and a second terminal configured to receive a second clock signal; a fourth transistor including a gate coupled to the second node, a first terminal configured to receive the gate-off voltage, and a second terminal coupled to the carry output node; a fifth transistor including a gate configured to receive the first clock signal, a first terminal configured to receive an input signal, and a second terminal coupled to the third node; a sixth transistor including a gate configured to receive a gate-on voltage, a first terminal coupled to the third node, and a second terminal coupled to the first node; a first capacitor including a first electrode coupled to the carry output node and a second electrode coupled to the first node; a seventh transistor including a gate coupled to the third node, a first terminal coupled to the second node, and a second terminal configured to receive the first clock signal; an eighth transistor including a gate configured to receive the first clock signal, a first terminal coupled to the second node, and a second terminal configured to receive the gate-on voltage; a ninth transistor including a gate coupled to the second node, a first terminal receiving the gate-off voltage, and a second terminal; a tenth transistor including a gate configured to receive the second clock signal, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the third node; and a second capacitor including a first electrode configured to receive the gate-off voltage and a second electrode coupled to the second node, wherein the mask signal has an on level or an off level according to a driving frequency of a panel area including a plurality of pixel rows in a first effective period of the carry signal, and The first transistor is configured to output a scan signal having an on-level when the masking signal has an on-level, and to output a scan signal having an off-level when the masking signal has an off-level, so that the scan driver provides multiple scan signals to the multiple pixel rows at different driving frequencies.

9. A display device, comprising: A display panel including a plurality of pixel rows; a data driver configured to provide a data signal to each of the plurality of pixel rows; A scan driver configured to provide a plurality of scan signals to the plurality of pixel rows respectively; as well as a controller configured to control the data driver and the scan driver, Wherein, the scan driver includes a plurality of stages, and each stage includes: a logic circuit configured to transmit an input signal to a first node in response to a first clock signal and to bootstrap the first node in response to a second clock signal; a carry output circuit configured to output the second clock signal as a carry signal in response to the voltage of the first node after bootstrapping, the carry signal being provided as an input signal for a next stage; and a mask control circuit configured to receive a mask signal and the carry signal, and output the mask signal as a scan signal provided to a pixel row corresponding to each stage among the plurality of pixel rows in response to the carry signal, wherein the masking signal has an on level or an off level in the first effective period of the carry signal according to the driving frequency of the display panel, and Wherein, the masking control circuit is configured to output a scanning signal with an on-level when the masking signal has an on-level, and to output a scanning signal with an off-level when the masking signal has an off-level, so that the scanning driver provides the multiple scanning signals to the multiple pixel rows at different driving frequencies.

Images