Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

The present application provides a silicon carbide semiconductor device capable of inhibiting peeling and cracking of barrier metal and a manufacturing method of the silicon carbide semiconductor device. A first recess (10a) reflecting a recess (7a) of an upper surface of a gate electrode (7) inside a trench (5) is provided on an upper surface of an interlayer insulating film (10). A second recess (10b) in which an upper end of a side surface of the interlayer insulating film (10) is removed in a fan shape is provided at a boundary of the upper surface and the side surface of the interlayer insulating film (10). A convex (10e, 10f) caused by the first recess and the second recess (10a, 10b) is formed on a surface of the interlayer insulating film (10), and more than three concaves and convexes are repeatedly provided by the first recess, the second recess (10a, 10b), and the convex (10e, 10f). Angles (θ1, θ2) of vertices of the convex (10e, 10f) of the surface of the interlayer insulating film (10) are obtuse angles of 100° or more. Barrier metal (12) covering the interlayer insulating film (10) has concaves and convexes reflecting the concaves and convexes of the surface of the interlayer insulating film (10).

Description

Technical Field

[0001] This invention relates to silicon carbide semiconductor devices and methods for manufacturing silicon carbide semiconductor devices. Background Technology

[0002] While finer trench pitch enables higher current density and smaller chip size in trench-gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors, MOS-type field effect transistors with an insulated gate consisting of a metal-oxide-semiconductor three-layer structure), the increased unevenness on the upper surface of the interlayer insulating film and the exposed portion of the semiconductor substrate at the contact holes leads to poorer step coverage of the uppermost aluminum (Al) metal electrode layer (hereinafter referred to as the Al metal electrode layer).

[0003] Conventionally, in trench-gate MOSFETs using silicon (Si) as the semiconductor material, to planarize the Al metal electrode layer, after forming the contact hole, the interlayer insulating film is softened and deformed, causing the upper surface of the interlayer insulating film to become a convex curved surface along the direction away from the semiconductor substrate. This reduces the unevenness formed by the upper surface of the interlayer insulating film and the exposed portion of the front side of the semiconductor substrate at the contact hole. In the case of silicon carbide (SiC) as the semiconductor material, the upper surface of the interlayer insulating film is also made into the same curved surface as in the case of silicon as the semiconductor material to smooth the Al metal electrode layer (for example, see Patent Document 1 below).

[0004] The structure of conventional trench gate MOSFETs will be explained. Figure 10 This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. Figure 10 It is the following patent document 1 Figure 1 . Figure 10 The conventional silicon carbide semiconductor device 130 shown is a vertical MOSFET with a typical trench gate on the front side of a semiconductor substrate 120 made of silicon carbide, and the upper surface of the interlayer insulating film 110 covering the gate electrode 107 is a curved surface that is convexly curved along the direction away from the semiconductor substrate 120. The interlayer insulating film 110 is a double-layer structure consisting of a first insulating layer 108 and a second insulating layer 109 sequentially stacked on the front side of the semiconductor substrate 120, covering the gate electrode 107.

[0005] The first insulating layer 108 is an NSG (Non doped Silicate Glass) film. The upper surface of the first insulating layer 108 is flat. The second insulating layer 109 is a BPSG (Boron Phospho Silicate Glass) film. The thickness of the second insulating layer 109 is thick at the center of the trench 105 and becomes thinner as it approaches the contact hole 115. The upper surface of the second insulating layer 109 is a curved surface that is convex in a direction away from the semiconductor substrate 120. By making the upper surface of the second insulating layer 109 a curved surface, the unevenness formed by the upper surface of the interlayer insulating film 110 and the portion of the front surface of the semiconductor substrate 120 exposed at the contact hole 115 becomes small.

[0006] Thus, the respective surfaces of the metal electrode layers 112 and 113 that are sequentially stacked on the interlayer insulating film 110 are also smoothed. The symbols 111 to 113 constitute the source electrode 114. The symbol 112 is a laminated film of a titanium (Ti) film and an aluminum silicon (AlSi) film. The symbol 113 is a laminated film of a nickel (Ni) plating film and a gold (Au) plating film. The symbols 101 to 107, 116, and 117 are, respectively, an n - type drift region, a p-type base region, an n + type source region, a p + type contact region, a trench, a gate insulating film, a source electrode, an n + type drain region, and a drain electrode.

[0007] In the case of a MOSFET using silicon carbide as a semiconductor material (hereinafter referred to as SiC-MOSFET), in order to form an ohmic contact between the source electrode 114 and the semiconductor substrate 120, a nickel silicide (NiSi) film 111 is required as the lowermost layer of the source electrode 114. The nickel silicide film 111 is in ohmic contact with the portion of the front surface of the semiconductor substrate 120 exposed at the contact hole 115. On the nickel silicide film 111, a Ti film or a TiN film, or a metal laminated film in which both are combined, is required as a barrier metal that prevents the diffusion of aluminum atoms from the Al metal electrode layer 112 to the semiconductor substrate 120.

[0008] As a SiC-MOSFET of a conventional trench gate structure, a device in which the upper surface of the interlayer insulating film is a curved surface that is convexly curved in a direction away from the semiconductor substrate and a barrier metal is provided so as to cover the upper surface of the interlayer insulating film over the entire front surface of the semiconductor substrate has been proposed (for example, refer to Patent Documents 2 to 4 described below). In Patent Documents 2 and 3 described below, as the barrier metal, a tungsten alloy film containing titanium is provided. In Patent Document 4 described below, as the barrier metal, a single-layer titanium nitride (TiN) film or a laminated film in which a titanium (Ti) film and a titanium nitride film are sequentially stacked is provided.

[0009] Further, as a SiC-MOSFET of the related art trench gate structure, there is disclosed a device in which a recess deepest toward the drain side is generated on the upper surface of the gate electrode and in the approximate center of the trench, and a recess is left in the approximate center of the trench, which is recessed toward the drain side, by reflecting the recess of the upper surface of the gate electrode on the upper surface of the interlayer insulating film (for example, refer to Patent Document 5 (Fig. 28)). In Patent Document 5, the both side portions of the recess of the upper surface of the interlayer insulating film protrude in a shape of being convex along a direction departing from the semiconductor substrate and having a sharp front end due to the recess, and a concave-convex is also formed on the upper surface of the barrier metal, which is formed by reflecting the concave-convex of the upper surface of the interlayer insulating film.

[0010] Prior Art Documents

[0011] Patent Documents

[0012] Patent Document 1: Japanese Patent No. 6475142

[0013] Patent Document 2: Japanese Laid-Open Patent Publication No. 2010-272676

[0014] Patent Document 3: Japanese Laid-Open Patent Publication No. 2010-267899

[0015] Patent Document 4: International Publication No. 2016 / 039074

[0016] Patent Document 5: Japanese Laid-Open Patent Publication No. Hei 7-235676 SUMMARY

[0017] Technical Problem

[0018] However, in the related art silicon carbide semiconductor device 130 (refer to Figure 10 ), in a case where a laminated film of a titanium film and a titanium nitride film is provided as a barrier metal, the following problem occurs. Figure 11 is a cross-sectional view schematically showing a state observed by observing the interlayer insulating film and the barrier metal of the related art silicon carbide semiconductor device. Figure 11 The related art silicon carbide semiconductor device 140 shown in Figure 10 differs from the related art silicon carbide semiconductor device 130 shown in

[0019] Figure 11 is a cross-sectional view schematically showing a state observed by observing the interlayer insulating film 110 and the barrier metal 141 of the related art silicon carbide semiconductor device 140 with a scanning electron microscope (SEM: Scanning Electron Microscope). In Figure 11In the drawing, the illustration of each portion except for the trench 105, the gate insulating film 106, and the gate electrode 107 in the inside of the semiconductor substrate 120 is omitted. The Al metal electrode layer 112 is, for example, an aluminum silicon film.

[0020] The barrier metal 141 is provided from the surface of the nickel silicide film 111 to the surface of the interlayer insulating film 110. The barrier metal 141 is, for example, a laminated film in which a titanium nitride film, a titanium film, and a titanium nitride film are laminated in this order. The stress of the titanium film and the titanium nitride film constituting the barrier metal 141 is strong. Therefore, if the upper surface of the interlayer insulating film 110 becomes a curved surface which is convex in the direction away from the semiconductor substrate 120, the step coverage of the barrier metal 141 on the interlayer insulating film 110 becomes poor.

[0021] The barrier metal 141 is higher in the rate of smoothing discontinuity at the position where the step coverage is poor, and the surface irregularity becomes large. The portion of the surface of the barrier metal 141 where the irregularity is large shrinks due to the tensile stress, and the stress resistance at the portion is weakened. The portion of the surface of the barrier metal 141 where the irregularity is large is specifically, for example, a portion 141a of the barrier metal 141 directly above the trench 105. The step coverage of the portion of the barrier metal 141 on the nickel silicide film 111 is good, and the portion does not shrink.

[0022] The deformation of the barrier metal 141 due to the stress difference applied to the barrier metal 141 can cause peeling and cracking of the barrier metal 141. Regarding the peeling and cracking of the barrier metal 141, according to the inventors' intensive studies, the following points are confirmed. The main point of the cracking of the barrier metal 141 is a boundary 141b between the side wall of the contact hole 115 and the front surface of the semiconductor substrate 120. The cracking of the barrier metal 141 is not regular, is randomly generated, and is not dependent on the layout of the gate electrode 107. The barrier metal 141 peels from the cracking of the barrier metal 141.

[0023] The present application is to solve the problems of the above-described prior art, and aims to provide a silicon carbide semiconductor device and a manufacturing method of a silicon carbide semiconductor device capable of suppressing peeling and cracking of a barrier metal.

[0024] Technical Solution

[0025] To solve the above problems and achieve the object of the present application, a silicon carbide semiconductor device of the present application has the following features. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided in contact with the first semiconductor region between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of the first conductivity type is selectively provided in contact with the second semiconductor region between the first main surface of the semiconductor substrate and the second semiconductor region. A trench reaches the first semiconductor region through the third semiconductor region and the second semiconductor region from the first main surface of the semiconductor substrate. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween. An interlayer insulating film covers the gate electrode. A contact hole reaches the semiconductor substrate through the interlayer insulating film in a depth direction.

[0026] A first electrode is provided on a surface of the interlayer insulating film and connected to the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode is electrically connected to the first semiconductor region. Three or more recesses are provided separately from each other on the surface of the interlayer insulating film. The surface of the interlayer insulating film has a shape in which three or more concavities and convexities are repeated, the concavities and convexities being caused by the recesses and convexities, the convexities having vertices at boundaries between inner walls of the recesses and the surfaces of the recesses. The first electrode has a first electrode film to a third electrode film. The first electrode film is in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode film containing titanium is provided along the surface of the first electrode film and the surface of the interlayer insulating film. A third electrode film containing aluminum is provided on the surface of the second electrode film. The second electrode film has a concave-convex shape that reflects the concavities and convexities of the surface of the interlayer insulating film caused by the recesses.

[0027] In addition, to solve the above problems and achieve the object of the present application, a silicon carbide semiconductor device of the present application has the following features. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided in contact with the first semiconductor region between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of the first conductivity type is selectively provided in contact with the second semiconductor region between the first main surface of the semiconductor substrate and the second semiconductor region. A trench reaches the first semiconductor region through the third semiconductor region and the second semiconductor region from the first main surface of the semiconductor substrate. A gate electrode is provided inside the trench with a gate insulating film interposed therebetween.

[0028] An interlayer insulating film covers the gate electrode. A contact hole reaches the semiconductor substrate through the interlayer insulating film in a depth direction. A first electrode is provided on a surface of the interlayer insulating film and is connected to the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode is electrically connected to the first semiconductor region. Three or more recesses are provided on the surface of the interlayer insulating film, and the surface of the interlayer insulating film has a shape in which three or more concavities and convexities caused by the recesses are repeated. The recess closest to the contact hole has a predetermined depth smaller than a thickness of the interlayer insulating film, and is continuous with the contact hole.

[0029] The opening width of the contact hole is wider at a position farther from the semiconductor substrate than at a position closer to the semiconductor substrate, through the recess closest to the contact hole. The first electrode has a first electrode film to a third electrode film. The first electrode film is in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole. A second electrode film containing titanium is provided along a surface of the first electrode film and a surface of the interlayer insulating film. A third electrode film containing aluminum is provided on a surface of the second electrode film. The second electrode film has a concave-convex shape that reflects the concavities and convexities of the surface of the interlayer insulating film caused by the recesses.

[0030] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-described application, a difference in level of the concavities and convexities of the surface of the interlayer insulating film caused by the recesses is 0.1 μm or more and less than 0.5 μm.

[0031] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-described application, a difference in level of the concavities and convexities of the surface of the interlayer insulating film caused by the recesses is 0.3 μm or less.

[0032] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-described application, the plurality of recesses of the surface of the interlayer insulating film have a first recess and a second recess. The first recess is provided on an upper surface of the interlayer insulating film, reflecting a depression generated at a contact surface at which the gate electrode contacts the interlayer insulating film. The second recess is provided at a boundary between the upper surface of the interlayer insulating film and a side surface of the interlayer insulating film, and is depressed in a circular arc shape, and is continuous with the contact hole.

[0033] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-mentioned application, the first recessed portion and the second recessed portion are provided separately from each other. The surface of the interlayer insulating film between the first recessed portion and the second recessed portion is a first flat surface. The depth of the second recessed portion is 20% or more and 50% or less of the thickness from the first flat surface of the interlayer insulating film to the upper surface of the gate insulating film on the first main surface of the semiconductor substrate.

[0034] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-mentioned application, on the surface of the interlayer insulating film, there is a first convex portion having a triangular cross-sectional shape with the vertex at the boundary between the inner wall of the recessed portion and the first flat surface. The angle of the vertex of all the first convex portions is an obtuse angle of 100° or more.

[0035] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-mentioned application, the larger the angle of the vertex of the first convex portion disposed closer to the trench, the larger the angle of the vertex.

[0036] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-mentioned application, the angle of the vertex of the first convex portion disposed closer to the trench is an obtuse angle of 110° or more.

[0037] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-mentioned application, the side surface of the interlayer insulating film is a second flat surface having a slope with respect to the first main surface of the semiconductor substrate. On the surface of the interlayer insulating film, there is a second convex portion having a triangular cross-sectional shape with the vertex at the boundary between the inner wall of the second recessed portion and the second flat surface. The angle of the vertex of the second convex portion is an obtuse angle of 100° or more.

[0038] Further, the silicon carbide semiconductor device of the present application is characterized in that, in the above-mentioned application, the angle of the vertex of the second convex portion is smaller than the angle of the vertex of the first convex portion.

[0039] Further, in order to solve the above-mentioned problems, to achieve the object of the present application, the manufacturing method of the silicon carbide semiconductor device of the present application has the following features. A first process is performed to form a trench reaching a predetermined depth from the first main surface of a semiconductor substrate. A second process is performed to form a gate insulating film along the first main surface of the semiconductor substrate and the inner wall of the trench. A third process is performed to stack a polysilicon layer on the first main surface of the semiconductor substrate and fill the inside of the trench with the polysilicon layer. A fourth process is performed to etch back the polysilicon layer until the gate insulating film on the first main surface of the semiconductor substrate is exposed, and only the polysilicon layer to be a gate electrode is left in the inside of the trench.

[0040] A fifth step is performed to form an interlayer insulating film covering the gate electrode on the first main surface of the semiconductor substrate. A sixth step is performed to form a contact hole reaching the semiconductor substrate through the interlayer insulating film in the depth direction. A seventh step is performed to planarize the interlayer insulating film by heat treatment. An eighth step is performed to form a first electrode film in ohmic contact with the semiconductor substrate inside the contact hole. A ninth step is performed to form a second electrode film containing titanium along the surface of the first electrode film and the surface of the interlayer insulating film. A tenth step is performed to form a third electrode film containing aluminum on the surface of the second electrode film. In the fourth step, the surface of the gate electrode is recessed.

[0041] In the fifth step, a first recess reflecting the recess of the surface of the gate electrode is left on the surface of the interlayer insulating film. The sixth step includes a mask forming step, a first groove forming step, a second groove forming step, and a removing step. In the mask forming step, an etching mask partially opened corresponding to the formation region of the contact hole is formed on the surface of the interlayer insulating film. In the first groove forming step, isotropic etching is performed using the etching mask to form a first groove having a predetermined depth from the surface of the interlayer insulating film. In the second groove forming step, anisotropic etching is performed using the etching mask to form a second groove reaching the interlayer insulating film in the depth direction from the bottom surface of the first groove. In the removing step, the etching mask is removed.

[0042] Further, the manufacturing method of a silicon carbide semiconductor device of the present application is characterized in that, in the above-described application, in the fourth step, the surface of the gate electrode is recessed to a depth of 0.1 μm or more and less than 0.5 μm.

[0043] Further, the manufacturing method of a silicon carbide semiconductor device of the present application is characterized in that, in the above-described application, in the first groove forming step, the predetermined depth of the first groove is set to 20% or more and 50% or less of the thickness from the surface of the portion of the interlayer insulating film other than the first recess to the upper surface of the gate insulating film on the first main surface of the semiconductor substrate.

[0044] Further, the manufacturing method of the silicon carbide semiconductor device of the present application is characterized in that, in the fifth step, a first insulating layer and a second insulating layer are sequentially stacked as the interlayer insulating film, the second insulating layer has a higher boron concentration and a higher phosphorus concentration than the first insulating layer, the boron concentration of the second insulating layer is 1 wt% or more and 3 wt% or less, and the phosphorus concentration of the second insulating layer is 1 wt% or more and 3 wt% or less. In the first trench forming step, the first trench is formed in the second insulating layer. In the second trench forming step, the second trench is formed which penetrates the second insulating layer and the first insulating layer in the depth direction from the bottom surface of the first trench. In the seventh step, the temperature of the heat treatment is set to 1000°C or lower.

[0045] According to the present application described above, the surface of the interlayer insulating film is shaped so that the concavo-convex is repeated, thereby dispersing the stress of the barrier metal applied to the surface of the interlayer insulating film. Further, the adhesion of the interlayer insulating film to the barrier metal is improved by the anchoring effect of the concavo-convex of the surface of the interlayer insulating film.

[0046] Technical Effects

[0047] According to the silicon carbide semiconductor device and the manufacturing method of the silicon carbide semiconductor device of the present application, the effect of being able to suppress the peeling and the cracking of the barrier metal is exerted. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device of the embodiment.

[0049] Figure 2 is a cross-sectional view shown in a part of Figure 1 .

[0050] Figure 3 is a cross-sectional view showing the state in the manufacturing process of the silicon carbide semiconductor device of the embodiment.

[0051] Figure 4 is a cross-sectional view showing the state in the manufacturing process of the silicon carbide semiconductor device of the embodiment.

[0052] Figure 5 is a cross-sectional view showing the state in the manufacturing process of the silicon carbide semiconductor device of the embodiment.

[0053] Figure 6 is a cross-sectional view showing the state in the manufacturing process of the silicon carbide semiconductor device of the embodiment.

[0054] Figure 7 is a cross-sectional view showing the state in the manufacturing process of the silicon carbide semiconductor device of the embodiment.

[0055] Figure 8This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to an embodiment.

[0056] Figure 9 This is a cross-sectional view showing the state during the manufacturing process of the silicon carbide semiconductor device according to an embodiment.

[0057] Figure 10 This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0058] Figure 11 It is a schematic cross-sectional view showing the state obtained by observing the interlayer insulating film and barrier metal of a conventional silicon carbide semiconductor device.

[0059] Symbol Explanation

[0060] 1:n - 1: p-type drift region, 2: p-type base region, 3: n-type base region + Source region, 4:p + Type contact area, 5: trench, 6: gate insulating film, 7: gate electrode, 7a: recess on the upper surface of the gate electrode, 8: first insulating layer, 9: second insulating layer, 10: interlayer insulating film, 10a: first recess on the upper surface of the interlayer insulating film, 10b: second recess at the upper end of the side surface of the interlayer insulating film, 10c: first flat surface on the upper surface of the interlayer insulating film, 10d: side surface (second flat surface) of the interlayer insulating film, 10e-10g: convex portions on the surface of the interlayer insulating film 10, 11: nickel silicide film, 12: barrier metal, 13: Al metal electrode layer, 14: source electrode, 15: contact hole, 15a: first trench formed in the interlayer insulating film, 15b: second trench formed in the interlayer insulating film, 16: n + Type drain region, 17: drain electrode, 20: semiconductor substrate, 21: n + Type-starting substrate, 22:n - 23: p-type epitaxial layer; 30: silicon carbide semiconductor device; 41: polysilicon layer; 42: resist film; d1: depth of the recess on the upper surface of the gate electrode; d2: depth of the first recess on the upper surface of the interlayer insulating film; d3: depth of the second recess on the upper surface of the interlayer insulating film; d10: total thickness of the interlayer insulating film; d11: thickness of the first insulating layer; d12: thickness of the second insulating layer; d13: thickness of the Al metal electrode layer; w1, w2: lateral opening width of the contact hole and trench arrangement; w11: lateral opening width of the resist film (etching mask) and trench arrangement; X: lateral direction parallel to the front side of the semiconductor substrate and orthogonal to the trench arrangement direction; Y: lateral direction of the trench arrangement; Z: depth direction; θ1~θ3: angle of the apex of the protrusion on the surface of the interlayer insulating film. Detailed Implementation

[0061] Hereinafter, preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers or regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols for n or p respectively indicate that the impurity concentration is higher and lower than that of layers or regions without + and - symbols. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used to denote the same components, and repeated descriptions are omitted.

[0062] (Implementation Method)

[0063] The structure of the silicon carbide semiconductor device described in the embodiment is explained. Figure 1 This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. Figure 2 It is magnification Figure 1 A cross-sectional view shown as a part of the whole. Figure 2 The image schematically illustrates observation using a scanning electron microscope. Figure 1 The state obtained by the interlayer insulating film 10 and barrier metal 12 on the semiconductor substrate (semiconductor chip) 20. Figure 2 In the text, the internal parts of the semiconductor substrate 20, except for the trench gate, are omitted.

[0064] Figure 1 , Figure 2 The silicon carbide semiconductor device 30 of the illustrated embodiment is a vertical trench-gate SiC-MOSFET with a conventional trench gate on the front side of a semiconductor substrate 20 made of silicon carbide, and has three recesses (one first recess 10a and two second recesses 10b described later) on the surface of the interlayer insulating film 10 covering the gate electrode 7. The trench gate includes the trench 5, the gate insulating film 6, and the gate electrode 7, which will be described later.

[0065] Inside the semiconductor substrate 20, n is provided - Type-shifting region (first semiconductor region) 1. On the front side of semiconductor substrate 20, with n - Between type drift region 1 and n - A p-type base region (second semiconductor region) 2 is disposed at the contact ground of the p-type drift region 1. Between the front side of the semiconductor substrate 20 and the p-type base region 2, n-type base regions are selectively disposed at the contact ground of the p-type base region 2. + Source region (third semiconductor region) 3 and p + Type 4 contact area.

[0066] n + Type source region 3 and p + The contact area 4 is exposed on the front side of the semiconductor substrate 20. Alternatively, the contact area 4 may not be provided. + Type contact area 4. Without setting p +In the case of contact region 4, p-type base region 2 replaces p. + Type contact area 4 is exposed on the front side of semiconductor substrate 20. + The depth of the source region 3, measured from the front side of the semiconductor substrate 20, is, for example, about 0.5 μm.

[0067] The semiconductor substrate 20 can be made of silicon carbide. + n are sequentially stacked on the type starting substrate 21. - An epitaxial substrate is fabricated from epitaxial layers 22 and 23 of the p-type drift region 1 and the p-type base region 2. In this case, n + Type source region 3 and p + The contact regions 4 are respectively disposed on the surface region of the p-type epitaxial layer 23, and the portion of the p-type epitaxial layer 23 other than the surface region becomes the p-type base region 2.

[0068] Trench 5 extends from the front side of semiconductor substrate 20 through n + The source region 3 and the p-type base region 2 reach the n-type drift region 1. The upper and lower corners of the trench 5 can be rounded with a predetermined curvature. The upper corner of the trench 5 is the boundary between the front surface of the semiconductor substrate 20 and the sidewall of the trench 5. The lower corner of the trench 5 is the boundary between the bottom surface of the trench 5 and the sidewall.

[0069] Inside the trench 5, a gate insulating film 6 is disposed along the inner wall of the trench 5. The gate insulating film 6 extends from the sidewall of the trench 5 toward the front surface of the semiconductor substrate 20. Inside the trench 5, a gate electrode 7, for example made of polysilicon (poly-Si), is disposed on the gate insulating film 6. On the upper surface of the gate electrode 7 (the contact surface that contacts the interlayer insulating film 10), a recess 7a is formed at approximately the center of the trench 5, extending to the drain side (the bottom surface side of the trench 5).

[0070] The recess 7a on the upper surface of the gate electrode 7 is formed by the polysilicon layer 41 (described later) used to form the gate electrode 7. Figure 3 This is caused by the erosion of the gate electrode 7 along the sidewall of the trench 5, separated from the gate insulating film 6 by n. + The source region 3 can be positioned relative to the source region 3. The depth d1 of the recess 7a on the upper surface of the gate electrode 7 is, for example, more than 0.1 μm and less than 0.5 μm at the deepest part (approximately the center of the trench 5), preferably less than 0.3 μm.

[0071] The interlayer insulating film 10 is a two-layer structure of the first insulating layer 8 and the second insulating layer 9 which are sequentially stacked on the front surface of the semiconductor substrate 20. The first insulating layer 8 does not contain boron (B) and phosphorus (P), or is formed of an insulating material having a very low boron concentration and a very low phosphorus concentration compared with the second insulating layer 9. The second insulating layer 9 is formed of an insulating material containing boron and phosphorus in predetermined concentrations described later. The softening point of the second insulating layer 9 is lower than the softening point of the first insulating layer 8.

[0072] Specifically, the first insulating layer 8 is, for example, an NSG (non-doped silicate glass) film. The first insulating layer 8 has a function of preventing boron and phosphorus in the second insulating layer 9 from diffusing toward the gate electrode 7. The first insulating layer 8 can contain boron and phosphorus diffused from the second insulating layer 9. The first insulating layer 8 covers the upper surfaces of the gate insulating film 6 and the gate electrode 7 on the front surface of the semiconductor substrate 20.

[0073] In a case where the upper surface of the gate electrode 7 is located deeper on the drain side than the upper side corner portion of the trench 5, the first insulating layer 8 also covers the gate insulating film 6 on the surface of the upper side corner portion of the trench 5. The thickness d11 of the first insulating layer 8 is substantially the same on the entire front surface of the semiconductor substrate 20, for example, in the order of 100 nm or more and 300 nm or less. The substantially same thickness means the same thickness within a range including an error allowed due to a process variation.

[0074] The second insulating layer 9 is provided on the first insulating layer 8. The second insulating layer 9 does not contact the gate insulating film 6 and the gate electrode 7. The second insulating layer 9 is, for example, a BPSG film, and has a higher boron concentration and a higher phosphorus concentration than the second insulating layer 109 (see FIG. 2) constituting the interlayer insulating film 110 of the conventional structure (see FIG. 1). Figure 10 and Figure 11 By providing the first insulating layer 8 between the second insulating layer 9 and the gate electrode 7, it is possible to suppress a change in the conductivity of the gate electrode 7 caused by boron and phosphorus in the second insulating layer 9.

[0075] The boron concentration of the second insulating layer 9 can be, for example, in the order of 1 wt% or more and 3 wt% or less, and preferably in the order of 1.6 wt% or more and 2.6 wt% or less. The phosphorus concentration of the second insulating layer 9 can be, for example, in the order of 1 wt% or more and 3 wt% or less, and preferably in the order of 1.5 wt% or more and 2.5 wt% or less. The reason for this is that, by setting the boron concentration and the phosphorus concentration of the second insulating layer 9 in the above-described ranges, the second insulating layer 9 easily flows even if the reflow temperature of the interlayer insulating film 10 is lowered compared with the conventional method.

[0076] In a case where the boron concentration and the phosphorus concentration of the second insulating layer 9 are less than the above lower limit value, it is not possible to lower the reflow temperature of the interlayer insulating film 10 than that of the conventional method. The reason is that, in a case where the boron concentration and the phosphorus concentration of the second insulating layer 9 are less than the above lower limit value, if the reflow temperature of the interlayer insulating film 10 is lower than that of the conventional method, the second insulating layer 9 is difficult to flow, and it is not possible to form the first recessed portion 10a, the second recessed portion 10b, and the first flat surface 10c, the second flat surface 10d described later on the surface of the second insulating layer 9. In a case where the boron concentration and the phosphorus concentration of the second insulating layer 9 exceed the above upper limit value, peeling of the second insulating layer 9 can occur.

[0077] The thickness d12 of the second insulating layer 9 is thicker than the thickness d11 of the first insulating layer 8, and is, for example, in the order of 400 nm or more and 800 nm or less. The total thickness d10 of the interlayer insulating film 10 is in a thickness that can electrically insulate the gate electrode 7 and the source electrode (first electrode) 14, and is, for example, in the order of 800 nm (for example, the thickness d11 of the first insulating layer 8 is in the order of 200 nm, and the thickness d12 of the second insulating layer 9 is in the order of 600 nm). Since the concavo-convex is formed on the front surface of the interlayer insulating film 10 due to the first recessed portion 10a, the second recessed portion 10b, and the convex portions 10e to 10g described later, it is easy to secure the total thickness d10 of the interlayer insulating film 10 for electrically insulating the gate electrode 7 and the source electrode 14.

[0078] On the upper surface of the interlayer insulating film 10, a first recessed portion 10a is provided at a portion opposite to the recessed portion 7a of the upper surface of the lower layer gate electrode 7 in the depth direction Z (i.e., substantially the center of the trench 5), and the first recessed portion 10a is a recessed portion that is left as it is to reflect the recessed portion 7a of the upper surface of the gate electrode 7. The upper surface of the interlayer insulating film 10 is a portion of the contact surface (surface) of the interlayer insulating film 10 that contacts the barrier metal 12, except for the surface (side surface of the interlayer insulating film 10) that becomes the side wall of the contact hole 15.

[0079] Reference Signs List Figure 1 At the boundary between the upper surface of the interlayer insulating film 10 and the side surface of the interlayer insulating film 10 (hereinafter, referred to as the upper end of the side surface of the interlayer insulating film 10), a second recessed portion 10b is formed on the surface of the second insulating layer 9, and the second recessed portion 10b is a downward convex arc-shaped recessed portion that is formed by removing the upper end of the side surface of the interlayer insulating film 10 in a fan shape in a cross-sectional view. The second recessed portion 10b is formed by retaining the side wall and the bottom corner of the first groove 15a (see Figure 8 ) formed in the second insulating layer 9 by isotropic etching described later. The bottom corner of the first groove 15a is the boundary between the bottom surface and the side wall of the first groove 15a.

[0080] Further, for example, refer to Figure 2The second recess 10b of the side upper end of the interlayer insulating film 10 can be a shape in which the side upper end of the interlayer insulating film 10 is chamfered by a depth d3 described later. The shape in which the side upper end of the interlayer insulating film 10 is chamfered is, for example, a flat surface having a larger inclination than the side of the interlayer insulating film 10 with respect to the front surface of the semiconductor substrate 20, or a curved surface close to a flat surface having a larger inclination than the side of the interlayer insulating film 10 with respect to the front surface of the semiconductor substrate 20 and slightly convex downward.

[0081] The depth d2 of the first recess 10a of the upper surface of the interlayer insulating film 10 is substantially the same as the depth d1 of the recess 7a of the upper surface of the gate electrode 7. Substantially the same depth means the same depth within a range including an error allowed due to a process variation. The depth d3 of the second recess 10b of the side upper end of the interlayer insulating film 10 is a radius of the circular-arc-shaped second recess 10b, and is a depth of 0.1 μm or more from the upper surface of the interlayer insulating film 10 and 20% or more and 50% or less of the maximum value of the total thickness d10 of the interlayer insulating film 10.

[0082] Between the first recess 10a and the second recess 10b of the upper surface of the interlayer insulating film 10 is a first flat surface 10c that is smoothly continuous with the inner walls of the first recess 10a and the second recess 10b, respectively. The side of the interlayer insulating film 10 is a second flat surface 10d that is smoothly continuous with the inner wall of the second recess 10b of the side upper end of the interlayer insulating film 10. The first recess 10a is substantially parallel to the front surface of the semiconductor substrate 20. The second flat surface 10d can have an inclination with respect to the front surface of the semiconductor substrate 20.

[0083] The convex portions 10e to 10g are formed on the surface of the interlayer insulating film 10 in a substantially triangular cross-sectional shape with the inner walls of the first recess 10a and the second recess 10b and the first flat surface 10c and the second flat surface 10d as one side and with the boundary of the two sides as a vertex. The angles θ1 to θ3 of the vertices of these convex portions 10e to 10g are, for example, obtuse angles of 100° or more. By the first recess 10a and the second recess 10b, the convex portions 10e to 10g with obtuse vertices can be increased on the surface of the interlayer insulating film 10 compared to the conventional structure (see FIG. 1). Figure 11

[0084] Specifically, in the embodiment, three convex portions (indicated by symbols 10e to 10g) are respectively formed between the first recess 10a of the upper surface of the interlayer insulating film 10 and the two sides (second flat surfaces 10d) of the interlayer insulating film 10, and thus six convex portions are formed in total on the surface of the interlayer insulating film 10. On the other hand, in the conventional structure (see FIG. 1), Figure 10 Figure 11 ​​In the interlayer insulating film 110, the surface of the interlayer insulating film 110 is smoothly continuous from the side surface of the interlayer insulating film 110 to the upper surface, and thus there is no convex portion on the surface of the interlayer insulating film 110.

[0085] The larger the angles θ1 to θ3 of the apexes of the convex portions 10e to 10g are, the closer the convex portions are disposed to the trench 5. That is, the angle θ1 of the apex of the convex portion 10e formed by the inner wall of the first recessed portion 10a and the first flat surface 10c is the largest, and can be, for example, an obtuse angle of 110° or more. The angles θ2 of the apexes of the convex portions 10f formed by the first flat surface 10c and the inner wall of the second recessed portion 10b and the angles θ3 of the apexes of the convex portions 10g formed by the inner wall of the second recessed portion 10b and the second flat surface 10d are smaller than the angle θ1 of the apex of the convex portion 10e (θ1 > θ2, θ1 > θ3).

[0086] Thus, by providing the first recessed portion 10a and the second recessed portion 10b separately from each other on the surface of the interlayer insulating film 10, three or more concave-convex portions are repeatedly formed on the surface of the interlayer insulating film 10, the concave-convex portions being caused by the first recessed portion 10a, the second recessed portion 10b, and the convex portions 10e to 10g having apexes at the boundaries between the inner walls of the first recessed portion 10a and the second recessed portion 10b and the first flat surface 10c and the second flat surface 10d. The height difference of the concave-convex portions on the surface of the interlayer insulating film 10 caused by the first recessed portion 10a, the second recessed portion 10b, and the convex portions 10e to 10g corresponds to the depths d2, d3 of the first recessed portion 10a and the second recessed portion 10b on the surface of the interlayer insulating film 10, and is substantially the same as the depth dl of the recessed portion 7a of the upper surface of the gate electrode 7.

[0087] The contact hole 15 is provided which penetrates the interlayer insulating film 10 in the depth direction and reaches the semiconductor substrate 20. In the contact hole 15, the n + type source region 3 and the p + type contact region 4 are exposed. By the second recessed portion 10b which is continuous with the contact hole 15 on the upper end of the side surface of the interlayer insulating film 10, the opening width of the contact hole 15 in the arrangement direction (lateral direction Y) of the trench 5 is wider by one step on the upper end side away from the semiconductor substrate 20 than on the semiconductor substrate 20 side (w1 > w2).

[0088] The source electrode 14 includes a nickel silicide film (first electrode film) 11, a barrier metal (second electrode film) 12, and a metal electrode layer containing aluminum (Al) (Al metal electrode layer: third electrode film) 13. The lowermost nickel silicide film 11 is in ohmic contact with the portion of the front surface of the semiconductor substrate 20 exposed in the contact hole 15 (n + type source region 3 and the p + type contact region 4, or only the p + type contact region 4) to form ohmic contact between the source electrode 14 and the semiconductor substrate 20.

[0089] The barrier metal 12 is provided in a substantially uniform thickness from the surface of the nickel silicide film 11 along the surface of the interlayer insulating film 10, and has a concavo-convex shape reflecting the concavo-convex shape of the surface of the interlayer insulating film 10 caused by the first recessed portion 10a, the second recessed portion 10b, and the convex portions 10e to 10g. The barrier metal 12 has a function of preventing diffusion of aluminum atoms from the Al metal electrode layer 13 toward the semiconductor substrate 20. The barrier metal 12 has a function of preventing mutual reaction between the Al metal electrode layer 13 and the semiconductor substrate 20 in the manufacturing process.

[0090] The barrier metal 12 has a single layer of a titanium (Ti) film or a titanium nitride (TiN) film, or a laminated structure in which these are arbitrarily laminated in multiple layers, and for example, can be a laminated film of a three-layer structure in which a titanium nitride film, a titanium film, and a titanium nitride film are sequentially laminated. The uppermost layer of the Al metal electrode layer 13 is, for example, an aluminum silicon (AlSi) film. The thickness d13 of the Al metal electrode layer 13 is, for example, about 5 μm.

[0091] On the surface region of the back surface of the semiconductor substrate 20, the n + type drain region 16 is provided over the entire region of the back surface of the semiconductor substrate 20. In the case where the semiconductor substrate 20 is the epitaxial substrate described above, the n + type starting substrate 21 becomes the n + type drain region 16. The drain electrode (second electrode) 17 is provided over the entire surface of the back surface of the semiconductor substrate 20. The drain electrode 17 is in ohmic contact with the n + type drain region 16.

[0092] Next, a manufacturing method of the silicon carbide semiconductor device of the embodiment will be described. Figures 3 to 9 is a cross-sectional view showing a state in the manufacturing process of the silicon carbide semiconductor device of the embodiment. First, an n + type starting substrate 21 made of silicon carbide is prepared. An epitaxial layer 22, 23 (see Figure 1 ) is sequentially laminated on the front surface of the n + type starting substrate 21 to produce a semiconductor substrate (semiconductor wafer) 20. The main surface of the semiconductor substrate 20 on the p-type epitaxial layer 23 side is set as the front surface, and the main surface of the semiconductor substrate 20 on the n + type starting substrate 21 side is set as the back surface.

[0093] Next, as shown in Figure 3 , a process group of photolithography and ion implantation is repeatedly performed under different conditions to selectively form an n + type source region 3 and a p + type contact region 4 in the inner portion of the p-type epitaxial layer 23 in the surface region of the front surface of the semiconductor substrate 20. Thus, the p-type epitaxial layer 23 is left with the n + type source region 3 and the p +The portion outside the type contact region 4 becomes the p-type base region 2.

[0094] Next, a through-hole formation is formed from the front side of the semiconductor substrate 20. + The source region 3 and the base region 2 of the p-type reach as n - Type Drift Region 1 n - The trench 5 of the epitaxial layer 22 is formed (first step). Next, a gate insulating film 6 is formed along the front side of the semiconductor substrate 20 and the inner wall of the trench 5 (second step). Next, a polysilicon layer 41 is deposited on the front side of the semiconductor substrate 20 to completely fill the interior of the trench 5 (third step).

[0095] Next, as Figure 4 As shown, the gate insulating film 6 on the front side of the semiconductor substrate 20 is used as an etch stop layer, and the polysilicon layer 41 is etched back until the gate insulating film 6 on the front side of the semiconductor substrate 20 is exposed. Then, the polysilicon layer 41 is over-etched with a predetermined etching amount, and the surface of the polysilicon layer 41 is collapsed inside the trench 5 to a position with a depth d1 lower than the upper surface of the gate insulating film 6 on the front side of the semiconductor substrate 20 (fourth step).

[0096] Thus, the polysilicon layer 41 that serves as the gate electrode 7 is retained only inside the trench 5, and a recess 7a is formed on the upper surface of the gate electrode 7. The etch-back of the polysilicon layer 41 can be, for example, chemical dry etching (CDE), which etches the silicon (polysilicon layer 41) by highly reactive fluorine radicals generated in a plasma of a mixed gas of carbon tetrafluoride (CF4) with oxygen (O2) added.

[0097] Next, as Figure 5 As shown, on the surface of the gate insulating film 6 and the upper surface of the gate electrode 7 on the front side of the semiconductor substrate 20, for example, NSG and BPSG are sequentially deposited as the first insulating layer 8 and the second insulating layer 9 of the interlayer insulating film 10 (fifth process). A depression is formed on the surface (upper surface) of the interlayer insulating film 10, which is formed by reflecting the depression 7a on the upper surface of the gate electrode 7 on the upper surface of the second insulating layer 9. The depression on the surface of the interlayer insulating film 10 is left as a first recess 10a. The depth d2 of the first recess 10a is approximately the same as the depth d1 of the depression 7a on the upper surface of the gate electrode 7.

[0098] Next, as Figure 6 As shown, a resist film 42 is formed on the surface of the interlayer insulating film 10, and an opening is formed in the portion of the resist film 42 corresponding to the formation area of ​​the contact hole 15 (mask forming process). The resist film 42 is formed as a first recess 10a covering the upper surface of the second insulating layer 9. Next, as... Figure 7As shown, the resist film 42 is used as an etching mask, and the interlayer insulating film 10 is selectively removed, for example, by isotropic etching based on CDE, to form a first trench 15a of a predetermined depth d3 on the upper surface of the second insulating layer 9 (first trench formation process).

[0099] At this time, isotropic etching is performed for a predetermined time to form a first groove 15a with a predetermined depth d3 (e.g., about 0.3 μm) on the upper surface of the second insulating layer 9. The isotropic etching of the interlayer insulating film 10 is performed in the depth direction Z, and also in the transverse directions X and Y. Therefore, the interlayer insulating film 10 is etched (side-etched) directly below the resist film 42, and the width of the first groove 15a in the transverse direction Y (opening width w1) is greater than the opening width w11 of the resist film 42 in the transverse direction Y.

[0100] Next, as Figure 8 As shown, the resist film 42 is used as an etching mask, and the interlayer insulating film 10 is selectively removed by anisotropic etching to form a second trench 15b that penetrates the interlayer insulating film 10 from the bottom surface of the first trench 15a along the depth direction Z (second trench formation process). Since anisotropic etching is basically not performed in the transverse X and Y directions, the width of the second trench 15b in the transverse Y direction (opening width w2) is approximately the same as the opening width w11 of the resist film 42 in the transverse Y direction, and is narrower than the width of the first trench 15a in the transverse Y direction (opening width w1).

[0101] Contact holes 15 are formed by these first grooves 15a and second grooves 15b that are continuous along the depth direction Z (sixth step). Due to the difference in the width of the first groove 15a and the second groove 15b in the transverse Y direction, the opening width of the contact hole 15 in the transverse Y direction is wider by a step on the opening side away from the semiconductor substrate 20 than on the semiconductor substrate 20 side. The sidewall and bottom corner of the first groove 15a retained at the upper corner of the contact hole 15 form the second recess 10b at the upper end of the side surface of the interlayer insulating film 10.

[0102] Next, as Figure 9 As shown, the resist film 42 is removed (removal step), and then the second insulating layer 9 is softened and made to flow by heat treatment at a low temperature (reflow temperature) of, for example, below 1000°C, thereby planarizing the interlayer insulating film 10 (reflow) (seventh step). By setting the reflow temperature of the interlayer insulating film 10 to the above range, a first recess 10a, a second recess 10b, a first flat surface 10c, and a second flat surface 10d can be left on the surface of the second insulating layer 9 after the reflow of the interlayer insulating film 10.

[0103] Further, by setting the upper limit value of the reflow temperature of the interlayer insulating film 10 to the above range, the gate electrode 7 is not heated at a temperature exceeding 1000°C, so that deterioration of the gate characteristics can be prevented. Next, by heat treatment, the nickel (Ni) film deposited at the portion of the front surface of the semiconductor substrate 20 exposed at the contact hole 15 is silicidized by reacting with the semiconductor substrate 20, so that a nickel silicide film 11 which is in ohmic contact with the semiconductor substrate 20 is formed (eighth step).

[0104] Next, a barrier metal 12 is formed along the surface of the portion of the front surface of the semiconductor substrate 20 exposed at the contact hole 15 and the surface of the interlayer insulating film 10 (ninth step). On the surface of the interlayer insulating film 10, the first recessed portion 10a and the second recessed portion 10b are formed so as to form the first flat surface 10c and the second flat surface 10d, and the convex portions (first convex portion, second convex portion) 10e to 10g are generated by the first recessed portion 10a, the second recessed portion 10b, and the first flat surface 10c and the second flat surface 10d, so that a plurality of (a total of six) concave-convex portions are formed.

[0105] The contact area between the interlayer insulating film 10 and the barrier metal 12 is increased by the concave-convex portions on the surface of the interlayer insulating film 10 caused by the first recessed portion 10a, the second recessed portion 10b, and the convex portions 10e to 10g. Therefore, by the anchoring effect caused by the concave-convex portions on the surface of the interlayer insulating film 10, the adhesion between the interlayer insulating film 10 and the barrier metal 12 is improved compared to the conventional structure. Further, by the convex portions 10e to 10g on the surface of the interlayer insulating film 10, the total thickness d10 of the interlayer insulating film 10 is easily ensured to be a thickness at which the barrier metal 12 can be electrically insulated from the gate electrode 7.

[0106] Next, by depositing an Al metal electrode layer 13 on the surface of the barrier metal 12 (tenth step), a source electrode 14 composed of the nickel silicide film 11, the barrier metal 12, and the Al metal electrode layer 13 is formed. Next, a drain electrode 17 is formed on the back surface of the semiconductor substrate 20 (the back surface of the n + type drain region 16 of the n + type starting substrate 21). Thereafter, by cutting (dicing) the semiconductor substrate (semiconductor wafer) 20 to singulate it into individual chip shapes (semiconductor chips), the SiC-MOSFET shown in FIG. 1 is completed. Figure 1

[0107] ​As described above, according to the embodiment, the upper surface of the interlayer insulating film has a first recessed portion recessed in correspondence with the recess of the upper surface of the gate electrode. At the boundary between the upper surface and the side surface of the interlayer insulating film 10, a second recessed portion is provided in which the upper end of the side surface of the interlayer insulating film is removed in a fan shape. The surface between the first recessed portion and the second recessed portion of the interlayer insulating film and the surface between the second recessed portion and the semiconductor substrate are flat surfaces. The surface of the interlayer insulating film has three or more recessed and protruded portions repeatedly formed by the first recessed portion, the second recessed portion, and a protruded portion having a vertex at the boundary between the inner wall of the first recessed portion, the inner wall of the second recessed portion, and the first flat surface and the second flat surface.

[0108] The vertex of the protruded portion of the surface of the interlayer insulating film is an obtuse angle, and the interlayer insulating film is planarized as compared with a conventional structure in which only the upper surface of the interlayer insulating film has a first recessed portion (see, for example, FIG. 28 of Patent Document 5). The barrier metal has a recessed and protruded shape reflecting the recessed and protruded shape of the surface of the lower layer interlayer insulating film. Since the barrier metal has a recessed and protruded shape, stress applied to the barrier metal is dispersed. In addition, the adhesion of the interlayer insulating film to the barrier metal is improved by the anchoring effect of the recessed and protruded portions formed on the surface of the interlayer insulating film. Thus, peeling and cracking of the barrier metal can be suppressed.

[0109] Hereinbefore, the present application is not limited to the above-described embodiments, and various changes can be made within the scope of the present application. For example, in the above-described embodiments, a case in which the surface of the interlayer insulating film has a shape in which three recessed and protruded portions are repeatedly formed and the recessed and protruded portions are caused by a first recessed portion, a second recessed portion, and a protruded portion having a vertex at the boundary between the inner wall of the first recessed portion, the inner wall of the second recessed portion, and the first flat surface and the second flat surface is exemplified, but the present application is not limited thereto. As long as the recessed and protruded portions of the surface of the interlayer insulating film have a difference in level within the above-described range, a plurality of recessed portions can be formed on the surface of the interlayer insulating film so that the surface of the interlayer insulating film has a shape in which four or more recessed and protruded portions are repeatedly formed.

[0110] In addition, for example, in the above-described embodiments, a MOSFET is exemplified, but the present application is not limited thereto. The present application can be applied to various semiconductor devices capable of adopting a trench gate structure, such as an IGBT (Insulated Gate Bipolar Transistor) and a diode. In addition, the present application is also applicable to a case in which the conduction type (n-type, p-type) is reversed.

[0111] Industrial Applicability

[0112] As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device of the present application are useful for a power semiconductor device used for a power conversion device, a power supply device for various industrial machines, and the like.

Claims

1. A silicon carbide semiconductor device, characterized by, Possessing: a first semiconductor region of a first conductivity type provided inside a semiconductor substrate; a second semiconductor region of a second conductivity type provided between a first main surface of the semiconductor substrate and the first semiconductor region in contact with the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region in contact with the second semiconductor region; a trench reaching the first semiconductor region from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region; a gate electrode provided inside the trench through a gate insulating film; an interlayer insulating film covering the gate electrode; a contact hole reaching the semiconductor substrate through the interlayer insulating film in a depth direction; a first electrode provided on a surface of the interlayer insulating film and connected to the second semiconductor region and the third semiconductor region inside the contact hole; and a second electrode electrically connected to the first semiconductor region, three or more recesses are provided separately from each other on the surface of the interlayer insulating film, the surface of the interlayer insulating film has a shape in which three or more concavities and convexities are repeated, the concavities and convexities being caused by the recesses and convexities, the convexities having vertices at boundaries between inner walls of the recesses and surfaces of the recesses, the first electrode has: a first electrode film in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole; a second electrode film provided along the surface of the first electrode film and the surface of the interlayer insulating film and containing titanium; and a third electrode film provided on the surface of the second electrode film and containing aluminum, the second electrode film has a concave-convex shape that reflects the concavities and convexities of the surface of the interlayer insulating film caused by the recesses, μ μ The height difference of the concavo-convex caused by the recesses of the surface of the interlayer insulating film is 0.1 Possessing: m above and less than 0.5 a first semiconductor region of a first conductivity type provided inside a semiconductor substrate; m.

2. A silicon carbide semiconductor device, characterized by, a second semiconductor region of a second conductivity type provided between a first main surface of the semiconductor substrate and the first semiconductor region in contact with the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region in contact with the second semiconductor region; a trench reaching the first semiconductor region from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region; a gate electrode provided inside the trench through a gate insulating film; an interlayer insulating film covering the gate electrode; a contact hole reaching the semiconductor substrate through the interlayer insulating film in a depth direction; a first electrode provided on a surface of the interlayer insulating film and connected to the second semiconductor region and the third semiconductor region inside the contact hole; and a second electrode electrically connected to the first semiconductor region, three or more recesses are provided on the surface of the interlayer insulating film, the surface of the interlayer insulating film having a shape in which three or more concavities and convexities caused by the recesses are repeated, ​ ​ ​ The recess closest to the contact hole has a predetermined depth that is smaller than a thickness of the interlayer insulating film, and is continuous with the contact hole, An opening width of the contact hole is wider at a position farther from the semiconductor substrate than at a position closer to the semiconductor substrate through the recess closest to the contact hole, The first electrode has: a first electrode film that is in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole; a second electrode film that is provided along a surface of the first electrode film and a surface of the interlayer insulating film, and contains titanium; and a third electrode film that is provided on a surface of the second electrode film, and contains aluminum, The second electrode film has a concave-convex shape that reflects a concave-convex of the surface of the interlayer insulating film caused by the recess, μ The height difference of the concavo-convex caused by the recesses of the surface of the interlayer insulating film is 0.1 μ m above and less than 0.5 3. The silicon carbide semiconductor device according to claim 1 or 2, wherein m. provided with: The height difference of the concavo-convex caused by the recesses of the surface of the interlayer insulating film is 0.3 a first semiconductor region of a first conductivity type that is provided inside a semiconductor substrate; m or less.

4. A silicon carbide semiconductor device, characterized by, a second semiconductor region of a second conductivity type that is provided between a first main surface of the semiconductor substrate and the first semiconductor region in contact with the first semiconductor region; a third semiconductor region of the first conductivity type that is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region in contact with the second semiconductor region; a trench that reaches the first semiconductor region from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region; a gate electrode that is provided inside the trench through a gate insulating film; an interlayer insulating film that covers the gate electrode; a contact hole that reaches the semiconductor substrate through the interlayer insulating film in a depth direction; a first electrode that is provided on a surface of the interlayer insulating film, and is connected to the second semiconductor region and the third semiconductor region inside the contact hole; and a second electrode that is electrically connected to the first semiconductor region, three or more recesses are provided separately from each other on the surface of the interlayer insulating film, the surface of the interlayer insulating film has a shape in which three or more concave-convexes are repeated, the concave-convexes being caused by the recesses and convexes, the convexes having vertices at boundaries of the surfaces between inner walls of the recesses and the recesses, the recesses of the surface of the interlayer insulating film have: a first recess that is provided on an upper surface of the interlayer insulating film, reflecting a depression generated at a contact surface of the gate electrode in contact with the interlayer insulating film; and a second recess that is provided at a boundary between the upper surface of the interlayer insulating film and a side surface of the interlayer insulating film, is continuous with the contact hole, and is depressed in a circular arc shape, the first recess and the second recess are provided separately from each other, a surface of the interlayer insulating film between the first recess and the second recess is a first flat surface, a depth of the second recess is 20% or more and 50% or less of a thickness from the first flat surface of the interlayer insulating film to an upper surface of the gate insulating film on the first main surface of the semiconductor substrate, the first electrode has: ​ ​ ​ ​ a first electrode film that is in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole; a second electrode film that is provided along a surface of the first electrode film and a surface of the interlayer insulating film, and contains titanium; and a third electrode film that is provided to a surface of the second electrode film, and contains aluminum, the second electrode film is in a concave-convex shape that reflects the concave-convex of the surface of the interlayer insulating film caused by the recesses.

5. A silicon carbide semiconductor device, characterized by, provided with: a first semiconductor region of a first conductivity type that is provided inside a semiconductor substrate; a second semiconductor region of a second conductivity type that is provided between a first main surface of the semiconductor substrate and the first semiconductor region in contact with the first semiconductor region; a third semiconductor region of the first conductivity type that is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region in contact with the second semiconductor region; a trench that reaches the first semiconductor region from the first main surface of the semiconductor substrate through the third semiconductor region and the second semiconductor region; a gate electrode that is provided inside the trench through a gate insulating film; an interlayer insulating film that covers the gate electrode; a contact hole that reaches the semiconductor substrate through the interlayer insulating film in a depth direction; a first electrode that is provided to a surface of the interlayer insulating film, and is connected to the second semiconductor region and the third semiconductor region inside the contact hole; and a second electrode that is electrically connected to the first semiconductor region, a surface of the interlayer insulating film is provided with three or more recesses, and the surface of the interlayer insulating film is in a shape in which three or more concave-convexes caused by the recesses are repeated, the recess closest to the contact hole has a predetermined depth that is smaller than a thickness of the interlayer insulating film, and is continuous with the contact hole, an opening width of the contact hole is wider at a position farther from the semiconductor substrate than at a position closer to the semiconductor substrate through the recess closest to the contact hole, the recesses of the surface of the interlayer insulating film have: a first recess that is provided to an upper surface of the interlayer insulating film reflecting a depression generated at a contact surface of the gate electrode in contact with the interlayer insulating film; and a second recess that is provided to a boundary between the upper surface of the interlayer insulating film and a side surface of the interlayer insulating film, is continuous with the contact hole, and is depressed in a circular arc shape, the first recess and the second recess are provided separately from each other, a surface of the interlayer insulating film between the first recess and the second recess is a first flat surface, a depth of the second recess is 20% or more and 50% or less of a thickness from the first flat surface of the interlayer insulating film to an upper surface of the gate insulating film on the first main surface of the semiconductor substrate, the first electrode has: a first electrode film that is in ohmic contact with the second semiconductor region and the third semiconductor region inside the contact hole; a second electrode film that is provided along a surface of the first electrode film and a surface of the interlayer insulating film, and contains titanium; and a third electrode film that is provided to a surface of the second electrode film, and contains aluminum, ​ The second electrode film has a concave-convex shape which reflects the concave-convex of the surface of the interlayer insulating film caused by the recesses.

6. The silicon carbide semiconductor device according to claim 4 or 5, wherein the surface of the interlayer insulating film has first convex portions having a triangular cross-sectional shape with a boundary between the inner wall of the recess and the first flat surface as a vertex, all of the angles of the vertices of the first convex portions are obtuse angles of 100° or more.

7. The silicon carbide semiconductor device according to claim 6, wherein the angle of the vertex of the first convex portion is larger as the first convex portion is disposed closer to the trench.

8. The silicon carbide semiconductor device according to claim 7, wherein the angle of the vertex of the first convex portion disposed closer to the trench is an obtuse angle of 110° or more.

9. The silicon carbide semiconductor device according to claim 6, wherein the side surface of the interlayer insulating film is a second flat surface having a slope with respect to the first main surface of the semiconductor substrate, the surface of the interlayer insulating film has second convex portions having a triangular cross-sectional shape with a boundary between the inner wall of the second recess and the second flat surface as a vertex, the angle of the vertex of the second convex portion is an obtuse angle of 100° or more.

10. The silicon carbide semiconductor device according to claim 9, wherein the angle of the vertex of the second convex portion is smaller than the angle of the vertex of the first convex portion.

11. A method of manufacturing a silicon carbide semiconductor device, characterized by, including: a first step of forming a trench reaching a predetermined depth from a first main surface of a semiconductor substrate; a second step of forming a gate insulating film along the first main surface of the semiconductor substrate and the inner wall of the trench; a third step of depositing a polysilicon layer on the first main surface of the semiconductor substrate and filling the inside of the trench with the polysilicon layer; a fourth step of etching back the polysilicon layer until the gate insulating film on the first main surface of the semiconductor substrate is exposed, leaving only the polysilicon layer as a gate electrode in the inside of the trench; a fifth step of forming an interlayer insulating film covering the gate electrode on the first main surface of the semiconductor substrate; a sixth step of forming a contact hole reaching the semiconductor substrate through the interlayer insulating film in the depth direction; a seventh step of planarizing the interlayer insulating film by heat treatment; an eighth step of forming a first electrode film in ohmic contact with the semiconductor substrate in the inside of the contact hole; a ninth step of forming a second electrode film containing titanium along the surface of the first electrode film and the surface of the interlayer insulating film; and a tenth step of forming a third electrode film containing aluminum on the surface of the second electrode film, μ In the fourth process, a surface of the gate electrode is made to have a recess of a depth of 0.1 μ more than 0.5 in the fifth step, leaving first recesses on the surface of the interlayer insulating film which reflect the depressions of the surface of the gate electrode, m the sixth step includes: a mask forming step of forming an etching mask having a portion opened corresponding to the formation region of the contact hole on the surface of the interlayer insulating film; a first groove forming step of forming a first groove having a predetermined depth from the surface of the interlayer insulating film by isotropic etching using the etching mask, ​ a second trench formation step of forming a second trench that penetrates the interlayer insulating film in a depth direction from a bottom surface of the first trench by anisotropic etching using the etching mask; and a removal step of removing the etching mask.

12. A method of manufacturing a silicon carbide semiconductor device, characterized by comprises: a first step of forming a trench reaching a predetermined depth from a first main surface of a semiconductor substrate; a second step of forming a gate insulating film along the first main surface of the semiconductor substrate and an inner wall of the trench; a third step of depositing a polysilicon layer on the first main surface of the semiconductor substrate and filling an inside of the trench with the polysilicon layer; a fourth step of etching back the polysilicon layer until the gate insulating film on the first main surface of the semiconductor substrate is exposed, leaving only the polysilicon layer as a gate electrode in the inside of the trench; a fifth step of forming an interlayer insulating film covering the gate electrode on the first main surface of the semiconductor substrate; a sixth step of forming a contact hole that penetrates the interlayer insulating film in a depth direction to reach the semiconductor substrate; a seventh step of planarizing the interlayer insulating film by heat treatment; an eighth step of forming a first electrode film that is in ohmic contact with the semiconductor substrate in the inside of the contact hole; a ninth step of forming a second electrode film containing titanium along a surface of the first electrode film and a surface of the interlayer insulating film; a tenth step of forming a third electrode film containing aluminum on a surface of the second electrode film, in the fourth step, the surface of the gate electrode is recessed, in the fifth step, a first recessed portion that reflects the recess of the surface of the gate electrode is left on a surface of the interlayer insulating film, the sixth step includes: a mask formation step of forming an etching mask that is partially opened corresponding to a formation region of the contact hole on the surface of the interlayer insulating film; a first trench formation step of forming a first trench of a predetermined depth from a surface of the interlayer insulating film by isotropic etching using the etching mask; a second trench formation step of forming a second trench that penetrates the interlayer insulating film in a depth direction from a bottom surface of the first trench by anisotropic etching using the etching mask; and a removal step of removing the etching mask, in the first trench formation step, the predetermined depth of the first trench is set to 20% or more and 50% or less of a thickness from a surface of a portion of the interlayer insulating film other than the first recessed portion to an upper surface of the gate insulating film on the first main surface of the semiconductor substrate.

13. The method according to claim 11 or 12, wherein in the fifth step, a first insulating layer and a second insulating layer are sequentially stacked as the interlayer insulating film, a boron concentration and a phosphorus concentration of the second insulating layer are higher than those of the first insulating layer, the boron concentration of the second insulating layer is 1 wt% or more and 3 wt% or less, and the phosphorus concentration of the second insulating layer is 1 wt% or more and 3 wt% or less, in the first trench formation step, the first trench is formed in the second insulating layer, In the second groove forming step, the second groove is formed which penetrates the second insulating layer and the first insulating layer in a depth direction from a bottom surface of the first groove, In the seventh step, the temperature of the heat treatment is set to 1000°C or lower.

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