A gating tube with a superlattice-like structure and a preparation method thereof

Abstract

The present invention discloses a gate tube with a superlattice-like structure and a preparation method thereof, belonging to the field of micro-nanoelectronic technology. The gate tube includes a substrate, and a first metal electrode layer, a superlattice-like layer and a second metal electrode layer stacked on the substrate in sequence, the superlattice-like layer includes n+1 first sublayers and n second sublayers stacked alternately in a periodic manner, the material of the first sublayer is amorphous carbon, and the material of the second sublayer is a sulfur compound with a gating property. The amorphous carbon of the first sublayer contacts the first metal electrode layer and the second metal electrode layer as a buffer layer, which can prevent atomic drift in the sulfur compound material with a gating property caused by high temperature, and can also avoid cross contamination by introducing new materials. Due to the low thermal conductivity of amorphous carbon, the gate tube of the present application can not only ensure that the threshold voltage of the gate tube is not affected, but also make the heat diffused to the gate tube unit when the phase change material melts smaller after integration with the phase change memory unit.

Description

Technical Field

[0001] The invention relates to the field of micro-nanoelectronic technology, and in particular to a gating tube with a superlattice-like structure and a preparation method thereof. Background Art

[0002] With the vigorous development of big data, cloud computing and the Internet of Things industry, accompanied by the explosive growth of massive information and the ever-expanding market demand, efficient storage and convenient transmission of data are strict requirements for storage technology in the contemporary era, and various new high-performance storage technologies have also emerged. Among them, phase change storage technology has been widely recognized in the industry because of its relatively mature material system, simple preparation process, good compatibility with CMOS, high device reliability, and advantages in speed and service life.

[0003] There is a leakage current problem in phase change memory. The gate current may flow through the surrounding units and affect the reliability of the device, so each storage unit must be connected to a gate tube. Since the phase change material changes from crystalline to amorphous state, the gate tube needs to provide a large enough reset current to heat it to a certain temperature. In this process, the atoms in the sulfur compound material with gate performance in the gate tube will drift due to the high temperature, which will cause the gate tube to fail. Summary of the invention

[0004] In order to improve the temperature stability of the gate tube, an embodiment of the present invention provides a gate tube with a superlattice-like structure and a preparation method thereof. The technical solution is as follows:

[0005] On the one hand, an embodiment of the present invention provides a gate tube with a superlattice-like structure, the gate tube comprising a substrate, and a first metal electrode layer, a superlattice-like layer and a second metal electrode layer stacked in sequence on the substrate, the superlattice-like layer comprising n+1 first sublayers and n second sublayers stacked periodically and alternately, the material of the first sublayer is amorphous carbon, and the material of the second sublayer is a sulfur compound with gating properties.

[0006] Optionally, the first sublayer has a thickness of 5-30 nm.

[0007] Optionally, the second sublayer has a thickness of 5-20 nm.

[0008] Optionally, the number n of alternating stacking cycles of the first sub-layer and the second sub-layer is 5-20.

[0009] Optionally, the first metal electrode layer and the second metal electrode layer are both inert electrodes, and the materials of the inert metal electrode layers include: Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2, at least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 An alloy material composed of any two or more of ITO, ITO and IZO.

[0010] On the other hand, an embodiment of the present invention further provides a method for preparing a gate tube having a superlattice-like structure, the method comprising:

[0011] providing a substrate;

[0012] preparing a first metal electrode layer on the substrate;

[0013] A quasi-superlattice layer is prepared on the first metal electrode layer, wherein the quasi-superlattice layer includes n+1 first sublayers and n second sublayers which are periodically and alternately stacked, wherein the material of the first sublayer is amorphous carbon, and the material of the second sublayer is a sulfur compound having a gating property;

[0014] A second metal electrode layer is prepared on the superlattice-like layer.

[0015] Optionally, preparing a superlattice-like layer on the first metal electrode layer comprises:

[0016] The first sub-layer and the second sub-layer are sequentially deposited on the first metal electrode layer until the number of alternating stacking cycles n is completed.

[0017] Optionally, the deposition includes physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition or metal organic deposition.

[0018] Optionally, the first sublayer has a thickness of 5-30 nm.

[0019] Optionally, the second sublayer has a thickness of 5-20 nm.

[0020] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0021] (1) The amorphous carbon of the first sublayer is in contact with the first metal electrode layer and the second metal electrode layer as a buffer layer. Since the radius of carbon atoms in amorphous carbon is very small, the bond length formed between them is very small, which is smaller than the diameter of atoms in the sulfur compound. The atoms in the sulfur compound cannot pass through the amorphous carbon layer, thereby preventing the atomic drift in the sulfur compound material with gating performance caused by high temperature, and avoiding cross contamination by introducing new materials. At the same time, compared with the gating tube of the switching material of the same thickness, due to the low thermal conductivity of amorphous carbon, the gating tube of the present application can not only ensure that the threshold voltage of the gating tube is not affected, but also make the heat diffused to the gating tube unit when the phase change material melts smaller after integration with the phase change memory unit.

[0022] (2) Due to the inhibition of crystallization, the thinner the thickness of the sulfur compound, the more stable its bonding. The insertion of the amorphous carbon layer of the first sub-layer separates the sulfur compound with gating performance in the thickness direction, so that the thickness of the second sub-layer 132 is only 5 to 20 nm, so that the sulfur compound of the second sub-layer has good temperature stability, thereby improving the temperature stability of the entire gating tube unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a schematic structural diagram of a gating tube having a superlattice-like structure provided by an embodiment of the present invention;

[0025] Figure 2 It is a flow chart of a method for preparing a gating tube having a superlattice-like structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0027] The embodiment of the present invention provides a gate tube having a superlattice-like structure. Figure 1 is a schematic diagram of the structure of a gate tube having a superlattice-like structure provided by an embodiment of the present invention, such as Figure 1 shown.

[0028] A gate tube with a superlattice-like structure, the gate tube includes a substrate 110, and a first metal electrode layer 120, a superlattice-like layer 130 and a second metal electrode layer 140 stacked in sequence on the substrate 110, the superlattice-like layer 130 includes n+1 first sublayers 131 and n second sublayers 132 that are periodically and alternately stacked, the material of the first sublayer 131 is amorphous carbon, and the material of the second sublayer 132 is a sulfur compound with a gating property.

[0029] The amorphous carbon of the first sublayer acts as a buffer layer in contact with the first metal electrode layer and the second metal electrode layer. Since the radius of carbon atoms in amorphous carbon is very small, the bond length formed between them is very small, which is smaller than the diameter of atoms in sulfur compounds. The atoms in sulfur compounds cannot pass through the amorphous carbon layer, thereby preventing atomic drift in sulfur compound materials with gating properties caused by high temperature, and avoiding cross contamination by introducing new materials. At the same time, compared with the gating tube of the switching material of the same thickness, due to the low thermal conductivity of amorphous carbon, the gating tube of the present application can not only ensure that the threshold voltage of the gating tube is not affected, but also make the heat of the phase change material melting and diffusing to the gating tube unit smaller when integrated with the phase change memory unit.

[0030] It can be understood that the sulfur-based compound with gating properties in the second sublayer refers to a sulfur-based compound that can achieve an instantaneous transition from a high resistance state to a low resistance state under an electrical signal operation, and instantly and spontaneously returns to the high resistance state when the electrical signal operation is removed.

[0031] In some implementations, the chalcogenide compound with gating performance may be a compound composed of one of the first elements (Si, Ge, Sn) and one or two of the second elements (S, Se, Te), specifically, GeTe, GeS, SiTe, SnTe, SnSe, GeSeTe, etc.

[0032] Optionally, the thickness of the first sublayer 131 may be 5-30 nm to obtain a better buffering effect and prevent atomic drift in the chalcogenide material with gating performance caused by high temperature.

[0033] Optionally, the number n of alternating stacking cycles of the first sub-layer and the second sub-layer is 5-20.

[0034] Optionally, the thickness of the second sublayer 132 may be 5 to 20 nm. Due to the suppression of crystallization, the thinner the thickness of the sulfur-based compound, the more stable its bonding. Due to the insertion of the amorphous carbon layer of the first sublayer 131, the sulfur-based compound with gating performance is separated in the thickness direction, so that the thickness of the second sublayer 132 is only 2 to 20 nm, so that the sulfur-based compound of the second sublayer has good temperature stability, thereby improving the temperature stability of the entire gating tube unit.

[0035] Optionally, the thickness of the first sublayer 131 is greater than the thickness of the second sublayer 132 , so as to better physically and thermally separate the sulfur-based compounds having gating properties.

[0036] Optionally, the number of alternating stacking cycles n of the first sublayer 131 and the second sublayer 132 is 5 to 20. This makes the coupling between adjacent wells stronger, forms periodic quantum potential wells in the superlattice-like layer 130, and expands the discrete energy levels in each quantum well into an energy band, thereby reducing the band gap width, so that the threshold voltage of the gate tube with the superlattice-like layer 130 is lower, which can not only reduce power consumption, but also better integrate with the storage device unit.

[0037] Optionally, the first metal electrode layer 120 and the second metal electrode layer 140 are both inert metal electrode layers. Since it is difficult for the inert metal in the inert metal electrode layer to combine with other elements, on the one hand, it can effectively prevent the active metal conductive particles in the superlattice layer 130 from diffusing into the electrode, thereby improving the cycle characteristics of the device; on the other hand, it can also effectively prevent the device failure caused by oxidation or corrosion of the inert metal electrode layer.

[0038] Preferably, the material of the inert metal electrode layer includes: Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , at least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 An alloy material composed of any two or more of ITO, ITO and IZO.

[0039] The embodiment of the present invention provides a method for preparing a gate tube having a superlattice-like structure. Figure 2 is a flow chart of a method for preparing a gate tube having a superlattice-like structure provided by an embodiment of the present invention, such as Figure 2 As shown, the method includes:

[0040] providing a substrate;

[0041] preparing a first metal electrode layer on a substrate;

[0042] A superlattice-like layer is prepared on the first metal electrode layer, wherein the superlattice-like layer includes n+1 first sublayers and n second sublayers which are periodically and alternately stacked, wherein the material of the first sublayer is amorphous carbon, and the material of the second sublayer is a sulfur compound with gating performance;

[0043] A second metal electrode layer is formed on the superlattice-like layer.

[0044] Specifically, the method may include:

[0045] S11: providing a substrate.

[0046] In this embodiment, the substrate may be a semiconductor substrate. Specifically, the semiconductor substrate may be a semiconductor substrate having a crystal phase of <100> , a silicon wafer with a layer of silicon dioxide on the surface.

[0047] When implementing, the substrate can be cleaned first, and the silicon wafer can be placed in acetone and alcohol for ultrasonic cleaning for about ten minutes; after the ultrasonic cleaning, the residual liquid on the surface can be blown away with a nitrogen gun and dried for later use. On the cleaned silicon wafer, a dense layer of silicon dioxide is grown using plasma enhanced chemical vapor deposition or atomic layer deposition.

[0048] S12: preparing a first metal electrode layer on the substrate;

[0049] Specifically, the first metal electrode layer is an inert metal electrode layer, and the material of the inert metal electrode layer includes: Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , at least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 An alloy material composed of any two or more of ITO, ITO and IZO.

[0050] During implementation, a 100 nm thick Pt metal layer may be deposited on the substrate by magnetron sputtering as the first metal electrode layer.

[0051] S13: depositing a quasi-superlattice layer on the first metal electrode layer, the quasi-superlattice layer comprising n+1 first sublayers and n second sublayers that are periodically and alternately stacked, the material of the first sublayer is amorphous carbon, and the material of the second sublayer is a sulfur compound with gating performance;

[0052] Specifically, the first sublayer and the second sublayer are sequentially deposited on the first metal electrode layer until the number of alternating stacking cycles n is completed, where n is a positive integer. The deposition may include forming the first sublayer or the second sublayer by physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition or metal organic deposition process.

[0053] It can be understood that the sulfur-based compound with gating properties in the second sublayer refers to a sulfur-based compound that can achieve an instantaneous transition from a high resistance state to a low resistance state under an electrical signal operation, and instantly and spontaneously returns to the high resistance state when the electrical signal operation is removed.

[0054] In some implementations, the chalcogenide compound with gating performance may be a compound composed of one of the first elements (Si, Ge, Sn) and one or two of the second elements (S, Se, Te), specifically, GeTe, GeS, SiTe, SnTe, SnSe, GeSeTe, etc.

[0055] Preferably, the number n of alternating stacking periods of the first sublayer and the second sublayer in the superlattice-like layer is 5-20.

[0056] Optionally, the thickness of the first sublayer may be 5-30 nm to obtain a better buffering effect and prevent atomic drift in the chalcogenide material with gating performance caused by high temperature.

[0057] Optionally, the thickness of the second sublayer can be 5 to 20 nm. When the thickness of the second sublayer is thinner, its bonding is more stable, so that the gate tube has better temperature stability. Due to the insertion of the amorphous carbon layer in the first sublayer, the sulfur-based compounds with gating performance are separated in the thickness direction, so that the thickness of the second sublayer is only 5 to 20 nm, so that the sulfur-based compounds in the second sublayer have good temperature stability, thereby improving the temperature stability of the entire gate tube unit.

[0058] When implemented, an amorphous carbon material layer with a thickness of 5 nm can be deposited on the first metal electrode layer as the first sublayer; then a GeS material layer with a thickness of 5 nm can be grown as the second sublayer; then an amorphous carbon material layer-GeS material layer-amorphous carbon material layer-…-GeS-amorphous carbon material layer can be grown alternately to form a quasi-superlattice layer. The quasi-superlattice layer includes n+1 amorphous carbon material layers and n GeS material layers.

[0059] The amorphous carbon of the first sublayer is in contact with the first metal electrode layer and the second metal electrode layer as a buffer layer, which can prevent atomic drift in the sulfur compound material with gating performance caused by high temperature, and can also avoid cross contamination by introducing new materials. At the same time, compared with the gating tube of the switching material of the same thickness, the gating tube of the present application can not only ensure that the threshold voltage of the gating tube is not affected, but also, due to the low thermal conductivity of amorphous carbon, when integrated with the phase change memory unit, the heat of the phase change material melting and diffusing to the gating tube unit is smaller.

[0060] S14: preparing a second metal electrode layer on the superlattice-like layer.

[0061] A second metal electrode layer is prepared on the superlattice-like layer. Specifically, the second metal electrode layer is an inert metal electrode layer, and the materials of the inert metal electrode layer include: Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , at least one of ITO and IZO, or Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 An alloy material composed of any two or more of ITO, ITO and IZO.

[0062] During implementation, a 100 nm thick W metal layer may be formed on the superlattice-like layer by magnetron sputtering as the second metal electrode layer.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A gate tube having a superlattice-like structure, characterized in that: The gating tube includes a substrate, and a first metal electrode layer, a quasi-superlattice layer and a second metal electrode layer stacked in sequence on the substrate, the quasi-superlattice layer includes n+1 first sublayers and n second sublayers stacked periodically and alternately, the material of the first sublayer is amorphous carbon, the material of the second sublayer is a sulfur compound with gating performance, wherein the thickness of the second sublayer is 5~20nm; n is a positive integer.

2. The gating tube according to claim 1, characterized in that: The thickness of the first sublayer is 5-30 nm.

3. The gating tube according to claim 1, characterized in that: The number n of alternating stacking cycles of the first sub-layer and the second sub-layer is 5-20.

4. The gating tube according to any one of claims 1 to 3, characterized in that: The first metal electrode layer and the second metal electrode layer are both inert electrodes, and the material of the inert electrodes includes: at least one of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO, or an alloy material composed of any two or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO2, ITO and IZO.

5. A method for preparing a gate tube having a superlattice-like structure, characterized in that: The preparation method comprises: providing a substrate; preparing a first metal electrode layer on the substrate; A superlattice-like layer is prepared on the first metal electrode layer, wherein the superlattice-like layer comprises n+1 first sublayers and n second sublayers which are periodically and alternately stacked, wherein the material of the first sublayer is amorphous carbon, and the material of the second sublayer is a sulfur compound having a gating property; n is a positive integer; A second metal electrode layer is prepared on the superlattice-like layer.

6. The preparation method according to claim 5, characterized in that: Preparing a superlattice-like layer on the first metal electrode layer, comprising: The first sub-layer and the second sub-layer are sequentially deposited on the first metal electrode layer until the number of alternating stacking cycles n is completed.

7. The preparation method according to claim 6, characterized in that: The deposition includes physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, atomic layer deposition or metal organic deposition.

8. The preparation method according to any one of claims 5 to 7, characterized in that: The thickness of the first sublayer is 5-30 nm.

9. The preparation method according to any one of claims 5 to 7, characterized in that: The thickness of the second sublayer is 5-20 nm.

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