A bandgap reference circuit for ultra-low voltage scenarios

Abstract

The present invention discloses a bandgap reference circuit applied to ultra-low voltage scenarios, including: a first startup circuit, a second startup circuit and a core circuit; the first startup circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a resistor R1; the source of M1, the source of M2 and the drain of M3 are all connected to a power supply; the gate of M1, the gate of M2 and the source of M3 are connected to each other, and are connected in series with R1 and then grounded; the drain of M1, the drain of M2 and the gate of M3 are all connected to the core circuit; the second startup circuit includes a fourth MOS tube M4, a fifth MOS tube M5, a triode J1 and a comparator U1; the in-phase input terminal of U1 is connected to the drain of M4 and the emitter of J1 respectively; the base and collector of J1 are connected and then grounded; the inverting input terminal of U1 is connected to the core circuit, and the output terminal is connected to the gate of M5; the source of M5 is grounded, and the drain is connected to the gate of M4; the source of M4 is connected to the power supply. The present invention can work in a working voltage scenario of 1V or even lower.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly to a bandgap reference circuit applied to ultra-low voltage scenarios. Background Art

[0002] With the rise of smart IoT, ultra-low voltage chips are widely used in various scenarios such as IoT RF, battery management, sensor front end and energy harvesting. As a general analog technology, the working principle of the bandgap reference circuit is: based on the temperature-independent characteristics of the bandgap voltage of silicon materials, the negative temperature coefficient of the base-emitter voltage of the bipolar transistor and the positive temperature coefficient of the difference between the base-emitter voltages of the two bipolar transistors at different current densities are used to compensate each other, so that the output voltage reaches a very low temperature drift. The bandgap reference circuit of the existing technology usually requires a higher voltage, about higher than 1.5V, to generate a reference voltage output of about 1.2V, which cannot adapt to ultra-low voltage scenarios below 1.0V.

[0003] Therefore, how to provide a bandgap reference circuit that can operate at an operating voltage of 1V or even lower is a problem that those skilled in the art need to solve urgently. Summary of the invention

[0004] In view of this, the present invention provides a bandgap reference circuit applied to ultra-low voltage scenarios, which can operate in operating voltage scenarios of 1V or even lower.

[0005] In order to achieve the above object, the present invention adopts the following technical solution:

[0006] A bandgap reference circuit applied to an ultra-low voltage scenario, comprising: a first startup circuit, a second startup circuit and a core circuit connected in sequence;

[0007] The first startup circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a resistor R1; the source of the first MOS tube M1, the source of the second MOS tube M2 and the drain of the third MOS tube M3 are all connected to the power supply; the gate of the first MOS tube M1, the gate of the second MOS tube M2 and the source of the third MOS tube M3 are connected to each other, connected in series with the resistor R1 and then grounded; the drain of the first MOS tube M1, the drain of the second MOS tube M2 and the gate of the third MOS tube M3 are all connected to the core circuit;

[0008] The second startup circuit includes a fourth MOS tube M4, a fifth MOS tube M5, a transistor J1 and a comparator U1; the non-inverting input terminal of the comparator U1 is respectively connected to the drain of the fourth MOS tube M4 and the emitter of the transistor J1; the base and collector of the transistor J1 are connected and then grounded; the inverting input terminal of the comparator U1 is connected to the core circuit, and the output terminal is connected to the gate of the fifth MOS tube M5; the source of the fifth MOS tube M5 is grounded, and the drain is connected to the gate of the fourth MOS tube M4; the source of the fourth MOS tube M4 is connected to the power supply.

[0009] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the core circuit includes a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, an operational amplifier U2, a transistor J2 and a transistor J3; wherein the non-inverting input terminal of the operational amplifier U2 is respectively connected to the inverting input terminal of the comparator U1 and the emitter of the transistor J2; the base and the collector of the transistor J2 are both grounded; the inverting input terminal of the operational amplifier U2 is respectively connected to the emitter of the transistor J3, the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2; the base and the collector of the transistor J3 are both grounded; the output terminal of the operational amplifier U1 is respectively connected to the gate of the third MOS transistor M3, the gate of the fourth MOS transistor M4, the drain of the fifth MOS transistor M5, the gate of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8; the drain of the sixth MOS transistor M6, the drain of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are all connected to the power supply.

[0010] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the core circuit also includes: a resistor R2, a resistor R3, a resistor R4 and a resistor R5; one end of the resistor R2 is grounded, and the other end is respectively connected to the inverting input end of the comparator U1 and the non-inverting input end of the operational amplifier U2; one end of the resistor R3 is connected to the emitter of the transistor J2, and the other end is respectively connected to the inverting input end of the comparator U1, the non-inverting input end of the operational amplifier U2 and the drain of the eighth MOS tube M8; one end of the resistor R4 is grounded, and the other end is respectively connected to the inverting input end of the operational amplifier U2 and the drain of the first MOS tube M1; one end of the resistor R5 is grounded, and the other end is connected to the source of the sixth MOS tube M6.

[0011] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the third MOS tube M3 is composed of four PMOS tubes connected in parallel.

[0012] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the fourth MOS transistor M4 is composed of 7 PMOS transistors connected in parallel.

[0013] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the sixth MOS transistor M6 is composed of four PMOS transistors connected in parallel.

[0014] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the seventh MOS transistor M7 is composed of four PMOS transistors connected in parallel.

[0015] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the eighth MOS transistor M8 is composed of 6 PMOS transistors connected in parallel.

[0016] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the transistor J1 is composed of 27 transistors connected in parallel.

[0017] Preferably, in the above-mentioned bandgap reference circuit applied to an ultra-low voltage scenario, the transistor J2 is composed of 8 transistors connected in parallel.

[0018] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a bandgap reference circuit for use in ultra-low voltage scenarios, and the beneficial effects of the present invention are as follows:

[0019] 1. The present invention combines the first startup circuit with the second startup circuit so that the low voltage reference can work normally during power on and power off and normal operation. The circuits of the first startup circuit and the second startup circuit and their combination need to be protected.

[0020] 2. The operating voltage of the core circuit of the present invention is the sum of the operating voltage (0.7) of the transistors J2 and J3 and the Vdsat (0.1) of the PMOS tube, which can work at about 0.8V, meeting the voltage requirement of the low-voltage reference. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0022] Figure 1 The accompanying drawing is a schematic diagram of the structure of the reference circuit provided by the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] like Figure 1 As shown, an embodiment of the present invention discloses a bandgap reference circuit applied to an ultra-low voltage scenario, comprising: a first startup circuit, a second startup circuit and a core circuit connected in sequence;

[0025] The first startup circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a resistor R1; the source of the first MOS tube M1, the source of the second MOS tube M2 and the drain of the third MOS tube M3 are all connected to the power supply; the gate of the first MOS tube M1, the gate of the second MOS tube M2 and the source of the third MOS tube M3 are connected to each other, connected in series with the resistor R1 and then grounded; the drain of the first MOS tube M1, the drain of the second MOS tube M2 and the gate of the third MOS tube M3 are all connected to the core circuit;

[0026] The second startup circuit includes a fourth MOS tube M4, a fifth MOS tube M5, a transistor J1 and a comparator U1; the non-inverting input terminal of the comparator U1 is respectively connected to the drain of the fourth MOS tube M4 and the emitter of the transistor J1; the base and collector of the transistor J1 are connected and then grounded; the inverting input terminal of the comparator U1 is connected to the core circuit, and the output terminal is connected to the gate of the fifth MOS tube M5; the source of the fifth MOS tube M5 is grounded, and the drain is connected to the gate of the fourth MOS tube M4; the source of the fourth MOS tube M4 is connected to the power supply.

[0027] The core circuit includes a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, an operational amplifier U2, a triode J2, a triode J3, a resistor R2, a resistor R3, a resistor R4 and a resistor R5; wherein, the non-inverting input terminal of the operational amplifier U2 is respectively connected to the inverting input terminal of the comparator U1 and the emitter of the triode J2; the base and the collector of the triode J2 are both grounded; the inverting input terminal of the operational amplifier U2 is respectively connected to the emitter of the triode J3, the drain of the first MOS tube M1 and the drain of the second MOS tube M2; the base and the collector of the triode J3 are both grounded; the output terminal of the operational amplifier U1 is respectively connected to the gate of the third MOS tube M3, the gate of the fourth MOS tube M4, the drain of the fifth MOS tube M5, the gate of the sixth MOS tube M6, the gate of the seventh MOS tube M7 and the gate of the eighth MOS tube M8; the drain of the sixth MOS tube M6, the drain of the seventh MOS tube M7 and the source of the eighth MOS tube M8 are all connected to the power supply.

[0028] One end of the resistor R2 is grounded, and the other end is respectively connected to the inverting input terminal of the comparator U1 and the non-inverting input terminal of the operational amplifier U2; one end of the resistor R3 is connected to the emitter of the transistor J2, and the other end is respectively connected to the inverting input terminal of the comparator U1, the non-inverting input terminal of the operational amplifier U2 and the drain of the eighth MOS tube M8; one end of the resistor R4 is grounded, and the other end is respectively connected to the inverting input terminal of the operational amplifier U2 and the drain of the first MOS tube M1; one end of the resistor R5 is grounded, and the other end is connected to the source of the sixth MOS tube M6.

[0029] In other embodiments, the third MOS tube M3 is composed of 4 PMOS tubes connected in parallel. The fourth MOS tube M4 is composed of 7 PMOS tubes connected in parallel. The sixth MOS tube M6 is composed of 4 PMOS tubes connected in parallel. The seventh MOS tube M7 is composed of 4 PMOS tubes connected in parallel. The eighth MOS tube M8 is composed of 6 PMOS tubes connected in parallel. The transistor J1 is composed of 27 transistors connected in parallel. The transistor J2 is composed of 8 transistors connected in parallel.

[0030] The expression of the reference voltage of the present invention is:

[0031]

[0032] In the above formula, ΔV BE Represents the voltage deviation between transistor J2 and transistor J3, V BE Represents the voltage difference between the base and emitter of transistor J1, V ref Indicates the reference voltage output value.

[0033] Figure 1The implementation is divided into three parts: the first startup circuit, the second startup circuit and the core circuit. The first startup circuit is composed of the components resistor R1, the first MOS tube M1, the second MOS tube M2 and the third MOS tube M3, and is mainly responsible for the startup of the core circuit. The second startup circuit is composed of the components fourth MOS tube M4, the fifth MOS tube M5, the transistor J1 and the comparator U1. It is mainly responsible for detecting whether the core circuit starts normally. If not, pull the core circuit back to normal working state. The core circuit is composed of the sixth MOS tube M6, the seventh MOS tube M7, the eighth MOS tube M8, the operational amplifier U2, the transistor J2, the transistor J3, the resistor R2, the resistor R3, the resistor R4 and the resistor R5. It is mainly responsible for realizing the output voltage that does not change with temperature. ref The operating voltage of the core circuit is the sum of the operating voltage of transistors J2 and J3 and the Vdsat of the PMOS tube. Vdsat represents the voltage difference between the drain and the source when M3, M4, M6, M7, and M8 work in saturation state, which meets the low-voltage requirements of the application scenario.

[0034] Bandgap reference circuits generally have two or more degenerate points: Figure 1 As shown, the bandgap reference circuit has three simple degenerate points, and a startup circuit is required to pull the reference to the desired degenerate point.

[0035] The first degenerate point is the situation where the current of each device is all zero, which is an undesirable degenerate point. When the circuit works at this degenerate point. Usually the first startup circuit will work. At this time, point E is usually low level. M1 and M2 are turned on. Current is injected into point B through M1. Current is injected into the op amp through M2 to make the op amp work. In this way, the op amp makes point D low level, so that M8, M7, M6, M4, and M3 are all injected with current. So that the reference enters other degenerate points. When the current of M3 increases, point E rises, causing M1 and M2 to be cut off. The first startup circuit completes the startup task.

[0036] When current flows through the MOS tubes of M8, M7, M6, M4, and M3, current must flow through R2 and R4. If the voltages at points A and B are not enough to turn on J2 and J3, the second abnormal degenerate point will be reached. At this time, the second startup circuit starts to work. The current of M4 generates a voltage after flowing through J1. By reasonably designing the current of M4 and the number of transistors in J3, the voltage at point C is higher than the voltage at point A. In this way, the output of comparator U1 is high, and point D is further pulled down through M5, so that M8, M7, M6, M4, and M3 continue to increase the current, and finally J2 and J3 are turned on. At this time, the voltage at point C is lower than the voltage at point A, the output of comparator U1 is low, and M5 is cut off. The reference enters the normal working mode.

[0037] If the voltage suddenly drops and then returns to normal, the transistor will enter the off state and enter the first degenerate point. At this time, as long as the comparator U1 works, the circuit can escape from the first degenerate point and work normally.

[0038] During normal operation, due to some reasons, the bandgap reference may enter a state where the BJT is turned off. By adding a second startup circuit, entering the second degeneracy point can also be avoided.

[0039] The embodiment of the present invention has two key settings, namely, the combination setting of the first startup circuit and the second startup circuit, and the setting of the core circuit. Among them, by combining the first startup circuit and the second startup circuit, the low voltage reference can work normally during power on and off and normal operation. The circuits of the first startup circuit and the second startup circuit and their combination need to be protected.

[0040] The operating voltage of the core circuit of the present invention is the sum of the operating voltage (0.7) of the transistors J2 and J3 and the Vdsat (0.1) of the PMOS tube, which can work at about 0.8V, meeting the voltage requirement of the low voltage reference.

[0041] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0042] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bandgap reference circuit for ultra-low voltage scenarios, characterized in that: include: A first startup circuit, a second startup circuit, and a core circuit connected in sequence; The first startup circuit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a resistor R1; the source of the first MOS tube M1, the source of the second MOS tube M2 and the drain of the third MOS tube M3 are all connected to the power supply; the gate of the first MOS tube M1, the gate of the second MOS tube M2 and the source of the third MOS tube M3 are connected to each other, connected in series with the resistor R1 and then grounded; the drain of the first MOS tube M1, the drain of the second MOS tube M2 and the gate of the third MOS tube M3 are all connected to the core circuit; The second startup circuit includes a fourth MOS tube M4, a fifth MOS tube M5, a transistor J1 and a comparator U1; The non-inverting input terminal of the comparator U1 is connected to the drain of the fourth MOS tube M4 and the emitter of the triode J1 respectively; the base and collector of the triode J1 are connected and then grounded; the inverting input terminal of the comparator U1 is connected to the core circuit, and the output terminal is connected to the gate of the fifth MOS tube M5; the source of the fifth MOS tube M5 is grounded, and the drain is connected to the gate of the fourth MOS tube M4; the source of the fourth MOS tube M4 is connected to the power supply; The core circuit includes a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, an operational amplifier U2, a transistor J2 and a transistor J3; wherein the non-inverting input terminal of the operational amplifier U2 is respectively connected to the inverting input terminal of the comparator U1 and the emitter of the transistor J2; the base and collector of the transistor J2 are both grounded; the inverting input terminal of the operational amplifier U2 is respectively connected to the emitter of the transistor J3, the drain of the first MOS tube M1 and the drain of the second MOS tube M2; the base and collector of the transistor J3 are both grounded; the output terminal of the operational amplifier U1 is respectively connected to the gate of the third MOS tube M3, the gate of the fourth MOS tube M4, the drain of the fifth MOS tube M5, the gate of the sixth MOS tube M6, the gate of the seventh MOS tube M7 and the gate of the eighth MOS tube M8; the drain of the sixth MOS tube M6, the drain of the seventh MOS tube M7 and the source of the eighth MOS tube M8 are all connected to the power supply; The core circuit also includes: a resistor R2, a resistor R3, a resistor R4 and a resistor R5; one end of the resistor R2 is grounded, and the other end is respectively connected to the inverting input end of the comparator U1 and the non-inverting input end of the operational amplifier U2; one end of the resistor R3 is connected to the emitter of the transistor J2, and the other end is respectively connected to the inverting input end of the comparator U1, the non-inverting input end of the operational amplifier U2 and the drain of the eighth MOS tube M8; one end of the resistor R4 is grounded, and the other end is respectively connected to the inverting input end of the operational amplifier U2 and the drain of the first MOS tube M1; one end of the resistor R5 is grounded, and the other end is connected to the source of the sixth MOS tube M6.

2. The bandgap reference circuit for ultra-low voltage scenarios according to claim 1, characterized in that: The third MOS tube M3 is composed of four PMOS tubes connected in parallel.

3. The bandgap reference circuit for ultra-low voltage scenarios according to claim 1, characterized in that: The fourth MOS tube M4 is composed of seven PMOS tubes connected in parallel.

4. The bandgap reference circuit for ultra-low voltage scenarios according to claim 1, characterized in that: The sixth MOS tube M6 is composed of four PMOS tubes connected in parallel.

5. The bandgap reference circuit applied to ultra-low voltage scenarios according to claim 1, characterized in that: The seventh MOS tube M7 is composed of four PMOS tubes connected in parallel.

6. The bandgap reference circuit for ultra-low voltage scenarios according to claim 1, characterized in that: The eighth MOS tube M8 is composed of six PMOS tubes connected in parallel.

7. The bandgap reference circuit applied to ultra-low voltage scenarios according to claim 1, characterized in that: Transistor J1 is composed of 27 transistors connected in parallel.

8. The bandgap reference circuit for ultra-low voltage scenarios according to claim 1, characterized in that: Transistor J2 is composed of 8 transistors connected in parallel.

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