Half-bridge semiconductor devices

Abstract

This disclosure relates to a discrete half-bridge semiconductor device comprising: a first cascode arrangement and a second cascode arrangement; each of the first cascode arrangement and the second cascode arrangement comprising a high-voltage FET die and a low-voltage FET die; wherein the source of the high-voltage FET die is mounted on and connected to the drain of the low-voltage FET die; and the source of the low-voltage FET die and the gate of the high-voltage FET die are connected at a common connection pad to the drain terminal of the high-voltage FET die of the second cascode arrangement.

Description

Technical Field

[0001] This disclosure relates to discrete half-bridge semiconductor devices. Specifically, this disclosure relates to a discrete half-bridge semiconductor device comprising a depletion-mode transistor die and an enhancement-mode transistor die arranged in a common-source, common-gate configuration, and an associated method for assembling such a discrete half-bridge semiconductor device. Background Technology

[0002] The cascode arrangement of transistors is well-known, particularly for using normally off, low-voltage semiconductor dies to control zero gate-source voltage, and high-voltage semiconductor dies to be normally on (or in depletion mode). The cascode arrangement can be used in switching mode applications, especially in power supplies requiring efficient power switching.

[0003] Typically, this is achieved through an external connection between two common-source, common-gate arrangements 100 and 100'. Figure 1 The diagram shows a half-bridge arrangement of the type shown. External connections can be arranged as tracks or conductive traces on a printed circuit board (PCB), or as wire connections between two cascode arrangements. In the half-bridge arrangement, the drain of the second cascode arrangement 100' is connected to the source terminal of the first cascode arrangement 100, which is shared with the gate of the high-voltage device 104.

[0004] Figure 1 The common-source cascode arrangements 100 and 100' can each include normally-off (or enhancement-mode) low-voltage devices 102 and 102', which are connected in series with each high-voltage depletion-mode device 104 and 104' via a common connection from the gate of the high-voltage device 104 and 104' to the source of the low-voltage device 102 and 102', and from the drain of the low-voltage device 102 and 102' to the source of the high-voltage device 104 and 104'. Therefore, when the drain-source voltage of the low-voltage enhancement-mode device 102 and 102' reaches the threshold voltage of the high-voltage device 104, the high-voltage depletion-mode device 104 and 104' can be turned off. Thus, adding low-voltage enhancement-mode devices 102 and 102' to the common-source cascode arrangement with high-voltage depletion-mode devices 104 and 102' allows normally-on high-voltage devices to be used as normally-off or enhancement-mode devices.

[0005] The aforementioned connection between the two cascode arrangements 100 and 100' can suffer from DC power and switching losses due to the inductive effect in the wires during operation. Using wire bonding results in higher parasitic inductance and capacitance, which can lead to so-called gate bounce. Gate bounce is a faulty turn-on mechanism in which, during high-frequency switching operation, a high-voltage device switches to the "on" state when it should be in the "off" state. Furthermore, especially under high-voltage operation of high-voltage devices, device resistance such as RDSon can increase, and wire connections can become faulty.

[0006] Other issues are known to exist with this arrangement. For example, in switching mode applications, power density is important for switching power conversion, and power density can be improved by minimizing switching losses in cascode and half-bridge connections.

[0007] Furthermore, the aforementioned known arrangement is complex to manufacture and requires two separate and optimized device packages to form the half-bridge arrangement. Summary of the Invention

[0008] Various example embodiments address problems such as those solved above and / or other problems that may become apparent from the following disclosure, relating to improving the electrical and thermal performance of high-voltage and low-voltage transistors with cascode connections in a half-bridge configuration. In particular, various example embodiments utilize optimized layouts to reduce parasitic inductance and resistance to allow for higher-frequency operation with reduced electromagnetic interference (EMI) and lower electromagnetic coupling (EMC).

[0009] In some example embodiments, aspects of this disclosure relate to the placement of a high-voltage transistor die relative to a low-voltage transistor die in a cascode arrangement and the manner in which two such cascode arrangements are electrically connected to form a half-bridge configuration.

[0010] According to an embodiment, a discrete half-bridge semiconductor device is provided, comprising: a first cascode arrangement and a second cascode arrangement; each of the first cascode arrangement and the second cascode arrangement includes a high-voltage FET device die and a low-voltage FET device die; wherein the source of the high-voltage FET device die is mounted on and connected to the drain of the low-voltage FET device die; and the source of the low-voltage FET device die and the gate of the high-voltage FET device die are connected to the drain terminal of the high-voltage FET device die of the second cascode arrangement at a common connection pad.

[0011] High-voltage FET device dies can be horizontal devices, while low-voltage FET device dies are vertical devices.

[0012] High-voltage FET die can be flipped onto a low-voltage FET die.

[0013] Regarding the first cascode arrangement, the gate terminal of the high-voltage FET die and the source terminal of the low-voltage FET die can be mounted on the corresponding contact pads. Regarding the second cascode arrangement, the drain terminal of the high-voltage FET die can be mounted on the corresponding contact pads.

[0014] The corresponding contact pads can be arranged on the first common conductive component.

[0015] The first common conductive member can form an electrical connection between the first cascode arrangement and the second cascode arrangement.

[0016] The first common connection between the first cascode arrangement and the second cascode arrangement can be substantially within the discrete half-bridge semiconductor device.

[0017] The discrete half-bridge semiconductor device according to the embodiment also includes a first common connection and a second common connection between the source terminal of the high-voltage FET device die and the drain terminal of the low-voltage FET device die.

[0018] The discrete half-bridge semiconductor device according to an embodiment also includes a third common connection arranged in a second common-source cascode configuration between the source terminal of the low-voltage FET device die and the gate terminal of the high-voltage FET device die.

[0019] Each of the first common connection, the second common connection, and the third common connection is a conductive component that includes contact pads for accommodating the respective terminals of the corresponding high-voltage FET device die and the low-voltage FET device die.

[0020] High-voltage FET devices are depletion-mode devices, while low-voltage FET devices are enhancement-mode devices.

[0021] According to an embodiment, a method for manufacturing a discrete half-bridge semiconductor device is provided, the method comprising: providing a first cascode arrangement and a second cascode arrangement, each of the first cascode arrangement and the second cascode arrangement including a high-voltage FET device die and a low-voltage FET device die; mounting the source of the high-voltage FET device die to the drain of the low-voltage FET device die, and directly connecting the source of the high-voltage FET device die to the drain of the low-voltage FET device die; and connecting the source of the low-voltage FET device die and the gate of the high-voltage FET device die to the drain terminal of the high-voltage FET device die of the second cascode arrangement at a common connection pad. Attached Figure Description

[0022] To provide a detailed understanding of the features of this disclosure, a more specific description has been given with reference to some of the embodiments shown in the accompanying drawings. However, it will be noted that the drawings illustrate only typical embodiments and are therefore not intended to limit the scope thereof. The drawings are provided to facilitate understanding of this disclosure and are not necessarily drawn to scale. The advantages of the claimed subject matter will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying drawings, in which the same reference numerals have been used to denote the same elements, in which:

[0023] Figure 1This is a circuit diagram of a known half-bridge arrangement of depletion-mode transistor dies and enhancement-mode transistor dies with a common-source, common-gate configuration.

[0024] Figure 2a A top view of a half-bridge arrangement of depletion mode transistor dies and enhancement mode transistor dies according to an embodiment is shown.

[0025] Figure 2b A side view of a half-bridge arrangement of depletion mode transistor dies and enhancement mode transistor dies according to an embodiment is shown.

[0026] Figure 2c A top-side perspective view of a half-bridge arrangement of depletion-mode transistor dies and enhancement-mode transistor dies according to an embodiment is shown.

[0027] Figure 2d A back-side perspective view of a half-bridge arrangement of depletion-mode transistor dies and enhancement-mode transistor dies according to an embodiment is shown.

[0028] Figure 3a A top side view of a half-bridge arrangement of depletion mode transistor dies and enhancement mode transistor dies according to an embodiment is shown.

[0029] Figure 3b A side view of a half-bridge arrangement of depletion mode transistor dies and enhancement mode transistor dies according to an embodiment is shown.

[0030] Figure 3c A top-side perspective view of a half-bridge arrangement of depletion-mode transistor dies and enhancement-mode transistor dies according to an embodiment is shown.

[0031] Figure 3d A back-side perspective view of a half-bridge arrangement of depletion-mode transistor dies and enhancement-mode transistor dies according to an embodiment is shown.

[0032] Figure 4 A top-side perspective view of a half-bridge arrangement of depletion-mode transistor dies and enhancement-mode transistor dies according to an embodiment is shown; and

[0033] Figures 5a to 5h The steps in an example process flow for assembling a half-bridge semiconductor device according to an embodiment are shown. Detailed Implementation

[0034] In the following description of the embodiments, one or more high-voltage device dies may be selected from GaN-based transistors, GaN-based HEMTs, or SiC-based transistors, and one or more low-voltage device dies may be field-effect transistors.

[0035] Figures 2a to 2d A half-bridge semiconductor device 200 according to an embodiment is shown. The half-bridge semiconductor device 200 includes a first cascode arrangement 201 and a second cascode arrangement 203. The first cascode arrangement 201 includes a high-voltage device die 202 and a low-voltage device die 206. Similarly, the second cascode arrangement 203 includes a high-voltage device die 204 and a low-voltage device die 208. In the case of the first cascode arrangement 201 and the second cascode arrangement 203, the high-voltage device dies 202 and 204 can be depletion-mode or normally-on HEMTs or JFETs, and can be, for example, GaN or SiC-based devices. The low-voltage device dies 206 and 208 can be enhancement-mode or normally-off MOSFETs.

[0036] The high-voltage depletion-mode device dies 202 and 204 can be gallium nitride (GaN) or silicon carbide (SiC) based JFETs or HEMTs, and the low-voltage enhancement-mode device dies 206 and 208 can be silicon (Si) based MOSFETs. Both the high-voltage and low-voltage devices are integrated into a single semiconductor device package 200. As described above, the high-voltage devices 202 and 204 and the low-voltage devices 206 and 208 are separate semiconductor device dies. The high-voltage devices 202 and 204 and the low-voltage devices 206 and 208 are configured and integrated within a single package to form a half-bridge semiconductor device 200 according to an embodiment.

[0037] High-voltage devices 202 and 204, such as HEMTs, each have their gate, source, and drain terminals formed on their common (top) surface, and are thus considered lateral devices, as opposed to vertical devices in which at least one terminal is formed on a bottom surface opposite to the top surface. The half-bridge semiconductor device 200 includes various contact pads for mounting each of the high-voltage devices 202 and 204 and the low-voltage devices 206 and 208 and electrically connecting them to their respective source, gate, and drain terminals.

[0038] Regarding the first cascode arrangement 201, the gate terminal H1G of the high-voltage device 202 is electrically connected to and mounted on the corresponding gate pad 210. The drain terminal H1D of the high-voltage device is electrically connected to and mounted on the drain pad 214. The drain pad 214 integrally forms the drain pin or lead 218 of the half-bridge semiconductor device 200. The source terminal H1S of the high-voltage device is electrically connected to and directly mounted on the drain terminal L1D of the low-voltage device 206.

[0039] The source terminal L1S of the low-voltage device 206 is also mounted on the aforementioned gate pad 210 relative to the high-voltage device 202, thereby completing the connection from the common high-voltage device gate terminal H1G to the low-voltage device source terminal L1S, and thus completing the connection with... Figure 1 The circuitry is consistent with the first cascode arrangement of the cascode connection. This arrangement is discussed in more detail below in the context of the common connection pad.

[0040] Similarly, regarding the second cascode arrangement 203, the gate terminal H2G of the high-voltage device 204 is electrically connected to and mounted on the corresponding gate pad 212. The drain terminal H2D of the high-voltage device is electrically connected to and mounted on the drain pad 216. The drain pad 216 integrally forms the drain pin or lead 220 of the half-bridge semiconductor device 200. As discussed below, the drain pad 216 also forms a half-bridge connection between the first cascode arrangement 201 and the second cascode arrangement 203. As with the first cascode arrangement 201, the source terminal H2S of the high-voltage device is electrically connected to and mounted directly on the drain terminal L2D of the low-voltage device 208.

[0041] The source terminal L2S of the low-voltage device 208 is also mounted on the aforementioned gate pad 212 relative to the high-voltage device 204, thereby completing the connection from the common high-voltage device gate terminal to the low-voltage device source terminal, and thus completing the connection with... Figure 1 The circuits are consistent with the second common source cascode arrangement of the common source cascode connection.

[0042] In the case of the first cascode arrangement and the second cascode arrangement, the high voltage devices 202 and 204, which are lateral devices as described above, are rotated or flipped so that the corresponding gate terminals H1G and H2G and drain terminals H1D and H2D are electrically connected to the corresponding gate pads 210 and 212 and drain pads 214 and 216, and mounted on the corresponding gate pads 210 and 212 and drain pads 214 and 216.

[0043] The flip-flop or inverted orientation of the high-voltage devices 202 and 204 reduces parasitic phenomena such as inductance and resistance. The reduction of parasitic phenomena is due to the direct connection of the corresponding gate terminals H1G, H2G and drain terminals H1D, H2D mounted on the corresponding gate pads 210, 212 and drain pads 214, 216, which reduces the distance between them and thereby reduces parasitic diffusion resistance and inductance.

[0044] The low-voltage devices 206 and 208 in both the first and second cascode configurations are arranged such that drain terminals L1D and L2D are located on the respective first or top side of the device, and gate terminals L1G and L2G and source terminals L1S and L2S are located on the second or bottom side of the low-voltage devices 206 and 208 opposite to the first side. In this respect, the low-voltage devices 206 and 208 can be vertical devices. In this manner, the low-voltage devices 206 and 208 facilitate interaction with… Figure 1 circuit Figure 1 This leads to the common source and common grid connection of the corresponding high voltage transverse devices 202 and 204.

[0045] The gate terminals L1G and L2G of the low-voltage devices 206 and 208 are electrically connected to the corresponding gate pads 222 and 224 and mounted on the corresponding gate pads 222 and 224. The corresponding gate pads 222 and 224 each form gate pins or leads for the corresponding low-voltage devices 206 and 208.

[0046] For the first cascode arrangement 201, the gate terminal H1G of the high-voltage device 202 is electrically connected to the source terminal L1S of the low-voltage device 206. This connection is achieved via a drain pad 216 (discussed above regarding the drain pad of the drain terminal H2D of the high-voltage device), which serves as a common connection pad 216 for both electrical and mechanical connection of the first cascode arrangement 201 and connection from the first cascode arrangement 201 to the second cascode arrangement 203. In this respect, the gate terminal H1G of the high-voltage device 202, the source terminal L1S of the low-voltage device 206, and the drain terminal of the high-voltage device 204 are electrically and mechanically connected to the top surface of the common connection pad 216. The corresponding electrical and mechanical connections to the common connection pad 216 can be made using suitable solder materials or conductive adhesives, and this connection is discussed in more detail below with respect to the method of assembling the semiconductor device according to the embodiment.

[0047] The top surface of the common connection pad 216 includes a recess or cut-out portion 226 formed thereon. The recess 226 is arranged to mountably accommodate the source terminal L1S of the low-voltage device 206 thereon, in such a way that the depth of the recess 226 formed in the common connection pad 216 is substantially equal to the thickness of the low-voltage device 206 and any suitable solder material or conductive adhesive disposed on its contact terminals. In this way, when the high-voltage device 202 is mounted on the common connection pad 216 and the low-voltage device 206, the top surface of the high-voltage device 202 (which is the surface including the contact terminals) is substantially parallel and is not inclined relative to the common connection pad 216 and / or the low-voltage device 206.

[0048] The thickness of the drain pad 214 is equal to the thickness of the common connection pad 216 outside the recess 226. This ensures that the drain terminal H1D and gate terminal H1G of the high-voltage device 202 are at the same level. At the recess 226, the thickness of the gate pad 222 is equal to the thickness of the common connection pad 216. When the low-voltage device 206 is mounted on the recess 226 and the gate pad 222, this ensures that the drain terminal H1D, gate terminal H1G, and source terminal H1S of the high-voltage device 202 are flush with each other, and the back surface (opposite to the surface including the terminals) is also flush with each of the aforementioned pads.

[0049] Because the drains of low-voltage devices 206 and 208 are directly connected to the sources of high-voltage devices 202 and 204 and mounted on the sources of high-voltage devices 202 and 204, this stacking and flipping arrangement of low-voltage devices 206 and 208 and high-voltage devices 202 and 204 allows for near-monocoque integration (as with a single die) behavior of the high-voltage and low-voltage devices.

[0050] The inverted and flipped arrangement of low-voltage devices 206 and 208, and their stacking on high-voltage devices 202 and 204, avoids interconnections such as wires, traces, or terminals between the drain and source, thereby reducing any parasitic inductance or resistive effects and allowing for high operating frequencies. This stacking arrangement also reduces cost and improves manufacturability because it eliminates the need for dedicated interconnects.

[0051] and Figure 1 The half-bridge circuit is consistent with that, according to Figures 2a to 2dThe configuration of this embodiment includes an electrical connection between a first cascode arrangement 201 and a second cascode arrangement 203, whereby a common connection pad 216 is electrically and mechanically connected to the drain terminal H2D of the high-voltage device 204 in the second cascode arrangement 203. In this respect, the common connection pad 216 is integrally formed as the drain pad of the high-voltage device 204. Therefore, in this manner, the common connection pad 216 provides a connection pad for each of the following terminals: the gate terminal H1G of the high-voltage device 204, the source terminal L1S of the low-voltage device 206, each of the first cascode arrangement 201; and the drain terminal H2D of the high-voltage device 204 in the second cascode arrangement 203. This results in an optimal half-bridge configuration for high-frequency applications because the intermediate node formed by the common connection pad 216 between the first cascode arrangement 201 and the second cascode arrangement 203 is formed of a single conductive material, which reduces inductance that could prevent high-frequency operation.

[0052] Regarding the second common-source common-gate arrangement 203, and... Figure 1 The half-bridge circuit is consistent with that, according to Figures 2a to 2d In this embodiment, the source terminal L2S of the low-voltage device 208 is also mounted on the gate pad 212, thereby forming a connection from the gate of the high-voltage device 204 to the low-voltage source. Similar to the first cascode arrangement 201, the gate pad 212 includes a recessed portion 228 forming a drain pad for electrically and mechanically mounting the drain terminal L2D of the low-voltage device 208 thereon. The gate terminal of the low-voltage device 208 is electrically and mechanically mounted on a corresponding gate pad 224, and at the recessed portion 228, the thickness of the gate pad 224 is equal to the thickness of the gate pad 212. This ensures that the device is flush with the device discussed above relative to the first cascode arrangement 201.

[0053] For each of the pads mentioned above, each may include a lead portion extending from it. The lead portion is configured to externally connect the corresponding source, gate, or drain terminal to a carrier such as a printed circuit board (PCB). The lead portion may be configured to extend beyond the coverage area of ​​the semiconductor device package material 230, such as... Figure 2c and Figure 2d As shown, this is a known leaded package. Similarly, the lead portion may not extend beyond the coverage area of ​​the semiconductor device package material 230, as... Figures 3a to 3d As shown in the embodiments, it is known to be a non-leaded package. In this respect, leads may extend partially to the sidewalls of the semiconductor device 200 to form side-solderable leads.

[0054] From the above discussion, those skilled in the art will therefore see that the corresponding high-voltage devices 202, 204 and low-voltage devices 206, 208 of the first and second cascode arrangements are mounted in a stacked arrangement. This stacked arrangement, together with the inverted arrangement of the high-voltage device 202, allows for optional additional electrical connections, such that the drain-source lead 220 provides an electrical path (drain-source connection) to the intermediate node of the first and second cascode arrangements. This allows for the measurement of parasitic phenomena, electrical connections, and operating parameters of the devices during use. Furthermore, it minimizes the occurrence of undesirable gate bounce when the semiconductor devices are operating.

[0055] like Figure 4 As shown in the embodiments, the back side of each of the high-voltage devices 202 and 204 (which is the side of the high-voltage devices 202 and 204 opposite to the side on which the active terminal H1S, gate terminal H1G, and drain terminal H1D are formed) may include an optional heat dissipation element 226. The heat dissipation element 226 may be formed of a conductive material and is configured and arranged to dissipate heat from each of the high-voltage devices 202 and 204 during operation. As mentioned above, the high-voltage devices 202 and 204 are arranged in the semiconductor device 200 such that there are no electrical terminals on one side of the high-voltage devices 202 and 204. Therefore, the heat dissipation element 226 can be placed directly on the high-voltage device 202 as shown, without the need to electrically isolate the back side of the high-voltage devices 202 and 204 from the heat dissipation element 226. This direct placement of the heat dissipation element 226 allows for more efficient heat dissipation during operation of the semiconductor device 200. Furthermore, the inverted or flipped orientation of the high-voltage devices 202 and 204, combined with the stacked arrangement of the low-voltage devices 206 and 208 as discussed above, results in a common-source, common-gate arrangement, where additional isolation materials such as ceramic or DBC can be avoided. Figure 2a or Figure 3a Consistent with the embodiments, the optional heat dissipation element 226 may be included on a leaded or non-leaded package.

[0056] Reference Figures 5a to 5h An example method for assembling a semiconductor device 200 according to an embodiment is described. The following discussion relates to a method of assembling a semiconductor device using both leads and heat dissipation element 226; however, those skilled in the art will see that this method is equally applicable to manufacturing... Figures 2a to 2d , Figures 3a to 3d , Figure 4 and Figures 5a to 5h The method of the embodiment.

[0057] Prior to assembling the semiconductor device 200, each of the source, gate, and drain pads, as well as the gate lead, can be formed from a single conductive material as understood in the art. An example method for forming the respective pads and leads is to stamp a metallic conductive material. The stamping process defines the corresponding contour of the pads and, if necessary, can also define any recesses or removed portions in the pads or leads.

[0058] The corresponding high-voltage device pads and low-voltage device pads mentioned above are shown in... Figure 5a This forms the starting point for the method of assembling the half-bridge semiconductor device 200 according to the embodiment. Although not shown previously (for clarity), the bonding pads 232 may be arranged in an upright manner on the respective device pads to facilitate the electrical and mechanical connections of the respective devices.

[0059] like Figure 5b As shown, appropriate solder or conductive adhesive material 234 is applied to the pads at the locations where the source terminals L1S, L2S and gate terminals L1G, L2G of the low-voltage devices 206, 208 will be mounted (see Figure 1). Figure 5c For example, solder or adhesive material 234 can be distributed via screen printing, but a skilled technician will understand that any suitable method can be used. (See reference...) Figure 5c The low-voltage devices 206 and 208 are then mounted on the pads at the corresponding positions of the source terminals L1S and L2S and the gate terminals L1G and L2G of the low-voltage devices 206 and 208, which correspond to the corresponding positions of the solder or adhesive material 234 on the pads.

[0060] Now refer to Figure 5d After placing the low-voltage devices 206 and 208, appropriate solder or conductive adhesive material 236 is applied to the corresponding pads on which the drain terminals H1D and H2D of the high-voltage devices 202 and 204 are connected to the gate terminals H1G and H2G. Appropriate solder or conductive adhesive material 236 is also applied to the drain terminals L1D and L2D of the low-voltage devices 206 and 208 for subsequent attachment of the corresponding source terminals H1S and H2S of the high-voltage devices to the drain terminals L1D and L2D of the low-voltage devices 206 and 208.

[0061] Reference Figure 5e The high-voltage devices 202 and 204 are then mounted on the pads at the corresponding positions of their drain terminals H1D and H2D and gate terminals H1G and H2G, corresponding to the positions of the solder or adhesive material 234 on the pads. The source terminals H1S and H2S of the high-voltage devices 202 and 204 are mounted on the corresponding drain terminals L1D and L2D of the low-voltage devices 206 and 208.

[0062] After placing the high-voltage devices 202 and 204, the process can continue to mold the half-bridge semiconductor device 200 by encapsulating the device 200 in the molding material 230, followed by trimming and forming device leads. Figure 5g As shown in the image.

[0063] Optionally, the heat dissipation element 226 can be arranged on the high-voltage devices 202 and 204. For example... Figure 5f As shown, adhesive material is applied to the upper surfaces of high-voltage devices 202 and 204, and then heat dissipation element 226 is fixedly attached to the upper surfaces of high-voltage devices 202 and 204.

[0064] Although the above process involves forming the half-bridge semiconductor device 200 into a leaded package, those skilled in the art will understand that the process is also applied to forming non-leaded packages.

[0065] When the half-bridge semiconductor device is mounted on an external carrier such as a printed circuit board, the above embodiments provide lower loop inductance.

[0066] Specific and preferred aspects of the invention are set forth in the appended independent claims. Combinations of features from the dependent and / or independent claims may be appropriately combined, and not limited to those described in the claims.

[0067] The scope of this disclosure includes any novel feature or combination of features, or any generalization thereof, explicitly or implicitly disclosed herein, whether or not it relates to the claimed invention or alleviates any or all the problems solved by the invention. The applicant hereby notifies that new claims may be made for these features during the proceedings of this application or any such further application derived therefrom. In particular, with reference to the appended claims, features of dependent claims may be combined with features of independent claims, and features of individual independent claims may be combined in any suitable manner rather than solely in the specific combinations listed in the claims.

[0068] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination.

[0069] The term "comprising" does not exclude other elements or steps, and the term "a (an)" does not exclude multiple elements. Reference numerals in the claims should not be construed as limiting the scope of the claims.

Claims

1. A discrete half-bridge semiconductor device, comprising: First common source and common gate arrangement; Second common source and common gate arrangement; Each of the first cascode arrangement and the second cascode arrangement includes a high-voltage FET device die and a low-voltage FET device die; The source of the high-voltage FET device die is mounted on the drain of the low-voltage FET device die and connected to the drain of the low-voltage FET device die. and The source of the low-voltage FET die arranged in the first common-source cascode configuration, the gate of the high-voltage FET die arranged in the first common-source cascode configuration, and the drain of the high-voltage FET die arranged in the second common-source cascode configuration are electrically and mechanically connected to a common connection pad.

2. The discrete half-bridge semiconductor device according to claim 1, wherein, The high-voltage FET device die is a horizontal device die, and the low-voltage FET device die is a vertical device die.

3. The discrete half-bridge semiconductor device according to claim 1, wherein, The high-voltage FET die is flipped onto the inverted low-voltage FET die.

4. The discrete half-bridge semiconductor device according to claim 2, wherein, The high-voltage FET die is flipped onto the inverted low-voltage FET die.

5. The discrete half-bridge semiconductor device according to any one of claims 1 to 4, wherein, Regarding the first cascode arrangement, the gate terminal of the high-voltage FET die and the source terminal of the low-voltage FET die are mounted on corresponding contact pads, and regarding the second cascode arrangement, the drain terminal of the high-voltage FET die is mounted on corresponding contact pads.

6. The discrete half-bridge semiconductor device according to claim 5, wherein, The contact pads of the gate terminal of the first common-source cascode high-voltage FET device die, the contact pads of the source terminal of the first common-source cascode low-voltage FET device die, and the contact pads of the drain terminal of the second common-source cascode high-voltage FET device die are arranged on a first common conductive member.

7. The discrete half-bridge semiconductor device according to claim 6, wherein, The first common conductive member forms an electrical connection between the first cascode arrangement and the second cascode arrangement.

8. The discrete half-bridge semiconductor device according to claim 6, wherein, The first common conductive component between the first cascode arrangement and the second cascode arrangement is inside the discrete half-bridge semiconductor device.

9. The discrete half-bridge semiconductor device according to claim 7, wherein, The first common conductive component between the first cascode arrangement and the second cascode arrangement is inside the discrete half-bridge semiconductor device.

10. The discrete half-bridge semiconductor device according to any one of claims 1 to 4, further comprising a first common connection and a second common connection between the source terminal of the high-voltage FET device die and the drain terminal of the low-voltage FET device die.

11. The discrete half-bridge semiconductor device according to any one of claims 1 to 4, further comprising a third common connection arranged in the second common-source-common-gate configuration between the source terminal of the low-voltage FET device die and the gate terminal of the high-voltage FET device die.

12. The discrete half-bridge semiconductor device according to claim 10, wherein, Each of the first common connection and the second common connection is a conductive component, which includes contact pads for accommodating corresponding terminals of the respective high-voltage FET device die and the low-voltage FET device die.

13. The discrete half-bridge semiconductor device according to claim 11, wherein, The third common connection is a conductive component that includes a contact pad for accommodating the source terminal of the low-voltage FET die and the gate terminal of the high-voltage FET die in the second common-source, common-gate arrangement.

14. The discrete half-bridge semiconductor device according to any one of claims 1 to 4, wherein, The high-voltage FET die is a depletion-mode device, and the low-voltage FET die is an enhancement-mode device.

15. A method for manufacturing a discrete half-bridge semiconductor device, the method comprising: A first cascode arrangement and a second cascode arrangement are provided, each of the first cascode arrangement and the second cascode arrangement including a high-voltage FET device die and a low-voltage FET device die; The source of the high-voltage FET device die is mounted to the drain of the low-voltage FET device die, and the source of the high-voltage FET device die is directly connected to the drain of the low-voltage FET device die. as well as The source of the low-voltage FET die arranged in the first common-source cascode configuration, the gate of the high-voltage FET die arranged in the first common-source cascode configuration, and the drain of the high-voltage FET die arranged in the second common-source cascode configuration are electrically and mechanically connected to a common connection pad.

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