Media scrubber in storage system

Abstract

The present application relates to a media scrubber for a memory system. A controller may count the number of forwarded codewords in a memory medium, for example, during a scrubbing cycle. The controller may add the number to the total number of forwarded codewords in the memory medium. The controller may avoid forwarding additional codewords based on the number. When a spare bit is assigned to an erroneous bit in a codeword, the controller may write a valid logic state to the spare bit. Individual memory cells may indicate a change in spare bit assignment and whether the spare bit contains a valid logic state. The controller may retrieve a codeword from the memory medium and invert one or more bits of the codeword before writing the codeword to the memory medium.

Description

[0001] Cross-references

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 043052, filed on July 23, 2019, by Pawlowski, entitled “MEDIA SCRUBBER IN MEMORY SYSTEM,” which claims priority to U.S. Patent Application No. 16 / 516,936, filed on July 19, 2019, by Pawlowski, entitled “MEDIA SCRUBBER IN MEMORY SYSTEM,” and U.S. Provisional Patent Application No. 62 / 702,765, filed on July 24, 2018, by Pawlowski, entitled “MEDIA SCRUBBER IN MEMORY SYSTEM,” each of which is assigned to the assignee of this application, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to media scrubbers in storage systems. Background Art

[0004] The following relates generally to operating a memory subsystem or system, and more particularly, to media scrubber operations in a memory system.

[0005] A computing system may include a memory subsystem or system that includes various types of memory devices and controllers coupled to one or more buses to manage information in multiple electronic devices such as computers, wireless communication devices, the Internet of Things, cameras, digital displays, etc. Memory devices are widely used to store information in such electronic devices. Information is stored by programming different states of the memory device. For example, a binary device has two states, which are usually represented by a logical "1" or a logical "0". In other systems, more than two states can be stored in the memory device. In order to access the stored information, the components of the electronic device can read or read out the stored states in the memory device. In order to store information, the components of the electronic device can write or program states in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, NAND memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory can maintain its logic state for an extended period of time even in the absence of external power. Volatile memory cells (e.g., DRAM cells) may lose their stored state over time when disconnected from an external power source.

[0007] Improving computing systems may include enhancing the performance of memory systems, such as reducing power consumption, increasing memory capacity and reliability, improving read / write speeds, providing non-volatility through the use of permanent memory media, or reducing manufacturing costs at a certain performance point, among other metrics. Summary of the invention

[0008] A method is described. The method may include: identifying a value of a first counter associated with a storage medium, the first counter indicating a first number of codewords retained at the storage medium during a first duration, the first number of codewords being configured as forwarded codewords; setting a value of a second counter associated with the storage medium based at least in part on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the storage medium during a second duration, the second number of codewords being configured as forwarded codewords; and receiving a first codeword from the storage medium based at least in part on setting the value of the second counter.

[0009] Another method is described. The method may include: receiving a codeword retained at a portion of a memory medium, the codeword including a plurality of bits including a number of spare bits for the codeword; accessing a memory array of a port manager based at least in part on receiving the codeword; performing an error control operation on the codeword to restore a logic state of the plurality of bits based at least in part on accessing the memory array of the port manager; and writing a logic state of a bit in the plurality of bits at a spare bit in the number of spare bits based at least in part on performing the error control operation.

[0010] Another method is described. The method may include: receiving a codeword from an address of a storage medium, the codeword comprising a set of bits; inverting a portion of the set of bits based at least in part on receiving the codeword; setting a value of a bit in the set of bits to indicate a codeword condition including an inverted state of the codeword based at least in part on inverting the portion of the set of bits; and writing the codeword back to the address of the storage medium based at least in part on setting the value of the bit indicating the inverted state. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a computing system supporting media scrubber operations in a memory system according to aspects disclosed herein is presented.

[0012] Figure 2 An example of a computing system supporting media scrubber operations in a memory system according to aspects disclosed herein is presented.

[0013] Figure 3

[0046] Examples of codeword formats supporting media scrubber operations in a memory system according to aspects disclosed herein are presented.

[0014] Figure 4 Examples of configurations of memory dies and configurations of memory media that support media scrubber operations in a memory system according to aspects disclosed herein are presented.

[0015] Figure 5 A block diagram of a device supporting media scrubber operations in a memory system according to aspects disclosed herein is shown.

[0016] Figures 6 to 8 One or more methods of supporting media scrubber operations in a memory system according to aspects disclosed herein are presented. DETAILED DESCRIPTION

[0017] The performance of a computing system (e.g., a server including a memory system or subsystem) can depend on various factors, such as providing reliable information to the computing system with low latency (e.g., load-to-use latency). In the context of a computing system or subsystem, data that carries information can be referred to as a codeword. In some cases, a codeword can include a certain amount of user data and additional bits (e.g., bits that support error control operations) that carry various information to provide reliable user data with low latency. Codewords can be associated with elements of a computing system such as a memory medium of a memory system or subsystem and can be transmitted and received during one or more access operations or background operations or both. Background operations in a computing system can refer to processes that run without external or user intervention (e.g., access commands from a host device).

[0018] In some cases, memory cells of one or more memory dies in a memory medium may support a limited number of access operations (e.g., read cycles or write cycles or both) before becoming unreliable or problematic. In some cases, a memory cell may experience a change in electrical characteristics (e.g., a threshold voltage of the memory cell) after a certain period of time without access operations. Such changes (e.g., an increase in the threshold voltage of the memory cell) may adversely affect the operating window of the memory cell, so that the error rate of the memory medium, such as the raw bit error rate (RBER), may increase. When a memory cell becomes unreliable (e.g., due to a limited number of access operations that the memory cell can support or an inherent change in the electrical characteristics of the memory cell without access operations, or both), the information generated by the memory cell may become erroneous, less reliable, or invalid, and such memory cells (or information generated by the memory cell) may be referred to as error bits. When a certain number of memory cells associated with a codeword generate error bits, the codeword (e.g., user data in the codeword) may exceed the error recovery capability of the memory system or subsystem and become erroneous, less reliable, or invalid.

[0019] In some cases, one or more spare bits in a codeword may be allocated to take the error bit in the codeword. In some cases, the overall unstable state of the codeword may require the codeword to be configured as a forwarding codeword pointing to a different address to retrieve reliable user data. In some cases, performing access operations (e.g., read operations, write operations) can mitigate the undesired changes in the electrical characteristics of the memory cell that retains the codeword. Therefore, the various functions described herein (e.g., allocating one or more spare bits to take the error bit in the codeword, writing one or more spare bits with valid information to replace the error bit supporting low latency operation, counting and monitoring the number of forwarding codewords retained at the storage medium, and periodically performing access operations for the codeword set retained at the storage medium) can be efficiently performed to improve the reliability of the system. In some cases, the various functions described herein may be referred to as media scrubber operations and may be performed as part of one or more background operations to improve the overall performance of the computing system.

[0020] A controller (e.g., a port manager associated with a storage medium) may, in some cases, count or monitor the number of forwarding codewords retained in the storage medium as part of a media scrubber operation. The controller may identify a value of a first counter associated with the storage medium. The first counter may indicate the number of codewords configured as forwarding codewords during a scrubbing period (e.g., a duration during which a media scrubber operation may be performed for the storage medium). The controller may set (e.g., preliminarily set, update) a value of a second counter associated with the storage medium based on the value of the first counter, wherein the second counter may indicate a total number of forwarding codewords that may be accumulated in the storage medium during a lifecycle of the storage medium. The lifecycle of the storage medium may refer to an estimated duration for which the storage medium meets a set of operating criteria.

[0021] The controller may also reset the value of the first counter based on setting the value of the second counter before initiating the next scrubbing cycle to count another number of codewords configured as forwarding codewords in the next scrubbing cycle. In this way, the controller may count the number of codewords configured as forwarding codewords during a given scrubbing cycle and may accumulate the total number of forwarding codewords retained at the storage medium over the life cycle of the storage medium. In some cases, the controller may avoid configuring additional codewords as forwarding codewords based on the number of forwarding codewords during the scrubbing cycle or during the life cycle of the storage medium.

[0022] The memory array of the memory die may be configured to include a set of minimum replacement regions (MSRs). The MSR may be configured to efficiently manage (e.g., replace, replace) a reasonable fault accommodation area for error bits in the memory array. In some cases, the MSR may include a group of memory cells configured as data units associated with error control operations. Further, each bit of a codeword (e.g., each of the 1,408 bits in the codeword) may be associated with a corresponding MSR in a set (e.g., 1,408 MSRs). A group of MSRs (e.g., a group of MSRs operating in parallel) across a channel set of memory media may retain a certain number of codewords. A group of MSRs configured to generate a certain number of codewords may be referred to as an MSR stripe or an MSR region. In some cases, an MSR stripe may be associated with a bit (e.g., a flag) in a separate memory array, wherein the bit may be configured to indicate a change in a replacement relationship (e.g., one or more indications of spare bit allocation for replacing one or more error bits) for a certain number of codewords retained at the MSR stripe.

[0023] The controller may, in some cases, allocate one or more spare bits (e.g., corresponding to one or more MSRs of the spare bits) in a codeword to fetch an erroneous bit (e.g., an MSR corresponding to the erroneous bit) in a codeword (e.g., one of a number of codewords retained at the MSR stripe) as part of a media scrubber operation (e.g., during a first media scrubbing cycle for an MSR stripe). The controller may set a bit (e.g., a flag) in a separate memory array to indicate such a change in the replacement relationship associated with the codeword retained at the MSR stripe. Setting the bit (e.g., a flag) may also indicate that, although the replacement relationship of the spare bit may have been determined, the spare bit may not contain a valid logic state for the codeword.

[0024] The controller may, in some cases, access the codeword as part of a media scrubber operation (e.g., during a second media scrub cycle for an MSR stripe), replace the erroneous bit with the one or more spare bits according to a replacement relationship stored in a separate memory array, and perform an error control operation to restore the logic state of the codeword (e.g., the codeword containing the one or more spare bits replacing the erroneous bit). The controller may write the restored logic state (e.g., a valid logic state) at the one or more spare bits and may reset the bit (e.g., a flag) in the separate memory array. In this way, the one or more spare bits may contain the valid logic state of the codeword, and the bit (e.g., the flag) may indicate that the one or more spare bits contain the valid logic state to be implemented (multiplexed into the bit stream of the codeword with a series of data bursts) when the host requests the codeword.

[0025] The controller may, in some cases, retrieve the codeword from the storage medium as part of a media scrubber operation, invert at least some, if not all, of the bits of the codeword before writing the codeword back to the storage medium. Writing the codeword back to the storage medium may mitigate undesirable changes in the electrical characteristics of the memory cells retaining the codeword—for example, drift of the threshold voltage of the memory cells that may occur during extended periods of time without access operations. Inverting the logic state of the memory cells (e.g., writing a logic "1" to a memory cell retaining a logic "0" or vice versa) may further mitigate undesirable changes in the electrical characteristics of the memory cells.

[0026] The following will Figure 1 The features of the present disclosure introduced herein are further described at an exemplary system level in the context of Figures 2 to 4 Specific examples of configurations of the system and the storage media of the system are described in the context of. These and other features of the present disclosure are further illustrated by Figure 5 Installation diagram and Figures 6 to 8A flowchart of a device diagram depicting various components associated with a controller is shown and described with reference to the flowchart relating to operations in a media scrubber operation in a memory system.

[0027] Figure 1 An example of a computing system 100 supporting media scrubber operations in a memory system according to aspects disclosed herein is shown. The computing system 100 can include a host device 105 coupled to a device 140 via a host interface 115 (which can also be referred to as a host link). The host device 105 can be or include a server, a system on a chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU), among other examples. In some examples, the host device 105 can access (e.g., read from, write to) one or more memory media 130 located in the device 140 via the host interface 115.

[0028] The host interface 115 (e.g., a host link) may be compatible with a protocol (e.g., Gen-Z, a Cache Coherent Interconnect for Accelerators (CCIX) protocol) or employ a protocol to facilitate access operations between the host device 105 and the one or more memory media 130. The host interface 115 may be configured to transfer data at a first data transfer rate (e.g., 25 gigabytes per second (GBps)) in at least one direction (e.g., sending or receiving). In some examples, when the transaction size is 64 bytes, the 25 GBps data transfer rate may support approximately 586 million transactions per second. In other examples, when the transaction size is 128 bytes, the 25 GBps data transfer rate may support approximately 312.5 million transactions per second.

[0029] Device 140 may in some cases be referred to as a memory system or subsystem or a memory device. In some cases, device 140 may include a power management component. The power management component may monitor power levels that may indicate a power change or loss associated with device 140 or computing system 100. In some cases, fluctuations in power levels may exceed a normal range to indicate such a power change or loss event. Device 140 may include a controller 120 that may be coupled to one or more memory media 130 via a channel 125. In some cases, channel 125 may be referred to as an aggregate channel 125 that includes a plurality of memory media 130, as described in reference to FIG. Figure 2The device 140 may include a non-volatile memory 131 coupled to the controller 120 via the channel 126. In some examples, the controller 120, the one or more memory media 130, or the non-volatile memory 131, or any combination thereof, may be integrated with, in contact with, or placed on a board (e.g., a peripheral component interconnect express (PCIe) board). In some cases, the non-volatile memory 131 may be integrated as part of the controller 120.

[0030] The controller 120 may include various functional blocks that facilitate the operation of the device 140 in conjunction with the one or more memory media 130. In some cases, power management components may be integrated as part of the controller 120. In some cases, the controller 120 may include aspects of an interface controller to accommodate different specifications, limitations, or characteristics associated with the host interface 115, the channel 125, the channel 126, or any combination thereof. In some examples, the controller 120 may be an ASIC, a general purpose processor, other programmable logic device, a discrete hardware component (e.g., a chiplet), or the controller may be a combination of components.

[0031] In some cases, the controller 120 may be combined with the controller 120 to perform various operations (eg, write data to a memory cell, read data from a memory cell, Figure 3 The local controller (e.g., local to storage medium 130-a) of the described codeword format arrangement codewords reads data from or writes data at storage medium 130 (e.g., storage medium 130-a). In some examples, the local controller can send the requested data to controller 120 via one of channels 125, which can be an example of an aggregate channel.

[0032] Each memory medium (e.g., memory medium 130-a) may include multiple memory dies (e.g., forty-four (44) memory dies) to obtain a specified or desired memory capacity of the memory medium. In some examples, the memory dies may include a three-dimensional cross-point array of chalcogenide-containing memory cells (e.g., including 3D XPoint TM In some embodiments, a codeword (e.g., a codeword containing 128 bytes of user data) may be partitioned across the multiple memory dies within a memory medium (e.g., memory medium 130-a).

[0033] In some cases, each memory die in the plurality of memory dies (e.g., each 3DXP memory die) can generate a certain amount of data (e.g., 128 bits of data) from the memory die as a whole in association with an access operation (e.g., a read operation). The certain amount of data (e.g., 128 bits of data) can include a series of bursts (e.g., sixteen (16) bursts), each burst including a certain amount of data (e.g., eight (8) bits of data) transmitted from the memory die on a bus (e.g., an 8-bit wide bus). As an example, when the memory medium includes eleven (11) memory dies operating in parallel, and when each of the eleven (11) memory dies generates eight (8) bits of data at a given burst, the memory medium can generate 88 bits of data for a given burst. Since eleven (11) memory dies can generate data over a total of sixteen (16) bursts, each burst containing 88 bits of data from the eleven (11) memory dies, a data unit associated with the memory medium during an access operation - e.g., a data unit transmitted over a channel (e.g., an aggregate channel) - can contain 1,408 bits.

[0034] Thus, in this example, a codeword (e.g., a unit of data during a transaction of an access operation) associated with the memory medium may include 1,408 bits. In some cases, a burst may be referred to as a channel burst or a data burst. In some cases, a channel between controller 120 and a memory medium (e.g., memory medium 130-a) may include multiple channels, each of which may be referred to as a channel. Figure 3 and 4 Described may be associated with one or more memory dies of a memory medium (eg, memory medium 130 - a ).

[0035] The memory medium (e.g., memory medium 130-a) may include a set of memory dies each including a memory array. Each memory die in the set (e.g., each memory array) may be configured to include a set of MSRs, as described in reference to Figure 4 As described. The MSRs may be configured as reasonable fault containment areas for efficiently managing (e.g., replacing, substituting) erroneous bits in the memory array. In addition, at least some (if not each) of the MSRs in the set may be associated with a counter configured to count the number of erroneous bits in the MSRs of the set.

[0036] The channel 125 may be configured to transport data (e.g., codewords) between the controller 120 and the one or more storage media 130. Each channel in the channel 125 (e.g., channel 125-a, which may be an example of an aggregate channel) may include multiple other channels (e.g., channels with a bandwidth smaller than channel 125-a) for transmitting data (e.g., codewords) in parallel. In some cases, a codeword may include user data (e.g., 128 bytes of user data in a codeword) and other data sets (e.g., remaining data in a codeword for generating reliable data with low latency). Each channel in the channel 125 (e.g., channel 125-a, which may be an example of an aggregate channel) may include additional channels to carry information related to various auxiliary functions such as metadata. In some cases, a codeword format (which may also be referred to as a codeword layout) or a forwarding codeword format (e.g., a forwarding codeword layout) may define how each channel in the channel 125 (e.g., channel 125-a) may transport data (e.g., codewords) between the controller 120 and the one or more storage media 130.

[0037] The non-volatile memory 131 may include an array of non-volatile memory cells that can maintain their logic state for an extended period of time even in the absence of external power. For example, the non-volatile memory cells may be or may include 3D XPoint TM Memory cells, PCM cells, FeRAM cells, or NAND memory cells. In addition, the non-volatile memory 131 can be configured to communicate information with the controller 120 through the channel 126. For example, the non-volatile memory 131 can receive information from the controller 120 through the channel 126 and save the information when a power change or loss related to the computing system 100 is detected.

[0038] In some cases, a memory subsystem or system that may include device 140 may include a power management component for managing power change or loss events. The power management component may be operable to detect signs of power change or loss (e.g., an indication of a power level at which a power change or loss may occur) and transmit an indication of the signs of power change or loss to controller 120. Upon receiving the indication, controller 120 may transfer information stored in a memory array (e.g., an SRAM memory array) in controller 120 (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit allocations to error bits) to non-volatile memory 131. Non-volatile memory 131 may store information so that the information may be stored even without power supply to the memory subsystem or system that may include device 140. When power to computing system 100 is restored or otherwise adjusted, controller 120 may retrieve information from non-volatile memory 131 based on the information stored in non-volatile memory 131 to continue operations that have been interrupted by the power change or loss event.

[0039] A controller (e.g., controller 120) may in some cases count the number of forwarding codewords retained in a storage medium (e.g., storage medium 130-a) as part of a media scrubber operation. A forwarding codeword may include a certain number of copies of the forwarding address of the codeword, as shown in FIG. Figure 3 As described. The controller 120 may identify a value of a first counter associated with the memory medium. The first counter may indicate the number of codewords configured as forwarded codewords during a scrubbing cycle (e.g., a duration during which a media scrubber operation may be performed for the memory medium). The controller may set (e.g., preliminarily set, update) a value of a second counter associated with the memory medium based on the value of the first counter, wherein the second counter may indicate a total number of forwarded codewords that may be accumulated in the memory medium during a lifecycle of the memory medium. The lifecycle of the memory medium may refer to an estimated duration for which the memory medium meets a set of operating criteria, such as a raw bit error rate (RBER) associated with memory die contained in the memory medium, a preconfigured ratio between the number of forwarded codewords and the total number of codewords retained in the memory medium, or a load-to-use latency, among other examples.

[0040] The controller 120 may also receive the first codeword from the storage medium based on setting the value of the second counter. In some cases, the controller 120 may initiate the next scrubbing cycle by receiving the first codeword from the storage medium. In some cases, the controller 120 may also reset the value of the first counter based on setting the value of the second counter before initiating the next scrubbing cycle to count another number of codewords configured as forwarded codewords during the next scrubbing cycle. The period may be the duration of a preconfigured period of scrubbing based on retrieving a set of codewords from the storage medium. For example, a preconfigured period for performing one or more media scrubber operations may correspond to several hours. In some cases, the controller 120 may receive the first codeword by retrieving the first codeword as part of a periodic background operation (e.g., a media scrubber operation) that is independent of an access command from the host.

[0041] In this manner, controller 120 can count the number of codewords configured as forwarding codewords during a given scrubbing cycle and can accumulate the total number of forwarding codewords retained at a storage medium (e.g., storage medium 130-a) over the lifecycle of the storage medium. In some cases, the controller can avoid configuring additional codewords as forwarding codewords based on the number of forwarding codewords during a scrubbing cycle or during the lifecycle of the storage medium.

[0042] Figure 2 An example of a computing system 200 that supports media scrubber operations in a memory system according to aspects disclosed herein is shown. The computing system 200 may be a reference Figure 1 The computing system 200 may include a host device 205 that is coupled to a memory subsystem or system 220 using at least one host interface (e.g., host interface 215-a). In some cases, the host interface 215 may be referred to as one or more host links. The host device 205 may be a reference Figure 1 The host device 105 is described as an example. The host interface 215 may be referenced Figure 1 Described example of host interface 115. In some examples, host interface 215 can be configured to transfer data at a first data transfer rate (eg, 50 GBps with 25 GBps in each direction).

[0043] The computing system 200 may include a memory subsystem or system 220. The memory subsystem or system 220 may be a reference Figure 1140. The memory subsystem or system 220 may be referred to as one or more memory devices. The memory subsystem or system 220 may include a controller 230. In some cases, the memory subsystem or system 220 may include a power management component. The power management component may monitor power levels that may indicate a power change or loss associated with the memory subsystem or system 220 or the computing system 200. In some cases, fluctuations in power levels may exceed a normal range to indicate such a power change or loss event. The controller 230 may be a reference Figure 1 An example of controller 120 is depicted. Controller 230 may include interface component 210 and multiple port managers 260. In some cases, power management components may be integrated as part of controller 230.

[0044] The interface component 210 can be configured to facilitate data exchange between the host device 205 and the memory subsystem or system 220 through the host interface 215. The interface component 210 can be configured to exchange data with the plurality of port managers 260 (e.g., using the signal paths 250). Each of the signal paths 250 can be configured to exchange data at a rate (e.g., 12.8 GBps) that is different from the first data transfer rate of the host interface 215. In some cases, the interface component 210 can be configured to provide a routing network function to allow more than one host interface (e.g., host interface 215-a and host interface 215-b) to be associated with the plurality of port managers 260.

[0045] The memory subsystem or system 220 may include non-volatile memory 296. The non-volatile memory 296 may be configured to communicate information with the controller 230 via the channel 292. The non-volatile memory 296 may be a reference Figure 1 The example of non-volatile memory 131 described above. In addition, channel 292 can be a reference Figure 1 126 described herein or include aspects of the described channels. Further, the non-volatile memory 296 can be configured to communicate information with the port manager 260 in the controller 230. For example, the port manager 260 can pass various information (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit assignments to error bits) to the non-volatile memory 296 via the channel 292 and save the information in the non-volatile memory 296 when the port manager 260 receives an indication of a power change or loss associated with the computing system 200 or the memory subsystem or system 220. In some cases, the non-volatile memory 296 can be integrated as part of the controller 230.

[0046] Each of the plurality of port managers 260 (e.g., port manager 260-b) can be coupled to a storage medium (e.g., storage medium 295-b) via an aggregate channel (e.g., aggregate channel 290-b). In some cases, each of the plurality of port managers can be coupled to a different one or more storage media 295. In some instances, individual port managers (e.g., port manager 260-a) of the plurality of port managers 260 can operate independently of each other (e.g., port managers 260-b, 260-c, and 260-c) and can support access operations or background operations associated with one or more storage media 295. The one or more storage media 295 can be referenced to a plurality of storage media 295. Figure 1 Examples of the one or more storage media 130 are described. In some cases, each of the one or more storage media 295 can be referred to as a media port.

[0047] Each of the aggregated channels 290 may include one or more channels 291. In some cases, the channels 291 may be referred to as logical channels 291. In some instances, each channel 291 may be associated with one or more memory dies in a memory medium (e.g., memory medium 295-a) and may have a bandwidth that is less than the bandwidth of an aggregated channel (e.g., aggregated channel 290-b). In some instances, an aggregated channel (e.g., aggregated channel 290-a) may include eleven (11) channels 291 (e.g., channels 291-a through 291-k). As will be appreciated by one of ordinary skill in the art, the multiple channels 291 (e.g., channels 291-a through 291-k) are depicted with respect to the port manager 260-a, thereby representing one of the aggregated channels 290 (e.g., aggregated channel 290-a), while the other aggregated channels 290 (e.g., aggregated channels 290-b, 290-c, and 290-d) are depicted with respect to the port managers 260-b, 260-c, and 260-d, without showing the multiple channels 291 associated with each aggregated channel, and this depiction is done in order to increase visibility and clarity of the features shown.

[0048] An individual memory medium (e.g., memory medium 295-a) of the one or more memory media 295 may include one or more memory devices (e.g., 3DXP memory dies). In some cases, the memory devices in the individual memory media may be configured to operate in parallel to obtain a desired (or specified) aggregate bandwidth through one of the aggregate channels 290. As an example, a 3DXP memory die may be configured to have an 8-bit wide data bus and may be associated with each channel (e.g., channel 291-a) of channels 291, such that each channel 291 is 8 bits wide. Additionally, the 3DXP memory die may be configured to generate 128 bits of data during a series of sixteen (16) bursts, where each burst may generate 8 bits of data on channel 291. Thus, the 128 bits of data may be viewed as a single unit of data generated by each 3DXP memory die based on an access command (or during background operation) to read a memory cell within the 3DXP memory die.

[0049] In some cases, a codeword (or forwarding codeword) can be configured to include a set of bit fields indicating multiple data bursts (e.g., a series of sixteen (16) bursts) across multiple channels (e.g., eleven (11) channels 291-a through 291-k generating 88 bits of data per data burst). Thus, a codeword can, in some cases, include 1,408 bits of information. The description herein can be understood from a logical view of the memory medium. A number of physical 3DXP memory dies greater than the number of logical 3DXP memory dies can exist in the memory medium, thereby accounting for overhead associated with various access operations (e.g., read operations, write operations) or background operations associated with the memory medium. Within the memory medium, as described in reference Figure 3 As described, a codeword may be divided into portions and written to or read from more than one die (eg, 128 bytes of user data retained across ten (10) 3DXP memory dies).

[0050] Various examples described herein use 3DXP memory dies (e.g., including 3D XPoint TM Memory cells) are used to illustrate how the memory media 295 may be configured and operated in conjunction with the port manager 260. In some cases, the memory media 295 may include other types of memory devices that use memory technologies other than 3D XPoint memory technology, such as FeRAM technology, PCM technology, MRAM technology, etc. Thus, the concepts disclosed herein are not limited to a particular memory technology (e.g., 3D XPoint TM memory technology).

[0051] The memory medium (e.g., memory medium 295-a) may include a set of memory dies each including a memory array. Each memory die in the set (e.g., each memory array) may be configured to include a set of MSRs, as described in reference to Figure 4 As described. The MSR can be configured as a reasonable fault accommodation area for efficiently managing (e.g., replacing, substituting) erroneous bits in the memory array. In some cases, each bit of the codeword (e.g., each of the 1,408 bits in the codeword) can be associated with a corresponding MSR in a set (e.g., 1,408 MSRs). A group of MSRs across a channel set of memory media (e.g., channels 291-a to 291-k of memory media 295-a) can be configured to operate in parallel to retain or generate a certain number of codewords. In some cases, a group of MSRs configured to generate a certain number of codewords can be referred to as an MSR stripe or MSR region. In addition, at least some (if not each) MSR in the set can be associated with a counter configured to count the number of erroneous bits in the MSRs in the set.

[0052] A port manager (e.g., port manager 260-a) may in some cases count the number of forwarding codewords retained in a storage medium (e.g., storage medium 295-a) as part of a media scrubber operation. A forwarding codeword may contain a certain number of copies of the forwarding address of the codeword, as described in reference to Figure 3 As described. The port manager 260-a may identify a value of a first counter associated with the storage medium. The first counter may indicate a first number of codewords configured as forwarding codewords during a first duration. In some cases, the first duration may be based on a preconfigured period for retrieving a set of codewords from the storage medium. The port manager 260-a may set (e.g., preliminarily set, update) a value of a second counter associated with the storage medium based on the value of the first counter, wherein the second counter may indicate a second number of forwarding codewords that may be accumulated in the storage medium during a second duration. In some cases, the second duration may be based on a life cycle of the storage medium (e.g., an estimated duration that the storage medium meets a set of operating criteria). The port manager 260-a may also receive a first codeword from the storage medium based on setting the value of the second counter.

[0053] In some cases, the port manager 260-a may determine that the first codeword satisfies a condition for configuring the first codeword as a forwarding codeword. The condition may be based on, for example, Figure 3The port manager 260-a may further configure the first codeword as a forwarding codeword based on determining that the first codeword satisfies the condition. In some cases, the port manager 260-a may write the first codeword back to a storage medium (e.g., storage medium 295-a) based on configuring the first codeword as a forwarding codeword.

[0054] In some cases, the port manager 260-a may update the value of the first counter based on configuring the first codeword as a forwarding codeword. The port manager 260-a may also determine an updated value of the first counter relative to a first threshold associated with the number of forwarding codewords retained at the memory medium. In some cases, the first threshold may be related to the number of codeword forwarding events allowed during the first duration. In some cases, the number of codeword forwarding events may be preconfigured based on a ratio between the total number of forwarding codewords budgeted in the memory medium and the total number of codewords retained in the memory medium. In other cases, the first threshold may be related to one or more defect mechanisms that may make the memory cell cluster unreliable or problematic. As a result of updating the value of the first counter (e.g., configuring the codeword as a forwarding codeword during the scrubbing cycle), the port manager 260-a may determine that the value of the first counter (e.g., the updated number of codeword forwarding events) may be equal to the number of codeword forwarding events allowed during the first duration or within a determined range of the number of codeword forwarding events allowed during the first duration.

[0055] Further, the port manager 260-a may receive a second codeword from the memory medium based on updating the value of the first counter. The port manager 260-a may also determine, based on receiving the second codeword, that the second codeword satisfies a condition for configuring the second codeword as a forwarding codeword. In some cases, the port manager 260-a may refrain from configuring the second codeword as a forwarding codeword based on the updated value of the first counter relative to the first threshold. For example, the port manager 260-a may initiate an alternative error control scheme (e.g., a channel of replacement codewords) rather than configuring the second codeword as a forwarding codeword. The channel of replacement codewords may be a more efficient scheme for managing error bits in codewords when the error bits may be due to one or more defect mechanisms associated with a memory die of the memory medium.

[0056] In some cases, the port manager 260-a may determine that the first codeword corresponds to the last codeword retained at the storage medium (e.g., completing a media scrubber operation for a current scrubbing cycle). The port manager 260-a may also update the value of the second counter based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword retained at the storage medium. In some cases, the port manager 260-a may determine an updated value of the second counter relative to a second threshold associated with the number of forwarded codewords retained at the storage medium. The port manager 260-a may also avoid configuring a codeword as a forwarded codeword based on the updated value of the second counter. In some cases, the second threshold may be related to the number of codeword forwarding events allowed during the life cycle of the storage medium. In some cases, the number of codeword forwarding events allowed during the life cycle of the storage medium may be preconfigured based on a ratio between the total number of forwarded codewords budgeted for the storage medium and the total number of codewords retained in the storage medium.

[0057] Figure 3 Examples of codeword formats, shown as 300-a and 300-b (which may also be referred to as codeword layouts 300-a and 300-b), that support media scrubber operations in a memory system according to aspects disclosed herein are shown. Codeword formats 300-a and 300-b may be examples of codeword formats for entire codewords. A codeword may include information indicating that a codeword is stored across multiple channels (e.g., reference Figure 2 A set of bit fields for multiple data bursts for the described channels 291-a to 291-k). Figure 3 Also included are displays for individual channels (e.g., reference Figure 2 Formats 301 to 305 (also referred to as layouts) of various configurations of channels 291 - a ) are described. Figure 3 Also shown is a format 306, which may correspond to a portion of a codeword (eg, a subset of the bit fields during one or more first data bursts across the plurality of lanes).

[0058] As examples of codeword formats and structures, codeword formats 300-a and 300-b may include a number of fields (e.g., bit fields) of data (e.g., 1,408 bits of data) that may be stored by a storage medium (e.g., reference Figure 1 and 2The described memory medium 130-a or memory medium 295-a) is generated in response to an access command or during a background operation, or both. A codeword may contain 128 bytes (e.g., 1,024 bits) of user data. The remaining bit fields within the codeword (e.g., 384 bits of data) may carry various information that may facilitate delivery of accurate user data during an access operation or during a background operation, or both. Further, the remaining bits that carry the various information may be configured to facilitate low latency operations (e.g., standby replacement) associated with the codeword during an access operation.

[0059] Codeword formats 300-a and 300-b may span multiple channels (e.g., channels 310-a through 310-k). One of these channels (e.g., 310-a through 310-k) may be a reference channel. Figure 2 Instances of or including aspects of the described channels 291 (e.g., channels 291-a). In some cases, each channel in the plurality of channels 310 (e.g., channels 310-a) can be associated with one or more 3DXP dies that can include an 8-bit wide data bus. For example, each channel can generate a total of 128 bits of data as a single object of a transaction (e.g., communication, operation) associated with an access command (e.g., a read command) or a background operation or both. Further, the 128 bits of data can be generated as a series of sixteen (16) data bursts, each data burst being configured to generate eight (8) bits of data on an 8-bit wide data bus. Thus, each channel within the codeword format (e.g., each channel in channels 310-a through 310-k) can correspond to 128 bits of data comprising sixteen (16) groups of 8-bit data, such as G7..G0 of channel 310-g, where G7..G0 can represent a series of eight (8) zeros and ones, where G7 can be the most significant bit (e.g., the eighth bit in the series of eight (8) zeros and ones) and G0 can be the least significant bit (e.g., the first bit in the series of eight (8) zeros and ones), where each of the sixteen (16) groups of 8-bit data can be associated with one of the sixteen (16) data bursts.

[0060] In one example, codeword formats 300-a and 300-b may span eleven (11) channels, and each of the eleven (11) channels may generate 8 bits of data at each data burst, and a total of 88 bits of data may be generated at each data burst across the eleven (11) channels (e.g., a first data burst 320-1 of 88 bits of data). Thus, codeword formats 300-a and 300-b may include 1,408 bits of data (e.g., a first data burst 320-1 through a 16th data burst 320-16, where each data burst generates 88 bits of data) as a single object of a transaction to a memory medium (e.g., memory medium 130-a or memory medium 295-a). Codeword formats 300-a and 300-b may support reliable transactions (e.g., conveying accurate content of user data) with low latency (e.g., a small number of clock edges for generating user data).

[0061] Each field (e.g., each bit field) or set of fields (e.g., a set of bit fields) within a codeword may contain information that facilitates reliable user data transactions with low latency. In some cases, one or more fields (e.g., bit fields) within the codeword format may be configured to indicate a codeword condition (e.g., using one or more CwCon bits). A codeword may be configured to be in one of a plurality of possible states (e.g., four states) indicated using the CwCon bits.

[0062] As an example, one or more CwCon bits may indicate that the codeword is one of a normal codeword or a forwarding codeword. As an example, a normal codeword may include codeword formats 300-a and 300-b. A forwarding codeword may include a codeword layout that can facilitate valid replacement addresses (e.g., forwarding addresses) for identifying codewords. In some cases, a forwarding codeword may include at least one copy of an effective address associated with a codeword. Further, one or more CwCon bits may additionally or alternatively indicate that the codeword is one of a non-inverted codeword or an inverted codeword. In some cases, the logical states (e.g., 1 and 0) of bits within an inverted codeword may need to be inverted (e.g., flipped, reversed) before the information of the inverted codeword can be interpreted (e.g., parsed), while a non-inverted codeword may not need to be inverted before the information of the non-inverted codeword is interpreted (e.g., parsed).

[0063] Controller (for example, reference Figure 1 and 2 The controller 120 or port manager 260-a described above may in some cases remove data from storage media (e.g., reference Figure 1 and 2The described storage medium 130-a or storage medium 295-a) retrieves the codeword and inverts at least some, if not all, of the bits of the codeword before writing the codeword back to the storage medium. Writing the codeword back to the storage medium can mitigate undesirable changes in the electrical characteristics of the memory cells retaining the codeword - for example, drift of the threshold voltage of the memory cells that may occur during extended periods of time without access operations. Inverting the logic state of the memory cells (e.g., writing a logic "1" to a memory cell retaining a logic "0" or vice versa) can further mitigate undesirable changes in the electrical characteristics of the memory cells.

[0064] In some cases, the controller may receive a codeword from an address of a storage medium, the codeword comprising a set of bits (e.g., a set of bit fields). The controller may also invert a portion of the bits based on receiving the codeword. In some cases, the controller may set a value of a bit in the set (e.g., a CwCon bit) to indicate a codeword condition comprising an inverted state of the codeword based on inverting the portion of the bits. The controller may also write the codeword back to the address of the storage medium based on setting the value of the bit indicating the inverted state. In some cases, the portion of the bits may include each bit in the set. In some cases, the controller may retrieve each of a plurality of codewords retained at the storage medium as part of a periodic background operation (e.g., a media scrubber operation) independent of an access command from a host, wherein the portion of the bits may be inverted based on retrieving each of the plurality of codewords.

[0065] In some cases, one or more fields within the codeword format may be configured to indicate the number of access operations (e.g., read operations, write operations) associated with the codeword (e.g., WrCnt bits). In some cases, one or more fields within the codeword format may be configured to indicate that a portion of the codeword may be invalid (e.g., using a poison or indication bit). In some cases, one or more fields within the codeword format may be configured as cyclic redundancy check (CRC) bits that may identify error bits related to error control operations.

[0066] In some cases, one or more fields in the codeword format can be configured as codeword error control code bits (e.g., CwECC bits) that support error control operations. In some cases, one or more fields in the codeword format can be configured as XOR bits. Each XOR bit in the XOR bit can contain a digital or Boolean logical exclusive OR (XOR) product of the corresponding bits of other channels of the corresponding data burst. Therefore, the XOR bit can support the repair of the corresponding bits of other channels and can be referred to as a repair bit. In some cases, each XOR bit (e.g., XOR / Sub bit or XORSub bit) can replace a field in the codeword instead of a repair field.

[0067] In some cases, one or more fields within the codeword format may be configured as spare bits (e.g., CRC / spare bits, XORSub / spare bits). Among other alternatives, the bits configured as spare bits may be configured as CRC bits or XOR bits (or XORSub bits). As an example, Figure 3 The codeword formats 300-a and 300-b, respectively depicted in , may include up to twenty-two (22) spare bits - for example, twenty (20) CRC / spare bits and two (2) XORSub / spare bits. That is, some fields of CRC bits may be configured as spare bits. Similarly, some fields of repair bits (e.g., XORSub bits) may be configured as spare bits. Thus, a certain number of spare bits within a codeword may be configurable in that the certain number of spare bits may be exchangeable for a certain number of CRC bits or XORSub bits. In some cases, the number of spare bits in a codeword may be based on the memory technology (e.g., 3DXPoint) used to construct the memory medium (e.g., memory medium 130, memory medium 295). TM , FeRAM, MRAM technology) is determined by the maturity of the technology.

[0068] In some cases, the spare bits can be configured to operate as spare bits to replace bits of the codeword that are designated to have failed (e.g., erroneous bits). In some cases, the bits that are designated to have failed can be associated with MSRs of a memory die (e.g., MSRs that include a certain number of memory cells that may have become erroneous or unreliable). The spare bits (e.g., MSRs corresponding to the spare bits) can be routed (e.g., multiplexed using a multiplexing component) to replace (e.g., substitute) the bits that are designated to have failed (e.g., MSRs corresponding to erroneous bits) to support reliable transactions of user data within the codeword.

[0069] Still refer to Figure 3 , various fields (eg, bit fields) within the codeword format may be configured (eg, arranged) to support low latency operations during access operations associated with the memory medium. Figure 3 Formats 301 through 305 are included that show various configurations of 8-bit groups for separate channels (e.g., each of channels 310-a through 310-k). For example, each of formats 301 through 305 includes eight (8) bit groups that a memory device (e.g., a 3DXP die) within a memory medium (e.g., memory medium 295-a) may generate at a given burst of data. Example formats are described below, but the disclosure herein is not limited to these examples.

[0070] Format 301 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / spare bits (which may be configured as CRC bits or spare bits), and one or more (e.g., three) fields of CRC bits. Format 302 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / spare bits (which may be configured as CRC bits or spare bits), one or more (e.g., two) fields of CRC bits, and one or more (e.g., three) fields of WrCnt bits (e.g., counter bits).

[0071] Format 303 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / spare bits (which may be configured as CRC bits or spare bits), and one or more (e.g., three) fields of WrCnt bits (e.g., counter bits). Format 304 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / spare bits (which may be configured as CRC bits or spare bits), one or more (e.g., two) fields of WrCnt bits (e.g., counter bits), and one or more (e.g., two) fields of corrupted bits (e.g., bits indicating invalidity of a portion of a codeword). Format 305 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of XORSub / spare bits (which may be configured as XORSub bits or spare bits), and one or more (e.g., three) fields of XORSub bits.

[0072] Codeword formats 300-a and 300-b may also display a 1,024-bit user data field (e.g., channels 310-a to 310-h on the second data burst 320-2 to the 16th data burst 320-16 and channels 310-i and 310-j on the second data burst 320-2 to the fifth data burst 320-5), a CwECC field (e.g., channels 310-i and 310-j on the 6th data burst 320-6 to the 16th data burst 320-16), and an XOR / Sub field (e.g., channel 310-k on the second data burst 320-2 to the 16th data burst 320-16).

[0073] As an example of a codeword format that supports low latency operation, a subset of bit fields corresponding to a first data burst (e.g., data burst 320-1) may be configured as shown in format 306. In format 306, each 8-bit group of lane 310-a (e.g., A7..A0) and lane 310-b (e.g., B7..B0) may be configured to have format 301. Likewise, the 8-bit groups of lane 310-c (e.g., C7..C0) may be configured to have format 302. At least some (if not every) 8-bit groups of lanes 310-d (e.g., D7..D0) through 310-i (e.g., I7..I0) may be configured to have format 303. The 8-bit groups of lane 310-j (e.g., J7..J0) may be configured to have format 304. Additionally, the 8-bit groups of lane 310-k (e.g., K7..K0) may be configured to have format 305.

[0074] As a result of configuring a subset of the bit fields of a first data burst (e.g., first data burst 320-1) corresponding to codeword formats 300-a and 300-b (e.g., 88 bits totaling eight (8) bits from each of eleven (11) channels), the first data burst of 88 bits (e.g., 88 bits of format 306) may contain information for facilitating low latency reliable transactions for access operations associated with the codeword (e.g., reading 1,024 bits of user data). In some cases, a port manager (e.g., port manager 260-a) may receive a first portion of a codeword associated with a memory medium (e.g., bits of format 306 corresponding to first data burst 320-1). During a subsequent data burst, the port manager may parse (e.g., interpret) the first portion of the codeword (e.g., identifying the spare bits) concurrently with receiving additional portions of the codeword (e.g., bits of codeword formats 300-a and 300-b corresponding to second data burst 320-2, etc.). Thus, the port manager may parallelize various operations associated with the codewords to provide for reliable, low latency communications or information exchange with the host.

[0075] When the codeword becomes unreliable or almost unreliable, the controller (e.g., reference Figure 1 and 2The controller 120 or port manager 260-a described may configure a codeword as a forwarding codeword. Compared to codeword formats that include user data (e.g., codeword formats 300-a and 300-b), a forwarding codeword format (which may also be referred to as a forwarding codeword layout) may include a certain number of copies of a forwarding address (e.g., a replacement address) to facilitate access to user data. Additionally, in some cases, the forwarding codeword format may include a certain number of bit fields (e.g., one or more CwCon bits) indicating a codeword condition. The forwarding codeword format may also support low latency operations, which in turn may include determining that a codeword is a forwarding codeword and identifying a forwarding address from the forwarding codeword.

[0076] In some cases, the controller may decide to configure the codeword as a forward codeword without waiting for the codeword (e.g., the user data therein) to exceed the error recovery capability of the memory system or subsystem to become unrecoverable. Since the codeword may contain information related to error control operations (e.g., one or more CRC bits, one or more CwECC bits), the controller may determine the number of erroneous bits (e.g., faulty bits) in the codeword based on performing error control operations on the codeword during an access operation (e.g., a read operation) in some cases. The controller may determine the number of erroneous bits relative to (e.g., exceeding, equal to, approaching) an error threshold (e.g., an error threshold at which the codeword may become unreliable or invalid). In some cases, the error threshold may be related to the allowable limit of the number of erroneous bits in the codeword (e.g., the number of erroneous bits that the codeword is pre-configured to recover).

[0077] The controller may configure the codeword as a forwarded codeword according to a forwarded codeword format based on determining the number of error bits in the codeword. In some cases, the error threshold may be configurable based on a number of factors (e.g., the memory technology of the memory device used to manufacture the memory media, the maturity of such memory technology, the memory media usage pattern). The controller may also set one or more CwCon bits to indicate that the codeword is a forwarded codeword.

[0078] Figure 4 An example of a configuration 401 of a memory array and a configuration 402 of a memory medium to support media scrubber operations in a memory system according to aspects disclosed herein is shown. The memory array depicted in configuration 401 may be a reference Figure 1 and 2 Examples of memory dies in the described memory media (e.g., memory media 130 or memory media 295). The memory media depicted in configuration 402 may be referenced Figure 1 and 2Examples of described storage media (eg, storage media 130 or storage media 295). The storage media depicted in configuration 402 may include a number of memory arrays (eg, forty-four (44) memory arrays) that may each be configured according to configuration 401.

[0079] Configuration 401 may include a memory array 410. In some cases, memory array 410 may include a set of memory cells (eg, 512 Gigabit memory cells, 2 39 Memory cells). Memory array 410 can be organized to have array width 415 and array depth 425. In some cases, array width 415 can be referred to as die width 415, and array depth 425 can be referred to as die depth 425. Further, array width 415 and array depth 425 can each be divided into a certain number of partitions. In some cases, array width 415 can be divided into 128 sections. Thus, section 420 depicted in configuration 401 can represent one of the 128 sections in array width 415. Further, each section (e.g., section 420) can be divided into 128 blocks, so that array depth 425 can be divided into 128 bars. Bars can be referred to as sections, sub-sections, parts, elements, etc. Thus, bar 430 depicted in configuration 401 can represent one of the 128 bars in array depth 425.

[0080] Thus, a memory array 410 (e.g., 512-gigabit memory cells) may be divided into a number of segments 435 (e.g., segments 435-a, 435-b, or 435-c) each depicted as a box within the memory array 410 as an example. In this example, the memory array 410 may include 16,384 segments as a result of dividing the array width 415 into 128 segments that are each further divided into 128 bars (e.g., sections, sub-segments, portions, elements) in the array depth 425. Each segment 435 of the memory array 410 may be referred to as an MSR 435. In some cases, an MSR 435 may include a group of memory cells (e.g., 2 MSRs) that may be configured as data units associated with error control operations. 25 The MSR may be configured as a reasonable fault containment area for efficiently managing (eg, replacing, substituting) erroneous bits in the memory array 410.

[0081] The number of segments (e.g., 128 segments) in array width 415 can be determined based on the manner in which a memory array (e.g., memory array 410) is constructed in a memory die. For example, memory array 410 can have a certain number of tiles (e.g., 128 tiles), and the number of segments in array width 415 can be based on the number of tiles of memory array 410. Similarly, the number of bars (e.g., 128 bars) in array depth 425 can be determined based on common characteristics associated with various functional components such as row decoders, column decoders, etc. As a result of partitioning memory array 410 as depicted in configuration 401, each segment 435 (e.g., including 2 of the 16,384 MSRs in memory array 410 containing 512 Gbits) can be determined based on the number of bars in array depth 425. 25 The size of the memory cell unit (e.g., MSR of 2 memory cells) can provide a group of memory cells (e.g., data cells) to efficiently manage (e.g., replace, substitute) error bits in the memory array 410 without incurring significant overhead. In some cases, the size of the memory cell unit (e.g., MSR of 2 memory cells) can be used to efficiently manage (e.g., replace, substitute) error bits in the memory array 410 without incurring significant overhead. 25 Memory cells) can be referred to as the data granularity for supporting efficient error control operations associated with storage media.

[0082] Still referring to configuration 401, a stick 430 spanning a number of sectors (e.g., 128 sectors) can represent a first number of bits (e.g., 128 bits) generated by the memory array 410 as part of a codeword (e.g., part of a codeword containing 1,408 bits). The first number of bits (e.g., 128 bits) of the stick 430 can be further down-multiplexed into a second number of sets of bits (e.g., eight (8) bits), wherein each set of the second number of bits (e.g., eight (8) bits) can be generated at a given data burst (e.g., one of sixteen (16) data bursts producing a total of 128 bits). Thus, the stick 430 can produce a portion of a codeword wherein each segment 435 (e.g., MSR 435) contributes one bit of the first number of bits (e.g., 128 bits) of the codeword. Further, the stick 430 (e.g., 128 bits produced over 16 data bursts) can correspond to a channel (e.g., referring to Figure 2 A complete codeword (e.g., a 1,408-bit codeword) can be generated when a number of memory arrays 410 (e.g., eleven (11) memory arrays 410) are operated in parallel such that each memory array 410 can generate a portion of the bits that make up a complete codeword—for example, each memory array 410 generates 128 bits over sixteen (16) data bursts across eleven (11) channels, for a total of 1,408 bits for the codeword.

[0083] Configuration 402 may include a collection of memory arrays 410 (eg, forty-four (44) memory arrays 410) to implement a memory medium (eg, reference Figure 1 and 2 4. The desired or specified capacity of the storage medium 130 or storage medium 295 described above. The set of memory arrays in the storage medium can be arranged to form a plurality of channels for the storage medium. In some cases, the storage medium can include eleven (11) channels (e.g., channels 440-a through 440-k) as shown in configuration 402. Each channel 440 can be a reference Figure 2 Instances of channels 291 (e.g., channels 291-a through 291-k) described herein or including aspects of the channels. Further, each channel 440 can be configured to include a subset of memory arrays. In some cases, a channel (e.g., channel 440-a) can include four (4) memory arrays 410-a through 410-d. Thus, each of the plurality of channels can, in some cases, include a total number of sticks 430 (e.g., 512 sticks) corresponding to a multiple of the number of sticks of memory arrays 410 within the channel (e.g., 128 sticks) multiplied by the number of memory arrays 410 (e.g., four (4) memory arrays).

[0084] In some cases, a group of MSRs across multiple channels (e.g., eleven (11) channels, i.e., channels 440-a through 440-k) that generate codewords may be referred to as an MSR stripe (e.g., MSR stripe 445 depicted in configuration 402). MSR stripes may also be referred to as MSR regions. For example, the memory medium of configuration 402 includes 512 MSR stripes (e.g., 512 MSR regions). Likewise, MSR stripes (e.g., MSR stripe 445) may correspond to a collective array depth (e.g., collective die depth) of the memory medium—for example, MSR stripe 445 depicted in configuration 402 may correspond to the 130th array depth of the memory medium (e.g., the 130th MSR stripe out of a total array depth of 512 MSR stripes), where each memory array 410 includes 128 MSR stripes. In some cases, a flag may be associated with an MSR stripe (or MSR region) to indicate a change in the allocation of spare bits associated with a codeword retained at the MSR stripe (e.g., MSR stripe 345 or MSR region 345). The flag may be part of a separate memory array (e.g., SRAM memory cells), which in some cases may be integrated into a controller (e.g., reference 1). Figure 1 and 2 Controller 120 or port manager 260-a) as described.

[0085] At least some (if not each) MSR (e.g., MSR 435-a, MSR 435-b, MSR 435-c) of a memory array (e.g., memory array 410) may be associated with a counter configured to count the number of error bits therein. For example, a port manager (e.g., reference Figure 2 The described port manager 260-a) can read codewords from an MSR stripe (e.g., MSR stripe 445) and perform error control operations on the codewords as part of a background operation (e.g., a media scrubber operation). The port manager can identify a certain number of error bits and correct the certain number of error bits in the codeword using a set of bits in the codeword (e.g., bits that support error correction functions). Each error bit in the certain number of error bits (e.g., an erroneous or unreliable memory cell) can correspond to a corresponding MSR of the MSR stripe. The port manager can update a first counter associated with a first MSR of the MSR stripe to count the number of error bits (e.g., an error bit count) in the first MSR of the MSR stripe.

[0086] The port manager may sort the values ​​(e.g., error bit counts) stored in the counters of the codeword (e.g., 1,408 counters each corresponding to the 1,408 MSRs) to identify a subset of values ​​that are greater than the remaining values. For example, the port manager may sort the values ​​(e.g., error bit counts) in descending order to identify a subset of values ​​(e.g., the 160 highest error bit counts of the 1,408 error bit counts associated with the codeword). In this way, the port manager may identify a subset of MSRs that each contain a higher number of error bits than other MSRs. The port manager may identify the subset of MSRs (e.g., 160 of the 1,408 MSRs) as candidates for replacement (e.g., replacing such MSRs with reliable MSRs, such as spare MSRs). In some cases, the port manager may configure the number of values ​​in the subset based on the number of error bits identified in the codeword (e.g., 200 highest error bit counts instead of 160 highest error bit counts). In some cases, such number of values ​​in a subset (e.g., a subset of MSRs identified as candidates for replacement) can be based on various factors (e.g., the memory technology of the memory devices used to manufacture the memory media, the maturity of such memory technology, memory media usage patterns).

[0087] Further, the port manager may replace one or more MSRs with a higher error bit count (e.g., a subset of MSRs identified as candidates for replacement) with a set of spare MSRs until the set of spare MSRs is exhausted. The port manager may determine to replace an MSR based on a number of error bits (e.g., error bit count) in the MSR relative to a threshold (e.g., a bit level replacement threshold). In some cases, the port manager may determine to replace an MSR with an error bit count equal to or greater than the threshold. The threshold may be based on a raw bit error rate (RBER) associated with the memory media. In some cases, the threshold may be based on a size of the MSR (e.g., 2 in the MSR). 25 In some cases, the threshold value may be configurable (eg, programmable) to account for the maturity of technology used to manufacture memory cells of the memory media, such as process variations that may affect electrical characteristics of memory cells of the memory media.

[0088] The port manager may allocate spare MSRs (e.g., spare bits in a codeword) to replace any of the MSRs identified as candidates for replacement (e.g., erroneous bits in a codeword). In some cases, spare bits (e.g., spare MSRs) may be allocated on a first-identify, first-allocate basis. The port manager may repeatedly allocate spare bits to erroneous bits in a codeword until all spare bits (e.g., reference bits) are allocated. Figure 3 The method may further include allocating the spare bits (e.g., spare MSRs) to a different erroneous bit (e.g., a different MSR containing a number of erroneous bits equal to or greater than the bit level threshold) to a codeword until at most twenty-two (22) spare bits are allocated. In some cases, the spare bits (e.g., spare MSRs) may be reallocated to different erroneous bits (e.g., different MSRs containing a number of erroneous bits equal to or greater than the bit level threshold). In other cases, once the spare bits have been allocated to the corresponding erroneous bits, each spare bit may remain allocated to the corresponding erroneous bit in the codeword.

[0089] The port manager may, in some cases, allocate one or more spare bits (e.g., one or more MSRs corresponding to the spare bits) in a codeword as part of a media scrubber operation (e.g., during a first media scrub cycle for an MSR stripe) to replace an erroneous bit (e.g., an MSR corresponding to the erroneous bit) in a codeword (e.g., one of the codewords retained at the MSR stripe). The port manager may set a bit (e.g., a flag) in a separate memory array to indicate such a change in the replacement relationship associated with the codeword retained at the MSR stripe. Setting the bit (e.g., a flag) may also indicate that, although the replacement relationship for the spare bit may have been determined, the spare bit may not contain a valid logic state for the codeword.

[0090] The port manager may maintain a replacement relationship (e.g., spare bit assignments to corresponding error bits) for codewords retained at memory media (e.g., MSR stripes) in a separate memory array. In some cases, the memory array may be integrated as part of the port manager. In some cases, the separate memory array may include static random access memory (SRAM) cells.

[0091] The size of the memory array allocated to preserve the replacement relationship (e.g., the number of SRAM cells) can be based on a bit indicating a change in the replacement relationship (e.g., a flag indicating a change in spare allocation), an identification of a channel associated with the codeword (e.g., an identification of the channel to be replaced), a number of spare bits in the codeword (e.g., up to twenty-two (22) spare bits), an identification of an MSR in a first number of MSRs associated with the codeword (e.g., 1,408 MSRs), a number of bits associated with the forwarded codeword in the memory medium, an error correction capability for the replacement relationship, a number of memory die corresponding to the channels associated with the codeword (e.g., four (4) memory die per channel), or a second number of MSR groups in a memory die in the number of memory dies (e.g., 128 MSR sticks), or any combination thereof.

[0092] The port manager may, in some cases, access the codeword as part of a media scrubber operation (e.g., during a second media scrub cycle for an MSR stripe), replace the erroneous bit with the one or more spare bits according to a replacement relationship saved in a memory array (e.g., an SRAM cell), and perform an error control operation to restore the logic state of the codeword (e.g., a codeword including the one or more spare bits replacing the erroneous bit). The port manager may write the restored logic state (e.g., a valid logic state) at the one or more spare bits and may reset the bit (e.g., a flag) in the memory array (e.g., an SRAM cell). In this way, the one or more spare bits may contain the valid logic state of the codeword, and the bit (e.g., a flag) may indicate that the one or more spare bits in the codeword contain the valid logic state to be implemented (multiplexed into the bit stream of the codeword with a series of data bursts) when the host requests the codeword.

[0093] In some cases, the port manager may receive a codeword retained at a portion of a storage medium, the codeword comprising a plurality of bits including a certain number of spare bits for the codeword. The port manager may also access a memory array of the port manager based on receiving the codeword. In some cases, the port manager may perform an error control operation on the codeword based on accessing the memory array of the port manager to restore a logic state of the plurality of bits. The port manager may also write a logic state of a bit in the plurality of bits at a spare bit in the certain number of spare bits based on performing the error control operation. In some cases, receiving the codeword may include retrieving each of the plurality of codewords retained at the portion of the storage medium as part of a regular background operation independent of an access command from a host.

[0094] In some cases, the port manager may replace a bit in the plurality of bits with a spare bit in the certain number of spare bits based on accessing the memory array, wherein performing an error control operation on the codeword may be based on replacing a bit in the plurality of bits. The port manager may also identify a value of a flag in the memory array based on accessing the memory array, the value of the flag indicating a change in a replacement relationship for codewords retained at the portion of the memory medium, wherein performing an error control operation on the codeword may be based on identifying the value of the flag. In some cases, the port manager may reset the value of the flag in the memory array based on a logic state of a bit in the plurality of bits written, the value of the flag indicating that a spare bit in the certain number of spare bits contains a logic state valid for replacing a bit in the plurality of bits.

[0095] In some cases, the port manager may receive an indication of a power level from a power management component coupled to the port manager and pass information stored in a memory array (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit assignments to error bits) to a memory array such as a reference. Figure 1 and 2 Non-volatile memory (eg, persistent memory) is described.

[0096] Figure 5 A block diagram 500 of a controller 515 supporting media scrubber operations in a memory system according to aspects disclosed herein is shown. The controller 515 may be a reference Figures 1 to 2 1 and 2. The controller 515 may include a bias component 520, a timing component 525, an access manager 530, a codeword manager 535, and an error control manager 540. Each of these modules may be in communication with each other, directly or indirectly (eg, via one or more buses).

[0097] The access manager 530 may receive the first codeword from the storage medium based on setting the value of the second counter. In some cases, the access manager 530 may receive the second codeword from the storage medium based on updating the value of the first counter. In some cases, the access manager 530 may write the first codeword back to the storage medium based on configuring the first codeword as a forwarded codeword. In some cases, receiving the first codeword may further include retrieving the first codeword as part of a regular background operation independent of an access command from the host.

[0098] In some cases, the access manager 530 may receive a codeword reserved at a portion of the storage medium, the codeword including a plurality of bits including a number of spare bits for the codeword. In some cases, the access manager 530 may write a logic state of a bit in the plurality of bits at a spare bit in the number of spare bits based on performing an error control operation. In some cases, receiving the codeword may further include retrieving each of the plurality of codewords reserved at the portion of the storage medium as part of a regular background operation independent of access commands from a host, wherein access to the memory array may be based on retrieving each of the plurality of codewords.

[0099] In some cases, the access manager 530 may receive a codeword from an address of the storage medium, the codeword comprising a set of bits. In some cases, the access manager 530 may write the codeword back to the address of the storage medium based on setting the value of the bit indicating the inversion state.

[0100] The codeword manager 535 may identify a value of a first counter associated with the storage medium, the first counter indicating a first number of codewords retained at the storage medium during a first duration, the first number of codewords being configured as forwarded codewords. In some cases, the codeword manager 535 may set a value of a second counter associated with the storage medium based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the storage medium during a second duration, the second number of codewords being configured as forwarded codewords. In some cases, the codeword manager 535 may configure the first codeword as a forwarded codeword based on the determination.

[0101] In some cases, the codeword manager 535 may update the value of the first counter based on configuring the first codeword as a forwarded codeword. In some cases, the codeword manager 535 may determine an updated value of the first counter relative to a first threshold associated with the number of forwarded codewords retained at the storage medium. In some cases, the codeword manager 535 may refrain from configuring the second codeword as a forwarded codeword based on the updated value of the first counter relative to the first threshold. In some cases, the codeword manager 535 may determine that the first codeword corresponds to the last codeword retained at the storage medium. In some cases, the codeword manager 535 may update the value of the second counter based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword retained at the storage medium.

[0102] In some cases, the codeword manager 535 may determine an updated value of the second counter relative to a second threshold associated with the number of forwarding codewords retained at the storage medium. In some cases, the codeword manager 535 may avoid configuring the codeword as a forwarding codeword based on the updated value of the second counter. In some cases, the codeword manager 535 may reset the value of the first counter based on setting the value of the second counter, wherein receiving the first codeword may be based on resetting the value of the first counter. In some cases, the first duration may be based on a preconfigured period for retrieving the set of codewords from the storage medium. In some cases, the second duration may be based on a life cycle of the storage medium, and wherein the life cycle of the storage medium may be based on an estimated duration for the storage medium to meet a set of operating criteria. In some cases, the forwarding codeword may include a certain number of copies of the forwarding address of the first codeword.

[0103] In some cases, the codeword manager 535 may invert a portion of the set of bits based on receiving a codeword, wherein the codeword may include the set of bits. In some cases, the codeword manager 535 may set the value of a bit in the set of bits to indicate a codeword condition including an inverted state of the codeword based on inverting the portion of bits. In some cases, the portion of bits may include each bit in the set of bits.

[0104] The error control manager 540 may determine that the first codeword satisfies a condition for configuring the first codeword as a forwarding codeword, the condition being based on the number of erroneous bits in the first codeword. In some cases, the error control manager 540 may determine that the second codeword satisfies a condition for configuring the second codeword as a forwarding codeword based on receiving the second codeword.

[0105] In some cases, the error control manager 540 may access a memory array of the port manager based on receiving the codeword. In some cases, the error control manager 540 may perform an error control operation on the codeword based on accessing the memory array of the port manager to restore a logic state of a plurality of bits of the codeword. In some cases, the error control manager 540 may replace a bit of the plurality of bits with a spare bit of the certain number of spare bits based on accessing the memory array, wherein performing the error control operation on the codeword may be based on replacing a bit of the plurality of bits. In some cases, the error control manager 540 may identify a value of a flag in the memory array based on accessing the memory array, the value of the flag indicating a change in a replacement relationship for the codeword retained at the portion of the memory medium, wherein performing the error control operation on the codeword may be based on identifying the value of the flag.

[0106] In some cases, the error control manager 540 may reset a value of a flag in the memory array based on a logic state of a bit in the plurality of bits written, the value of the flag indicating that a spare bit in the number of spare bits contains a logic state valid for replacing a bit in the plurality of bits. In some cases, a size of the memory array for holding a replacement relation for codewords retained at the portion of the memory medium may be based on a bit indicating a change in the replacement relation, an identification of a lane associated with the codeword, a number of spare bits in the codeword, an identification of a minimum replacement region (MSR) in a first number of MSRs associated with the codeword, a number of bits associated with a forwarded codeword in the memory medium, an error correction capability of the replacement relation, a number of memory dies corresponding to a lane associated with the codeword, or a second number of MSR groups in a memory die in the number of memory dies, or any combination thereof.

[0107] Figure 6 A flow chart illustrating a method 600 for supporting media scrubber operations in a memory system according to aspects disclosed herein is shown. The operations of the method 600 may be performed as described in reference to Figures 1 to 2 For example, the operations of method 600 may be implemented by the controller or components thereof described herein. Figures 1 to 2 The controller 120 or controller 230 described herein may be executed. In some examples, the controller 230 may execute a set of codes for controlling the functional elements of the device to perform the functions described below. Additionally or alternatively, the controller 230 may use dedicated hardware to perform various aspects of the functions described below.

[0108] At 605, the controller 230 may identify a value of a first counter associated with the storage medium, the first counter indicating a first number of codewords retained at the storage medium during a first duration, the first number of codewords being configured as forwarded codewords. The operation of 605 may be based on reference Figure 1-5 In some examples, aspects of the operation of 605 may be performed as described in reference Figure 5 The described codeword manager performs

[0109] At 610, the controller 230 may set a value of a second counter associated with the storage medium based on the value of the first counter, the second counter indicating a second number of codewords retained at the storage medium during a second duration, the second number of codewords being configured as forwarded codewords. The operation of 610 may be based on reference Figure 1-5 In some examples, aspects of the operation of 610 may be performed as described in reference Figure 5 The described codeword manager performs

[0110] At 615, the controller 230 may receive a first codeword from the memory medium based on setting the value of the second counter. The operation of 615 may be based on reference Figure 1-5 In some instances, aspects of the operation of 615 may be performed as described in reference Figure 5 The described access manager is executed.

[0111] An apparatus is described for performing one or more methods, such as method 600. The apparatus may include: means for identifying a value of a first counter associated with a storage medium, the first counter indicating a first number of codewords retained at the storage medium during a first time duration, the first number of codewords being configured as forwarded codewords; means for setting a value of a second counter associated with the storage medium based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the storage medium during a second time duration, the second number of codewords being configured as forwarded codewords; and means for receiving the first codeword from the storage medium based on setting the value of the second counter.

[0112] Another apparatus for performing one or more methods, such as method 600, is described. The apparatus may include a storage medium and a controller in electronic communication with the storage medium, wherein the controller may be operable to: identify a value of a first counter associated with the storage medium, the first counter indicating a first number of codewords retained at the storage medium during a first duration, the first number of codewords being configured as forwarded codewords; set a value of a second counter associated with the storage medium based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the storage medium during a second duration, the second number of codewords being configured as forwarded codewords; and receive the first codeword from the storage medium based on setting the value of the second counter.

[0113] Some instances of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for determining that the first codeword satisfies a condition for configuring the first codeword as a forwarding codeword, the condition being based on the number of error bits in the first codeword. Some instances of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for configuring the first codeword as a forwarding codeword based on the determination. Some instances of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for updating a value of a first counter based on configuring the first codeword as a forwarding codeword. Some instances of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for determining an updated value of the first counter relative to a first threshold value associated with the number of forwarding codewords retained at the storage medium.

[0114] Some examples of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for receiving a second codeword from a storage medium based on updating the value of the first counter. Some examples of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for determining that the second codeword satisfies a condition for configuring the second codeword as a forwarding codeword based on receiving the second codeword. Some examples of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for avoiding configuring the second codeword as a forwarding codeword based on an updated value of the first counter relative to a first threshold.

[0115] Some instances of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for determining that the first codeword corresponds to the last codeword retained at the storage medium. Some instances of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for updating the value of the second counter based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword retained at the storage medium. Some instances of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for determining an updated value of the second counter relative to a second threshold value associated with the number of forwarded codewords retained at the storage medium. Some instances of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for avoiding configuring a codeword as a forwarded codeword based on the updated value of the second counter.

[0116] Some instances of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for writing the first codeword back to the storage medium based on configuring the first codeword as a forwarding codeword. Some instances of the methods 600 and apparatus described herein may further include a process, feature, component, or instruction for resetting the value of the first counter based on setting the value of the second counter, wherein receiving the first codeword may be based on resetting the value of the first counter. In some instances of the methods 600 and apparatus described herein, the first duration may be based on a preconfigured period for retrieving the set of codewords from the storage medium. In some instances of the methods 600 and apparatus described herein, the second duration may be based on a life cycle of the storage medium, and wherein the life cycle of the storage medium may be based on an estimated duration for the storage medium to meet a set of operating criteria.

[0117] In some examples of the methods 600 and apparatus described herein, receiving the first codeword may further include retrieving the first codeword as part of a regular background operation independent of access commands from the host. In some examples of the methods 600 and apparatus described herein, forwarding the codeword may include a number of copies of the forwarding address of the first codeword.

[0118] Figure 7 A flow chart illustrating a method 700 for supporting media scrubber operations in a memory system according to aspects disclosed herein is shown. The operations of the method 700 may be performed as described with reference to Figures 1 to 2 For example, the operations of method 700 may be implemented by the controller or components thereof described herein. Figures 1 to 2The controller 120 or controller 230 described herein may be executed. In some examples, the controller 230 may execute a set of codes for controlling the functional elements of the device to perform the functions described below. Additionally or alternatively, the controller 230 may use dedicated hardware to perform various aspects of the functions described below.

[0119] At 705, the controller 230 may receive a codeword retained at a portion of a storage medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword. The operation of 705 may be performed according to reference Figure 1-5 In some examples, aspects of the operation of 705 may be performed as described in reference Figure 5 The described access manager is executed.

[0120] At 710, the controller 230 may access the memory array of the port manager based on the received codeword. The operation of 710 may be performed according to reference Figure 1-5 In some examples, aspects of the operation of 710 may be performed as described in reference Figure 5 The described error control manager is implemented.

[0121] At 715, the controller 230 may perform an error control operation on the codeword based on accessing the memory array of the port manager to restore the logic state of the plurality of bits. The operation of 715 may be based on reference Figure 1-5 In some instances, aspects of the operation of 715 may be performed as described in reference Figure 5 The described error control manager is implemented.

[0122] At 720, the controller 230 may write the logic state of a bit in the plurality of bits at a spare bit in the number of spare bits based on performing an error control operation. The operation of 720 may be based on reference Figure 1-5 In some examples, aspects of the operation of 720 may be performed as described in reference Figure 5 The described access manager is executed.

[0123] An apparatus is described for performing one or more methods such as method 700. The apparatus may include: means for receiving a codeword retained at a portion of a memory medium, the codeword including a plurality of bits including a number of spare bits for the codeword; means for accessing a memory array of a port manager based on receiving the codeword; means for performing an error control operation on the codeword to restore a logic state of the plurality of bits based on accessing the memory array of the port manager; and means for writing a logic state of a bit in the plurality of bits at a spare bit in the number of spare bits based on performing the error control operation.

[0124] Another apparatus for performing one or more methods such as method 700 is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller may be operable to: receive a codeword retained at a portion of the memory medium, the codeword including a plurality of bits including a number of spare bits for the codeword; access a memory array of a port manager based on receiving the codeword; perform an error control operation on the codeword to restore a logic state of the plurality of bits based on accessing the memory array of the port manager; and write a logic state of a bit in the plurality of bits at a spare bit in the number of spare bits based on performing the error control operation.

[0125] Some examples of the method 700 and apparatus described herein may further include a process, feature, means, or instruction for replacing a bit in the plurality of bits with a spare bit in the number of spare bits based on accessing a memory array, wherein performing an error control operation on a codeword may be based on replacing a bit in the plurality of bits.

[0126] Some examples of the methods 700 and apparatus described herein may further include a process, feature, means or instruction for identifying a value of a flag in the memory array based on accessing the memory array, the value of the flag indicating a change in a replacement relationship for codewords retained at the portion of the memory medium, wherein performing error control operations on the codewords may be based on the value of the identified flag. Some examples of the methods 700 and apparatus described herein may further include a process, feature, means or instruction for resetting a value of a flag in the memory array based on a logic state of a bit in the plurality of bits written thereto, the value of the flag indicating that a spare bit in the number of spare bits contains a logic state valid for replacing a bit in the plurality of bits.

[0127] In some examples of the methods 700 and apparatus described herein, a size of a memory array for holding a substitution relation for codewords retained at the portion of the memory medium can be based on a bit indicating a change in the substitution relation, an identification of a channel associated with the codeword, a number of spare bits in the codeword, an identification of a minimum substitution region (MSR) in a first number of MSRs associated with the codeword, a number of bits associated with forwarded codewords in the memory medium, an error correction capability of the substitution relation, a number of memory die corresponding to the channel associated with the codeword, or a second number of MSR groups in a memory die in the number of memory dies, or any combination thereof.

[0128] In some examples of the methods 700 and devices described herein, receiving the codeword can further include retrieving each of a plurality of codewords retained at the portion of the storage medium as part of a periodic background operation independent of access commands from the host, wherein accessing the memory array can be based on retrieving each of the plurality of codewords.

[0129] Figure 8 A flow chart illustrating a method 800 for supporting media scrubber operations in a memory system according to aspects disclosed herein is shown. The operations of the method 800 may be performed as described in reference to Figures 1 to 2 For example, the operations of method 800 may be implemented by the controller or components thereof described herein. Figures 1 to 2 The controller 120 or controller 230 described herein may be executed. In some examples, the controller 230 may execute a set of codes for controlling the functional elements of the device to perform the functions described below. Additionally or alternatively, the controller 230 may use dedicated hardware to perform various aspects of the functions described below.

[0130] At 805, the controller 230 may receive a codeword from an address of a memory medium, the codeword comprising a set of bits. The operation of 805 may be performed according to the reference Figure 1-5 In some instances, aspects of the operation of 805 may be performed as described in reference Figure 5 The described access manager is executed.

[0131] At 810, the controller 230 may invert a portion of the bits based on the received codeword. The operation of 810 may be based on the reference codeword. Figure 1-5 In some examples, aspects of the operation of 810 may be performed as described in reference Figure 5 The described codeword manager performs

[0132] At 815, the controller 230 may set the value of the bits in the set to indicate a codeword condition including an inverted state of the codeword based on inverting the portion of the bits. The operation of 815 may be based on reference Figure 1-5 In some instances, aspects of the operation of 815 may be performed as described in reference Figure 5 The described codeword manager performs

[0133] At 820, the controller 230 may write the codeword back to the address of the memory medium based on the value of the bit indicating the inversion state being set. The operation of 820 may be based on reference Figure 1-5 In some examples, aspects of the operation of 820 may be performed as described in reference Figure 5 The described access manager is executed.

[0134] An apparatus is described for performing one or more methods, such as method 800. The apparatus may include: means for receiving a codeword from an address of a storage medium, the codeword including a set of bits; means for inverting a portion of the bits based on receiving the codeword; means for setting values ​​of bits in the set to indicate a codeword condition including an inverted state of the codeword based on inverting the portion of the bits; and means for writing the codeword back to the address of the storage medium based on setting the values ​​of the bits indicating the inverted state.

[0135] Another apparatus is described for performing one or more methods, such as method 800. The apparatus may include a storage medium and a controller in electronic communication with the storage medium, wherein the controller may be operable to: receive a codeword from an address of the storage medium, the codeword including a set of bits; invert a portion of the bits based on receiving the codeword; set values ​​of bits in the set to indicate a codeword condition including an inverted state of the codeword based on inverting the portion of the bits; and write the codeword back to the address of the storage medium based on setting the values ​​of the bits indicating the inverted state.

[0136] In some examples of the methods 800 and apparatus described herein, the portion of bits may include each bit in the set. In some examples of the methods 800 and apparatus described herein, receiving the codeword may further include retrieving each codeword of a plurality of codewords retained at the storage medium as part of a regular background operation independent of access commands from a host, wherein inverting the portion of bits may be based on successively retrieving each codeword of the plurality of codewords.

[0137] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible.Furthermore, instances of two or more methods may be combined in a method.

[0138] The information and signals described herein may be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have various bit widths.

[0139] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components that are electronically communicating or coupled to each other may actively exchange electrons or signals (e.g., in an energized circuit) or may not actively exchange electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals when the circuit is energized. For example, two components that are physically connected by a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

[0140] The chalcogenide material may be a material or alloy containing at least one of the elements S, Se and Te. The phase change material discussed herein may be a chalcogenide material. The chalcogenide material may include an alloy of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to: Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge- As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te- Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, a hyphenated chemical composition symbol indicates an element contained in a particular compound or alloy and is intended to represent all stoichiometric amounts containing the indicated element. For example, Ge-Te may contain Ge x Te y , where x and y can be any positive integer. Other examples of variable resistance materials can include binary metal oxide materials or mixed valence oxides including two or more metals such as transition metals, alkaline earth metals and / or rare earth metals. Examples are not limited to specific variable resistance materials or materials associated with memory elements of memory cells. For example, other examples of variable resistance materials can be used to form memory elements and can include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, etc.

[0141] The devices discussed herein, including the memory media 130, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP) or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0142] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented within the scope of the claims or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example (example / instance) or illustration", rather than "preferred" or "better than other examples". In order to provide an understanding of the described techniques, the detailed description includes specific details. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0143] In the drawings, similar components or features may have the same reference number. Further, individual components of the same type may be distinguished by following the reference number with a dash and a second reference that distinguishes between the similar components. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number, regardless of the second reference number.

[0144] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description herein may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0145] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0146] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function can be stored on a computer-readable medium as one or more instructions or codes or transmitted by a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software, hardware, firmware, hard wiring, or any combination of these items executed by a processor. The features of the implementation functions can also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. Moreover, as used herein (included in the claims), as used in a list of items (e.g., a list of items starting with phrases such as "at least one of ... or "one or more of ..."), "or" indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a conditional closed set. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope disclosed herein. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0147] Computer-readable media includes both non-transitory computer storage media and communication media, and the communication media includes any media that promotes computer programs to be transferred from one place to another.Non-transitory storage media can be any available media that can be accessed by a general-purpose computer or a special-purpose computer.By way of example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, disk storage devices or other magnetic storage devices or can be used for carrying or storing desired program code components in the form of instructions or data structures and can be accessed by a general-purpose computer or a special-purpose computer or a general-purpose processor or a special-purpose processor.In addition, any connection is appropriately referred to as computer-readable media.For example, if coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are used to transmit software from a website, a server or other remote sources, the coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0148] The description herein is provided to enable those skilled in the art to form or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is intended to conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operation, comprising: identifying a value of a first counter associated with a storage medium, the first counter indicating a first number of codewords retained at the storage medium during a first time duration, the first number of codewords being configured as forwarded codewords, wherein the first time duration is based on a preconfigured period for retrieving a set of codewords from the storage medium; setting a value of a second counter associated with the storage medium based on the value identifying the first counter, the second counter indicating a second number of codewords retained at the storage medium during a second time duration, the second number of codewords being configured as forwarded codewords, wherein the second time duration is based on a lifecycle of the storage medium, and wherein the lifecycle of the storage medium is based on an estimated duration that the storage medium meets a set of operating criteria; as well as A first codeword is received from the memory medium based on setting the value of the second counter.

2. The method according to claim 1, further comprising: determining that the first codeword satisfies a condition for configuring the first codeword as a forwarding codeword, the condition being based on a number of error bits in the first codeword; as well as The first codeword is configured as the forwarding codeword based on the determination.

3. The method according to claim 2, further comprising: updating the value of the first counter based on configuring the first codeword as the forwarding codeword; as well as An updated value of the first counter relative to a first threshold associated with a number of forwarding codewords retained at the memory medium is determined.

4. The method according to claim 3, further comprising: receiving a second codeword from the memory medium based on updating the value of the first counter; determining, based on receiving the second codeword, that the second codeword satisfies a condition for configuring the second codeword as a second forwarding codeword; as well as Configuring the second codeword as the second forwarding codeword is avoided based on an updated value of the first counter relative to the first threshold.

5. The method according to claim 3, further comprising: determining that the first codeword corresponds to a last codeword retained at the storage medium; as well as The value of the second counter is updated based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword retained at the memory medium.

6. The method according to claim 5, further comprising: determining an updated value of the second counter relative to a second threshold associated with the number of forwarded codewords retained at the storage medium; as well as Avoid configuring a codeword as the forwarding codeword based on the updated value of the second counter.

7. The method according to claim 2, further comprising: The first codeword is written back to the storage medium based on configuring the first codeword as the forwarding codeword.

8. The method according to claim 1, further comprising: The value of the first counter is reset based on setting the value of the second counter, wherein receiving the first codeword is based on resetting the value of the first counter.

9. The method of claim 1 , wherein receiving the first codeword further comprises: The first codeword is retrieved as part of a regular background operation independent of access commands from the host.

10. The method of claim 1, wherein the forwarding codeword comprises a number of copies of a forwarding address of the first codeword.

11. A method for memory operation, comprising: receiving a codeword retained at a portion of a storage medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword; accessing a memory array of the port manager based on receiving the codeword; replacing a bit in the plurality of bits with a spare bit in a number of spare bits based on accessing the memory array; performing an error control operation on the codeword based on replacing the bit in the plurality of bits to restore logic states of the plurality of bits; as well as Based on performing the error control operation, a logic state of the bit in the plurality of bits is written at the spare bit in the number of spare bits.

12. The method according to claim 11, further comprising: A value of a flag in the memory array is identified based on accessing the memory array, the value of the flag indicating a change in a replacement relationship for the codewords retained at the portion of the memory medium, wherein performing the error control operation on the codewords is based on identifying the value of the flag.

13. The method according to claim 11, further comprising: A value of a flag in the memory array is reset based on the logic state written to the bit of the plurality of bits, the value of the flag indicating that the spare bit of the number of spare bits includes the logic state valid for replacing the bit of the plurality of bits.

14. The method of claim 11, wherein a size of the memory array used to hold a replacement relationship for the codewords retained at the portion of the memory medium is based on: bits indicating a change in the replacement relationship, an identification of a channel associated with the codeword, the number of spare bits in the codeword, an identification of an MSR in a first number of minimum replacement regions MSRs associated with the codeword, a number of bits associated with a forwarded codeword in the memory medium, an error correction capability of the replacement relationship, a number of memory dies corresponding to the channel associated with the codeword or a second number of MSR groups in a memory die in the number of memory dies, or any combination thereof.

15. The method of claim 11, wherein receiving the codeword further comprises: Each of a plurality of codewords retained at the portion of the memory medium is retrieved as part of a periodic background operation independent of access commands from a host, wherein accessing the memory array is based on retrieving each of the plurality of codewords.

16. A method for memory operation, comprising: receiving a codeword from an address of a storage medium, the codeword comprising a set of bits; inverting a portion of the set of bits based on receiving the codeword; setting values ​​of bits in the set of bits to indicate a codeword condition including an inversion state of the codeword based on inverting the portion of the set of bits, wherein the inversion state indicates a non-inverted codeword or an inverted codeword; and The codeword is written back to the address of the memory medium based on setting the value of the bit indicating the inversion state.

17. The method of claim 16, wherein the portion of the set of bits includes every bit in the set of bits.

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