Data processing system

Abstract

The present invention relates to a data processing system. A data processor includes: an execution unit (42) that executes instructions to perform data processing operations; a register file (46) that can store data values ​​used by the execution unit and generated by the execution unit during operation; and a buffer (52) located between the register file and the execution unit, for providing data values ​​from the register file to the execution unit for use when executing instructions, and receiving output data values ​​from the execution unit to write to the register file. Instructions to be executed by the execution unit (42) of the data processor have an associated buffer eviction priority indication, which indicates the priority with which output data values ​​that will be generated when executing the instruction are evicted from the buffer (52). The buffer eviction priority indication is then used when selecting data values ​​to be evicted from the buffer (52).

Description

Technical Field

[0001] The present invention generally relates to the operation of a data processor that executes program instructions to perform processing operations, such as operations in a graphics processor that executes a graphics processing pipeline that includes one or more programmable processing stages ("shaders"). Background Art

[0002] Graphics processing is typically performed in a pipelined manner, where one or more pipelined stages operate on data to generate a final rendered output, such as a displayed frame. Many graphics processing pipelines today include one or more programmable processing stages, commonly referred to as "shaders." For example, a graphics processing pipeline may include one or more of, and typically all of, the following: a geometry shader, a vertex shader, and a fragment (pixel) shader. These shaders are programmable processing stages that execute a shader program on input data values ​​to generate a desired output data set, such as appropriately shaded and rendered fragment data in the case of a fragment shader, for processing by the rest of the graphics processing pipeline and / or for output.

[0003] In a graphics shader operation, each "item" of graphics work (an "item" in this regard is typically a vertex or sample position (e.g., in the case of a fragment shader)) in generating graphics output (such as a render target, e.g., a frame) will be processed by an execution thread, which will execute the instructions in the shader program in question for the "item" of graphics work in question.

[0004] To execute shader programs, a graphics processor (graphics processing unit (GPU)) will include one or more appropriate execution units (one or more circuits) for this purpose. An execution unit will include programmable processing circuitry for executing shader programs (the "shaders" of the graphics processing pipeline).

[0005] When executing the shader program, the actual data processing operations performed by the shader execution unit are typically performed by corresponding functional units (circuits) of the execution unit (such as math units (circuits)) in response to and under the control of the instructions in the (shader) program being executed. Thus, for example, the appropriate functional units (such as math units) will perform data processing operations in response to and as required by the instructions in the (shader) program being executed.

[0006] When executing instructions in a program, an execution unit (e.g., an appropriate functional unit of the execution unit, such as a math unit) will typically read one or more input data values ​​(operands), perform a processing operation using those input data values ​​to generate output data values, and then return the output data values, e.g., for further processing by subsequent instructions in the program being executed and / or for output (for other uses outside of execution of the program being executed).

[0007] Input data values ​​to be used when executing an instruction will typically be stored in a suitable storage unit accessible to the execution (functional) unit, such as a register file (a set of registers) of and / or accessible to the execution unit, and output data values ​​generated by the execution (functional) unit when executing the instruction will correspondingly be written back to the storage unit, such as the register file, for future use. Thus, when executing an instruction, the execution unit will read input data values ​​(operands) from a suitable storage unit, such as a register file, and write its output values ​​back to the storage unit (e.g., the register file).

[0008] To facilitate this operation, the instruction to be executed will typically indicate the locations of the input data values ​​(operands) for the instruction (e.g., in terms of registers storing these values) and, correspondingly, the locations to which the output data values ​​are to be written (again, for example and typically in terms of the identity of the registers to which the output data values ​​are to be written). Then, when executing the instruction, the execution unit will read the input values ​​from the indicated locations (e.g., registers) and write its output values ​​back to the indicated destination locations (e.g., registers). Summary of the Invention

[0009] Applicants recognize that there is room for improvement in the operation when executing sequences of instructions in an execution unit of a data processor, such as a graphics processor.

[0010] According to a first aspect of the present invention, there is provided a method of operating a data processing system, the data processing system comprising:

[0011] A data processor in which an execution thread can execute program instructions to perform data processing operations, the data processor comprising:

[0012] an execution unit, which, when in operation, can execute instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and

[0013] a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread;

[0014] The data processor further comprises:

[0015] a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and

[0016] a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion;

[0017] The method comprises the following steps:

[0018] For a program comprising a set of instructions to be executed by the execution unit of the data processor:

[0019] associating at least one instruction of the program to be executed by the execution unit of the data processor with an indication representing a priority for evicting from the buffer an output data value to be generated upon execution of the instruction;

[0020] The execution unit writes the following to the buffer when executing the following instruction in the program, the instruction having an associated indication indicating a priority for evicting from the buffer an output data value that will be generated when executing the instruction:

[0021] an output data value generated when executing the instruction, and an indication associated with the instruction indicating the priority for evicting the output data value from the buffer;

[0022] and

[0023] When a data value is to be evicted from the buffer, the buffer controller:

[0024] selecting a data value for eviction from the buffer using, at least in part, any indication of a priority for eviction from the buffer stored with the data value in the buffer;

[0025] and

[0026] The selected data value is evicted from the buffer.

[0027] According to a second aspect of the present invention, there is provided a data processing system, the data processing system comprising:

[0028] A data processor in which an execution thread can execute program instructions to perform data processing operations, the data processor comprising:

[0029] an execution unit, which, when in operation, can execute instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and

[0030] a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread;

[0031] The data processor further comprises:

[0032] a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and

[0033] a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion;

[0034] The data processing system further includes:

[0035] processing circuitry which, for a program comprising a set of instructions to be executed by the execution unit of the data processor, is operable to:

[0036] At least one instruction of the program to be executed by the execution unit of the data processor is associated with an indication representing a priority for evicting from the buffer an output data value to be generated upon execution of the instruction; wherein:

[0037] The execution unit of the data processor is further configured to, upon executing the following instruction in the program, write the following to the buffer, the execution unit having an associated indication indicating a priority for evicting from the buffer output data values ​​to be generated upon execution of the instruction:

[0038] an output data value generated when the instruction is executed, and an indication associated with the instruction indicating the priority for evicting the output data value from the buffer; and

[0039] The buffer controller is further configured to, when a data value is to be evicted from the buffer:

[0040] selecting a data value for eviction from the buffer using, at least in part, any indication of a priority for eviction from the buffer stored with the data value in the buffer;

[0041] and

[0042] The selected data value is evicted from the buffer.

[0043] The present invention relates to a data processor for executing instructions to perform data processing operations. The data processor comprises a suitable storage portion (such as a register file) in which input data values ​​and output data values ​​for the data processing operations performed by executing the instructions are stored.

[0044] However, in the present invention, in addition to the "main" storage part (such as a register file) that stores input values ​​and output values ​​for instructions, the data processor also includes a buffer located between the "main" storage part (such as the register file) and the execution unit that processes the data values. When in operation, the buffer can store data values ​​from the "main" storage part for use by the execution unit, and data values ​​output by the execution unit for storage in the "main" storage part.

[0045] As will be discussed in more detail below, the buffer can serve as a relatively local temporary storage for data values ​​used and / or generated by the execution unit as it executes instructions, thereby, for example, reducing the need to retrieve data values ​​from or write data values ​​to "main" storage (such as a register file) as the instruction sequence is executed. This can then reduce the bandwidth of the "main" storage (register file), and thus correspondingly reduce energy consumption, and make the bandwidth of the "main" storage (e.g., register file) available for other uses.

[0046] For example, an output value written by one instruction and read by a subsequent instruction can be retained in a buffer between the execution of the two instructions, thereby avoiding the need to write the value out to "main" storage (e.g., a register file) and then read the value back from the "main" storage for the subsequent instruction. This can reduce latency between the execution of instructions and avoid the need to read data values ​​from "main" storage (e.g., a register file), and potentially also avoid the need to write data values ​​to main storage (e.g., a register file), thereby reducing main storage bandwidth and reducing energy consumption.

[0047] As will be discussed further below, the applicant has also recognised that, while the use of such a buffer between an execution unit and, for example, a register file is beneficial, as discussed above, it may not be practical or desirable for the buffer to have the capacity to store as many data values ​​(entries) as the main storage (e.g., register file). Therefore, the intermediate buffer should, and preferably does, only have capacity for a limited number of data values ​​(entries). The effect of this is that it may be desirable to be able to replace entries in the buffer with new input data values ​​for an instruction and / or output data values ​​generated by an instruction during use. Therefore, some mechanism will be required to control the replacement of data values ​​in the buffer. In the present invention, this is facilitated by having a buffer controller that can selectively evict data values ​​from the buffer during operation (e.g., when space in the buffer is required for a new data value).

[0048] Furthermore, in the present invention, an instruction that generates an output data value to be written to a buffer may include an indication of a priority for evicting the output data value for the instruction from the buffer. As will be discussed further below, the applicant has recognized that by providing such an indication ("hint") to indicate the priority for evicting data values ​​from the buffer, this can allow for more efficient and effective eviction of data values ​​from the buffer, thereby, for example, reducing stall cycles and improving average utilization of buffer resources, which in turn can further reduce the bandwidth of main storage (e.g., register file), thereby reducing energy consumption and allowing the bandwidth of main storage (register file) to be used for other purposes.

[0049] In particular, applicants have recognized that while data values ​​to be evicted from a buffer can be selected based on a relatively simple eviction scheme (such as a "first in, first out" or "least recently used" type scheme), this may not be the optimal eviction scheme for the buffer. In particular, applicants have recognized that when generating an instruction sequence for a program to be executed by an execution unit of a data processor, it is possible to determine those output data values ​​for that instruction that are more likely to be used by subsequent instructions (and, for example, only by subsequent instructions in the instruction sequence in question) (such that it may be beneficial to attempt to retain these data values ​​in the buffer), and vice versa. Thus, when generating an instruction sequence for a program to be executed by an execution unit, it is possible to determine a measure of the degree to which it is desirable to retain output data values ​​from that instruction in the buffer (and vice versa).

[0050] Applicants have also recognized that by including an indication of the "eviction priority" metric in the instruction itself, the metric can be indicated to the eviction process for the buffer. This facilitates a more direct communication of the "eviction priority" information to the execution unit (specifically, the execution unit's buffer controller), which then uses the "eviction priority" indication included in the instruction when selecting data values ​​to be evicted from the buffer.

[0051] Furthermore, because the "eviction priority" indication is included in the instruction itself, it can be ignored or disabled as desired if operation in the manner of the present invention is inappropriate or unsupported for any reason.

[0052] This directly provides more optimized data value eviction operations for the buffer without requiring significant modifications to the data processor and other aspects of its operation, and still provides improved average buffer utilization and reduced main storage (register file) bandwidth.

[0053] The data processor may be any desired and suitable data processor that can execute program instructions. Typically, the data processor is preferably a data processor that can perform vector (SIMD (Single Instruction Multiple Data)) processing, such as a graphics processor, a vector processor, a DSP, or a CPU (when performing SIMD processing). In a preferred embodiment, the data processor is a graphics processor (graphics processing unit (GPU)).

[0054] The methods of the present invention may be implemented for any suitable and desired program to be executed by a data processor. In the case of a graphics processor, the program may be (and preferably is) a (graphics) shader program. The program may be, for example, a geometry shader program (a program for performing geometry shading operations), a vertex shader program (a program for performing vertex shading operations), or a fragment shader program (a program for performing fragment shading operations).

[0055] The program will include a series of instructions to be executed. The set of instructions (sequence) executed for the program can be any desired and suitable instructions. The program instructions may include, for example, one or more or all of the following: arithmetic (mathematical) operations (addition, subtraction, multiplication, division, etc.), bit operations (negation, exchange, shift, etc.), logical operations (AND, OR, NAND, NOR, NOT, XOR, etc.), load-type instructions (such as change, texture or load instructions in the case of graphics processing), and storage-type instructions (such as blend or store instructions).

[0056] In a preferred embodiment, the present invention is used for executing a (programmable) processing stage of a data processing pipeline and is used when a data processor (an execution unit of the data processor) is executing a (programmable) processing stage of the data processing pipeline. Thus, in this case, the execution unit will execute a program (a set of instructions) to perform the processing operations of the (programmable) processing stage of the data processing pipeline.

[0057] In the case of a graphics processor executing a graphics processing pipeline, the programmable processing stage preferably comprises a programmable shading stage (shader). The programmable processing stage being executed by the program may be, for example, a geometry shading stage (geometry shader), a vertex shading stage (vertex shader), or a fragment shading stage (fragment shader).

[0058] Operations according to the methods of the present invention can be and preferably are applied to multiple processing stages of a data processing pipeline (where the pipeline includes multiple programmable processing stages). Preferably, operations according to the methods of the present invention are applied to all (programmable) processing stages that a data processor (e.g., a graphics processor) may need to execute.

[0059] For example, as needed and as the case may be, the operation of the method of the present invention may be performed for or with respect to each program and / or (programmable) processing stage executed by a data processor, or only for programs or processing stages of a particular class or type and not for other classes or types of programs or processing stages. For example, a compiler may indicate whether the present invention is to be used for a program to be executed.

[0060] The data processor may comprise a single execution unit, or may have multiple execution units. In the case of multiple execution units, each execution unit may preferably operate in the manner of the present invention.

[0061] Where there are multiple execution units, each execution unit may have its own storage and buffer located intermediate to that storage, or there may be a single storage and / or a single buffer shared among multiple (e.g., some or all) separate execution units.

[0062] Where there are multiple execution units, each execution unit may be provided as separate circuitry from the other execution units of the data processor, or the execution units may share some or all of their circuitry (circuit elements).

[0063] The or each execution unit may, and preferably does, include appropriate circuitry (processing circuitry / logic) for carrying out the operations required of the execution unit.

[0064] Thus, an execution unit will, for example, and preferably does, include a set of at least one functional unit (circuitry) that, when operative, can perform data processing operations for instructions executed by an execution thread. An execution unit may include only a single functional unit, or may include multiple functional units, depending on the operations to be performed by the execution unit.

[0065] The functional unit may include any desired and appropriate functional unit that can respond to program instructions and perform data processing operations according to program instructions when in operation. Therefore, preferably, the functional unit includes one or more or all of the following: a mathematical unit (mathematical logic unit) (addition, subtraction, multiplication, division, etc.), a bit operation unit (inversion, exchange, shift, etc.), a logical operation unit (AND, OR, NAND, NOR, NOT, XOR, etc.), a load-type unit (such as a change, texture or load unit in the case of a graphics processor), and a storage-type unit (such as a mixing or storage unit).

[0066] The functional units may be implemented as required and in any suitable way.A functional unit will comprise (be implemented as) suitable hardware elements, such as processing circuitry (logic).

[0067] The execution unit may, for example, include multiple groups of functional units, each of which performs a specific and, for example, different type of operation. For example, there may be a group of functional units (pipeline) for performing mathematical operations (math pipeline) (and in particular including mathematical units), another group of functional units for performing load / store operations (load / store pipeline) (and in particular including load and / or store type functional units), and so on.

[0068] In the case where the execution unit has multiple groups of functional units (pipelines), each group of functional units may have its own storage section and buffer located intermediate to the storage section, or there may be storage sections and / or buffers shared between multiple (e.g., some or all) separate groups of execution units.

[0069] In a preferred embodiment, all functional unit groups preferably have access to the (same) (shared) memory for the execution units, but on the other hand, preferably only some, but not all, functional unit groups have buffers for storing data values ​​local to the functional unit group. For example, the math pipeline (functional unit group) preferably has a buffer, but the load / store pipeline (functional unit group) may not have a buffer.

[0070] The data processor preferably also includes any other appropriate and desired units and circuits required for the operation of the execution unit, such as appropriate control circuitry (control logic) for controlling the execution unit to cause and perform desired and appropriate processing operations. In a preferred embodiment, the data processor preferably includes one or more of the following items, preferably all of the following items: one or more instruction decoding circuits, which when operated can decode the instructions to be executed so that the execution unit executes the required instructions; one or more instruction fetch circuits (before the decoding circuits) which when operated can fetch the instructions to be executed; an instruction cache; and an execution thread generator and scheduler (derivator) which generates (derives) threads for execution.

[0071] The storage unit that can store data for use by one or more execution units of the data processor during operation can take any suitable and desired form. The storage unit preferably takes the form of a suitable RAM (preferably SRAM). In a preferred embodiment, the storage unit has the form of a set of registers (register file) of the data processor or a set of registers (register files) that can be accessed by the data processor. There can be a single storage unit (register file) for all execution units of the data processor, or there can be multiple different groups of such storage units (register files), such as for corresponding individual execution units or subsets of the execution units of the data processor. The group of registers (register files) can be arranged in any suitable and desired manner, for example, including a single or multiple banks, etc.

[0072] The data processor preferably has an interface to and communicates with memory of the data processor or to which the data processor has access (such as a load / store pipeline) (such as the main memory of a data processing system of which the data processor is a part) to load data values ​​from memory into storage, and to write data values ​​from storage to memory.

[0073] The buffer may take any suitable and desired form, the buffer being located between the storage section and the execution unit, receiving data values ​​from the storage section (register file) and providing these data values ​​to the execution unit (to one or more functional units of the execution unit) for use when executing instructions, and receiving output data values ​​from the execution unit (from one or more functional units of the execution unit) to be written to the storage section (register file).

[0074] Again, there may be a single buffer between storage (register file(s)) and the execution units, or there may be multiple buffers, eg for respective execution units or subsets of execution units.

[0075] The buffer should and preferably is located locally (closer to) the execution unit it serves (as opposed to the storage (register file) from which data values ​​are loaded into and sent from the buffer for more "permanent" storage). In contrast to the storage (register file) which can be accessed by other execution units, components, elements, etc. of the data processor, the buffer is preferably accessible only to the execution unit or units it serves.

[0076] The buffer is preferably implemented as a set of flip-flops (rather than SRAM).

[0077] The buffer storing data values ​​between the main storage (register file) and the execution units can be configured in any suitable and desired manner. In a particularly preferred embodiment, the buffer can store a plurality of data value entries (but fewer than the entries (data values) of the "main" storage (register file)). In a preferred embodiment, the buffer can store approximately 8 entries (e.g., 8 entries) (while the register file can have, for example, approximately 64 registers per thread).

[0078] Each entry in the buffer may preferably store a single data value for each thread executing instructions in parallel (lockstep) (in a SIMD system). Thus, each entry in the buffer may store only a single data value (for a thread), but preferably stores multiple data values ​​(one for each of the multiple threads). For example, where the execution unit can execute 16 threads in parallel (lockstep), each buffer entry may preferably store 16 data values ​​(one for each thread).

[0079] Each entry in the buffer preferably stores a data value (for each of the threads in question) from (in the case of an input value) or for (in the case of an output value) a particular register.

[0080] In addition to the data value itself, each buffer entry preferably also stores an identifier (tag) for the entry (for the data value in the entry). The tag is preferably the index of the register from which the data value was taken (register index) (for input data values) or the index of the register to which the data value should be written (register index) (for output data values).

[0081] Each buffer entry preferably also has an associated "free" flag that can be set to indicate that the entry is free and therefore available for storing new data values.

[0082] In addition to storing data values, according to the present invention, a data entry in the buffer, and preferably a plurality of data entries, and preferably each data entry, may also store an indication of a priority for eviction of the data value stored in the buffer entry from the buffer. Thus, in a preferred embodiment, in accordance with the present invention, each buffer entry stores an eviction priority indication for it and includes a field for the eviction priority indication.

[0083] For any buffer entry storing an output data value generated by an instruction having an associated eviction priority indication, the eviction priority indication for that buffer entry will be set based on and corresponding to the eviction priority indication associated with the instruction in question.

[0084] On the other hand, for buffer entries that store data values ​​that are not output values ​​from instructions having an associated eviction priority indication, such as in the case of buffer entries that store input data values ​​for an instruction (data values ​​read from storage (register file)), the priority indication of these data entries is preferably set to a specific (preferably selected, preferably predefined) default (priority) value when loaded into the buffer (the buffer entry in question). In a preferred embodiment, the specific default eviction priority value indicates a low eviction priority, and preferably the lowest eviction priority that can be indicated. Thus, in a preferred embodiment, the eviction priority indication for buffer entries that store instruction input data values ​​(values ​​read from storage (register file)) is set to a low eviction priority, and preferably the lowest eviction priority that can be indicated. When such input value is used and is no longer needed, the input value (entry) can be marked as "free" and can therefore be used for new data.

[0085] In the present invention, instructions to be executed by a data processor may be associated with an indication indicating a priority for eviction from a buffer of output data values ​​that will be generated upon execution of the instructions. In a preferred embodiment, only certain, e.g., some (but not all) instructions in a program to be executed (such as selected instructions, e.g., meeting certain criteria) are associated with an eviction priority indication.

[0086] In a particularly preferred embodiment, (all) instructions that generate output values ​​have an associated eviction priority indication. Thus, in a particularly preferred embodiment, when applying the present invention to a program, all instructions in the program to be executed that write results (output data values) to a buffer (to storage) have an associated eviction priority indication.

[0087] Preferably, instructions that do not write output values ​​to a buffer (write to storage) do not have an associated eviction priority indication. Thus, in a preferred embodiment, instructions that do not produce a result (e.g., jumps, no-ops, instructions, etc.) do not have an associated eviction priority indication.

[0088] Similarly, instructions (such as load instructions) executed in a set of functional units (pipeline) that do not have a buffer between storage and the functional units, but instead, for example, write directly to storage, preferably do not have an associated eviction priority indication.

[0089] Of course, other configurations would be possible.

[0090] The indication representing the priority for eviction of output data values ​​for instructions from the buffer may be provided in any suitable and desired manner. For example, a particular type of instruction may be associated with a particular, preferably selected, preferably predefined, eviction priority indication (Priority), such that the eviction priority indication for a given instruction may be (and is) derived implicitly from the type of instruction in question (from its nature).

[0091] However, in a particularly preferred embodiment, an eviction priority indication is associated with an instruction (having an eviction priority indication) by explicitly indicating the eviction priority indication for the instruction. Thus, in a preferred embodiment, an instruction is associated with an eviction priority indication by providing an explicit and specific eviction priority indication for the instruction in question. This then allows, for example, the eviction priority to be set based on the instructions that will consume the result produced by the instruction in question (rather than based on the type of instruction that is producing an output data value).

[0092] In a preferred such embodiment, the indication is provided as part of (as part of) the encoding for the instruction, for example, and preferably, as a (defined) field in the encoding for the instruction, and preferably has a specific (preferably selected, preferably predefined) position in the instruction encoding.

[0093] In addition to the indication indicating the priority for evicting output data values ​​for the instruction from the buffer, the instruction may additionally include any suitable and desired information, such as fields.

[0094] In a preferred embodiment, the instruction (and each instruction) includes, in addition to an indication of eviction priority, one or more, and preferably all, of the following: an opcode indicating the operation to be performed in response to the instruction (the operation to be performed when the instruction is executed); an indication of the input data values ​​(operands) for the instruction (preferably in the form of indications of registers from which the input data values ​​(operands) are to be read); and an indication of where output data values ​​to be generated when the instruction is executed should be stored (again, preferably in the form of the identity of the registers to which the output data values ​​should be stored (written)).

[0095] The instructions may also include (encode) other information to control the execution of the instructions, for example for controlling the execution of the instructions according to the instruction set architecture of the data processor or data processing system in question.

[0096] Of course, other configurations would be possible.

[0097] The indication representing the priority for evicting output data values ​​for an instruction may take any suitable and desired form.

[0098] In a preferred embodiment, the eviction priority indication indicates the relative priority of eviction from the buffer. For example, a one-bit indication (flag) can be used to indicate one of two relative priority levels of eviction from the buffer (a higher eviction priority and a lower eviction priority), and a two-bit indication can be used to indicate any of four eviction priority levels (and so on). In a preferred embodiment, the eviction priority indication can indicate any of two eviction priority levels, or one of four relative eviction priority levels.

[0099] Eviction priority indications that indicate more than just different relative eviction priority levels may also be provided. For example, if desired, eviction priority indications that provide other forms of information that can be used to determine the priority of evicting data values ​​from the buffer may also or instead be used.

[0100] For example, the eviction priority indication may be in the form of (or include) an indication of how far in the future execution of the program the output data value will be used (e.g., based on the number of instructions before the data value is used) (and in a preferred embodiment, does so). The eviction priority indication may also or instead indicate whether the output data value will be needed (used) external to the execution unit executing the program, such as by another part of the data processor, e.g., an execution unit. This may also, or in addition to, provide as part of the eviction priority indication an indication of the relative eviction priority level of the instruction.

[0101] The eviction priority set (indicated) for an instruction may be selected and set based on any suitable and desired conditions and criteria.

[0102] In a preferred embodiment, the eviction priority of an instruction (output data value) is based on one or more, preferably multiple, and preferably all of the following: whether the output data value will be used as an input data value for another instruction in the program being executed (and in this case, preferably how far in the future the output data value will be used as an input data value for another instruction (preferably in terms of the number of instructions), and / or how many other instructions in the program being executed the output data value will be used as an input data value); whether the output data value will only be used (consumed) by the program being executed (of which the instruction is a part); whether the output data value will be needed for the execution of another, different program; whether the output data value of the instruction will only be used (consumed) by the execution unit that is executing the instruction to generate the output data value; whether the output data value for the instruction will be needed external to the execution unit that is executing the instruction, for example, for use by another execution unit or other processing unit (processing) of a data processor, or otherwise needs to be output from the execution unit, for example, to a memory.

[0103] In a preferred embodiment, in the case where the output data value will not (will not only) be consumed locally by the execution of the program in question (and / or by the execution unit in question), the instruction is associated with an indication that the output data value that will be generated when executing the instruction is evicted from the buffer with higher priority, as this should have the effect that the output data value will be written back to storage (register file) in priority, which must happen anyway, in order to make it available to other units of the data processor that will need it, etc.

[0104] Therefore, in a preferred embodiment, in cases where the output data value generated when executing the instruction will be needed when another program is executed and / or another execution unit needs the output data value, and / or in cases where the output data value needs to be output from the data processor in any case, the instruction is associated with an indication that it is a higher priority to evict the output data value from the buffer, because in this case it is likely that the output data value will have to be written back to storage (register file) at some point in order to make it available to other execution units or processors of the data processor, or to provide output to the data processor.

[0105] Correspondingly, any output data values ​​that will be required externally of the execution unit executing the instruction (e.g. which are to be passed to other parts / units of the data processor and / or written out to the (main) memory of or for the data processor (of the entire data processing system of which the data processor is a part)) are again preferably indicated as having a higher priority for eviction from the buffer, since these data values ​​must at some point be written back to storage (register file) and then to, for example, main memory etc.

[0106] Correspondingly, output data values ​​that will only be used (consumed) by the program being executed and / or used (consumed) within the execution unit that is executing instructions (program) are preferably marked as having a lower priority for eviction from the buffer, because in this case the output value can remain in the buffer and can be used from the buffer without having to be written back to the storage section (register file) at all.

[0107] Similarly, instructions whose output data values ​​will be used by other instructions in the program in question (and preferably, other instructions in the program in question that are relatively close in execution order to the instruction that generated the data value) are preferably marked as having a lower priority for eviction from the buffer because, in this case, an attempt is also made to retain these output data values ​​in the buffer so that the output data values ​​can be used from the buffer by subsequent instructions in the program without ever needing to be written back to storage.

[0108] This will help reduce the number of potential reads and writes to storage (register files) that may be required when executing the program in question.

[0109] In a preferred embodiment, a directive is set to a low (lower) eviction priority unless it is identified as being suitable for being set to a higher eviction priority, eg, the "default" setting is a low eviction priority.

[0110] Of course, other configurations and standards would be possible.

[0111] The selection and setting of the indication representing the eviction priority of instructions in a program to be executed by the data processor may be performed in any suitable and desired manner and by any suitable and desired element or component of the data processing system of which the data processor is a part.

[0112] In a particularly preferred embodiment, a compiler (compilation process) for a program being executed is operable and configured to select and set eviction priority indications for instructions in the program. In this regard, the applicant has recognized that the compiler of the program being executed will be able to determine information about how output data values ​​generated by instructions in the program are used and should know how to use the output data values, and that the compiler can therefore, for example and preferably based on one or more or all of the criteria discussed above, evaluate the use of the output data values ​​of the instructions in the program and then set eviction priority indications for the instructions in the compiled program that are provided to the data processor for execution accordingly.

[0113] Therefore, in a preferred embodiment, the processing circuitry operative to associate eviction priority indications with instructions in a program to be executed comprises a compiler (compiler circuitry) operative to (and configured to) compile the program for execution by the data processor (by an execution unit of the data processor).

[0114] Thus, in a preferred embodiment, a program (source code), for example, provided by an application on a host processor requiring data processing, is analyzed (for example and preferably by a compiler) to evaluate the use of output data values ​​generated by instructions in the program, and based on the analysis, an eviction priority indication is set for the output data values ​​of the instructions. This analysis and setting of the eviction priority indication is preferably based on and in accordance with any one or more or all of the conditions and criteria discussed above.

[0115] For example, a compiler may use any suitable and desired techniques and processes to select and set eviction priority indications for instructions in a program to be executed for operation in accordance with the present invention.

[0116] Thus, for example, a compiler may look at the dependencies of instructions in a program, the results that instructions will generate, and the inputs (operands) that instructions will use, etc., to select and set eviction priority indications for instructions operating in accordance with the present invention.

[0117] For example, the compiler is then preferably operatively operable and configured to, for example and preferably as part of encoding the instructions, associate the selected indications with instructions in or together with a compiled program that is provided to an execution unit of a data processor for execution.

[0118] Therefore, in a preferred embodiment, a compiler for a data processor:

[0119] For a program comprising a set of instructions to be executed by an execution unit of a data processor:

[0120] determining, for at least one instruction in a program to be executed by an execution unit of a data processor, a priority for evicting from a buffer output data values ​​to be generated when the instruction is executed; and

[0121] At least one instruction of a program to be executed by an execution unit of a data processor is associated with an indication representing a determined priority for evicting from a buffer an output data value to be generated upon execution of the instruction.

[0122] In embodiments, the compiler may also reorder instructions in a program, for example, to increase the likelihood that an output data value from an instruction will be available for use from a buffer before it is evicted from the buffer.

[0123] For example, the compiler may be run on a host processor of a data processing system. The data processor on which the program is to be executed may be another processor associated with the host processor (such as a graphics processor), so that the compiler and the compiled program are run on separate processors of the overall data processing system. However, other configurations are possible, such as the compiler running on the same processor as the compiled program, or the compiler running on a (completely) separate processor, such as the program being precompiled on a separate system and distributed in compiled form.

[0124] The invention also extends to the operation of a compiler in the manner of the invention.

[0125] Therefore, according to another aspect of the present invention, there is provided a method of compiling a program to generate instructions for a data processor, in which an execution thread executes the program instructions to perform a data processing operation, the data processor comprising:

[0126] an execution unit, which, when in operation, can execute instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and

[0127] a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread;

[0128] The data processor further comprises:

[0129] a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and

[0130] a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion;

[0131] The method comprises the following steps:

[0132] For a program comprising a set of instructions to be executed by the execution unit of the data processor:

[0133] determining, for at least one instruction in the program to be executed by the execution unit of the data processor, a priority for evicting from the buffer an output data value to be generated when executing the instruction; and

[0134] The at least one instruction in the program to be executed by the execution unit of the data processor is associated with an indication representing a determined priority for evicting from the buffer the output data value to be generated upon execution of the instruction.

[0135] According to another aspect of the present invention, a compiler is provided, comprising: a method for compiling a program to generate instructions for a data processor, wherein an execution thread can execute the program instructions to perform a data processing operation, the data processor comprising:

[0136] an execution unit, which, when in operation, can execute instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and

[0137] a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread;

[0138] The data processor further comprises:

[0139] a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and

[0140] a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion;

[0141] The compiler includes processing circuitry configured to:

[0142] For a program comprising a set of instructions to be executed by the execution unit of the data processor:

[0143] determining, for at least one instruction in the program to be executed by the execution unit of the data processor, a priority for evicting from the buffer an output data value to be generated when executing the instruction; and

[0144] The at least one instruction in the program to be executed by the execution unit of the data processor is associated with an indication representing a determined priority for evicting from the buffer the output data value to be generated upon execution of the instruction.

[0145] As will be understood by those skilled in the art, such embodiments of the invention can, and in the embodiments do, include any one or more or all of the features of the invention described herein, as appropriate.

[0146] When the instructions in the program have been properly associated with an indication of the priority for evicting data values ​​from the buffer, the program can be provided to the data processor (provided to the execution unit of the data processor) for execution. The data processor will then execute the program, including executing the instructions in the program.

[0147] The provision of the program to the data processor and its execution by the data processor (by one or more execution units of the data processor) may be done in any suitable and desired way, for example and preferably in accordance with the normal operation of the data processor and data processing system in question.

[0148] Thus, the execution unit will, for example, and preferably, execute the instructions in the program in sequence, including reading input (operand) data values ​​from the buffer and performing processing operations using those input data values, and then writing output data values ​​generated by executing the instructions to the buffer.

[0149] According to the present invention, when the execution of an instruction causes a data value to be written to a buffer, an eviction priority indication for that data value is also written to a corresponding entry in the buffer storing that data value (to be associated with the output data value in the buffer). Again, this can be done in any suitable and desired manner, for example, in accordance with the normal operation of the data processor in question to update the buffer with output data values ​​when executing instructions of a program.

[0150] The priority eviction indication for the data value that is written to the corresponding entry in the buffer storing the data value may be the eviction priority indication associated with the instruction (and in a preferred embodiment this is the case), or may be an eviction priority indication derived from (but e.g. not identical to) the eviction priority indication associated with the instruction itself.

[0151] Subject to operation in accordance with the invention when data values ​​(entries) are selected for eviction from the buffer, the operation of the buffer, in terms of loading data values ​​from storage (register file) for use by the execution units and returning output data values ​​from the execution units to storage (register file) via the buffer, may be performed in any suitable and desired manner, and for example and preferably in accordance with the existing operation and protocol of the data processor in question.

[0152] Thus, for example, input data values ​​to be used by an execution unit will be loaded from storage (e.g., a register file) into a buffer as appropriate, for example and preferably according to an existing data fetch operation of a data processor, and where these data values ​​are present in the buffer, the execution unit will then perform an appropriate processing operation using those data values. Correspondingly, output data values ​​generated by the execution unit will be written to the buffer and then, if necessary, written back from the buffer to storage (register file) (but in accordance with the operation for selecting data values ​​to be evicted from the buffer in accordance with the present invention).

[0153] In this operation, when the program is executed, when there is space in the buffer for new data values ​​(there are free (available) data value entries), any new input data values ​​or output data values ​​to be written to the buffer can be written directly to the appropriate free (available) entries in the buffer.

[0154] However, there will be situations where there are no free entries in the buffer for a new data value (whether an input data value to be used by an instruction or an output data value generated by an instruction), and in such situations it will be necessary to evict an existing data value (entry) from the buffer to make room for the new data value to be written to the buffer. According to the present invention, when a data value (entry) is to be evicted from a buffer (e.g., to provide room in the buffer for a new data value), the buffer controller selects a data value (entry) in the buffer using, at least in part, any stored indication of a priority for eviction from the buffer associated with a data value (entry) stored in the buffer.

[0155] The eviction process may, and in a preferred embodiment does, include first writing the data value being evicted to storage (register file) (and then marking the entry in the buffer for the evicted data value as free (available for use)). Preferably, this is done at least for some (preferably specific, preferably selected) data value evictions, for example and preferably when it is known that the data value will be needed in the future and / or by another unit of the data processor, etc.

[0156] In a preferred embodiment, the eviction process may include, at least for some (preferably specific, preferably selected) data values, directly marking an existing data value entry as free (available for use) without writing any data value stored in the data entry back to the storage (register file). This may be appropriate, for example, when a data value has been used from a buffer and is no longer needed, such that there is no need to actually write the data value to the storage for future use, and / or when it is known that the data value in the buffer is identical to a copy of the value already stored in the storage (register file).

[0157] Evicting a data value from a buffer preferably involves actually evicting the entry in the buffer storing the data value. Thus, the eviction process will include making the buffer entry storing the data value available for use (marking it as free). Thus, where appropriate, the data value in the buffer entry will be written back to storage (register file), and the buffer entry will then be marked as available for use (free).

[0158] In a particularly preferred embodiment, the buffer controller is configured to, when there is an idle (spare) write cycle from the buffer to storage, at least in part use the eviction priority indication associated with the entries in the buffer to determine whether any entry in the buffer should be written to storage during the (spare) write cycle. This is preferably in addition to the operations of selecting and evicting data entries when space is required in the buffer for new data entries. This will then, in effect, allow the buffer controller to use the spare buffer to storage write cycle to prematurely drain appropriate data entries from the buffer so that entries in the buffer can be used for the new data before it arrives.

[0159] Therefore, in a preferred embodiment, the buffer controller, when operative, performs and is configured to perform:

[0160] determining whether a write operation from the buffer to the storage portion is available in a current cycle and not already required by a buffer-to-storage portion write operation; and if it is determined that a write operation from the buffer to the storage portion is available and not already required by a buffer-to-storage portion write operation:

[0161] selecting data values ​​(entries) to be written from the buffer to the storage using available write operations using, at least in part, any eviction priority indications associated with the data values ​​in the buffer; and

[0162] The selected data value (entry) is written from the buffer to storage using an available write operation.

[0163] The eviction priority indication associated with and stored for the data value (entry) in the buffer may be used (eg, by the buffer controller) in any appropriate and desired manner when selecting a data value (entry) to evict from the buffer.

[0164] In a preferred embodiment, the buffer controller uses the eviction priority indication to identify the data value (entry) in the buffer with the indicated highest eviction priority (of the data values ​​(entries) in the buffer), and then selects one of the data entries with the indicated highest eviction priority for eviction. In the event that there are multiple data values ​​(entries) in the buffer that all have the same indicated highest eviction priority (of the data values ​​(entries) in the buffer), then the buffer controller should, and preferably does, select one of those multiple data values ​​(entries) for eviction. This selection can be based on any suitable and desired criteria, such as directly selecting the first data value (entry) in the buffer with the indicated highest eviction priority level for eviction, or preferably using a more complex eviction selection scheme to select from multiple data values ​​(entries) that all have the same indicated (highest) eviction priority level, such as and preferably using a least recently used (LRU) eviction policy to select which of the multiple data values ​​(entries) that all have the indicated highest eviction priority level to evict from the buffer.

[0165] Thus, for example, where individual data values ​​(entries) in a buffer can have one of two levels of eviction priority (a higher priority level and a lower priority level), the buffer controller will identify any data values ​​(entries) in the buffer that are indicated as having a higher level of eviction priority and then select one of those data values ​​(entries) to evict from the buffer, preferably using a least recently used protocol.

[0166] Correspondingly, for example, where individual data values ​​(entries) in the buffer can have one of four eviction level priorities, the buffer controller will identify the data values ​​(entries) in the buffer having the indicated highest one of the four eviction priority levels (so the highest level if there are any entries with the highest priority level, else the second highest priority level if there are no entries with the highest priority level but there are entries with the second highest level (and so on)), and then preferably select one of those data values ​​(entries) to evict from the buffer using a least recently used protocol.

[0167] Where the eviction priority indication indicates more than just the relative level of eviction priority of data values ​​(entries) in the buffer, then the buffer controller may use this information in any suitable and desired manner. For example, where the eviction priority indication indicates how far ahead in instruction execution any reuse of a data value will occur, the buffer controller may, and preferably does, take this information into account when selecting data values ​​(entries) to evict from the buffer. For example, and preferably, the buffer controller may, when operating, prioritize evicting from the buffer data values ​​(entries) that are indicated as being reused farther ahead in the execution of a program relative to other data values ​​(entries) in the buffer.

[0168] It would also be possible for the execution unit itself to include processing logic (hardware (circuitry)) that itself (attempts to) determine whether a data value (entry) in the buffer will be reused during program execution, for example by fetching instructions before execution (pre-fetching in the instruction stream) at runtime, thereby analyzing what input data values ​​(operands) will be used by future instructions in the instruction stream. This information can then be combined, for example, with an eviction priority indication provided with the instruction to, for example, provide for more complex data value (entry) selection and eviction from the buffer.

[0169] Of course, other configurations would be possible.

[0170] These structures are preferably used at least in situations where data values ​​(entries) need to be evicted from the buffer to allow new values ​​(entries) to be stored in the buffer. As discussed above, these structures can also be used in situations where available spare write cycles are used to evict buffer entries. Alternatively, in the latter situation, a different eviction selection strategy can be used, for example, using a "spare" buffer-to-storage write cycle to only evict data values ​​(entries) with an indicative highest eviction priority level from the buffer, such that if no data value (entry) indicated as having the indicative highest eviction priority level is present in the buffer, then no data value (entry) is evicted from the buffer in a spare write cycle, even if the spare write cycle is available.

[0171] The present invention also extends to the specific operation of the execution unit, buffer, and buffer controller in accordance with the present invention. Thus, according to another aspect of the present invention, there is provided a method of operating a data processor in which an execution thread can execute program instructions to perform data processing operations, the data processor comprising:

[0172] an execution unit, which, when in operation, can execute instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and

[0173] a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread;

[0174] The data processor further comprises:

[0175] a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and

[0176] a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion;

[0177] The method comprises the following steps:

[0178] The execution unit of the data processor:

[0179] The execution unit writes the following to the buffer when executing the following instruction in the program, the instruction having an associated indication indicating a priority for evicting from the buffer an output data value that will be generated when executing the instruction:

[0180] an output data value generated when executing the instruction, and an indication associated with the instruction indicating the priority for evicting the output data value from the buffer;

[0181] and

[0182] When a data value is to be evicted from the buffer, the buffer controller:

[0183] selecting a data value for eviction from the buffer using, at least in part, any indication of a priority for eviction from the buffer stored with the data value in the buffer;

[0184] and

[0185] The selected data value is evicted from the buffer.

[0186] According to another aspect of the present invention, a data processor is provided, in which an execution thread can execute program instructions to perform data processing operations, the data processor comprising:

[0187] an execution unit, which, when in operation, can execute instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and

[0188] a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread;

[0189] The data processor further comprises:

[0190] a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and

[0191] a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion;

[0192] in:

[0193] The execution unit of the data processor is further configured to, upon executing the following instruction in the program, write the following to the buffer, the execution unit having an associated indication indicating a priority for evicting from the buffer output data values ​​to be generated upon execution of the instruction:

[0194] an output data value generated when the instruction is executed, and an indication associated with the instruction indicating the priority for evicting the output data value from the buffer; and

[0195] The buffer controller is further configured to, when a data value is to be evicted from the buffer:

[0196] selecting a data value for eviction from the buffer using, at least in part, any indication of a priority for eviction from the buffer stored with the data value in the buffer;

[0197] and

[0198] The selected data value is evicted from the buffer.

[0199] As will be appreciated by those skilled in the art, these aspects and embodiments of the present invention can, and preferably do, include any one or more or all of the preferred and optional features of the invention described herein, as appropriate.

[0200] Thus, for example, the buffer controller preferably operates in one or more or all of the manners described above to evict data values ​​from the buffer using an associated priority indication for eviction from the buffer.

[0201] The results generated by executing the program can be used as desired. For example, they can be output, for example, to a memory.

[0202] In all cases, the results can be used by the data processor and the data processing system as the generated output. The output generated by the data processor can be any suitable desired output, for example, in the case of a graphics processor, it can be a rendering output, such as a frame (image) to be displayed, a texture (in render-to-texture) operation, etc.

[0203] In some embodiments, the data processor includes and / or communicates with one or more memories and / or memory devices that store data described herein and / or store software for performing the processes described herein. The data processor may also communicate with a host microprocessor and / or with a display that displays images based on data generated by the data processor.

[0204] In a preferred embodiment, the data processor is part of an overall data processing system that includes one or more memories and / or storage devices and a host processor (and optionally, a display). In a preferred embodiment, the host microprocessor is operable to execute an application that requires data processing by the data processor, wherein the data processor operates in accordance with the present invention when data is to be processed by the application executing on the host processor.

[0205] Of course, other arrangements would be possible.

[0206] The present invention can be used for all forms of output that can be generated using a data processor (and processing pipeline). For example, in the case of graphics processing, the graphics processing pipeline can generate frames for display, output rendered to a texture, etc. Output data values ​​from the processing are exported to an external device (e.g., main memory) for storage and use, such as to a frame buffer for display.

[0207] The invention is applicable to any suitable form or configuration of data processors and data processing systems.

[0208] In a preferred embodiment, the various functions of the present invention are performed on a single data processing platform that generates and outputs data, such as for a display device.

[0209] The invention is applicable to any suitable form or configuration of data processors and data processing systems.In a preferred embodiment, the various functions of the invention are performed on a single data processing platform that generates and outputs data.

[0210] The present invention may be implemented in any suitable system, such as a suitably configured microprocessor-based system. In a preferred embodiment, the present invention is implemented in a computer and / or microprocessor-based system.

[0211] The various functions of the present invention can be performed in any desired and suitable manner. For example, the functions of the present invention can be implemented in hardware or software as needed. Thus, for example, unless otherwise specified, the various functional elements, levels and "means" of the present invention may include suitable one or more processors, one or more controllers, functional units, circuits, circuit systems, processing logic, microprocessor structures, etc. that can perform various functions when working, such as suitable dedicated hardware elements (processing circuits) and / or programmable hardware elements (processing circuits) that can be programmed to operate in a desired manner.

[0212] As will be understood by those skilled in the art, it should also be noted that the various functions of the present invention can be replicated and / or performed in parallel on a given processor. Likewise, if desired, the various processing stages can share processing circuits, etc.

[0213] The data processing systems and processors may additionally include any one or more or all of the conventional functional units that data processing systems and processors include, along with any hardware necessary to perform the specific functions described above.

[0214] Those skilled in the art will also understand that all of the described aspects and embodiments of the present invention can, and preferably do, include any one or more or all of the preferred and optional features described herein, as appropriate.

[0215] The method according to the invention can be implemented at least in part using software (e.g. a computer program). It will therefore be understood that, when viewed from a further aspect, the present invention provides: computer software that is particularly adapted to perform the method described herein when installed on a data processing unit; a computer program element that includes computer software code portions to perform the method described herein when a program element is run on a data processing unit; and a computer program that includes code units that are adapted to perform the method or all the steps of the method described herein when the program is run on a data processing system. The data processor may be a microprocessor system, a programmable FPGA (field programmable gate array) or the like.

[0216] The invention also extends to a computer software carrier comprising such software which, when used to operate a processor, renderer or microprocessor system comprising a data processor, causes the data processor to perform together with the processor, renderer or microprocessor system the steps of the method of the invention. Such a computer software carrier may be a physical storage medium (such as a ROM chip, CD ROM, RAM, flash memory or disk) or may be a signal (such as a wired electrical signal, an optical signal or a wireless signal such as to a satellite).

[0217] It will also be understood that not all steps of the method of the present invention need to be performed by computer software, so in a broader aspect, the present invention provides computer software and such software is installed on a computer software carrier to perform at least one of the steps of the method set out herein.

[0218] Therefore, the present invention may be suitably embodied as a computer program product for use with a computer system. Such an implementation may include a series of computer-readable instructions fixed on a tangible, non-transitory medium (such as a computer-readable medium, for example, a disk, CD ROM, ROM, RAM, flash memory, or hard disk). Such an implementation may also include a series of computer-readable instructions that can be transmitted to a computer system via a modem or other interface device through a tangible medium (including but not limited to optical communication lines or analog communication lines) or invisibly using wireless technology (including but not limited to microwave, infrared, or other transmission technology). The series of computer-readable instructions embodies all or part of the functions previously described herein.

[0219] Those skilled in the art will appreciate that such computer-readable instructions can be written in a variety of programming languages ​​for use with many computer architectures or operating systems. Furthermore, such instructions can be stored using any current or future storage technology (including but not limited to semiconductor, magnetic, or optical), or transmitted using any current or future communication technology (including but not limited to optical, infrared, or microwave). It is contemplated that such a computer program product can be distributed as a removable medium with accompanying printed or electronic documentation (e.g., shrink-wrapped software, pre-loaded with a computer system, such as on a system ROM or fixed disk), or distributed from a server or electronic bulletin board over a network (e.g., the Internet or the World Wide Web). BRIEF DESCRIPTION OF THE DRAWINGS

[0220] Several preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0221] Figure 1 An exemplary computer graphics processing system is shown;

[0222] Figure 2 schematically illustrates a graphics processing pipeline capable of operating in the manner of the present invention;

[0223] Figure 3 A graphics processor is schematically shown;

[0224] Figure 4 An embodiment of an execution unit of a graphics processor is shown;

[0225] Figure 5 shows an embodiment of a buffer used in an embodiment of the present invention;

[0226] Figure 6 shows the instruction encoding used in the embodiment of the present invention;

[0227] Figure 7 Demonstrates shader program compilation;

[0228] Figure 8 An embodiment of shader program compilation is shown; and

[0229] Figure 9 The operation of the execution unit of the graphics processor in the embodiment of the present invention is schematically shown.

[0230] Where appropriate in the drawings, like reference numerals are used for like parts. DETAILED DESCRIPTION

[0231] Several preferred embodiments of the present invention will now be described in the context of a graphics processor that, when operational, can execute graphics shader programs.

[0232] Figure 1 A typical computer graphics processing system is shown.

[0233] An application 2 (e.g., a game) executing on a host processor 1 will request graphics processing operations from an associated graphics processing unit (GPU) (graphics processor) 3, which executes the graphics processing pipeline. To do this, the application will generate API (application programming interface) calls that are interpreted by a driver 4 for the graphics processor 3 running on the host processor 1 to generate appropriate commands to the graphics processor 3 to generate the graphics output requested by the application 2. To facilitate this, a set of "commands" is provided to the graphics processor 3 in response to commands for graphics output (e.g., to generate a frame to be displayed) from an application 2 running on the host system 1.

[0234] Figure 2 The graphics processing pipeline 5 executed by the graphics processor 3 is shown in greater detail.

[0235] Figure 2 The illustrated graphics processing pipeline 5 is a tile-based renderer and will therefore produce tiles of rendered output data arrays (eg output frames to be generated).

[0236] In tile-based rendering, rather than efficiently processing the entire rendered output (e.g., a frame) at once as in immediate mode rendering, the rendered output (e.g., a frame to be displayed) is typically divided into multiple smaller sub-regions called "tiles." The individual tiles (sub-regions) are rendered separately (usually one after the other), and the rendered tiles (sub-regions) are then reassembled to provide the complete rendered output, e.g., a frame for display. In such a setup, the rendered output is typically divided into sub-regions (tiles) of regular size and shape (usually, for example, square or rectangular), but this is not important.

[0237] The render output data array may typically be an output frame intended for display on a display device such as a screen or printer, but may also include, for example, intermediate data intended for use in a later rendering process (also known as "render to texture" output), etc.

[0238] When a computer graphics image is to be displayed, it is typically first defined as a series of primitives (polygons). These primitives are then divided (rasterized) into graphic fragments for subsequent rendering. During normal graphics rendering operations, the renderer will modify (for example) the color (red, green, and blue, RGB) and transparency (alpha, α) data associated with each fragment so that it can be displayed correctly. After the fragments have been fully processed by the renderer, their associated data values ​​are stored in memory, ready for output, such as for display.

[0239] Figure 2 The main elements and pipeline stages of the graphics processing pipeline 5 related to the operation of this embodiment are shown. As will be appreciated by those skilled in the art, there may be other elements in the graphics processing pipeline that are not described in the following. Figure 2 Other elements shown in FIG. It should also be noted that Figure 2 This is illustrative only, and for example the functional units and pipeline stages shown may in practice share a significant amount of hardware circuitry even if they are Figure 2 It will also be appreciated that Figure 2 The various stages, elements, units, etc. of the illustrated graphics processing pipeline may be implemented as desired and will accordingly include, for example, appropriate circuitry and / or processing logic, etc. for performing the necessary operations and functions.

[0240] like Figure 2 As shown, the graphics processing pipeline 5 includes multiple stages, including a vertex shader 20, a shell shader 21, a tessellator 22, a domain shader 23, a geometry shader 24, a rasterization stage 25, an early Z (depth) and stencil test stage 26, a renderer in the form of a fragment shading stage 27, a late Z (depth) and stencil test stage 28, a blending stage 29, a tile buffer 30, and a downsampling and write-out (multi-sample resolution) stage 31.

[0241] Vertex shader 20 takes input data values ​​associated with a vertex, among other things, defined for the output to be generated, and processes these data values ​​to generate a corresponding set of “vertex shaded” output data values ​​for use by subsequent stages of the graphics processing pipeline 5. For example, vertex shading modifies the input data to account for lighting effects in the image to be rendered.

[0242] The shell shader 21 operates on a set of tile control points and generates additional data called tile constants, the tessellation stage 22 subdivides the geometry to create a high-order representation of the shell, the domain shader 23 operates on the vertices output by the tessellation stage (similar to the vertex shader), and the geometry shader 24 processes entire primitives, such as triangles, points, or lines. Together with the vertex shader 20, these stages effectively perform all necessary fragment front-end operations, such as transformation and lighting operations, and primitive setup to set up primitives to be rendered in response to commands and vertex data provided to the graphics processing pipeline 5.

[0243] The rasterizer stage 25 of the graphics processing pipeline 5 operates to rasterize primitives that make up the rendered output (e.g., an image to be displayed) into individual graphics fragments for processing. To do this, the rasterizer 25 receives graphics primitives for rendering, rasterizes the primitives into sampling points, and generates graphics fragments with appropriate locations (indicating suitable sampling locations) for rendering the primitives.

[0244] The fragments generated by the rasterizer are then sent to the rest of the pipeline for processing.

[0245] The early Z / stencil stage 26 performs a Z (depth) test on the fragments received from the rasterizer 25 to see if any fragments can be discarded (culled) at this stage. To do this, it compares the depth value of the fragments issued from the rasterizer 25 (associated with the fragment) with the depth values ​​of already rendered fragments (these depth values ​​are stored in the depth (Z) buffer 30 that is part of the tile buffer) to determine whether the new fragment will be occluded by the already rendered fragments. At the same time, an early stencil test is performed.

[0246] Fragments that pass the fragment early Z and stencil test stage 26 are then sent to the fragment shading stage 27. The fragment shading stage 27 performs appropriate fragment processing operations on the fragments that pass the early Z and stencil test to process the fragments to generate appropriate rendered fragment data.

[0247] The fragment processing may include any suitable and desired fragment shading processing, such as executing a fragment shader program on the fragment, applying textures to the fragment, applying fog or other operations to the fragment, etc., to generate appropriate fragment data. In the present embodiment, the fragment shading stage 27 is in the form of a shader pipeline (programmable fragment shader).

[0248] Then comes the "late" fragment Z and stencil test stage 28, which, among other things, performs an end-of-pipeline depth test on the shaded fragment to determine whether the rendered fragment will actually be seen in the final image. This depth test uses the Z buffer value for the fragment's position in the Z buffer stored in the tile buffer 30 to determine whether the fragment data of the new fragment should replace the fragment data of the rendered fragment by comparing the depth value of the fragment (associated with the fragment) issued from the fragment shading stage 27 with the depth value of the rendered fragment (stored in the depth buffer), as is known in the art. This late fragment depth and stencil test stage 28 also performs any necessary "late" alpha and / or stencil testing on the fragment.

[0249] The fragments that have passed the post fragment test stage 28 are then subjected to any necessary blending operations with the fragments already stored in the tile buffer 30 in the blender 29. Any other necessary remaining operations on the fragments, such as dithering etc. (not shown), are also performed at this stage.

[0250] Finally, the (blended) output fragment data (values) are written to the tile buffer 30, from where they can be output to a frame buffer for display, for example. The depth values ​​of the output fragments are also suitably written to a Z-buffer within the tile buffer 30. The tile buffer stores color and depth buffers, which store appropriate colors, etc. or Z-values, respectively, for each sample point represented by the buffer (essentially, each sample point for the tile being processed). These buffers store arrays of fragment data representing a portion (tile) of the entire rendered output (e.g., an image to be displayed), where each group of sample values ​​in the buffer corresponds to a corresponding pixel of the entire rendered output (e.g., each 2×2 group of sample values ​​can correspond to an output pixel where 4× multisampling is used).

[0251] The tile buffer is provided as part of the RAM located (locally) in the graphics processing pipeline (chip).

[0252] Data from the tile buffer 30 is input to a downsampled (multi-sample resolution) write-out unit 31 and is thereby output (written back) to an external memory output buffer, such as a frame buffer of a display device (not shown). The display device may comprise, for example, a display comprising a pixel array, such as a computer monitor, or a printer.

[0253] The downsampling and write-out unit 31 downsamples the fragment data stored in the tile buffer 30 to an appropriate resolution for the output buffer (device) (i.e., so that a pixel data array corresponding to the pixels of the output device is generated) to generate output values ​​(pixels) for output to the output buffer.

[0254] When a tile of rendered output has been processed and its data exported to main memory (e.g., to a frame buffer in main memory (not shown)) for storage, the next tile is processed, and so on, until enough tiles have been processed to generate the entire rendered output (e.g., a frame (image) to be displayed). The process is then repeated for the next rendered output (e.g., frame), and so on.

[0255] Of course, other arrangements for the graphics processing pipeline 5 are possible.

[0256] The above describes Figure 1 Certain features of the operation of the graphics processing system shown in FIG. Figure 1 Other features of the operation of the graphics processing system are shown.

[0257] from Figure 2As can be seen, the graphics processing pipeline 5 includes a number of programmable processing or "shader" stages, namely a vertex shader 20, a hull shader 21, a domain shader 23, a geometry shader 24, and a fragment shader 27. The programmable shader stages execute respective shader programs, which have one or more input variables and generate a set of output variables, and which are provided by the application.

[0258] To this end, the application 2 provides shader programs implemented using a high-level shader programming language (e.g., GLSL, HLSL, OpenCL, etc.). A shader language compiler then converts these shader programs into binary code for the target graphics processing pipeline 5. This may include creating one or more intermediate representations of the program within the compiler.

[0259] The compiler 6 may, for example, be executed on a host processor 1 of a data processing system including a graphics processor 3. The compiler 6 may, for example, be part of a driver 4, where special API calls are present to cause the compiler to run. Thus, execution of the compiler may be part of the preparation of draw calls performed by the driver in response to API calls generated by an application.

[0260] However, other configurations would be possible, such as the compiler running on the same processor as the compiled code, or the compiler running on a separate processor, such as the program being precompiled on a separate system and distributed in compiled form.

[0261] Figure 2 The operating levels of the graphics processor 3 are schematically shown.

[0262] Figure 3 The functional units of the graphics processor 3 are shown, which are used to perform (and thus act as) Figure 2 Various processing operations and stages are shown in the graphics processing pipeline 5. Other functional units may be present in the graphics processor 3.

[0263] like Figure 3 As shown, the graphics processor 3 includes a rasterizer 40, a thread spawner 41, a programmable execution unit 42, a variation interpolator 43, a texture mapper 44, a blender 45 and storage in the form of a set of registers 46 in communication with a memory 47 of the data processing system.

[0264] Thread spawner 41 , in operation, may spawn execution threads for execution by programmable execution unit 42 , for example, for fragments received by thread spawner 41 from rasterizer 40 .

[0265] Programmable execution unit 42 executes shader programs when in operation to perform shader operations of the graphics processing pipeline, such as shell shaders, vertex shaders, and fragment shaders. To achieve this, programmable execution unit 42 receives execution threads from thread spawner 41 and executes the associated shader programs for those execution threads. As part of this operation and as Figure 3 As shown, the execution threads will read data from and write data to corresponding registers of the storage section (register file) 46 .

[0266] As part of this process and as Figure 3 As shown, the programmable execution unit 42 is capable of invoking a variation interpolator 43, a texture mapper 44, and a blender 45 to perform specific graphics processing operations. To do this, the programmable execution unit will send appropriate messages to (and receive appropriate responses from) the associated accelerator, for example, in response to specific instructions in the shader program being executed.

[0267] The variation interpolator 43 interpolates across graphics primitives as it operates, and as part of this operation often creates texture coordinates to be used when sampling the graphics texture.

[0268] The texture mapper 44 operates by sampling the graphics texture using texture coordinates (e.g., generated by the variation interpolator 43) and generating filtered texture sampling results therefrom. The filtered texture sampling results can then be returned to the programmable execution unit 42 for use, e.g., in shading the sampled points.

[0269] Blender 45 operates to blend fragment shading results generated, for example, by programmable execution unit 42 with previously generated fragment shader results (such as results already stored in a block buffer and / or frame buffer).

[0270] As discussed above, programmable execution unit 42 executes shader programs to be executed for execution threads received from thread spawner 41 to perform graphics processing operations.

[0271] Figure 4 It shows that the Figure 3 An embodiment of a programmable execution unit 42 of a graphics processor 3 is shown in FIG.

[0272] like Figure 4 As shown, the execution unit 42 includes a mathematical pipeline 50, which includes, in particular, one or more functional units in the form of a mathematical logic unit (ALU) 51, which is operable to perform mathematical operations on input data values ​​in response to instructions requiring mathematical operations in the program being executed by the execution unit 42 to provide appropriate output data values ​​53.

[0273] like Figure 4 As shown, the math pipeline 50 particularly includes an operand buffer 52, which is located between the register file 46 and the math logic unit 51 and can store input data values ​​(operands) from the register file 46 for use by the math logic unit 51 during operation, and can also store the operands of the operands in the register file 46. Figure 4 As shown, the operand buffer 52 is used to store the output data value (result) 53 generated by performing the mathematical operation, and then the output data value can be correspondingly written back from the operand buffer 52 to the register file 46. The register file 46 can have 64 entries, for example, wherein the operand buffer has fewer entries, such as 8 entries.

[0274] To facilitate this operation, the math pipeline 50 also includes an appropriate operand buffer controller (operand management unit) 54, which, when operative, controls the loading of data values ​​into the operand buffers 52 and the writing of data values ​​from the operand buffers 52 back to the register file 46 (the eviction of data values ​​from the operand buffers 52). This operation will be discussed in greater detail below.

[0275] The math pipeline 50 also includes appropriate instruction decoding circuitry 55 and a pipeline control unit 56 which is operative, inter alia, to cause the math logic unit 51 to perform the required mathematical operations in response to instructions in the program being executed.

[0276] like Figure 4 As shown, execution unit 42 also includes a load / store pipeline (unit) 57, which, when operated, can retrieve data values ​​from main memory 47 for loading into register file 46, and also write data values ​​from register file 46 to main memory 47. To facilitate this, load / store unit 57 includes: appropriate operand fetch circuitry 58, which, when operated, can retrieve data values ​​from register file 46 for writing to main memory 47; corresponding result write circuitry 59, which, when operated, can write data values ​​retrieved from main memory 47 into register file 46; and appropriate load / store unit 60 (circuitry), which, when operated, can load data values ​​from main memory 47 and store data values ​​in main memory 47.

[0277] like Figure 4 As shown, the execution unit 42 includes an operand buffer 52 located between the register file 46 and the math logic unit 51 of the math pipeline 50. When in operation, the operand buffer 52 can store input data values ​​used by the math logic unit 51 and output (result) data values ​​53 generated by the math logic unit 51.

[0278] Figure 5 An example configuration of operand buffer 52 , ie, an operand buffer layout, is shown.

[0279] like Figure 5 As shown, operand buffer 52 includes a plurality of entries 70 , each of which may store a corresponding data value 71 for each thread executing a given instruction in lockstep, and is identified by means of a tag 72 that allows identification of the data value stored in the entry.

[0280] Thus, in the present embodiment, each entry 70 in operand buffer 52 stores a data value from (or for) a particular register for each thread in a thread group executing a given instruction in parallel (in lockstep).

[0281] Correspondingly, the tag 72 of the data entry 70 is the register index of the register from which the set of data values ​​in the buffer entry (in the case of input data values) is taken, or in which the set of data values ​​in the buffer entry 70 should be stored (in the case of output data values ​​generated by executing the instruction). Thus, for each thread in the thread group, the buffer entry 70 will store, for that thread, a specific data value from or for the corresponding register for that thread.

[0282] Each buffer entry 70 also has an associated "free" flag 74, which may be set to indicate that the buffer entry is free (available) to store a new data value.

[0283] In accordance with the present invention, in this embodiment, operand buffer 52 also stores an indication of the priority of eviction from the operand buffer in the form of eviction priority flags 73 for each data value entry 70. These eviction priority flags 73 are used by operand management unit (controller) 54 when selecting data values ​​(and entries 70) for eviction from operand buffer 52. This operation will be discussed in more detail below.

[0284] In use of the operand buffer 52, when the math logic unit 51 generates an output data value to be written to the operand buffer 52, the data value is written to an entry 70 in the operand buffer 52 along with an eviction priority indicator associated with the instruction that generated the output data value. Thus, when an output value from the math logic unit 51 is written to the operand buffer 52, the output data value is written to the appropriate data value field in the operand buffer entry 70, and the eviction priority indicator associated with the instruction that generated the output data value is written to the eviction priority flags field 73 of the operand buffer entry 70 in question. If desired, an eviction priority indicator derived from (but different from) the eviction priority indicator associated with the instruction that generated the output data value may also be written to the eviction priority flags field 73 of the operand buffer entry 70 in question.

[0285] To trigger this operation, an instruction in a shader program to be executed by execution unit 42 may have associated with it an operand buffer eviction priority indication. Thus, the instruction encoding includes an eviction priority indication in the form of an eviction priority flag, which may then be used to set a corresponding eviction priority flag 73 in operand buffer 52.

[0286] Figure 6 FIG1 shows the instruction encoding with the eviction priority control flag used in this embodiment for this purpose. Figure 6 As shown, an instruction to be executed by execution unit 42 will include, among other things, an opcode 81, a destination register index 82 indicating where output values ​​generated by the instruction should be written, an appropriate source register index 83 indicating where input data values ​​for the instruction should be read from, and an operand buffer eviction priority indication in the form of an eviction priority flag 84 according to the present invention. Figure 6 As shown, instruction 80 may also include other desired parameters 85, eg, depending on the particular instruction set architecture of the data processor and data processing system in question.

[0287] In the present embodiment, the eviction priority indicator (flag) 84 associated with the instruction comprises a one-bit indicator (flag), which can be used to indicate one of two relative priorities (a higher eviction priority and a lower eviction priority) for eviction from the operand buffer. If desired, other structures may also be used or substituted, such as a two-bit indicator (flag) that can be used to indicate any of four eviction priorities; and / or an eviction priority indicator that provides other forms of information that can be used to determine the priority of eviction from the buffer of data values, such as an indication of how many instructions (if any) will be in program execution before the output of the instruction will be used.

[0288] When the shader program is compiled for execution by the execution unit 42 of the graphics processor 3 , the eviction priority flag 84 is included by the compiler (through the compilation process) in the instructions 80 executed by the execution unit 42 .

[0289] An application 2 requiring graphics processing will provide a shader program implemented in a high-level shader programming language (such as GLSL, HLSL, OpenCL, etc.). A shader language compiler will then convert these shader programs into binary code for the target graphics processing pipeline 3. This may include creating one or more intermediate representations of the program within the compiler. The compiler 6 may, for example, be part of a driver 4, where special API calls are made to enable the compiler to run. Thus, the execution of the compiler may be considered part of the draw call preparation that the driver performs in response to the API calls generated by the application. Of course, other compiler structures are possible.

[0290] Figure 7 This is illustrated and shows an application 2 providing a shader program in a high-level shader programming language to a driver 4 which then compiles the shader program into binary code for a graphics processor.

[0291] Figure 8 The compile process in this embodiment is shown.

[0292] like Figure 8 As shown, the compiler 6 receives a source shader program to be compiled (step 90). The compiler then parses the source shader program (step 91), analyzes and optimizes the shader program (step 92), and generates executable instructions for provision to the graphics processor to execute the shader program (step 93). As part of this process, the compiler evaluates, in particular, the use of output data values ​​generated by the instructions in the shader program, determines the appropriate eviction priority for the output values ​​generated by the instructions, and sets the eviction priority flags of the instructions in the shader program accordingly (step 94).

[0293] In this embodiment, if an output data value to be generated in executing the instruction will be needed externally to the execution unit 42 executing the instruction, e.g., to be passed to other parts / units of the graphics processor and / or written out to (main) memory of or for the graphics processor, the instruction is associated with a higher priority indication that instructs the output data value to be evicted from the operand buffer 52.

[0294] Correspondingly, output data values ​​that are to be used (consumed) only by the program being executed and / or within the execution unit executing the instruction (program) are marked as a lower priority for eviction from the buffer.

[0295] In this embodiment, unless an instruction is identified as being suitable for being set to a higher eviction priority, the instruction is set to a low (lower) eviction priority, ie, the "default" setting is a low eviction priority.

[0296] The compiled shader program instructions are then stored for later execution (for issuance to the graphics processor 3 for execution) (step 95). Figure 9 1 and 2. The execution of instructions in a program by the execution unit 42 in an embodiment of the present invention is shown. The figure specifically illustrates that the operand management unit (buffer controller) 54 uses the eviction priority flag 73 to control and select the eviction of entries in the operand buffer 52.

[0297] like Figure 9 As shown, the instruction decoding circuit 55 first decodes the instruction to be executed (step 101).

[0298] Operand buffer controller 54 will then, in operation, load the appropriate input data values ​​(operands) from registers 46 into operand buffer 52 for use in executing the instruction.

[0299] To achieve this, Figure 9 As shown, for each input operand (argument) of the decoded instruction, the operand buffer controller 54 determines whether there is an entry allocated for storing the input operand in the operand buffer 52 (step 102). If so, the process proceeds to the next input operand (argument) (steps 106 and 107), and so on.

[0300] On the other hand, if there is not yet an entry / exchange for storing the input data value (operand) (argument) in the operand buffer 52, then the operand buffer controller 54 determines whether there is an idle entry / exchange that can store the data value in the operand buffer (step 103). If there is an idle (available) entry / exchange in the operand buffer, then the input data value (argument) is read from register 46 and the input data value is stored in the idle entry / exchange (an idle entry / exchange in a plurality of idle entries) in the operand buffer 52 (step 105). Then, the process proceeds to the next input operand (argument) (steps 106 and 107), and the rest can be deduced by analogy.

[0301] On the other hand, if there is no space (free entry) for the required new data value in operand buffer 52, operand buffer controller 54 must first evict entries from operand buffer 52 to provide a free entry for storing the new data value (step 104). In the meantime, instruction execution is stalled (paused).

[0302] To evict an entry from the operand buffer, operand buffer controller 54 uses, among other things, the eviction priority flags 73 stored for the data entries 70 in operand buffer 52 to select the data entries in operand buffer 52 for eviction.

[0303] In the present embodiment, operand buffer controller 54 uses the eviction priority indication to identify the entry in operand buffer 52 (of the entries in the buffer) having the indicated highest eviction priority, and then selects one of those entries indicated as having the highest eviction priority for eviction, using a least recently used eviction policy to select which of all entries having the indicated highest eviction priority is the data entry to be evicted from the buffer.

[0304] Thus, where individual entries 70 in the operand buffer can have one of two eviction priority levels (a higher priority level and a lower priority level), the operand buffer controller 54 will identify any entries in the buffer that are indicated as having the higher level of eviction priority and then evict one of those entries from the buffer using the least recently used protocol, or, if no entry in the buffer is indicated as having the higher level of eviction priority, select one of the entries with the lower level of eviction priority to evict from the buffer using the least recently used protocol.

[0305] Of course, other configurations would be possible.

[0306] When an operand buffer entry to be evicted is selected, the buffer entry may be evicted. For example, if the data value in the operand buffer entry to be evicted is required in the future, the data value may first be written to register 46. The selected operand buffer entry is then marked as free (available), so that a new data value may be read from register 46 and stored in the newly freed operand buffer entry (step 105).

[0307] Again, the process then proceeds to the next input operand (argument), and so on, until all input operands (arguments) for the instruction (of all threads whose instructions are to be executed in lockstep) are present in the operand buffer 52 (step 107).

[0308] When input data value (operand / independent variable) is loaded into operand buffer in this way, the ejection priority indication (flag) of the operand buffer entries and sub-entries storing input data value is set to the ejection priority of expression minimum indicative level.Therefore, in the present embodiment, each entry and sub-entries 70 in operand buffer can have one of two ejection level priorities (higher priority level and lower priority level), and the ejection priority indication (flag) of the operand buffer entries and sub-entries storing input data value is set to the ejection priority of indication lower level.This helps to guarantee that input data value is retained in operand buffer for use.Having used this input value, so that when no longer needing this input value, then can its (entries and sub-entries) be marked as " idle ", therefore can be used for new data.

[0309] When all input operands (arguments) of the instruction (for all threads to be executed in lockstep) are present in the operand buffer 52 (step 107), the mathematical operation for the instruction can be performed. This is done by the math logic unit 51 of the math pipeline 50 under the control of the pipeline control unit 56.

[0310] To achieve this, Figure 9 As shown, operand buffer controller 54 first determines whether operand buffer 52 has an entry allocated for storing the output data value to be generated by the mathematical operation for the instruction (step 108). If so, processing continues with the mathematical operation of the instruction in steps 111 to 113 (which will be discussed further below).

[0311] On the other hand, if an entry for storing the output data value does not already exist in operand buffer 52, operand buffer controller 54 determines whether there is a free entry in the operand buffer that can store the output data value (step 109). If a free (available) entry exists in the operand buffer, processing continues with the mathematical operation of the instruction in steps 111 to 113 (discussed further below).

[0312] On the other hand, if there is no space (free entry) in operand buffer 52 for the required new output data value, operand buffer controller 54 must first evict entries from operand buffer 52 to provide a free entry for storing the new output data value (step 110). In the meantime, instruction execution is stalled (paused).

[0313] As discussed above, to evict entries from the operand buffer, the operand buffer controller 54 selects data entries in the operand buffer 52 for eviction in the manner discussed above with respect to step 104, particularly using the eviction priority flags 73 stored for the data entries 70 in the operand buffer 52. Thus, the operand buffer controller 54 will identify any entries in the buffer that are indicated as having the highest level of eviction priority and then select one of those entries for eviction from the buffer using the least recently used protocol, or, if no entry in the buffer is indicated as having a higher level of eviction priority, select one of the entries with a lower level of eviction priority for eviction from the buffer using the least recently used protocol.

[0314] When an operand buffer entry is selected for eviction, the buffer entry may be evicted. For example, if the data value in the operand buffer entry to be evicted is required in the future, the data value may first be written to register 46. The selected operand buffer entry is then marked as free (available) so that the new output data value may be stored in the newly freed operand buffer entry.

[0315] When (as soon as) there is an operand buffer entry available for the instruction's output data value, the execution unit performs the instruction's mathematical operation.

[0316] To achieve this, Figure 9 As shown, input data values ​​for the mathematical operation for the instruction are selected from the operand buffer 52 (step 111), then the math logic unit 51 performs the appropriate operation using those input values ​​(step 112), and the result of the mathematical operation is written to the allocated entry in the operand buffer 52 together with the indicated eviction priority flag 84 of the instruction (or the eviction priority indication based on the indicated eviction priority flag 84 of the instruction) (step 113).

[0317] The process can then continue with the next instruction to be executed, and so on.

[0318] Figure 9 Also shown is exemplary and optional background processing, as steps 114 to 116, in which, in any case, a spare "buffer to register file" write cycle can be used to evict operand buffer entries from operand buffer 52 to register 46. This will then help, for example, drain entries from operand buffer 52 when there is an opportunity to do so, thereby increasing the likelihood that there will be free entries in the operand buffer when needed. This can be done as background processing for operand buffer operations triggered by the execution of instructions.

[0319] like Figure 9 As shown, for this background processing, it is first determined whether a write from operand buffer 52 to register 46 is available (ie, not in use) (step 114). If not, no background eviction operation occurs.

[0320] On the other hand, if there is a spare write operation available, the operand buffer controller 54 determines whether any operand buffer entry is marked as the highest eviction priority that can be indicated (step 115). If there is an operand buffer entry marked as the highest eviction priority, the operand buffer controller 54 selects the operand buffer entry (or one of them) marked as the highest eviction priority (e.g., using an LRU policy) and writes the entry back to the register 46 using a spare register write cycle (step 116). The corresponding operand buffer entry is then marked as free (available).

[0321] On the other hand, even if there is a spare write cycle, if no operand buffer entry is marked as the highest eviction priority that can be indicated, then the spare write cycle is not used to evict the operand buffer entry (e.g., Figure 9 shown).

[0322] This therefore allows operand buffer entries that would in any case need to be written back to register file 46 to be evicted as a background process, thereby improving performance and, for example, saving energy.

[0323] As can be seen from the above, at least in preferred embodiments of the present invention, the present invention provides a more efficient mechanism for using a buffer located between a storage unit (such as a register file) and an execution unit (which executes instructions using values ​​from the storage unit (register file) and stores the values ​​in the storage unit (register file). This can improve the overall performance of the data processor and, for example, save energy.

[0324] In at least the preferred embodiment of the invention, this is achieved by associating with the instruction an eviction priority indication which provides a "hint" to the buffer controller to assist it in selecting data values ​​to evict from the buffer.

Claims

1. A method of operating a data processing system, the data processing system comprising: A data processor in which an execution thread executes program instructions to perform data processing operations, the data processor comprising: an execution unit, which, when in operation, is capable of executing instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread; The data processor further comprises: a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion; The method comprises the following steps: For a program comprising a set of instructions to be executed by the execution unit of the data processor: associating at least one instruction of the program to be executed by the execution unit of the data processor with an indication representing a priority for evicting from the buffer an output data value to be generated upon execution of the instruction; The execution unit writes the following to the buffer when executing the following instruction in the program, the instruction having an associated indication indicating a priority for evicting from the buffer an output data value that will be generated when executing the instruction: an output data value generated when executing the instruction, and an indication associated with the instruction indicating the priority for evicting the output data value from the buffer; and When a data value is to be evicted from the buffer, the buffer controller: selecting a data value for eviction from the buffer using, at least in part, any indication of a priority for eviction from the buffer stored with the data value in the buffer; and evict selected data values ​​from the buffer, wherein, for output data values ​​to be used outside the execution unit that is executing the program, an indication indicating a higher eviction priority is set; and An indication indicating a higher eviction priority is set for an instruction when an output data value of the instruction is needed outside the execution unit that is executing the instruction.

2. The method according to claim 1, wherein The indication representing a priority for evicting output data values ​​for an instruction from the buffer is provided as part of the instruction.

3. The method according to claim 1 or 2, wherein: The indication representing a priority for evicting output data values ​​for an instruction also represents a relative priority for eviction from the buffer.

4. The method according to claim 1 or 2, wherein: The indication representing the priority of evicting output data values ​​for the instruction further represents: How many instructions in a future execution of the program will there be before the output data value is used as input to an instruction in the program.

5. The method according to claim 1 or 2, wherein: The eviction priority set for a directive is also based on one or more of the following: whether the output data value is to be used as an input data value for another instruction in the program being executed; and Whether the output data value is to be used only by the program of which the instruction is a part.

6. The method according to claim 1 or 2, wherein: In the event that the output data value to be generated when executing the instruction is not to be consumed locally only by the execution unit executing the instruction, the instruction is associated with an indication representing a higher priority for eviction from the buffer.

7. The method according to claim 1 or 2, wherein: The buffer controller selects a data value in the buffer for eviction using, at least in part, any stored indication of a priority for eviction from the buffer associated with the data value stored in the buffer by: Data values ​​in the buffer having an indicated highest priority for eviction of data values ​​in the buffer are identified, and one of the data values ​​having the indicated highest priority for eviction is selected for eviction.

8. The method according to any one of claims 1 or 2, further comprising the steps of: determining whether a write operation from the buffer to the storage portion is available and not already required by a buffer to storage portion write operation; and In the event that a write operation from the buffer to the storage portion is determined to be available and not yet required by a buffer-to-storage write operation: selecting data values ​​to be written from the buffer to the storage portion using, at least in part, any eviction priority indications associated with data values ​​in the buffer; and The selected data value is written from the buffer to the memory portion using the available write operation.

9. The method according to claim 8, wherein The step of using, at least in part, any eviction priority indications associated with data values ​​in the buffer to select data values ​​to be written from the buffer to the storage portion using available write operations comprises: determining whether any of the data values ​​in the buffer has the highest eviction priority level that can be indicated; and selecting one of the data values ​​having the highest eviction priority level that can be indicated for eviction if at least one data value having the highest eviction priority level that can be indicated exists in the buffer; and In the event that no data value having the highest eviction priority level that can be indicated exists in the buffer, no selection of any data value for eviction using the available write operation occurs.

10. A data processing system, comprising: A data processor in which an execution thread executes program instructions to perform data processing operations, the data processor comprising: an execution unit, which, when in operation, is capable of executing instructions in a program to be executed to perform data processing operations for an execution thread executing the program; and a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread; The data processor further comprises: a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion; The data processing system further includes: processing circuitry, for a program comprising a set of instructions to be executed by said execution unit of said data processor, said processing circuitry being capable, when operating: At least one instruction of the program to be executed by the execution unit of the data processor is associated with an indication representing a priority for evicting from the buffer an output data value to be generated upon execution of the instruction; wherein: The execution unit of the data processor is further configured to write the following content to the buffer when executing the following instruction in the program, wherein the instruction has a value indicating that The buffer evicts an associated indication of the priority of the output data values ​​that will be generated when executing the instruction: an output data value generated when the instruction is executed, and an indication associated with the instruction indicating the priority for evicting the output data value from the buffer; and The buffer controller is further configured to, when a data value is to be evicted from the buffer: selecting a data value for eviction from the buffer using, at least in part, any indication of a priority for eviction from the buffer stored with the data value in the buffer; and evict selected data values ​​from the buffer, wherein, for output data values ​​to be used outside the execution unit that is executing the program, an indication indicating a higher eviction priority is set; and An indication indicating a higher eviction priority is set for an instruction when an output data value of the instruction is needed outside the execution unit that is executing the instruction.

11. The system according to claim 10, wherein: The indication representing a priority for evicting output data values ​​for an instruction from the buffer is provided as part of the instruction.

12. The system according to claim 10 or 11, wherein: The indication representing a priority for evicting output data values ​​for an instruction also represents a relative priority for eviction from the buffer.

13. The system according to claim 10 or 11, wherein: The indication representing the priority of evicting output data values ​​for the instruction further represents: How many instructions in a future execution of the program will there be before the output data value is used as input to an instruction in the program.

14. The system according to claim 10 or 11, wherein: The eviction priority set for a directive is based on one or more of the following: whether the output data value is to be used as an input data value for another instruction in the program being executed; and Whether the output data value is to be used only by the program of which the instruction is a part.

15. The system according to claim 10 or 11, wherein: In the event that the output data value to be generated when executing the instruction is not to be consumed locally only by the execution unit executing the instruction, the instruction is associated with an indication representing a higher priority for eviction from the buffer.

16. The system according to claim 10 or 11, wherein: The buffer controller selects a data value in the buffer for eviction using, at least in part, any stored indication of a priority for eviction from the buffer associated with the data value stored in the buffer by: Data values ​​in the buffer having an indicated highest priority for eviction of data values ​​in the buffer are identified, and one of the data values ​​having the indicated highest priority for eviction is selected for eviction.

17. The system according to any one of claims 10 or 11, wherein: The buffer controller is configured to: determining whether a write operation from the buffer to the storage portion is available and not already required by a buffer to storage portion write operation; and In the event that a write operation from the buffer to the storage portion is determined to be available and not yet required by a buffer-to-storage write operation: selecting data values ​​to be written from the buffer to the storage portion using, at least in part, any eviction priority indications associated with data values ​​in the buffer; and The selected data value is written from the buffer to the memory portion using the available write operation.

18. The system according to claim 17, wherein: The buffer controller is configured to select data values ​​to be written from the buffer to the storage portion using, at least in part, any eviction priority indications associated with data values ​​in the buffer by: determining whether any of the data values ​​in the buffer has the highest eviction priority level that can be indicated; and In the event that at least one data value having the highest eviction priority level that can be indicated exists in the buffer, selecting one of the data values ​​having the highest eviction priority level that can be indicated for eviction; and In the event that no data value having the highest eviction priority level that can be indicated exists in the buffer, no selection of any data value for eviction using the available write operation occurs.

19. A data processor, wherein an execution thread executes program instructions to perform data processing operations, the data processor comprising: an execution unit, which, when in operation, is capable of executing instructions in a program to be executed so as to perform data processing operations for an execution thread executing the program; as well as a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread; The data processor further comprises: a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion; in: The execution unit of the data processor is further configured to write the following content to the buffer when executing the following instruction in the program, wherein the instruction has a value indicating that The buffer evicts an associated indication of the priority of the output data values ​​that will be generated when executing the instruction: an output data value generated when the instruction is executed, and an indication associated with the instruction indicating the priority for evicting the output data value from the buffer; and The buffer controller is further configured to, when a data value is to be evicted from the buffer: selecting a data value for eviction from the buffer using, at least in part, any indication of a priority for eviction from the buffer stored with the data value in the buffer; and evict selected data values ​​from the buffer, wherein, for output data values ​​to be used outside the execution unit that is executing the program, an indication indicating a higher eviction priority is set; and An indication indicating a higher eviction priority is set for an instruction when an output data value of the instruction is needed outside the execution unit that is executing the instruction.

20. A method of compiling a program to generate instructions for a data processor, wherein an execution thread executes the program instructions to perform a data processing operation, the data processor comprising: an execution unit, which, when in operation, is capable of executing instructions in a program to be executed so as to perform data processing operations for an execution thread executing the program; as well as a storage unit, the storage unit being capable of storing data values ​​used by the execution unit when executing instructions to perform data processing operations for an execution thread, and the storage unit being capable of storing output data values ​​generated by the execution unit when performing data processing operations for instructions being executed by the execution thread; The data processor further comprises: a buffer located between the storage section and the execution unit, the buffer being operable to receive data values ​​from the storage section and provide the data values ​​to the execution unit for use in executing instructions, and to receive output data values ​​from the execution unit for writing to the storage section; and a buffer controller configured to select a data value in the buffer to be written to the storage portion and trigger writing of the selected data value from the buffer to the storage portion; The method comprises the following steps: For a program comprising a set of instructions to be executed by the execution unit of the data processor: determining, for at least one instruction in the program to be executed by the execution unit of the data processor, a priority for evicting from the buffer an output data value to be generated when executing the instruction; and the at least one instruction in the program to be executed by the execution unit of the data processor being associated with an indication representing a determined priority for evicting from the buffer the output data value to be generated upon execution of the instruction, wherein, for output data values ​​to be used outside the execution unit that is executing the program, an indication indicating a higher eviction priority is set; and An indication indicating a higher eviction priority is set for an instruction when an output data value of the instruction is needed outside the execution unit that is executing the instruction.

21. A non-transitory computer-readable storage medium storing a computer program which, when executed at a data processing apparatus, causes the data processing apparatus to perform the method according to any one of claims 1 to 9 and 20.

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