Parity generation circuit, memory controller and storage module containing the same

Abstract

The parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity bit for the original data in a first error correction mode with a first error correction capability. The second parity generation part is configured to generate a second parity bit using the first parity bit in a second error correction mode with a second error correction capability.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2019-0129436, filed on October 17, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology relate to memory systems, and more particularly, to parity generation circuits for multiple error correction levels, memory controllers, and memory modules including the parity generation circuits. Background Art

[0004] Generally, the path for transmitting information is called a channel. When information is transmitted using cable communication, the transmission line through which the information is transmitted can be used as a channel. When information is transmitted using wireless communication, the channel can be a space in which electromagnetic waves including information propagate. The process for storing data in a storage medium (e.g., a storage device) and for reading data from the storage medium can be performed through the channel.

[0005] When data is transmitted through a channel, errors may be included in the data. Therefore, people have been committed to developing devices and methods for detecting errors in erroneous data and removing the detected errors to restore the erroneous data to its original data. Error correction code (ECC) encoding operations and ECC decoding operations have been widely used in storage systems including storage media. The ECC encoding operation may correspond to the following process: generating transmission data by adding an error control code (or error correction code) to the original data (i.e., write data) before transmitting the original data to perform a write operation. The ECC decoding operation may correspond to the following process: performing a read operation to read out the data stored in the storage medium, and dividing the read data into the original data and the additional code so as to restore the read data to the original data. Summary of the invention

[0006] According to one embodiment, a parity generation circuit includes a first parity generation section and a second parity generation section. The first parity generation section is configured to generate a first parity bit for original data in a first error correction mode with a first error correction capability. The second parity generation section is configured to generate a second parity bit using the first parity bit in a second error correction mode with a second error correction capability.

[0007] According to another embodiment, a memory controller for controlling a write operation of a memory device includes an error correction code (ECC) encoder, the error correction code (ECC) encoder including a parity generation logic circuit configured to generate a parity bit for original data. The parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity bit in a first error correction mode with a first error correction capability. The second parity generation part is configured to generate a second parity bit using the first parity bit in a second error correction mode with a second error correction capability.

[0008] According to another embodiment, a storage module includes a plurality of storage media and a storage module controller for controlling access to the storage media. The storage module controller includes an error correction code (ECC) encoder having a parity generation logic circuit configured to generate parity bits for original data. The parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity bit in a first error correction mode with a first error correction capability. The second parity generation part is configured to generate a second parity bit using the first parity bit in a second error correction mode with a second error correction capability.

[0009] According to another embodiment, a method for generating parity bits includes: generating a first parity bit of original data in a first error correction mode with a first error correction capability. The method also includes: generating a second parity bit using the first parity bit in a second error correction mode with a second error correction capability.

[0010] According to another embodiment, a method for generating parity check bits includes: calculating a first parity check matrix for original data using a first encoding matrix in a first error correction mode; and outputting the first parity check matrix. The method also includes: calculating a second parity check matrix using the first encoding matrix and a transformation matrix in a second error correction mode. The method further includes: outputting the second parity check matrix in the second error correction mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Certain features of the disclosed technology are illustrated by various embodiments with reference to the included drawings, in which:

[0012] Figure 1 is a block diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0013] Figure 2 Shown included in Figure 1 An example of parity generation logic circuitry in a memory controller of FIG.

[0014] Figure 3 is a flowchart illustrating a method of generating parity bits according to an embodiment of the present disclosure.

[0015] Figure 4 is a block diagram illustrating a memory module including a parity generation logic circuit according to an embodiment of the present disclosure.

[0016] Figure 5 Shown included in Figure 4 An example of parity generation logic circuit in a memory module of FIG. DETAILED DESCRIPTION

[0017] In the description of the following embodiments, it should be understood that the terms "first" and "second" are intended to identify elements, rather than being used to define only the elements themselves or to represent a specific order. In addition, when an element is referred to as being "on", "above", "on", "below" or "below" another element, it is intended to represent a relative positional relationship, and is not intended to limit the following specific situation: the element directly contacts another element, or there is at least one intermediate element between them. Therefore, the terms such as "on ...", "above ...", "above ...", "below ...", "below ..." and "below ..." used in this article are only used to describe the purpose of a specific embodiment, and are not intended to limit the scope of the present disclosure. In addition, when an element is referred to as "connected" or "coupled" to another element, the element can be directly electrically or mechanically connected or coupled to another element, or a connection relationship or a coupling relationship can be formed by replacing another element between them.

[0018] Various embodiments relate to a parity generation circuit for multiple error correction levels, a memory controller, and a memory module including the parity generation circuit, and a method of generating parity bits.

[0019] Figure 1 is a block diagram showing an example of a memory controller 110 according to an embodiment of the present disclosure. Figure 1, the memory controller 110 may include an error correction code (ECC) logic circuit 120. The ECC logic circuit 120 may include an ECC encoder 122 and an ECC decoder 124. When the memory controller 110 operates in a write mode to store data in a memory device (not shown), the ECC encoder 122 may perform an ECC encoding operation. When the memory controller 110 operates in a read mode to read out data stored in the memory device, the ECC decoder 124 may perform an ECC decoding operation. The ECC encoder 122 may include a parity generation logic circuit 200.

[0020] In write mode, the ECC encoder 122 can receive raw data written to the storage device from an external device such as a host. The ECC encoder 122 can output a codeword after generating parity data by adding an error control code (or error correction code) to the raw data. The memory controller 110 can write the codeword output from the ECC encoder 122 to the storage device. The codeword can be configured to include raw data and parity data. The parity generation logic circuit 200 can generate parity data included in the codeword, which is generated by the ECC encoder 122.

[0021] In the read mode, the memory controller 110 may operate so that the read data (i.e., the codeword including the original data and the parity data) output from the memory device is input into the ECC decoder 124. The ECC decoder 124 may perform an ECC decoding operation for the codeword input to the ECC decoder 124. When an error is detected during the ECC decoding operation, the ECC decoder 124 may correct the error of the codeword and output the ECC decoded data. The ECC decoding operation may be performed in the following manner: calculating a syndrome of the codeword, calculating an error location polynomial using the syndrome, finding a solution to the error location polynomial to calculate the error location and error size, and correcting the detected error. The memory controller 110 may transmit the ECC decoded data output from the ECC decoder 124 to an external device (e.g., a host).

[0022] In the present embodiment, the ECC logic circuit 120 may have a variety of error correction capabilities, for example, a first error correction capability and a second error correction capability. In one embodiment, the error correction capabilities may be different according to the algorithm used in the error correction. For example, when a Reed-Solomon (RS) code including a symbol having a plurality of data bits and a plurality of parity bits is used as an error correction code, the error correction capability may be defined as the number of symbols whose errors are correctable. When a Bose-Chaudhuri-Hocquenghem (BCH) code including a binary data bit and a binary parity bit is used as an error correction code, the error correction capability may be defined as the number of bits whose errors are correctable. The first error correction capability may be different from the second error correction capability. The first error correction capability may be greater than the second error correction capability. The first error correction capability may be applied in the first error correction mode, and the second error correction capability may be applied in the second error correction mode. When the probability of error occurrence is relatively high during the write operation and the read operation, the ECC logic circuit 120 may operate in the first error correction mode. In this case, a relatively large number of first parity bits may be generated. In contrast, when the probability of error occurrence during write and read operations is relatively low, the ECC logic circuit 120 may operate in the second error correction mode. In this case, a relatively small number of second parity bits may be generated.

[0023] Figure 2 Shown included in Figure 1 An example of a parity generation logic circuit 200 in the memory controller 110 of FIG. Figure 2 , the parity check generation logic circuit 200 may include a first parity check generation part 210, a second parity check generation part 220 and a selection output part 230. In one embodiment, the selection output part 230 may be implemented using a multiplexer. The first parity check generation part 210 may generate a first parity check matrix PA1 for the original data. Each element in the first parity check matrix PA1 may include a first parity check symbol used in a first error correction mode in which a first error correction capability is applied. The second parity check generation part 220 may generate a second parity check matrix PA2 using the first parity check matrix PA1. Each element in the second parity check matrix PA2 may include a second parity check symbol used in a second error correction mode in which a second error correction capability is applied. Because the second parity check matrix PA2 is generated using the first parity check matrix PA1, the first parity check generation part 210 may operate in the first error correction mode and the second error correction mode. In contrast, the second parity check generation part 220 may operate only in the second error correction mode.

[0024] The following will describe an ECC encoding operation using an RS algorithm using an RS code. When a BCH code is used for the ECC encoding operation, the ECC encoding operation using the BCH code can be performed in the same manner as the ECC encoding operation using the RS algorithm, except that the data is processed in bits rather than symbols. In addition, the following ECC encoding operation will be described in conjunction with the following case, in which the original data includes "NN" data symbols (where "NN" is a natural number), the first parity check matrix PA1 includes "NP1" first parity check symbols (where "NP1" is a natural number), and the second parity check matrix PA2 includes "NP2" second parity check symbols (where "NP2" is a natural number. As shown in reference Figure 1 As described, because the error correction capability in the first error correction mode is greater than the error correction capability in the second error correction mode, the number of first parity symbols "NP1" in the first parity check matrix PA1 can be greater than the number of second parity symbols "NP2" in the second parity check matrix PA2.

[0025] The first parity generating part 210 may be configured to include a first encoding matrix logic circuit 211, a data inverse matrix logic circuit 212, and a first matrix multiplier 213. The first encoding matrix logic circuit 211 may output a first encoding matrix Encoding_Matrix1 calculated by Equation 1 below.

[0026] Encoding_Matrix1=[address(check1)] -1 ×[address(data1)]

[0027] (Equation 1)

[0028] In equation 1, [address(check1)] -1 Represents the inverse matrix of the matrix [address(check1)]. The matrix [address(check1)] ([address(check1)]) can be represented by the following equation 2.

[0029]

[0030] In Equation 2, the matrix [address(check1)] may have "NP1" rows and "NP1" columns. That is, in the first error correction mode, the number of rows and columns of the matrix [address(check1)] may be equal to the number of first parity check symbols "NP1". Each element constituting the matrix [address(check1)] may be multiplied by a parity check symbol to provide a constant used in calculating a syndrome. For example, the element "AP1" located at the intersection of the first row and the first column may be multiplied by a parity check symbol. 0,0 " is multiplied by the first parity symbol to provide a constant used in calculating the first syndrome. Similarly, the element "AP" located at the intersection of the NP1th row and the NP1th column can be NP1-1，NP1-1 ” is multiplied by the NP1th parity symbol to provide a constant used in calculating the NP1th syndrome.

[0031] In Equation 1, the matrix [address(data1)]([address(data1)]) can be expressed by the following Equation 3.

[0032]

[0033] In Equation 3, the matrix [address(data1)] may have "NP1" rows and "NN" columns. That is, the number of rows in the matrix [address(data1)] may be equal to the number of first parity symbols "NP1" in the first error correction mode, and the number of columns in the matrix [address(data1)] may be equal to the number of data symbols "NN" in the first error correction mode. Each element constituting the matrix [address(data1)] may be multiplied by a data symbol to provide a constant used in calculating a syndrome. For example, the element "AD" located at the intersection of the first row and the first column may be multiplied by the data symbol. 0,0 " is multiplied by the first data symbol to provide a constant used in calculating the first syndrome. Similarly, the element "AD" located at the intersection of the NP1th row and the NNth column can be NN-1，NP1-1 ” is multiplied by the NNth data symbol to provide a constant used in calculating the NP1th syndrome.

[0034] The data inverse matrix logic circuit 212 may output a data inverse matrix Data_Inverse_Matrix calculated by the following Equation 4.

[0035]

[0036] In Equation 4, the data inverse matrix Data_Inverse_Matrix may have "NN" rows and one column. The elements D0, D1, D2, ..., D constituting the data inverse matrix Data_Inverse_Matrix NN-2 and D NN-1 "NN" data symbols may be included.

[0037] The first matrix multiplier 213 may perform matrix multiplication of the first encoding matrix Encoding_Matrix1 output from the first encoding matrix logic circuit 211 and the data inverse matrix Data_Inverse_Matrix output from the data inverse matrix logic circuit 212 to generate and output the first parity check matrix PA1. Since the first encoding matrix Encoding_Matrix1 has a matrix form of "NP1×NN" and the data inverse matrix Data_Inverse_Matrix has a matrix form of "NN×1", the first parity check matrix PA1 may have a matrix form of "NP1×1", as shown in the following Equation 5.

[0038]

[0039] In Equation 5, the first parity check matrix PA1 may have "NP1" rows and one column. For certain described embodiments, a matrix having a matrix form of "A×B" means that the matrix has A rows and B columns. The elements P10, P11, P12, ..., P1 constituting the first parity check matrix PA1 are NP1-2 and P1 NP1-1 'NP1' first parity check symbols may be included. That is, the first parity check symbols used in the first error correction mode may respectively have values ​​corresponding to elements located in one column of the first parity check matrix PA1.

[0040] The first parity check matrix PA1 output from the first matrix multiplier 213 may be input to a first input terminal of the selection output part 230 implemented using a multiplexer. In addition, the first parity check matrix PA1 output from the first matrix multiplier 213 may be split into a low-order first parity check matrix PA1_1 and a high-order first parity check matrix PA1_2, and the low-order first parity check matrix PA1_1 and the high-order first parity check matrix PA1_2 may be input to the corresponding matrix adder 223 and the second matrix multiplier 222 included in the second parity check generating part 220. The low-order first parity check matrix PA1_1 may include elements arranged from the first row to the NP2th row among the elements of the first parity check matrix PA1, as shown in the following equation 6.

[0041]

[0042] In addition, the high-order first parity check matrix PA1_2 may include elements arranged from the (NP2+1)th row to the last row among the elements of the first parity check matrix PA1, as shown in the following Equation 7.

[0043]

[0044] The second parity check generating section 220 may be configured to include a transformation matrix logic circuit 221, a second matrix multiplier 222, and a matrix adder 223. The transformation matrix logic circuit 221 may output a transformation matrix Trans_Matrix, which is used to calculate a second parity check matrix PA2 using the first parity check matrix PA1. In the process for generating the transformation matrix Trans_Matrix, the second encoding matrix Encoding_Matrix2 used in the second error correction mode may be represented by the following equation 8.

[0045] Encoding_Matrix2=[address(check2)] -1 ×[address(data2)]

[0046] (Equation 8)

[0047] In Equation 8, [address(check2)] -1 represents the inverse matrix of the matrix [address(check2)]. The matrix [address(check2)] can be represented by the following equation 9.

[0048]

[0049] In Equation 9, the matrix [address(check2)] may have "NP2" rows and "NP2" columns. That is, in the second error correction mode, the number of rows and the number of columns of the matrix [address(check2)] may be equal to the number "NP2" of second parity check symbols. As with the matrix [address(check1)] represented by Equation 2, each element constituting the matrix [address(check2)] may be multiplied by a parity check symbol to provide a constant used in calculating a syndrome. For example, the element "AP" located at the intersection of the first row and the first column may be multiplied by a parity check symbol. 0,0 " is multiplied by the first parity symbol to provide a constant used in calculating the first syndrome. Similarly, the element "AP" located at the intersection of the NP2th row and the NP2th column may be NP2-1，NP2-1" is multiplied by the NP2th parity-check symbol to provide a constant used in calculating the NP2th syndrome.

[0050] In Equation 8, the matrix [address(data2)] can be expressed by the following Equation 10.

[0051]

[0052] In Equation 10, the matrix [address(data2)] may have "NP2" rows and "NN" columns. That is, the number of rows in the matrix [address(data2)] may be equal to the number "NP2" of second parity symbols in the second error correction mode, and the number of columns in the matrix [address(data2)] may be equal to the number "NN" of data symbols in the second error correction mode. As with the matrix [address(data1)] represented by Equation 3, each element constituting the matrix [address(data2)] may be multiplied by a data symbol to provide a constant used in calculating a syndrome. For example, the element "AD" located at the intersection of the first row and the first column may be multiplied by a data symbol. 0,0 " is multiplied by the first data symbol to provide a constant used in calculating the first syndrome. Similarly, the element "AD" located at the intersection of the NP2th row and the NNth column can be multiplied by NN-1，NP2-1 " is multiplied by the NNth data symbol to provide a constant used in calculating the NP2th syndrome.

[0053] Since the matrix [address(check2)] has a matrix form of "NP2×NP2" and the matrix [address(data2)] has a matrix form of "NP2×NN", the second encoding matrix Encoding_Matrix2 may have a matrix form of "NP2×NN". If the matrix [address(data2)] in Equation 8 is represented as "[address(check11)]×[address(check1)] -1 ×[address(data1)]”, then the second encoding matrix Encoding_Matrix2 of Equation 8 can be rewritten as the following Equation 11.

[0054] Encoding_Matrix2=[address(check2)] -1 ×[address(check11)]×[address(check1)] -1 ×[address(data1)]

[0055] (Equation 11)

[0056] In Equation 11, the matrix [address(check2)] -1 Can have the matrix form of "NP2×NP2", matrix [address(check11)] can have the matrix form of "NP2×NP1", matrix [address(check1)] -1 may have a matrix form of "NP1×NP1", and the matrix [address(data1)] may have a matrix form of "NP1×NN". In Equation 11, the matrix [address(check11)] may correspond to a matrix including elements arranged in some rows of the matrix [address(check1)]. This is to adjust the number of rows in the matrix [address(check11)] so that the number of rows in the matrix [address(check11)] is equal to the number of rows in the matrix [address(check2)] -1 Therefore, the matrix [address(check11)] may include elements arranged from the first row to the NP2th row in the matrix [address(check1)] of Equation 2, and may be represented by the following Equation 12.

[0057]

[0058] The matrix [address(check11)] represented by Equation 12 can be rewritten as the following Equation 13.

[0059]

[0060] As shown in Equation 13, the matrix [address(check11)] can be split into a matrix [address(check2)] and a matrix [Xmat], wherein the matrix [address(check2)] includes elements arranged from the first row to the NP2th row in the matrix [address(check11)] and has a matrix form of "NP2×NP2", and the matrix [Xmat] includes elements arranged from the (NP2+1)th row to the last row (i.e., the NP1th row) in the matrix [address(check11)] and has a matrix form of "NP2×(NP1-NP2)". All elements in the matrix [Xmat] can be arbitrary constants.

[0061] Meanwhile, in Equation 11, a matrix [address(check1)] having a matrix form of "NP1×NP1" -1The product with the matrix [address(data1)] having the matrix form of "NP1×NN" may be the same as the first encoding matrix Encoding_Matrix1 represented by Equation 1. Therefore, the second encoding matrix Encoding_Matrix2 of Equation 11 may be rewritten as the following Equation 14.

[0062] Encoding_Matrix2=[address(check2)] -1 ×[address(check11)]×(Encoding_Matrix1)

[0063] (Equation 14)

[0064] If Equation 13 is substituted into Equation 14, the second encoding matrix Encoding_Matrix2 can be expressed by the following Equation 15.

[0065] Encoding_Matrix2=[address(check2)] -1 ×[address(check2)|Xmat]]×(Encoding_Matrix1)

[0066] (Equation 15)

[0067] In Equation 15, since the matrix [address(check2)] having the matrix form of "NP2×NP2" -1 The product of the matrix [address(check2)] having the matrix form of “NP2×NP2” is the same matrix (identical matrix) having the matrix form of “NP2×NP2”, so the second encoding matrix Encoding_Matrix2 can be expressed by the following Equation 16.

[0068] Encoding_Matrix2=[Identical Matrix|Ymat]×(Encoding_Matrix1)

[0069] (Equation 16)

[0070] According to Equation 16, the second encoding matrix Encoding_Matrix2 can be calculated by multiplying the matrix [Identical_Matrix | Ymat] by the first encoding matrix Encoding_Matrix1. This means that the second parity check matrix PA2 including the second parity check symbol used in the second error correction mode can be calculated by multiplying the matrix [Identical_Matrix | Ymat] by the first parity check matrix PA1. Therefore, the second parity check matrix PA2 can be represented by the following Equation 17.

[0071]

[0072] In Equation 17, since the low-order first parity check matrix PA1_1 and the high-order first parity check matrix PA1_2 are obtained from the first parity check matrix PA1 output from the first parity check generating section 210, the calculation of the second parity check matrix PA2 may require only the matrix [Ymat]. That is, the transformation matrix logic circuit 221 of the second parity check generating section 220 may calculate and output the matrix [Ymat] having a matrix form of "NP2×(NP1-NP2)", as shown in Equation 16.

[0073] The second matrix multiplier 222 of the second parity check generating part 220 can perform a multiplication operation of the matrix [Ymat] output from the transformation matrix logic circuit 221 and the high-order first parity check matrix PA1_2, thereby outputting an intermediate matrix (mid-matrix) [MM]. The intermediate matrix [MM] output from the second matrix multiplier 222 can have a matrix form of "NP2×1". The intermediate matrix [MM] output from the second matrix multiplier 222 can be input to the matrix adder 223. The matrix adder 223 can perform an addition operation of the low-order first parity check matrix PA1_1 output from the first parity check generating part 210 and the intermediate matrix [MM] output from the second matrix multiplier 222, and can output the second parity check matrix PA2 as a result of the addition operation. The second parity check matrix PA2 can have a matrix form of "NP2×1". The second parity check matrix PA2 can be input to the second input terminal of the selection output part 230 (i.e., the multiplexer).

[0074] The multiplexer 230 may select and output data input to a first input terminal of the multiplexer 230 or data input to a second input terminal of the multiplexer 230 in response to an error correction mode control signal CS_ECL. The error correction mode control signal CS_ECL may be input to a control signal input terminal of the multiplexer 230. The first input terminal of the multiplexer 230 may receive the first parity check matrix PA1 output from the first parity check generating part 210. The second input terminal of the multiplexer 230 may receive the second parity check matrix PA2 output from the second parity check generating part 220. In one embodiment, in the first error correction mode, the error correction mode control signal CS_ECL having a logic "high (1)" level may be input to the first multiplexer 230. In this case, the multiplexer 230 may output the first parity check matrix PA1 input to the first input terminal of the multiplexer 230. In contrast, in the second error correction mode, the error correction mode control signal CS_ECL having a logic “low (0)” level may be input to the multiplexer 230. In this case, the multiplexer 230 may output the second parity check matrix PA2 input to the second input terminal of the multiplexer 230.

[0075] Figure 3 is a flow chart showing a method for generating parity bits according to an embodiment of the present disclosure. Figure 3 , at step 301, the original data may be input to the memory controller 110. In this case, at step 302, the first parity check matrix PA1 may be calculated using the first encoding matrix Encoding_Matrix1. At step 303, it may be determined whether the error correction mode is the first error correction mode or the second error correction mode. When the error correction mode is determined to be the first error correction mode at step 303, at step 304, the first parity check matrix PA1 calculated at step 302 may be output from the parity generation logic circuit 200. When the error correction mode is determined to be the second error correction mode at step 303, at step 305, the second parity check matrix PA2 may be calculated using the first encoding matrix Encoding_Matrix1 and the transformation matrix Trans_Matrix. The process of step 305 may be the same as that of reference 1. Figure 2 At step 306 , the second parity check matrix PA2 calculated at step 305 may be output from the parity check generation logic circuit 200 .

[0076] Figure 4 is a block diagram showing a storage module 400 according to an embodiment of the present disclosure. Figure 4, the storage module 400 may include a plurality of storage media (e.g., first to twentieth storage media 401-1, ..., and 401-20) and a storage module controller 410. In one embodiment, each of the first to twentieth storage media 401-1, ..., and 401-20 may be a storage chip. Sixteen storage media (e.g., first to sixteenth storage media 401-1, ..., and 401-16) among the first to twentieth storage media 401-1, ..., and 401-20 may be used as data chips in which data is stored. Four storage media (e.g., seventeenth to twentieth storage media 401-17, ..., and 401-20) among the first to twentieth storage media 401-1, ..., and 401-20 may be used as ECC chips that store parity bits generated in a first error correction mode. Two storage media (e.g., the seventeenth storage medium 401-17 and the eighteenth storage medium 401-18 among the seventeenth to twentieth storage media 401-17, ... and 401-20) for storing parity bits generated in the first error correction mode can be used as ECC chips for storing parity bits generated in the second error correction mode. Therefore, the seventeenth storage medium 401-17 and the eighteenth storage medium 401-18 can store parity bits in the first error correction mode and the second error correction mode, while the nineteenth storage medium 401-19 and the twentieth storage medium 401-20 can only store parity bits in the first error correction mode.

[0077] Because the number of ECC chips storing parity bits in the first error correction mode is different from the number of ECC chips storing parity bits in the second error correction mode, the error correction capability in the first error correction mode may also be different from the error correction capability in the second error correction mode. In the following description, it may be assumed that data access to each of the storage media 401-1 and 401-20 is performed in units of 32 bits, metadata data access to the storage media 401-1, ..., and 401-16 storing metadata is performed in units of 8 bits, and each symbol includes 7 bits.

[0078] Because the data access to each storage medium 401-1 and 401-20 is performed in units of 32 bits, five symbols can be generated in each storage medium. Each of the four symbols among the five symbols can include 7 bits of data, and the remaining one symbol among the five symbols can include 4 bits of data and 3 bits of arbitrary data. The 3 bits of arbitrary data are binary data for making the number of bits included in each symbol consistent, and the 3 bits of arbitrary data can include bits with a logic "low (0)" level. The first storage medium to the sixteenth storage medium 401-1, ..., and 401-16 storing data can be coupled to the storage module controller 410 in parallel, so as to receive or output data in units of 82 symbols. These 82 symbols can include 80 data symbols and 2 metadata symbols. Because the metadata includes 8 bits, one of the two metadata symbols can include 1 bit of metadata and 6 bits of arbitrary data.

[0079] In the first error correction mode, parity symbols may be stored in the seventeenth to twentieth storage media 401-17, ..., and 401-20. Each of the seventeenth to twentieth storage media 401-17, ..., and 401-20 may receive or output data in units of 32 bits, and 8 bits of metadata may be stored in the seventeenth to twentieth storage media 401-17, ..., and 401-20. Therefore, in the first error correction mode, 120 bits of parity data (i.e., 17 parity symbols) may be stored in the seventeenth to twentieth storage media 401-17, ..., and 401-20. In the second error correction mode, parity symbols may be stored in two storage media, for example, the seventeenth storage medium 401-17 and the eighteenth storage medium 401-18. Each of the seventeenth storage medium 401-17 and the eighteenth storage medium 401-18 can receive or output data in units of 32 bits, and 8 bits of metadata can be stored in the seventeenth storage medium 401-17 and the eighteenth storage medium 401-18. Therefore, in the second error correction mode, 56 bits of parity data (i.e., 8 parity symbols) can be stored in the seventeenth storage medium 401-17 and the eighteenth storage medium 401-18. In the first error correction mode capable of storing 17 parity symbols, errors of 8 data symbols can be corrected. In contrast, in the second error correction mode capable of storing 8 parity symbols, errors of 4 data symbols can be corrected.

[0080] The storage module controller 410 may communicate with an external device (e.g., a host) to control access to the storage media 401-1, ..., and 401-20. The storage module controller 410 may include an ECC logic circuit 420. The ECC logic circuit 420 may include an ECC encoder 422 and an ECC decoder 424. When the storage module controller 410 operates in a write mode, the ECC encoder 422 may perform an ECC encoding operation. When the storage module controller 410 operates in a read mode, the ECC decoder 424 may perform an ECC decoding operation. The ECC encoder 422 and the ECC decoder 424 may communicate with the reference 401-1, ..., and 401-20, respectively. Figure 1 The described ECC encoder 122 and ECC decoder 124 have the same configuration. Therefore, to avoid duplication of description, the ECC encoder 422 and ECC decoder 424 will not be described in detail below.

[0081] Figure 5 Shown included in Figure 4 The parity generation logic circuit 500 in the ECC encoder 422 is shown in FIG. Figure 5 , the parity check generation logic circuit 500 may include a first parity check generation part 510, a second parity check generation part 520 and a multiplexer 530. The first parity check generation part 510 may generate a first parity check matrix PA1 having a matrix form of "17×1". Each of the 17 elements in the first parity check matrix PA1 may constitute a first parity check symbol used in the first error correction mode. The second parity check generation part 520 may generate a second parity check matrix PA2 having a matrix form of "8×1" using the first parity check matrix PA1 output from the first parity check generation part 510. Each of the 8 elements in the second parity check matrix PA2 may constitute a second parity check symbol used in the second error correction mode. Because the second parity check matrix PA2 is generated using the first parity check matrix PA1, the first parity check generation part 510 may operate regardless of the error correction mode. In contrast, the second parity check generation part 520 may only operate in the second error correction mode.

[0082] The first parity generating part 510 may be configured to include a first encoding matrix logic circuit 511, a data inverse matrix logic circuit 512, and a first matrix multiplier 513. The first encoding matrix logic circuit 511 may output a first encoding matrix Encoding_Matrix1 having a matrix form of "17×82" as described with reference to Equations 1 to 3, and it may be represented by the following Equation 18.

[0083]

[0084] The data inverse matrix logic circuit 512 may output a data inverse matrix Data_Inverse_Matrix having a matrix form of “82×1” as described with reference to Equation 4, and it may be represented by the following Equation 19.

[0085]

[0086] The first matrix multiplier 513 may perform matrix multiplication of the first encoding matrix Encoding_Matrix1 having a matrix form of "17×82" output from the first encoding matrix logic circuit 511 and the data inverse matrix Data_Inverse_Matrix having a matrix form of "82×1" output from the data inverse matrix logic circuit 512, thereby generating and outputting a first parity check matrix PA1 having a matrix form of "17×1". The first parity check matrix PA1 may be represented by the following equation 20.

[0087]

[0088] The first parity check matrix PA1 having a matrix form of "17×1" output from the first matrix multiplier 513 may be input to a first input terminal of the multiplexer 530. In addition, as described with reference to Equation 6 and Equation 7, the first parity check matrix PA1 output from the first matrix multiplier 513 may be split into a low-order first parity check matrix PA1_1 and a high-order first parity check matrix PA1_2, and the low-order first parity check matrix PA1_1 and the high-order first parity check matrix PA1_2 may be input to corresponding matrix adders 523 and second matrix multipliers 522 included in the second parity check generating part 520. The low-order first parity check matrix PA1_1 may have a matrix form of "8×1", and the high-order first parity check matrix PA1_2 may have a matrix form of "9×1". The low-order first parity check matrix PA1_1 and the high-order first parity check matrix PA1_2 may be respectively represented by the following Equations 21 and 7.

[0089] Formula 22 expresses.

[0090]

[0091]

[0092] The second parity check generating part 520 may be configured to include a transformation matrix logic circuit 521, a second matrix multiplier 522, and a matrix adder 523. As described with reference to Equations 8 to 17, the transformation matrix logic circuit 521 may output a transformation matrix Trans_Matrix[Ymat] for calculating the second parity check matrix PA2 using the first parity check matrix PA1. The transformation matrix Trans_Matrix[Ymat] may be represented by the following Equation 23.

[0093]

[0094] The second matrix multiplier 522 of the second parity check generating part 520 can perform a multiplication operation of the transformation matrix [Ymat] output from the transformation matrix logic circuit 521 and the high-order first parity check matrix PA1_2, thereby outputting an intermediate matrix [MM] having a matrix form of "8×1". The calculation process of the intermediate matrix [MM] can be expressed by the following equation 24.

[0095]

[0096] The intermediate matrix [MM] output from the second matrix multiplier 522 may be input to the matrix adder 523. The matrix adder 523 may perform an addition operation of the low-order first parity check matrix PA1_1 output from the first parity check generating section 510 and the intermediate matrix [MM] output from the second matrix multiplier 522, and may output the second parity check matrix PA2 as a result of the addition operation. The process of calculating the second parity check matrix PA2 may be represented by the following equation 25.

[0097]

[0098] The multiplexer 530 may select and output data input to a first input terminal of the multiplexer 530 or data input to a second input terminal of the multiplexer 530 in response to an error correction mode control signal CS_ECL. The first input terminal of the multiplexer 530 may receive the first parity check matrix PA1 output from the first parity check generating section 510. The second input terminal of the multiplexer 530 may receive the second parity check matrix PA2 output from the second parity check generating section 520. In one embodiment, in the first error correction mode, the error correction mode control signal CS_ECL having a logic "high (1)" level may be input to the multiplexer 530. In this case, the multiplexer 530 may output the first parity check matrix PA1 input to the first input terminal of the multiplexer 530. In contrast, in the second error correction mode, the error correction mode control signal CS_ECL having a logic "low (0)" level may be input to the multiplexer 530. In this case, the multiplexer 530 may output the second parity check matrix PA2 input to the second input terminal of the multiplexer 530 .

[0099] According to the above embodiment, the first parity bit used for error correction in the first error correction mode can be used to generate the second parity bit used for error correction in the second error correction mode. Therefore, the layout area of ​​the parity generation logic circuit for multiple error correction levels can be reduced.

[0100] For illustrative purposes, embodiments of the disclosed technology have been disclosed above. It will be appreciated by those skilled in the art that various modifications, additions and substitutions are possible. Although the patent document contains many details, these details should not be interpreted as limitations on the scope of this teaching or the content that can be claimed for protection, but should be interpreted as possible specific feature descriptions for the specific embodiments of this teaching. Certain features described in the context of different embodiments in the patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Moreover, although the features may be described as working in certain combinations and even initially claimed for protection, one or more features in the combination may be removed from the claimed combination in some cases, and the claimed combination may refer to a sub-combination or a variation of a sub-combination.

Claims

1. A parity check generation logic circuit, comprising: a first parity generating section configured to generate a first parity bit for original data in a first error correction mode having a first error correction capability; and a second parity generating section configured to generate a second parity bit using the first parity bit in a second error correction mode having a second error correction capability, Wherein, when the original data consists of "NN" data symbols, the first parity check bit consists of "NP1" first parity check symbols, and the second parity check bit consists of "NP2" second parity check symbols, wherein "NN" is a natural number, "NP1" is a natural number, and "NP2" is a natural number, and the first parity check generating part includes: A first encoding matrix logic circuit configured to output a first encoding matrix having a matrix form of "NP1×NN"; a data inverse matrix logic circuit configured to output a data inverse matrix having a matrix form of "NN×1"; and A first matrix multiplier is configured to perform a multiplication operation of the data inverse matrix and the first encoding matrix to output a first parity check matrix having a matrix form of "NP1×1".

2. The parity generation logic circuit according to claim 1, further comprising: An output selection section is configured to selectively output one of the first parity bit and the second parity bit.

3. The parity generation logic circuit according to claim 2, in, The selection output part includes a multiplexer, and the multiplexer includes a first input terminal, a second input terminal, a control signal input terminal and an output terminal; wherein the first parity bit output from the first parity generating section is input to the first input terminal of the multiplexer; wherein the second parity bit output from the second parity generating section is input to the second input terminal of the multiplexer; and The multiplexer is configured to selectively output one of the first parity bit and the second parity bit through the output terminal of the multiplexer in response to an error correction mode control signal input to the control signal input terminal of the multiplexer.

4. The parity generation logic circuit according to claim 1, in, The first parity check bit includes a plurality of first parity check symbols; wherein the second parity check bit comprises a plurality of second parity check symbols; and The number of the first parity check symbols is greater than the number of the second parity check symbols.

5. The parity generation logic circuit according to claim 1, wherein: The second parity check generating part comprises: a transformation matrix logic circuit configured to output a transformation matrix having a matrix form of "NP2×(NP1-NP2)"; a second matrix multiplier configured to perform a multiplication operation of a low-order first parity check matrix having a matrix form of "(NP1-NP2)×1" obtained from the first parity check matrix and a transformation matrix having a matrix form of "NP2×(NP1-NP2)" to output an intermediate matrix having a matrix form of "NP2×1"; and A matrix adder configured to add a high-order first parity check matrix having a matrix form of "NP2×1" obtained from the first parity check matrix to the intermediate matrix to output a second parity check matrix having a matrix form of "NP2×1".

6. A memory controller for controlling a write operation of a memory device, the memory controller comprising: an error correction code (ECC) encoder including a parity generation logic circuit configured to generate parity bits for the original data, Wherein, the parity check generation logic circuit comprises: A first parity generating section configured to generate a first parity bit in a first error correction mode having a first error correction capability; and a second parity generating section configured to generate a second parity bit using the first parity bit in a second error correction mode having a second error correction capability, Wherein, when the original data consists of "NN" data symbols, the first parity check bit consists of "NP1" first parity check symbols, and the second parity check bit consists of "NP2" second parity check symbols, wherein "NN" is a natural number, "NP1" is a natural number, and "NP2" is a natural number, and the first parity check generating part includes: A first encoding matrix logic circuit configured to output a first encoding matrix having a matrix form of "NP1×NN"; a data inverse matrix logic circuit configured to output a data inverse matrix having a matrix form of "NN×1"; and A first matrix multiplier is configured to perform a multiplication operation of the data inverse matrix and the first encoding matrix to output a first parity check matrix having a matrix form of "NP1×1".

7. The memory controller according to claim 6, wherein: The parity generation logic circuit further includes a selection output portion configured to selectively output one of the first parity bit and the second parity bit.

8. The memory controller according to claim 7, in, The selection output part includes: a multiplexer including a first input terminal, a second input terminal, a control signal input terminal and an output terminal; wherein the first parity bit output from the first parity generating section is input to the first input terminal of the multiplexer; wherein the second parity bit output from the second parity generating section is input to the second input terminal of the multiplexer; and The multiplexer is configured to selectively output one of the first parity bit and the second parity bit through the output terminal of the multiplexer in response to an error correction mode control signal input to the control signal input terminal of the multiplexer.

9. The memory controller according to claim 6, in, The first parity check bit includes a plurality of first parity check symbols; wherein the second parity check bit includes a plurality of second parity check symbols; and The number of the first parity check symbols is greater than the number of the second parity check symbols.

10. The memory controller according to claim 6, wherein: The second parity check generating part comprises: a transformation matrix logic circuit configured to output a transformation matrix having a matrix form of "NP2×(NP1-NP2)"; a second matrix multiplier configured to perform a multiplication operation of a low-order first parity check matrix having a matrix form of "(NP1-NP2)×1" obtained from the first parity check matrix and a transformation matrix having a matrix form of "NP2×(NP1-NP2)" to output an intermediate matrix having a matrix form of "NP2×1"; and A matrix adder configured to add a high-order first parity check matrix having a matrix form of "NP2×1" obtained from the first parity check matrix to the intermediate matrix to output a second parity check matrix having a matrix form of "NP2×1".

11. A storage module comprising a plurality of storage media and a storage module controller for controlling access to the plurality of storage media, the storage module controller comprising: an error correction code (ECC) encoder having a parity generation logic circuit configured to generate parity bits for the original data, Wherein, the parity check generation logic circuit comprises: A first parity generating section configured to generate a first parity bit in a first error correction mode having a first error correction capability; and a second parity generating section configured to generate a second parity bit using the first parity bit in a second error correction mode having a second error correction capability, Wherein, when the original data consists of "NN" data symbols, the first parity check bit consists of "NP1" first parity check symbols, and the second parity check bit consists of "NP2" second parity check symbols, wherein "NN" is a natural number, "NP1" is a natural number, and "NP2" is a natural number, and the first parity check generating part includes: A first encoding matrix logic circuit configured to output a first encoding matrix having a matrix form of "NP1×NN"; a data inverse matrix logic circuit configured to output a data inverse matrix having a matrix form of "NN×1"; and A first matrix multiplier is configured to perform a multiplication operation of the data inverse matrix and the first encoding matrix to output a first parity check matrix having a matrix form of "NP1×1".

12. The storage module according to claim 11, wherein: The plurality of storage media include: a plurality of data chips configured to store data; a plurality of first ECC chips configured to store the first parity bits; and A plurality of second ECC chips are configured to store the first parity bits and the second parity bits.

13. The storage module according to claim 11, wherein: The parity generation logic circuit further includes: a selection output portion configured to selectively output one of the first parity bit and the second parity bit.

14. The storage module according to claim 11, in, The first parity check bit includes a plurality of first parity check symbols; wherein the second parity check bit comprises a plurality of second parity check symbols; and The number of the first parity check symbols is greater than the number of the second parity check symbols.

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