High voltage transistor structure and manufacturing method thereof

Abstract

The present disclosure relates to a high voltage transistor structure and a method for making the same, describing a method for forming (i) an input / output (I / O) fin field effect transistor having a polysilicon gate electrode and a silicon oxide gate dielectric integrated and (ii) a non-input / output field effect transistor having a metal gate electrode and a high dielectric constant gate dielectric. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and depositing a high dielectric constant dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high dielectric constant dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high dielectric constant dielectric layer, wherein the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method also includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

Description

Technical Field

[0001] The present disclosure relates to a transistor structure and a manufacturing method thereof. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices (e.g., metal oxide semiconductor field effect transistors (MOSFETs), including planar metal oxide semiconductor field effect transistors and fin field effect transistors (finFETs)). This size shrinkage increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] According to some embodiments of the present disclosure, a transistor structure includes a first transistor formed on a first region of a semiconductor substrate, wherein the first transistor includes a gate dielectric, a polysilicon gate electrode, and a first spacer structure, the polysilicon gate electrode being disposed on the gate dielectric, wherein the gate dielectric is longer than the polysilicon gate electrode. The first spacer structure abuts the sidewalls of the polysilicon gate electrode, such that the sidewalls of the first spacer structure are aligned with the sidewalls of the gate dielectric. The transistor structure also includes a second transistor formed on a second region of the semiconductor substrate, wherein the second transistor is narrower than the first transistor and includes a high dielectric constant gate dielectric, a metal gate electrode, and a second spacer structure. The metal gate electrode is disposed on and aligned with the high dielectric constant gate dielectric, such that the sidewalls of the metal gate electrode are aligned with the sidewalls of the high dielectric constant gate dielectric. The second spacer structure abuts the sidewalls of the metal gate electrode and the high dielectric constant gate dielectric.

[0004] According to some embodiments of the present disclosure, a method for manufacturing a transistor structure includes depositing a silicon oxide layer on a first region of a semiconductor substrate; depositing a high dielectric constant dielectric layer thinner than the silicon oxide layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide layer and the high dielectric constant dielectric layer; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer, and forming a second polysilicon gate electrode structure on the high dielectric constant dielectric layer, wherein the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method also includes forming a first spacer on the sidewall of the first polysilicon gate electrode structure so that the outer sidewall of the first spacer is aligned with the sidewall of the silicon oxide layer; forming a second spacer on the sidewall of the second polysilicon gate electrode structure and the high dielectric constant dielectric layer; and replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

[0005] According to some embodiments of the present disclosure, a transistor structure includes a first transistor formed on a first region of a semiconductor substrate, wherein the first transistor includes a silicon oxide gate dielectric, a polysilicon gate electrode, and a first spacer structure. The polysilicon gate electrode is disposed on the silicon oxide gate dielectric, and the sidewall edge of the polysilicon gate electrode is not aligned with the sidewall edge of the silicon oxide gate dielectric. The inner sidewall of the first spacer structure is adjacent to the sidewall edge of the polysilicon gate electrode. The transistor structure also includes a second transistor formed on a second region of the semiconductor substrate, wherein the second transistor is narrower than the first transistor and includes a high dielectric constant gate dielectric, a metal gate electrode, and a second spacer structure. The metal gate electrode is disposed on the high dielectric constant gate dielectric so that the sidewall edge of the metal gate electrode is aligned with the sidewall edge of the high dielectric constant gate dielectric. The second spacer structure is adjacent to the sidewall edge of the metal gate electrode and the high dielectric constant gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, the various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, according to the convention in the industry, various features are not drawn to scale. In fact, for the sake of clarity, the size of various features can be arbitrarily increased or reduced.

[0007] Figure 1 is an isometric view of an input / output planar field effect transistor (FET) structure with a polysilicon gate electrode and a silicon oxide gate dielectric according to some embodiments;

[0008] Figure 2 is an isometric view of two input / output fin field effect transistor structures having polysilicon gate electrodes and silicon oxide gate dielectrics according to some embodiments;

[0009] Figure 3 is a flow chart describing a method of forming an input / output field effect transistor structure having a polysilicon gate electrode and a silicon oxide gate dielectric in an input / output region of a substrate and forming a non-input / output field effect transistor structure having a metal gate electrode and a high-k gate dielectric in a non-input / output region of the substrate according to some embodiments;

[0010] Figures 4 to 10 is a cross-sectional view describing a process of manufacturing an input / output field effect transistor structure having a polysilicon gate electrode and a silicon oxide gate dielectric in an input / output region of a substrate and a non-input / output field effect transistor structure having a metal gate electrode and a high-k gate dielectric in a non-input / output region of the substrate according to some embodiments;

[0011] Fig.11 is an isometric view of a polysilicon gate electrode for an input / output field effect transistor structure after a chemical mechanical polishing (CMP) process according to some embodiments.

[0012]

Explanation of symbols

[0013] 100: Input / output field effect transistor structure

[0014] 105:Semiconductor substrate

[0015] 110: substrate isolation area

[0016] 115: Dielectric layer

[0017] 120: Gate dielectric layer

[0018] 125: Gate electrode layer

[0019] 125 L :length

[0020] 125 T :thickness

[0021] 125 W :width

[0022] 130: Spacer structure

[0023] 135: Silicide layer

[0024] 140: Source / drain region

[0025] 145: Silicide layer

[0026] 150: Etching stop layer

[0027] 200: Input / output FinFET structure

[0028] 205:Semiconductor fins

[0029] 260: Spacer structure

[0030] 300: Methods

[0031] 305: Operation

[0032] 310: Operation

[0033] 315: Operation

[0034] 320: Operation

[0035] 325: Operation

[0036] 330: Operation

[0037] 335: Operation

[0038] 400: Input / output substrate area

[0039] 405: Non-input / output substrate area

[0040] 410: high dielectric constant gate dielectric layer

[0041] 500: Input / output field effect transistor gate electrode structure

[0042] 500 H :high

[0043] 500 L :length

[0044] 505: Non-input / output field effect transistor gate electrode structure

[0045] 505 H :high

[0046] 515: Oxide layer

[0047] 520: Nitride layer

[0048] 600: lightly doped area

[0049] 610:Heavily doped area

[0050] 905:Metal gate electrode

[0051] 910: Non-input / output field effect transistor

[0052] 915: Input / output field effect transistor

[0053] AB: cutting line

[0054] C: Center

[0055] E: Edge

[0056] X: Axis

[0057] Y: Axis

[0058] Z: Axis DETAILED DESCRIPTION

[0059] The following disclosure provides different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and also includes an embodiment in which an additional feature can be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact.

[0060] Additionally, spatially relative terms, such as "below," "beneath," "below," "above," "over," and the like, may be used herein to facilitate describing the relationship of one element or feature to another element or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0061] As used herein, the term "nominal" refers to the expected or target value of a characteristic or parameter set for the operation of a component or process during the design phase of the component or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​is usually due to minor variations in the process or tolerances.

[0062] In some embodiments, the terms "approximately" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value).

[0063] As used in this disclosure, the term "vertical" refers to nominally perpendicular to the surface of a substrate.

[0064] Integrated circuits (ICs) may include a combination of semiconductor structures such as input / output (I / O) field effect transistors (FETs) and non-I / O field effect transistors (non-I / O FETs). The I / O field effect transistors may be part of a circuit formed in a peripheral region of the integrated circuit (referred to as an "I / O region" or "high voltage region"), for example, while the non-I / O devices may be part of a "core" circuit (referred to as a logic circuit or memory circuit) formed in a "core" region of the integrated circuit. The I / O devices may be configured to receive an input / output voltage or current of the integrated circuit and withstand a higher voltage or current than the non-I / O devices. For example, the I / O devices may be configured to process an input voltage from an external power source (e.g., a lithium-ion battery) and output a voltage of approximately 5 volts (V). In addition, these I / O devices may be part of a transformer circuit that outputs a distribution voltage of approximately 1 volt (which may then be distributed to the non-I / O field effect transistors). On the other hand, non-input / output devices are not configured to directly process input / output voltage / current, and they are referred to as core devices, logic devices, and / or memory devices. For example, non-input / output devices may include field effect transistors (e.g., NAND, NOR, inverters, or combinations thereof) that form logic gates. In addition, non-input / output devices may include memory devices (e.g., static random-access memory (SRAM) devices, dynamic random-access memory (DRAM) devices, other types of memory devices, or combinations thereof).

[0065] In order to improve manufacturing efficiency, it is desirable to form input / output and non-input / output field effect transistors simultaneously on the same substrate. In multiple technology nodes, metal gate materials and high-k dielectric materials (e.g., k values ​​greater than 3.9) have been used in the gate stack manufacturing of non-input / output field effect transistors to improve device performance and promote device size miniaturization. In order to make the manufacturing process between input / output and non-input / output field effect transistors more simplified, more coordinated and more efficient, metal gates and high-k dielectric materials have also been used for the gate stack of input / output field effect transistors.

[0066] Because the input / output and non-input / output field effect transistors are configured to operate at different voltages (e.g., about 5 volts and about 1 volt, respectively), their structures may differ in their physical dimensions. For example, the gate stack of the input / output field effect transistor may have a larger surface area (e.g., greater than about 1 square micron (μm)) than the gate stack of the non-input / output field effect transistor (which has a smaller size). 2 )) and include a thicker gate oxide. Due to the large size of the I / O field effect transistors, chemical mechanical planarization of these devices may be challenging if the material of the gate electrode is a metal or a metal-containing stack. For example, planarization of such large features can cause corrosion or "dishing" of the gate electrode of the I / O field effect transistor. As a result, the thickness of the gate electrode of the I / O field effect transistor may not be uniform across the device, which may degrade the performance and reliability of the I / O field effect transistor.

[0067] Embodiments of the present disclosure are directed to a method for forming a non-input / output field effect transistor having a metal gate electrode and a high-k gate dielectric and simultaneously forming an input / output field effect transistor having a polysilicon gate electrode and a silicon oxide gate dielectric. In some embodiments, the polysilicon gate electrode provides a restoring force for the chemical mechanical planarization recess and thus allows a larger input / output field effect transistor (e.g., equal to or greater than about 10 μm) to be formed in the process. 2 In some embodiments, the methods described herein can be applied to planar and non-planar transistors (eg, fin field effect transistors).

[0068] According to some embodiments, Figure 1 1 is an isometric view of a polysilicon input / output field effect transistor structure 100. The polysilicon input / output field effect transistor structure 100 is formed on a semiconductor substrate 105 between substrate isolation regions 110. In some embodiments, each substrate isolation region 110 can be a shallow trench isolation (STI) region that includes a dielectric material such as silicon dioxide (SiO2) or a low-k dielectric material (e.g., a k value less than about 3.9). The substrate isolation region 110 is formed in the semiconductor substrate 105 to provide electrical isolation between doped regions of the semiconductor substrate 105. For simplicity, Figure 1The doping region of the semiconductor substrate 105 is not shown. According to some embodiments, the semiconductor substrate 105 may include (i) silicon, (ii) a compound semiconductor, such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb), (iii) an alloy semiconductor, including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP) and / or gallium indium arsenide phosphide (GaInAsP), or (iv) a combination thereof. For illustrative purposes, crystalline silicon will be used as the semiconductor substrate 105 in the present disclosure. Based on the disclosure herein, other materials as described above may be used. These materials are all within the spirit and scope of the present disclosure.

[0069] The polysilicon input / output field effect transistor structure 100 is connected to an adjacent device or structure (in Figure 1 In some embodiments, the dielectric layer 115 may be an interlayer dielectric (e.g., silicon dioxide (SiO2), doped silicon dioxide (SiO2), or any other suitable dielectric material having a dielectric constant equal to or less than about 3.9 (e.g., about 3.6, about 3.3, etc.)). As an example and not limitation, Figure 1 As shown, dielectric layer 115 surrounds the side surfaces of polysilicon I / O FET structure 100 .

[0070] In some embodiments, the polysilicon input / output field effect transistor structure 100 includes a gate stack having a gate dielectric layer 120 formed on a semiconductor substrate 105 and a polysilicon gate electrode layer 125 disposed on the gate dielectric layer 120. By way of example and not limitation, the gate dielectric layer 120 may include silicon oxide (SiO2), which may be thermally grown on (e.g., in contact with) the semiconductor substrate 105. By way of example and not limitation, the gate dielectric layer 120 may be approximately 20 angstroms thick. The gate dielectric layer 120 allows the polysilicon input / output field effect transistor structure 100 to operate at a high gate voltage (e.g., about 5 volts). In some embodiments, the thickness of the polysilicon gate electrode layer 125 is about 125 angstroms. T The diameter is about 10 nanometers (nm) to about 300 nm, and the width is 125 W From about 0.1 micrometers (μm) to about 100 μm, length 125 L According to some embodiments, the surface area of ​​the polysilicon gate electrode layer 125 (eg, 125W ×125 L ) is greater than about 1 μm 2 In some embodiments, the surface area of ​​the polysilicon gate electrode layer 125 is about 1 μm 2 to about 10 μm 2 In some embodiments, the surface area of ​​the polysilicon gate electrode layer 125 is greater than about 10 μm 2 (For example, about 20 μm 2 ).

[0071] In some embodiments, even if the surface area of ​​the gate electrode is larger than about 10 μm 2 The polysilicon gate electrode layer 125 of the polysilicon input / output field effect transistor structure 100 can also provide a restoring force for the depression caused by the gate electrode chemical mechanical planarization process. In other words, after the gate chemical mechanical planarization process, the thickness 125 of the polysilicon input / output field effect transistor structure 100 is T In length 125 L and width 125 W According to some embodiments, after the gate chemical mechanical planarization process, the thickness 125 T In length 125 L and width 125 W The change in thickness can be about 10% or less. T , the thickness variation can be about 1 nm. Fig.11 According to some embodiments, (e.g., after chemical mechanical planarization) the center to edge thickness ratio (C / E) of the planarized polysilicon gate electrode layer 125 of the polysilicon input / output field effect transistor structure 100 is between about 0.9 and about 1. That is, along the xy plane, the center (C) thickness of the planarized polysilicon gate electrode layer 125 of the polysilicon input / output field effect transistor structure 100 is between about 90% and about 100% of the edge (E) thickness.

[0072] also, Figure 1 The polysilicon input / output field effect transistor structure 100 shown has a width 125 along the polysilicon gate electrode layer 125. W The spacer structure 130 is included on the sidewall of the . As an example and not limitation, the spacer structure 130 may include a nitride (eg, silicon nitride), and may further include one or more layers to form a spacer stack.

[0073] In some embodiments, the polysilicon gate electrode layer 125 includes a silicide portion, wherein a contact structure ( Figure 1In some embodiments, the silicided portion of the polysilicon gate electrode layer 125 is a capping silicide layer 135, which includes titanium silicide, nickel silicide, cobalt silicide, or any suitable silicide material that can be formed or grown on the polysilicon gate electrode layer 125. In some embodiments, the polysilicon gate electrode layer 125 is doped to make it conductive. By way of example and not limitation, the dopant concentration of the polysilicon gate electrode layer 125 can be about 10 13 Atoms / cubic centimeter (cm 3 ) and about 10 19 Atom / cm 3 between, and the dopant species can be n-type (eg, phosphorus, arsenic, antimony) or p-type (eg, boron, indium, and gallium).

[0074] In addition, the polysilicon input / output field effect transistor structure 100 may include a source / drain region 140 and a silicide layer 145. In some embodiments, an etch stop layer 150 is disposed on the sidewall surfaces of the substrate isolation region 110, the semiconductor substrate 105, the silicide layer 145, the gate dielectric layer 120, and the spacer structure 130. Figure 1 shown.

[0075] By way of example and not limitation, Figure 1 The polysilicon input / output field effect transistor structure 100 shown is a planar field effect transistor structure. However, this is not limiting, and the polysilicon input / output field effect transistor structure according to the embodiments described in the present disclosure can be formed on one or more semiconductor fins to form one or more non-planar polysilicon input / output field effect transistor structures (e.g., polysilicon input / output fin field effect transistor structures). For example, Figure 2 2 is an isometric view of two polysilicon input / output fin field effect transistor structures 200 formed on semiconductor fins 205. Figure 1 and Figure 2 The polysilicon input / output field effect transistor structure 100 and the polysilicon input / output fin field effect transistor structure 200 depicted in the drawings share similar structural elements (e.g., gate dielectric layer 120, polysilicon gate electrode layer 125, spacer structure 130, silicide layer 135, and etch stop layer 150). In addition, the surface areas of the polysilicon gate electrode layer 125 in the polysilicon input / output field effect transistor structure 100 and the polysilicon input / output fin field effect transistor structure 200 may be substantially equal (e.g., greater than about 1 μm 2 , at about 1 μm 2 and about 10 μm 2 Between, or greater than about 10μm 2 (For example, about 20 μm 2)). In some embodiments, the gate dielectric layer 120 is substantially thicker than the gate dielectric layers of the non-I / O FET and the non-I / O FinFET.

[0076] In some embodiments, Figure 1 The polysilicon input / output field effect transistor structure 100 shown can be formed simultaneously with non-input / output field effect transistor structures on the same semiconductor substrate. Figure 2 The illustrated polysilicon I / O FinFET structure 200 may be formed simultaneously with non-I / O FinFET structures on the same semiconductor substrate.

[0077] Figure 3 is a flow chart of method 300, which describes the process of forming planar and non-planar polysilicon input / output field effect transistor structures having polysilicon gate electrodes and silicon oxide gate dielectrics, and simultaneously forming non-input / output field effect transistor structures having metal gate electrodes and high-k gate dielectrics. Other manufacturing operations may be performed between the various operations of method 300 and may be omitted for clarity only. For purposes of example, the polysilicon input / output field effect transistor structure formed using method 300 will be described in this disclosure as a planar structure (e.g., polysilicon input / output field effect transistor structure 100). Based on the present disclosure, method 300 can be used to form non-planar input / output polysilicon field effect transistor structures (e.g., polysilicon input / output fin field effect transistor structure 200, as shown above, which share similar structural elements and surface areas). These non-planar input / output polysilicon field effect transistor structures (e.g., input / output polysilicon fin field effect transistor structures) are all within the spirit and scope of the present disclosure. The description of method 300 will refer to Figures 4 to 9 .

[0078] refer to Figure 3 and Figure 4 The method 300 begins with operation 305, which is a process of forming a gate dielectric layer in a first region of a semiconductor substrate and forming a high-k gate dielectric layer in a second region of the semiconductor substrate. In some embodiments, the first region of the semiconductor substrate corresponds to a region in which an input / output device is formed in an integrated circuit (e.g., an input / output region of the semiconductor substrate). The second region of the semiconductor substrate corresponds to a region in which a non-input / output device is formed in an integrated circuit (e.g., a non-input / output region of the semiconductor substrate).

[0079] By way of example and not limitation, refer to Figure 4, the gate dielectric layer 120 is formed in the input / output substrate region 400 (wherein the gate dielectric layer 120 corresponds to the gate dielectric layer of operation 305), and the high dielectric constant gate dielectric layer 410 is formed in the non-input / output substrate region 405 of the semiconductor substrate 105 (wherein the high dielectric constant gate dielectric layer 410 corresponds to the high dielectric constant gate dielectric layer of operation 305). Since the gate dielectric layer 120 is used for the input / output field effect transistor (rather than the non-input / output field effect transistor), the gate dielectric layer 120 is selectively formed in the input / output substrate region 400 of the semiconductor substrate 105, as shown in FIG. Figure 4 In some embodiments, Figure 4 The input / output substrate region 400 is spanned as Figure 1 4 is a cross-sectional view of the semiconductor substrate 105 along the cut line AB shown in FIG. According to some embodiments, the input / output substrate region 400 corresponds to an input / output region of the integrated circuit, and the non-input / output substrate region 405 corresponds to a non-input / output region (e.g., a core or logic region) of the integrated circuit. In some embodiments, the input / output substrate region 400 and the non-input / output substrate region 405 are not adjacent regions (e.g., the input / output substrate region 400 and the non-input / output substrate region 405 are spaced apart). The selective process of forming the gate dielectric layer 120 in the input / output substrate region 400 may include first forming the gate dielectric layer 120 on the input / output and non-input / output substrate regions, and then patterning the gate dielectric layer 120 to remove the gate dielectric layer 120 from the non-input / output substrate region 405. By way of example and not limitation, the gate dielectric layer 120 may be thermally grown or deposited in a thickness range between about 20 angstroms and about 500 angstroms.

[0080] By way of example and not limitation, the dielectric constant (k value) of the high-k gate dielectric layer 410 is greater than about 3.9 (e.g., about 4.0, about 10, about 20, about 30, etc.). In some embodiments, the high-k gate dielectric layer 410 is a metal oxide layer that is blanket deposited on the I / O and non-I / O substrate regions and then patterned such that Figure 4 4 is removed from the input / output substrate region 400. In some embodiments, the thickness of the high-k gate dielectric layer 410 is in a range of about 5 angstroms to about 20 angstroms. In some embodiments, an interfacial gate dielectric layer (at the interface) is formed between the high-k gate dielectric layer 410 in the non-input / output substrate region 405 and the semiconductor substrate 105. Figure 4 The interface gate dielectric layer may include, for example, silicon oxide or silicon oxynitride. In some embodiments, the high-k gate dielectric layer 410 and the interface gate dielectric layer form a gate dielectric stack in the non-I / O substrate region 405.

[0081] refer to Figure 3 The method 300 continues with operation 310, which is a process of depositing and patterning a polysilicon gate electrode layer on the gate dielectric layer 120 and the high-k gate dielectric layer 410 to form polysilicon gate electrode structures for input / output and non-input / output field effect transistors, respectively. Figure 5 , a polysilicon gate electrode layer 125 having a thickness between about 100 angstroms and about 3000 angstroms may be blanket deposited on the semiconductor substrate 105 and then patterned to form an input / output field effect transistor gate electrode structure 500 in the input / output substrate region 400 and simultaneously form a non-input / output field effect transistor gate electrode structure 505 in the non-input / output substrate region 405. In some embodiments, the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505 are formed using a single patterning operation. In some embodiments, during operation 310, patterning of the polysilicon gate electrode layer 125 may be performed with the aid of a hard mask stack, the hard mask stack including a bottom oxide layer 515 (e.g., a silicon oxide layer) and a top nitride layer 520 (e.g., a silicon nitride layer). The oxide layer 515 and the nitride layer 520 may protect the polysilicon gate electrode layer 125 during the etching operation of the aforementioned patterning process.

[0082] In some embodiments, the length of the I / O FET gate electrode structure 500 formed in the I / O substrate region 400 is greater than the length of the non-I / O FET gate electrode structure 505 formed in the non-I / O substrate region 405. For example, the length 500 of the I / O FET gate electrode structure 500 is greater than the length of the non-I / O FET gate electrode structure 505 formed in the non-I / O substrate region 405. L (e.g., gate length) is in the range of about 0.05 μm to about 50 μm, while the length of the non-input / output field effect transistor gate electrode structure 505 is (e.g., gate length) between about 5 nm and about 50 nm. In some embodiments, if the length 500 of the input / output field effect transistor gate electrode structure 500 is L If the length of the input / output field effect transistor gate electrode structure 500 is less than about 50 nm, the performance of the input / output field effect transistor may be adversely affected. For example, if the length of the input / output field effect transistor gate electrode structure 500 is less than about 0.05 μm, the input / output field effect transistor may have a high current density, but the amount of leakage current may be unacceptable. On the other hand, if the length of the input / output field effect transistor gate electrode structure 500 is less than about 50 nm, the performance of the input / output field effect transistor may be adversely affected. For example, if the length of the input / output field effect transistor gate electrode structure 500 is less than about 0.05 μm, the input / output field effect transistor may have a high current density, but the amount of leakage current may be unacceptable. LGreater than about 50 μm, the I / O FET gate electrode structure 500 may have a footprint (e.g., surface area) that reduces the space available for other integrated circuit components. In other words, there is a tradeoff between the size of the I / O FET gate electrode structure 500 and the space available for other integrated circuit components.

[0083] In some embodiments, after patterning, the I / O FET gate electrode structure 500 and the non-I / O FET gate electrode structure 505 may have substantially equal widths along the y-axis ( Figure 5 and have a height of 500 respectively along the z-axis direction. H and 505 H However, due to the difference in thickness between the gate dielectric layer 120 and the high-k gate dielectric layer 410, in the subsequent overall planarization operation, the height 500 H will become higher than the height 505 H short.

[0084] In some embodiments, during the patterning process of the polysilicon gate electrode layer 125, the gate dielectric layer 120 in the I / O substrate region 400 remains on the semiconductor substrate 105 and is not removed. On the other hand, the high-k gate dielectric layer 410 is patterned together with the polysilicon gate electrode layer 125. Therefore, the length 500 of the I / O field effect transistor gate electrode structure 500 is L The length of the non-input / output field effect transistor gate electrode structure 505 is substantially equal to the length of the high-k gate dielectric layer 410, as shown in FIG. Figure 5 shown.

[0085] According to some embodiments, the surface area or footprint of the I / O FET gate electrode structure 500 is greater than about 1 μm 2 , at about 1 μm 2 and about 10 μm 2 Between, or greater than about 10μm 2 (For example, about 20 μm 2 According to some embodiments, recess and space availability during chemical mechanical planarization are used to define, among other things, Figure 5 The lateral dimensions (eg, length and width) of the input / output field effect transistor gate electrode structure 500 are shown.

[0086] In some embodiments, the non-I / O field effect transistor gate electrode structure 505 is a sacrificial gate electrode structure that will be replaced by a metal gate electrode stack in subsequent operations.

[0087] refer to Figure 3 , method 300 continues with operation 315, which is a process of forming a spacer structure on the sidewall surface of the polysilicon gate electrode structure (e.g., the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505). By way of example and not limitation, Figure 6 The spacer structure 130 is shown formed on the sidewalls of the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505. By way of example and not limitation, the spacer structure 260 may be formed by blanket deposition of a spacer material (e.g., silicon nitride) followed by an anisotropic etching process. Figure 6 All horizontal surfaces (eg, the yx plane) of the depicted structure are selectively free of spacer material.

[0088] In some embodiments, once the spacer structure 130 is formed on the sidewall surface of the I / O field effect transistor gate electrode structure 500, the second etching process removes the portion of the gate dielectric layer 120 that is not masked (e.g., covered) by the spacer structure 130 in the I / O substrate region 400. In other words, the spacer structure 130 and the I / O field effect transistor gate electrode structure 500 act as an etching mask to define the length of the gate dielectric layer 120 of the I / O field effect transistor in the I / O substrate region 400. Therefore, as Figure 6 As shown, the spacer structure 130 does not cover the sidewall surface of the gate dielectric layer 120 in the I / O FET. In contrast, for non-I / O FETs, the spacer structure 130 extends over the sidewall surface of the high-k gate dielectric layer 410.

[0089] In some embodiments, before operation 315 of forming the spacer structure 130, a lightly doped region 600 is formed in the semiconductor substrate 105 by an ion implantation process using the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505 as implantation masks. Thereafter, after forming the spacer structure 130, a second ion implantation process forms heavily doped regions 610 in the input / output substrate region 400 and the non-input / output substrate region 405, respectively. During the second ion implantation process, the spacer structure 130 serves as an implantation mask. Therefore, the lightly doped region 600 is substantially aligned with the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505, and the heavily doped region 610 is substantially aligned with the spacer structure 130. In some embodiments, the lightly doped region 600 and the heavily doped region 610 together form the source / drain region of the input / output field effect transistor and the non-input / output field effect transistor.

[0090] In some embodiments, after forming the spacer structure 130, the top surface of the heavily doped region 610 is silicided to form a self-aligned silicide (salicide) layer 145 over the source / drain regions of the input / output field effect transistor and the non-input / output field effect transistor. By way of example and not limitation, the formation of the silicide layer 145 may be as follows. A metal layer may be blanket deposited on the semiconductor substrate 105. During a subsequent annealing process, silicide is formed where the deposited metal is in direct contact with the exposed silicon (e.g., the heavily doped region 610 of the semiconductor substrate 105). During the silicide process, the top surfaces of the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505 are not silicided because both structures are covered (e.g., not exposed) by the oxide layer 515 and the nitride layer 520. After the silicide process, the unreacted metal is removed, for example, by a wet etching process. In some embodiments, a second annealing process is performed after removing the unreacted metal to complete the silicidation process. As an example and not limitation, the silicide layer 145 may include nickel silicide, titanium silicide, cobalt silicide, tungsten silicide, or any other suitable metal silicide.

[0091] refer to Figure 3 The method 300 continues with operation 320, which is a process of forming an etch stop layer on the spacer structure 130, the input / output field effect transistor gate electrode structure 500, and the non-input / output field effect transistor gate electrode structure 505. In some embodiments, the etch stop layer can be blanket deposited to cover (e.g., conformally) all features configured on or in the semiconductor substrate 105. For example, Figure 7 As shown, an etch stop layer 150 is deposited on the input / output field effect transistor gate electrode structure 500, the non-input / output field effect transistor gate electrode structure 505, the spacer structure 130, the substrate isolation region 110, and the silicide layer 145. By way of example and not limitation, the etch stop layer 150 may be a nitride layer (e.g., a silicon nitride layer).

[0092] refer to Figure 3 and Figure 8, the method 300 continues with operation 325, which is a process of forming a dielectric layer 115 around the sidewall surfaces of the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505. By way of example and not limitation, the dielectric layer 115 can be blanket deposited on the semiconductor substrate 105 such that the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505 are embedded in the dielectric layer 115. A subsequent chemical mechanical planarization process removes excess dielectric material from the top surfaces of the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505. In some embodiments, the chemical mechanical planarization process removes a portion of the etch stop layer 150, the nitride layer 520, and the oxide layer 515, such that the top surface of the polysilicon gate electrode layer 125 is exposed in both the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505, as shown in FIG. Figure 8 As shown. In some embodiments, as a result of the above-mentioned chemical mechanical planarization process, in the input / output field effect transistor gate electrode structure 500 and the non-input / output field effect transistor gate electrode structure 505, the top surface of the polysilicon gate electrode layer 125 is substantially coplanar with the top surface of the dielectric layer 115. In some embodiments, after the chemical mechanical planarization process, the top surface of the input / output field effect transistor gate electrode structure 500 remains substantially flat without any depression. In addition, after the chemical mechanical planarization process, due to the difference in thickness between the gate dielectric layer 120 and the high dielectric constant gate dielectric layer 410, the input / output field effect transistor gate electrode structure 500 becomes shorter (for example, 500 H <505 H ).

[0093] refer to Figure 3 , the method 300 proceeds to operation 330, which is a process of replacing the gate electrode layer 125 in the non-input / output field effect transistor gate electrode structure 505 with a metal gate electrode structure. By way of example and not limitation, reference Fig. 9, selectively removing the metal gate electrode layer 125 and replacing it with the metal gate electrode 905 to form the non-input / output field effect transistor 910. In some embodiments, the metal gate electrode 905 includes one or more metal or metal-containing layers. By way of example and not limitation, the selective removal of the polysilicon gate electrode layer 125 from the non-input / output field effect transistor gate electrode structure 505 may be performed by masking the input / output substrate region 400 using a hard mask (e.g., a nitride layer) and removing the polysilicon gate electrode layer 125 from the non-input / output field effect transistor gate electrode structure 505 by a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the high-k gate dielectric layer 410 is not removed by an etching process that removes the polysilicon gate electrode layer 125 from the non-input / output field effect transistor gate electrode structure 505. Once the polysilicon gate electrode layer 125 has been selectively removed from the non-input / output field effect transistor gate electrode structure 505, the metal gate electrode 905 may then be deposited. In some embodiments, the material from the metal gate electrode 905 is blanket deposited in the input / output substrate region 400 and the non-input / output substrate region 405. A chemical mechanical planarization process is then performed to remove excess metal gate electrode material from the top surface of the dielectric layer 115 to form the non-input / output field effect transistor 910. During the chemical mechanical planarization process of the metal gate electrode material, the hard mask on the input / output substrate region 400 is removed (at Fig. 9 ), and expose the polysilicon gate electrode layer 125 (such as Fig. 9 ). In some embodiments, after the metal gate electrode chemical mechanical planarization process, the top surface of the input / output field effect transistor gate electrode structure 500 remains substantially flat without recesses. In some embodiments, during the chemical mechanical planarization process of the metal gate electrode material, the polysilicon gate electrode layer 125 of the input / output field effect transistor gate electrode structure 500 has a restoring force to the recesses.

[0094] refer to Figure 3 The method 300 ends at operation 335, which is to form a silicide on the top surface of the input / output field effect transistor gate electrode structure 500 to form Fig. 9 The process of forming the polysilicon input / output field effect transistor 915 is shown. In some embodiments, the silicidation process can be similar to the silicidation process described in the process of forming the silicide layer 145 above. In some embodiments, the non-input / output substrate area 405 can be covered with a hard mask (e.g., a nitride layer) during the silicidation process. Fig.10, a metal layer may be blanket deposited on the dielectric layer 115 over the input / output substrate region 400 and the non-input / output substrate region 405 ( Fig.10 Silicide is formed on the exposed top surface of the input / output field effect transistor gate electrode structure 500 during a subsequent annealing process. After the silicidation process, the unreacted metal is removed by, for example, a wet etching process. In some embodiments, a second annealing process is performed after the unreacted metal is removed to complete the silicidation process. Therefore, a silicide layer 135 is formed on the top surface of the polysilicon gate electrode layer 125, and a polysilicon input / output field effect transistor 915 is formed. By way of example and not limitation, the silicide layer 135 may include nickel silicide, titanium silicide, cobalt silicide, tungsten silicide, or any other suitable metal silicide. According to some embodiments, the process of forming the silicide layer 135 on the polysilicon gate electrode layer 125 may be combined with the process of forming a silicide layer in other areas of the integrated circuit.

[0095] In some embodiments, the method 300 may be used to form a non-planar input / output field effect transistor structure (eg, Figure 2 The input / output FinFET structure 200 is shown.

[0096] Embodiments of the present disclosure are directed to methods for integrating the formation of an input / output field effect transistor having a polysilicon gate electrode / silicon oxide gate dielectric and a non-input / output field effect transistor having a metal gate electrode / high-k gate dielectric. In some embodiments, during a chemical mechanical planarization process of the metal gate electrode of the non-input / output field effect transistor, the polysilicon gate electrode of the input / output field effect transistor provides a restoring force for the chemical mechanical planarization recess, thereby allowing the formation of a transistor having a larger footprint (e.g., greater than about 1 μm) 2 , at about 1 μm 2 and about 10 μm 2 Between, or greater than about 10μm 2 (For example, about 20 μm 2 ) of an input / output field effect transistor. In some embodiments, the method described in the present disclosure is applicable to planar and non-planar transistor structures (eg, fin field effect transistors).

[0097] In some embodiments, a transistor structure includes a first transistor formed on a first region of a semiconductor substrate, wherein the first transistor includes a gate dielectric, a polysilicon gate electrode, and a first spacer structure. The polysilicon gate electrode is disposed on the gate dielectric, wherein the gate dielectric is longer than the gate electrode. The first spacer structure abuts the sidewalls of the polysilicon gate electrode such that the sidewalls of the spacer structure are aligned with the sidewalls of the gate dielectric. The transistor structure also includes a second transistor formed on a second region of the semiconductor substrate, wherein the second transistor is narrower than the first transistor and includes a high dielectric constant gate dielectric, a metal gate electrode, and a second spacer structure. The metal gate electrode is disposed on and aligned with the high dielectric constant gate dielectric such that the sidewalls of the metal gate electrode are aligned with the sidewalls of the high dielectric constant gate dielectric. The second spacer structure abuts the sidewalls of the metal gate electrode and the high dielectric constant gate dielectric. In some embodiments, the surface area of ​​the polysilicon gate electrode is approximately 10 μm 2 and about 20 μm 2 In some embodiments, the center-to-edge thickness ratio of the polysilicon gate electrode is about 0.9. In some embodiments, the width of the polysilicon gate electrode and the width of the metal gate electrode are substantially equal. In some embodiments,

[0098] In some embodiments, a method for manufacturing a transistor structure includes depositing a silicon oxide layer on a first region of a semiconductor substrate; depositing a high-k dielectric layer thinner than the silicon oxide layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide layer and the high-k dielectric layer; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, wherein the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method also includes forming a first spacer on a sidewall of the first polysilicon gate electrode structure so that the outer sidewall of the first spacer is aligned with the sidewall of the silicon oxide layer; forming a second spacer on the sidewall of the second polysilicon gate electrode structure and the high-k dielectric layer; and replacing the second polysilicon gate electrode structure with a metal gate electrode structure. In some embodiments, patterning the polysilicon layer includes making the surface area of ​​the first polysilicon gate electrode structure larger than the surface area of ​​the second polysilicon gate electrode structure. In some embodiments, patterning the polysilicon layer includes forming a polysilicon layer having a thickness of about 10 μm. 2 to about 20 μm 2of the surface area of ​​the first polysilicon gate electrode structure. In some embodiments, replacing the second polysilicon gate electrode structure includes masking the first polysilicon gate electrode structure. In some embodiments, replacing the second polysilicon gate electrode structure includes exposing the first polysilicon gate electrode structure to a chemical mechanical planarization process. In some embodiments, the method further includes depositing a dielectric layer between the first polysilicon gate electrode structure and the second polysilicon gate electrode structure and planarizing the dielectric layer before replacing the second polysilicon gate electrode structure, so that a top surface of the dielectric layer and a top surface of the first polysilicon gate electrode structure and a top surface of the second polysilicon gate electrode structure are substantially coplanar. In some embodiments, planarizing the dielectric layer includes planarizing the dielectric layer so that the first polysilicon gate electrode structure is shorter than the second polysilicon gate electrode structure, and the center-to-edge thickness ratio of the first polysilicon gate electrode structure is between about 0.9 and about 1.

[0099] In some embodiments, a transistor structure includes a first transistor formed on a first region of a semiconductor substrate, wherein the first transistor includes a silicon oxide gate dielectric, a polysilicon gate electrode, and a first spacer structure. The polysilicon gate electrode is disposed on the silicon oxide gate dielectric, and the sidewall edge of the polysilicon gate electrode is not aligned with the sidewall edge of the silicon oxide gate dielectric. The inner sidewall of the first spacer structure abuts the sidewall edge of the polysilicon gate electrode. The transistor structure also includes a second transistor formed on a second region of the semiconductor substrate, wherein the second transistor is narrower than the first transistor and includes a high dielectric constant gate dielectric, a metal gate electrode, and a second spacer structure. The metal gate electrode is disposed on the high dielectric constant gate dielectric so that the sidewall edge of the metal gate electrode is aligned with the sidewall edge of the high dielectric constant gate dielectric. The second spacer structure abuts the sidewall edge of the metal gate electrode and the high dielectric constant gate dielectric. In some embodiments, the first spacer structure has a plurality of outer sidewall edges aligned with the sidewall edge of the silicon oxide gate dielectric. In some embodiments, the surface area of ​​the polysilicon gate electrode is about 10 μm 2 and about 20 μm 2 and a center-to-edge thickness ratio of the polysilicon gate electrode is between about 0.9 and about 1. In some embodiments, the silicon oxide gate dielectric is thicker than the high-k gate dielectric. In some embodiments, the metal gate electrode is taller than the polysilicon gate electrode, and a height difference between the metal gate electrode and the polysilicon gate electrode is equal to a thickness difference between the silicon oxide gate dielectric and the high-k gate dielectric.

[0100] It should be understood that the "Implementation" paragraphs in this disclosure, rather than the "Abstract" paragraphs, are intended to be used to interpret the claims. In this disclosure, the Abstract paragraphs may set forth one or more embodiments (but not all possible embodiments) of the present disclosure, and therefore, the Abstract paragraphs are not intended to limit the claims described later in any way.

[0101] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same benefits as the embodiments introduced herein. Those skilled in the art will also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A transistor structure, characterized in that: Include: A first transistor is formed on a first region of a semiconductor substrate, wherein the first transistor comprises: a first source / drain region disposed in the semiconductor substrate and comprising a lightly doped region in the semiconductor substrate; a gate dielectric disposed on the semiconductor substrate; a polysilicon gate electrode disposed on the gate dielectric, wherein the length of the gate dielectric is greater than the length of the polysilicon gate electrode, and a sidewall of the lightly doped region is aligned with a sidewall of the polysilicon gate electrode; as well as a first spacer structure adjacent to a sidewall of the polysilicon gate electrode; as well as a second transistor having a length shorter than that of the first transistor and formed on a second region of the semiconductor substrate, wherein the second transistor comprises: a high-k gate dielectric; a metal gate electrode; a second spacer structure adjacent to the sidewall of the metal gate electrode and the sidewall of the high-k gate dielectric; as well as A second source / drain region is disposed in the semiconductor substrate and is coplanar with the first source / drain region, wherein the second source / drain region directly contacts the bottom surface of the second spacer structure.

2. The transistor structure according to claim 1, characterized in that: The surface area of ​​the polysilicon gate electrode is 10 μm 2 and 20 μm 2 between.

3. The transistor structure according to claim 1, characterized in that: The center-to-edge thickness ratio of the polysilicon gate electrode is 0.

9.

4. The transistor structure according to claim 1, characterized in that: The width of the polysilicon gate electrode is equal to the width of the metal gate electrode.

5. The transistor structure according to claim 1, characterized in that: The metal gate electrode is higher than the polysilicon gate electrode, and the height difference between the metal gate electrode and the polysilicon gate electrode is equal to the thickness difference between the gate dielectric and the high dielectric constant gate dielectric.

6. The transistor structure according to claim 1, characterized in that: The thickness of the gate dielectric is greater than the thickness of the high-k gate dielectric, and the gate dielectric comprises silicon oxide.

7. The transistor structure according to claim 1, characterized in that: Also included is a silicide layer on the polysilicon gate electrode, wherein the silicide layer and the polysilicon gate electrode have equal surface areas.

8. The transistor structure according to claim 1, characterized in that: The first transistor is configured to operate at 5 volts and the second transistor is configured to operate at 1 volt.

9. A method for manufacturing a transistor, characterized in that: Include: Forming a plurality of lightly doped regions by performing an ion implantation process on a semiconductor substrate; Depositing a silicon oxide layer on a first region of the semiconductor substrate; Depositing a high-k dielectric layer on a second region of the semiconductor substrate, wherein the high-k dielectric layer is thinner than the silicon oxide layer; Depositing a polysilicon layer on the silicon oxide layer and the high-k dielectric layer; Patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer, and forming a second polysilicon gate electrode structure on the high-k dielectric layer, wherein the length of the first polysilicon gate electrode structure is greater than the length of the second polysilicon gate electrode structure, and the length of the silicon oxide layer is greater than the length of the first polysilicon gate electrode structure; forming a first spacer on a plurality of sidewalls of the first polysilicon gate electrode structure; forming a second spacer on a plurality of sidewalls of the second polysilicon gate electrode structure and a plurality of sidewalls of the high-k dielectric layer; Performing an ion implantation process on the semiconductor substrate using the first spacer and the second spacer as implantation masks to form a plurality of heavily doped regions, wherein the lightly doped regions and the heavily doped regions together serve as a first source / drain region and a second source / drain region, wherein the second source / drain region is coplanar with the first source / drain region, a sidewall of the lightly doped region of the first source / drain region is aligned with a sidewall of the first polysilicon gate electrode, and the second source / drain region directly contacts a bottom surface of the second spacer; and A metal gate electrode structure is used to replace the second polysilicon gate electrode structure.

10. The method according to claim 9, characterized in that Patterning the polysilicon layer includes forming a 10 μm 2 Up to 20μm 2 The surface area of ​​the first polysilicon gate electrode structure.

11. The method according to claim 10, characterized in that Patterning the polysilicon layer includes making the surface area of ​​the first polysilicon gate electrode structure larger than the surface area of ​​the second polysilicon gate electrode structure.

12. The method according to claim 9, characterized in that Replacing the second polysilicon gate electrode structure includes masking the first polysilicon gate electrode structure.

13. The method according to claim 9, characterized in that Replacing the second polysilicon gate electrode structure includes exposing the first polysilicon gate electrode structure to a chemical mechanical planarization process.

14. The method according to claim 9, characterized in that Also includes: Before replacing the second polysilicon gate electrode structure, a dielectric layer is deposited between the first polysilicon gate electrode structure and the second polysilicon gate electrode structure and the dielectric layer is planarized so that the top surface of the dielectric layer is coplanar with the top surface of the first polysilicon gate electrode structure and the top surface of the second polysilicon gate electrode structure.

15. The method according to claim 14, characterized in that Planarizing the dielectric layer includes planarizing the dielectric layer so that the first polysilicon gate electrode structure is shorter than the second polysilicon gate electrode structure, and a center-to-edge thickness ratio of the first polysilicon gate electrode structure is between 0.9 and 1.

16. A transistor structure, characterized in that: Include: A first transistor is formed on a first region of a semiconductor substrate, wherein the first transistor comprises: a first source / drain region disposed in the semiconductor substrate and comprising a lightly doped region in the semiconductor substrate; A silicon monoxide gate dielectric is disposed on the semiconductor substrate; a polysilicon gate electrode disposed on the silicon oxide gate dielectric, wherein the length of the silicon oxide gate dielectric is greater than the length of the polysilicon gate electrode, and a side wall of the lightly doped region is aligned with a side wall of the polysilicon gate electrode; as well as a first spacer structure having a plurality of inner sidewalls adjacent to a plurality of sidewall edges of the polysilicon gate electrode; as well as a second transistor formed on a second region of the semiconductor substrate, wherein the surface area of ​​the second transistor is smaller than the surface area of ​​the first transistor, and comprising: a high-k gate dielectric; a metal gate electrode disposed on the high-k gate dielectric; a second spacer structure adjacent to the plurality of sidewall edges of the metal gate electrode and the plurality of sidewall edges of the high-k gate dielectric; as well as A second source / drain region is disposed in the semiconductor substrate and is coplanar with the first source / drain region, wherein the second source / drain region directly contacts the bottom surface of the second spacer structure.

17. The transistor structure according to claim 16, characterized in that: The outer sidewall of the first spacer structure is aligned with the sidewall edge of the silicon oxide gate dielectric.

18. The transistor structure according to claim 16, characterized in that: The surface area of ​​the polysilicon gate electrode is 10 μm 2 and 20 μm 2 and a center-to-edge thickness ratio of the polysilicon gate electrode is between 0.9 and 1.

19. The transistor structure according to claim 16, characterized in that: The thickness of the silicon oxide gate dielectric is greater than the thickness of the high-k gate dielectric.

20. The transistor structure according to claim 16, characterized in that The metal gate electrode is higher than the polysilicon gate electrode, and the height difference between the metal gate electrode and the polysilicon gate electrode is equal to the thickness difference between the silicon oxide gate dielectric and the high dielectric constant gate dielectric.

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