Operational amplifier

Abstract

To provide an operational amplifier that can be used in high-voltage applications.SOLUTION: A first high breakdown voltage transistor Mhv1 has a source connected to a drain of a first transistor M1 and to a gate thereof, a first bias voltage Vbn2 is applied. A second high breakdown voltage transistor Mhv2 has a source connected to a drain of a second transistor M2 and to a gate thereof, the first bias voltage Vbn2 is applied. A bias voltage source 260 generates a bias voltage Vbn2 that changes in conjunction with an input voltage VIN.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to operational amplifiers. [Background technology]

[0002] An operational amplifier (differential amplifier) is used to amplify the difference between two input voltages. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-96970

[0004] [overview] The present disclosure has been made in this context, and one exemplary purpose of an embodiment thereof is to provide an operational amplifier that can be used in high-voltage applications.

[0005] The present disclosure relates to an operational amplifier having an input stage and an output stage. The input stage includes a first input terminal, a second input terminal, an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal, and a second transistor of the first polarity whose gate is connected to the second input terminal, a tail current source including a third transistor of the first polarity whose drain is connected to the input differential pair, a first high-voltage transistor of the first polarity whose source is connected to the drain of the first transistor and whose gate is applied with a first bias voltage, and a second transistor of the second polarity whose source is connected to the drain of the second transistor and whose gate is applied with a first bias voltage. The power supply includes an assist circuit including a second high-voltage transistor of a first polarity, an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor, a first current source connected to the drain of the first transistor and outputting a current in an enabled state, and a second current source connected to the drain of the second transistor and outputting a current in an enabled state, and which enables the first current source and the second current source when an input voltage generated at one of the first input terminal and the second input terminal falls within a predetermined voltage range.

[0006] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0007] [Figure 1] Figure 1 is a circuit diagram of an operational amplifier. [Figure 2] FIG. 2 is a circuit diagram of an input stage according to the comparison technique. [Figure 3] FIG. 3 is a diagram showing input / output characteristics of a voltage follower according to the comparative technique. [Figure 4] FIG. 4 is a circuit diagram of an input stage according to the embodiment. [Figure 5] FIG. 5 shows the voltages at several nodes of the input stage. [Figure 6] FIG. 6 is a diagram showing the input / output characteristics of a voltage follower configured using an operational amplifier according to the embodiment. [Figure 7] FIG. 7 is a diagram showing the input voltage dependency of the offset voltage of an operational amplifier. [Figure 8] FIG. 8 is a circuit diagram of an input stage according to a modified example. [Figure 9] FIG. 9 is a circuit diagram of an input stage according to a modified example.

[0008] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0009] In this specification, a transistor of the first polarity is either an N-type transistor (N-channel MOSFET or NPN-type bipolar transistor) or a P-type transistor (P-channel MOSFET or PNP-type bipolar transistor), and a transistor of the second polarity is the other of an N-type transistor and a P-type transistor.

[0010] An operational amplifier according to one embodiment has an input stage and an output stage. The input stage includes a first input terminal, a second input terminal, an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal and a second transistor of the first polarity whose gate is connected to the second input terminal, a tail current source including a third transistor of the first polarity whose drain is connected to the input differential pair, a first high-voltage transistor of the first polarity whose source is connected to the drain of the first transistor and whose gate receives a bias voltage, a second high-voltage transistor of the first polarity whose source is connected to the drain of the second transistor and whose gate receives a bias voltage, an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor, and a bias circuit that outputs a bias voltage that varies depending on an input voltage generated at one of the first input terminal and the second input terminal.

[0011] With this configuration, when the input voltage changes, the bias voltage and, therefore, the clamp levels of the drain voltages of the first and second transistors change accordingly, allowing the first and second transistors to continue operating in their saturation region, thereby expanding the operating range of the operational amplifier.

[0012] In one embodiment, the bias circuit may include an output node connected to the gates of the first and second high-voltage transistors, a current source, a third high-voltage transistor of a second polarity having a source connected to the current source, a drain connected to the output node, and a gate to which the second bias voltage is applied, and a fourth transistor of the second polarity having a source connected to the output node and a gate connected to one of the first and second input terminals. This configuration makes it possible to generate a bias voltage that is linked to the input voltage.

[0013] In one embodiment, the bias circuit may further include a fifth transistor having a gate and a drain connected to the drain of the fourth transistor.

[0014] In one embodiment, the bias circuit may further include a sixth transistor of the second polarity, having a source connected to the output node and a gate connected to the other of the first input terminal and the second input terminal.

[0015] In one embodiment, the operational amplifier may be monolithically integrated on a single semiconductor substrate. "Monolithically integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main circuit components are monolithically integrated, and some resistors, capacitors, etc. for adjusting the circuit constants may be provided outside the semiconductor substrate.

[0016] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0017] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0018] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0019] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0020] First, the basic configuration of an operational amplifier will be described with reference to FIG.

[0021] 1 is a circuit diagram of an operational amplifier 100. The operational amplifier 100 receives differential input signals Vp and Vn at differential input terminals INP and INN, and outputs an amplified output signal from an output terminal OUT. The operational amplifier 100 may be a voltage output type or a current output type transconductance amplifier. A power supply voltage V DD is supplied to the ground terminal GND, and the ground terminal GND is grounded.

[0022] The operational amplifier 100 includes an input stage 200 and an output stage 300. The input stage 200 may include a differential input stage that amplifies the potential difference between differential input signals Vp and Vn to generate a differential current, and a gain stage that further amplifies the differential current to generate an intermediate signal Vm.

[0023] The output stage 300 generates a signal corresponding to the intermediate signal Vm at the output terminal OUT. The output stage 300 functions as a buffer to prevent the operational amplifier 100 from being affected by a load (not shown) connected to the output terminal OUT.

[0024] The present inventors have considered increasing the voltage resistance of the input stage 200 and have come to recognize the following problem. Figure 2 is a circuit diagram of an input stage 200R according to a comparative technique. The input stage 200R operates using the voltage VDD of the power supply line 202 and the voltage VSS of the ground line 204 as rails.

[0025] The input stage 200R includes an input differential pair 210, a tail current source 220, an active load 230, a first high-voltage transistor Mhv1, a second high-voltage transistor Mhv2, and a bias voltage source 260R. The semiconductor integrated circuit according to the present disclosure is configured by combining high-voltage transistors with a relatively high drain-source breakdown voltage and normal-voltage transistors with a relatively low drain-source breakdown voltage. The high-voltage transistors have a breakdown voltage of, for example, several tens of volts, while the normal-voltage transistors have a breakdown voltage of several volts.

[0026] The input differential pair 210 includes a first transistor M1 and a second transistor M2, which are N-channel MOSFETs. The first transistor M1 and the second transistor M2 are normal voltage transistors, and their gates are connected to a first input terminal IN1 and a second input terminal IN2, respectively. The first input terminal IN1 is one of the differential inputs INP and INN of the operational amplifier 100, and the second input terminal IN2 is the other of the differential inputs INP and INN. The tail current source 220 includes a third transistor M3, and a bias voltage Vbn1 is applied to its gate so that a predetermined amount of tail current Itail flows.

[0027] A differential current corresponding to the potential difference between the input voltages VIN1 and VIN2 flows through the input differential pair 210. The differential currents Id1 and Id2 are supplied to the active load 230.

[0028] To increase the withstand voltage of the input stage 200R, a first high-voltage transistor Mhv1 and a second high-voltage transistor Mhv2 are added between the input differential pair 210 and the output stage 300. In this embodiment, the first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2 are preferably depletion-type transistors. The first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2 are N-channel MOSFETs, and a predetermined voltage Vbn2 is supplied to their gates. The first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2 each function as a clamp element that clamps the source voltage (i.e., the drain voltage of the first transistor M1 and the second transistor M2) so that it does not exceed Vlim = Vbn2 - Vgs. This limits the drain-source voltage of the first transistor M1 and the second transistor M2, thereby protecting the first transistor M1 and the second transistor M2.

[0029] The active load 230 is a folded cascode amplifier circuit and includes normal voltage transistors M11 to M16 and high voltage transistors Mhv11, Mhv12, Mhv13, and Mhv14. The high voltage transistors Mhv11 and Mhv12 clamp the drain voltage of the transistors M13 and M14 so that it does not exceed a clamp level determined by Vbn1-Vgs. The high voltage transistors Mhv13 and Mhv14 clamp the drain voltage of the transistors M15 and M16 so that it does not exceed a clamp level determined by Vbp+Vgs. The output terminal OUT of the active load 230 is connected to the output stage 300 located downstream. The active load 230 may be a current mirror circuit.

[0030] The bias voltage source 260R generates a constant bias voltage Vbn2 that is independent of the power supply voltage VDD, and supplies it to the gates of the first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2.

[0031] For example, the bias voltage source 260R includes a current source CS11, a third high-voltage transistor Mhv3, and a constant-voltage source 262. The current source CS11 includes a P-channel MOSFET transistor M6 biased to pass a constant current Ic11. The constant-voltage source 262 generates a constant voltage Vbn2 corresponding to the constant current Ic6. The third high-voltage transistor Mhv3 is a P-channel MOSFET connected between the drain of the transistor M6 and the constant-voltage source 262. A bias voltage Vbp is applied to the gate of the third high-voltage transistor Mhv3. The third high-voltage transistor Mhv3 clamps the voltage at the drain of the transistor M6 so that it does not fall below a clamp level Vbp+Vgs. The constant-voltage source 262 includes multiple constant-voltage elements connected in series. The constant-voltage elements can be Zener diodes, diodes, transistors, resistors, or a combination of these.

[0032] The above is the configuration of the input stage 200R according to the comparative technology. Assume that a voltage follower is configured using an operational amplifier 100R equipped with the input stage 200R. The voltage follower is a circuit in which the output terminal and inverting input terminal of the operational amplifier are connected.

[0033] Figure 3 shows the power supply voltage (VDD) dependency of the output voltage of a voltage follower according to the comparative technology. Here, an input voltage of 2.5V is applied to the non-inverting input terminal of the operational amplifier. In the voltage range of VDD > 2.5V, an output voltage equal to the input voltage is obtained.

[0034] According to this input stage 200R, by using a plurality of high-voltage transistors as a clamp circuit, it can be used in applications where the power supply voltage VDD is several tens of V. The inventors have studied the input stage 200R in FIG. 2 and have come to recognize the following problem.

[0035] Fig. 3 shows the input / output characteristics of a voltage follower according to the comparative technology. Graph (i) shows the ideal characteristics where the output voltage is equal to the input voltage. Graph (ii) shows the input / output characteristics when Vbn2=3V, and graph (iii) shows the input / output characteristics when Vbn2=2V. The lower part of Fig. 3 shows an enlarged view of the range of VIN=3 to 5V.

[0036] As the input voltage V increases, the source voltages of the first transistor M1 and the second transistor M2 increase accordingly. Meanwhile, in the input stage 200R of FIG. 2, the gate voltages of the first high-voltage transistor Mhv1 and the second high-voltage transistor Mhv2 are fixed to a constant bias voltage Vbn2, so the drain voltages of the first transistor M1 and the second transistor M2 are clamped to a constant voltage level. Therefore, as the input voltage V increases, the drain-source voltages of the first transistor M1 and the second transistor M2 decrease. When the input voltage V exceeds 4V, the first transistor M1 and the second transistor M2 transition from the saturation region to the linear region, degrading linearity. These are the issues that arise in the comparative technology.

[0037] Next, the input stage 200 according to the embodiment will be described.

[0038] 4 is a circuit diagram of an input stage 200 according to an embodiment. The input stage 200 includes an input differential pair 210, a tail current source 220, an active load 230, a first high-voltage transistor Mhv1, a second high-voltage transistor Mhv2, and a bias voltage source 260.

[0039] In the comparative technology, the bias voltage source 260R generates a bias voltage of a fixed constant level, whereas in this embodiment, the bias voltage source 260 outputs a bias voltage Vbn2 that is linked to the input voltage VIN generated at one of the first input terminal IN1 and the second input terminal IN2.

[0040] For example, the bias voltage source 260 includes a fourth transistor M4, a current source CS11, and a third high-voltage transistor Mhv3.

[0041] An output node 261 of the bias voltage source 260 is connected to the gate of the first high-voltage transistor Mhv1 and the gate of the second high-voltage transistor Mhv2.

[0042] The current source CS11 includes a P-channel MOSFET transistor M6 biased to pass a constant current Ic11. The third high-voltage transistor Mhv3 is a P-channel MOSFET connected between the drain of the transistor M6 and the output node 261. A bias voltage Vbp is applied to the gate of the third high-voltage transistor Mhv3. The third high-voltage transistor Mhv3 clamps the voltage at the drain of the transistor M6 so that it does not fall below a clamp level Vbp+Vgs.

[0043] The fourth transistor M4 is a P-channel MOSFET, with its source connected to the output node 261 and its gate connected to one (IN1) of the first input terminal IN1 and the second input terminal IN2.

[0044] A constant voltage circuit 264 that generates an appropriate potential difference is provided between the drain of the fourth transistor M4 and the ground line 204. For example, the constant voltage circuit 264 may include an N-channel MOSFET with its gate and drain wired together. The configuration of the constant voltage circuit 264 is not limited, and it may be composed of a Zener diode, a diode, a transistor, a resistor, or a combination of these.

[0045] The above is the configuration of input stage 200. Next, the operation will be explained.

[0046] 5 is a diagram showing voltages at several nodes of the input stage 200. Vd represents the drain voltages Vd1 and Vd2 of the first transistor M1 and the second transistor M2. Vs represents the source voltages of the first transistor M1 and the second transistor M2. Vbn2 is the bias voltage generated by the bias voltage source 260.

[0047] The bias voltage Vbn2 generated by the bias voltage source 260 is expressed by equation (1). Vbn2=VIN+Vgs4

[0048] The drain voltages Vd1 and Vd2 of the first transistor M1 and the second transistor M2 are expressed by equations (2) and (3), and vary with the input voltage VIN. Vd1=VIN+Vgs4-Vgsn1 …(2) Vd2=VIN+Vgs4-Vgsn2 …(3)

[0049] On the other hand, the source voltage Vs of the first transistor M1 and the second transistor M2 is expressed by the formula (4). Vs = VIN - Vgs1 = VIN - Vgs2 … (4) This becomes:

[0050] Therefore, the drain-source voltages Vds1 and Vds2 of the first transistor M1 and the second transistor M2 are expressed by the equations (5) and (6). Vds1=Vd1-Vs=VIN+Vgs4-Vgsn1-(VIN-Vgs1) =Vgs4-Vgsn1+Vgs1 …(5) Vds2=Vd2-Vs=VIN+Vgs4-Vgsn2-(VIN-Vgs2) =Vgs4-Vgsn2+Vgs2 …(6) From equations (5) and (6), it can be seen that the drain-source voltages Vds1 and Vds2 of the first transistor M1 and the second transistor M2 are constant regardless of the input voltage VIN and the bias voltage Vbn2.

[0051] 6 is a diagram showing the input / output characteristics of a voltage follower configured with an operational amplifier according to the embodiment. The solid line (i) represents the ideal characteristics, and the dashed line (ii) represents the input / output characteristics according to the embodiment. When the bias voltage Vbn2 is fixed, linearity deteriorates in the region where V > 4 V, but in this embodiment, high linearity is maintained up to V = 6 V.

[0052] 7 is a diagram showing the input voltage dependency of the offset voltage of an operational amplifier. In addition to the offset voltage of the operational amplifier according to the embodiment (solid line), Fig. 7 also shows the offset voltage of a comparative technology (dashed line). In the embodiment, an offset voltage of 15 μV or less can be achieved over a wide input voltage range, allowing the input voltage range on the power supply rail side to be expanded.

[0053] Fig. 8 is a circuit diagram of an input stage 200A according to a modified example. A bias voltage source 260A includes a sixth transistor M6 in addition to the bias voltage source 260 of Fig. 4. The sixth transistor M6 is a normal voltage P-channel MOSFET connected in parallel to the fourth transistor M4, and has its gate connected to the second input terminal IN2.

[0054] Considering the general use of operational amplifiers, an imaginary short exists in the steady state, so the input voltage VIN at the first input terminal IN1 and the second input terminal IN2 are equal. Therefore, for some applications, the configuration shown in Figure 4, which monitors only the voltage at either the first input terminal IN1 or the second input terminal IN2, works well.

[0055] On the other hand, in a transient state, a situation may occur in which the voltage VIN1 at the first input terminal IN1 and the voltage VIN2 at the second input terminal IN2 differ. The bias voltage source 260A in Fig. 8 can generate the bias voltage Vbn2 in conjunction with the higher of the two input voltages VIN1, VIN2.

[0056] In the explanation so far, the case where the input differential pair 210 is an N-channel MOSFET has been described, but the technology according to the present disclosure is also applicable to an operational amplifier 100 having an input differential pair 210 of P-channel MOSFETs.

[0057] 9 is a circuit diagram of an input stage 200B according to a modified example. The input stage 200B has a configuration in which the top and bottom (power supply line VDD and ground line VSS) of the input stage 200 in FIG. 4 are inverted, and the P-channel is changed to an N-channel and the N-channel is changed to a P-channel.

[0058] The embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0059] (Addendum) The present specification discloses the following techniques.

[0060] (Item 1) 1. An operational amplifier having an input stage and an output stage, The input stage comprises: a first input terminal; a second input terminal; an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal and a second transistor of a first polarity whose gate is connected to the second input terminal; a tail current source including a third transistor of a first polarity, the drain of which is connected to the input differential pair; a first high-voltage transistor of the first polarity, the source of which is connected to the drain of the first transistor and the gate of which is applied with a bias voltage; a second high-voltage transistor of the first polarity, the source of which is connected to the drain of the second transistor and the gate of which is applied with the bias voltage; an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor; a bias circuit that outputs the bias voltage that is linked to an input voltage generated at one of the first input terminal and the second input terminal; An operational amplifier comprising:

[0061] (Item 2) The bias circuit an output node connected to a gate of the first high-voltage transistor and a gate of the second high-voltage transistor; a current source; a third high-voltage transistor of a second polarity, the source of which is connected to the current source, the drain of which is connected to the output node, and the gate of which is applied with a second bias voltage; a fourth transistor of a second polarity, the fourth transistor having a source connected to the output node and a gate connected to one of the first input terminal and the second input terminal; Item 1. The operational amplifier of item 1, comprising:

[0062] (Item 3) 3. The operational amplifier of claim 2, wherein the bias circuit further includes a fifth transistor having a gate and a drain connected to the drain of the fourth transistor.

[0063] (Item 4) 4. The operational amplifier of item 2 or 3, wherein the bias circuit further includes a fifth transistor of a second polarity, the fifth transistor having a source connected to the output node and a gate connected to the other of the first input terminal and the second input terminal.

[0064] (Item 5) 5. The operational amplifier according to any one of items 1 to 4, which is monolithically integrated on a single semiconductor substrate. [Explanation of symbols]

[0065] 100 Op-Amps 200 input stages 300 output stage 202 Power Line 204 Ground Line Mhv1 First high voltage transistor Mhv2 Second high voltage transistor Mhv3 3rd high voltage transistor M1 First transistor M2 Second transistor M3 Third transistor M4 4th transistor M5 Fifth transistor M6 6th transistor 210 Input differential pair 220 Tail Current Source 230 Active Load CS11 current source 260 Bias Voltage Source

Claims

1. 1. An operational amplifier having an input stage and an output stage, The input stage comprises: a first input terminal; a second input terminal; an input differential pair including a first transistor of a first polarity whose gate is connected to the first input terminal and a second transistor of a first polarity whose gate is connected to the second input terminal; a tail current source including a third transistor of a first polarity, the drain of which is connected to the input differential pair; a first high-voltage transistor of the first polarity, the source of which is connected to the drain of the first transistor and the gate of which is applied with a bias voltage; a second high-voltage transistor of the first polarity, the source of which is connected to the drain of the second transistor and the gate of which is applied with the bias voltage; an active load connected to the drain of the first high-voltage transistor and the drain of the second high-voltage transistor; a bias circuit that outputs the bias voltage that is linked to an input voltage generated at at least one of the first input terminal and the second input terminal; An operational amplifier comprising:

2. The bias circuit an output node connected to a gate of the first high-voltage transistor and a gate of the second high-voltage transistor; a current source; a third high-voltage transistor of a second polarity, the source of which is connected to the current source, the drain of which is connected to the output node, and the gate of which is applied with a second bias voltage; a fourth transistor of a second polarity, the fourth transistor having a source connected to the output node and a gate connected to one of the first input terminal and the second input terminal; 10. The operational amplifier of claim 1, comprising:

3. 3. The operational amplifier of claim 2, wherein the bias circuit further includes a fifth transistor having a gate and a drain connected to the drain of the fourth transistor.

4. 4. The operational amplifier according to claim 2, wherein the bias circuit further includes a sixth transistor of a second polarity, the sixth transistor having a source connected to the output node and a gate connected to the other of the first input terminal and the second input terminal.

5. 4. The operational amplifier according to claim 1, which is monolithically integrated on a single semiconductor substrate.

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