Electronic Devices

Abstract

The present disclosure provides an electronic device having a peripheral area. The electronic device includes a first substrate, a second substrate, a first support member, a planar layer, and an alignment layer. The second substrate is arranged opposite to the first substrate. The first support member is arranged in the peripheral area and between the first substrate and the second substrate. The planar layer is arranged on the first substrate and has a first portion and an opening. The first portion is arranged in the opening, and the first support member and the first portion overlap in the normal direction of the first substrate. The alignment layer is arranged on the planar layer. The alignment layer on the first portion has a first thickness. The alignment layer in the opening has a second thickness. The first thickness is greater than or equal to zero and less than the second thickness.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device with an opening disposed in a peripheral area. Background Art

[0002] Electronic products have become an indispensable necessity in modern society. With the booming development of such electronic products, consumers have high expectations for the quality, function or price of these products.

[0003] Therefore, electronic products need to be improved, such as improving the reliability of electronic devices, but there are still some problems that need to be solved. Summary of the invention

[0004] The present disclosure is directed to an electronic device with better reliability or display quality.

[0005] According to an embodiment of the present disclosure, an electronic device has a peripheral area, including a first substrate, a second substrate, a first support, a planar layer, and an alignment layer. The second substrate is arranged opposite to the first substrate. The first support is arranged in the peripheral area and is arranged between the first substrate and the second substrate. The planar layer is arranged on the first substrate and has a first portion and an opening. The first portion is arranged in the opening, and the first support and the first portion overlap in the normal direction of the first substrate. The alignment layer is arranged on the planar layer. The alignment layer on the first portion has a first thickness. The alignment layer in the opening has a second thickness. The first thickness is greater than or equal to zero and less than the second thickness.

[0006] In summary, the electronic device of the disclosed embodiment can improve the structural reliability, reliability, performance or display quality of the electronic device by configuring the planar layer with the opening and the first portion located in the opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0008] Figure 1 A schematic top view of an electronic device according to an embodiment of the present disclosure;

[0009] Figure 2 for Figure 1 A schematic cross-sectional view of an electronic device taken along section line AA' and section line BB';

[0010] Figure 3 A top view schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0011] Figure 4 for Figure 3A schematic cross-sectional view of an electronic device taken along section line AA' and section line CC'. DETAILED DESCRIPTION

[0012] A structure (or layer, component, substrate) described in the present disclosure is located on another structure (or layer, component, substrate), which may mean that the two structures are adjacent and directly connected, or may mean that the two structures are adjacent but not directly connected, and the indirect connection means that there is at least one intermediate structure (or intermediate layer, intermediate component, intermediate substrate, intermediate interval) between the two structures, the lower surface of one structure is adjacent to or directly connected to the upper surface of the intermediate structure, and the upper surface of the other structure is adjacent to or directly connected to the lower surface of the intermediate structure, and the intermediate structure can be composed of a single-layer or multi-layer physical structure or non-physical structure, without limitation. In the present disclosure, when a certain structure is arranged "on" another structure, it may mean that the certain structure is "directly" on the other structure, or that the certain structure is "indirectly" on the other structure, that is, at least one structure is sandwiched between the certain structure and the other structure.

[0013] The electrical connection or coupling described in the present disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there is a switch, diode, capacitor, inductor, resistor, other suitable components, or a combination of the above components between the endpoints of the components on the two circuits, but it is not limited to these.

[0014] In the present disclosure, the thickness of each layer can be measured using a scanning electron microscope (SEM), a thin film thickness profiler (α-step), an ellipsometer, or other suitable methods. In detail, in some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image of the structure, and the thickness of each layer in the image can be measured. The above thickness can be the maximum thickness in the normal direction of any cross-sectional image. In other words, it can be the maximum thickness in a local area of ​​the electronic device. In addition, the above method of using a scanning electron microscope to measure the thickness includes disassembling the electronic device to obtain a single substrate and then using a scanning electron microscope to measure the layer thickness. In the present disclosure, the thickness can be measured using an optical microscope (OM), a scanning electron microscope, or other suitable methods.

[0015] The display device disclosed in the present invention can be applied to various electronic devices. The electronic device may include a display device, an antenna device, a sensing device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include a liquid crystal or a light emitting diode; the light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro LED or a quantum dot light emitting diode (QD, which may be, for example, QLED, QDLED), fluorescence, phosphorescence, or other suitable materials, and the materials may be arranged and combined in any manner, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The splicing device may, for example, be a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any arrangement or combination of the aforementioned, but is not limited thereto. The following text will use a display device as an electronic device or a splicing device to illustrate the contents of the present disclosure, but the present disclosure is not limited thereto.

[0016] In the present disclosure, the various embodiments described below may be mixed and matched for use without departing from the spirit and scope of the present disclosure. For example, some features of one embodiment may be combined with some features of another embodiment to form another embodiment.

[0017] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Figure 1 This is a top view of an electronic device according to an embodiment of the present disclosure. For the sake of clarity and convenience of description, Figure 1 Several elements are omitted from illustration. Figure 2 for Figure 1 Schematic diagram of a cross section of an electronic device along section line AA' and section line BB'. For the sake of clarity and convenience of description, Figure 2 Some components are omitted from the illustration. Figure 1 as well as Figure 2, the electronic device 10 includes a first substrate 100, a second substrate 200, a support member (including a first support member PS1), a planar layer 130 and an alignment layer 150. In the present embodiment, the second substrate 200 is disposed opposite to the first substrate 100, and the first support member PS1 is disposed between the first substrate 100 and the second substrate 200. The planar layer 130 is disposed on the first substrate 100, and has a first portion 131 and an opening 133. The first portion 131 of the planar layer 130 is located in the opening 133 in the normal direction N, and the first support member PS1 and the first portion 131 overlap in the normal direction N of the first substrate 100. The alignment layer 150 is disposed on the planar layer 130. In the present embodiment, the electronic device 10 may further include a plurality of conductive layers (including a first conductive layer M1 and a second conductive layer M2 (indicated at Figure 4 )), insulating layer 140, packaging element 160, light shielding layer BM, filling layer 220 (overcoat layer, OC) or display medium layer DM (marked on Figure 4 ). The insulating layer 140 is disposed on the flat layer 130. The packaging element 160 is disposed on the insulating layer 140 to surround the support. The light shielding layer BM is disposed on the second substrate 200, and the leveling layer 220 is disposed on the light shielding layer BM, so that the light shielding layer BM is located between the leveling layer 220 and the second substrate 200. The first support member PS1 can be disposed on the leveling layer 220. In addition, the light shielding layer BM is disposed between the second substrate 200 and the first support member PS1. In this embodiment, the opening 133 of the flat layer 130 can form a accommodating space, so that the area of ​​the flat layer 130 contacting the packaging element 160 is increased. In addition, the alignment layer 150 can be formed in the accommodating space of the opening 133 to increase the contact area between the alignment layer 150 and the flat layer 130. In this way, the adhesion between the packaging element 160 and the flat layer 130 and / or the alignment layer 150 and the flat layer 130 can be improved to increase the reliability of the electronic device 10. In addition, the accommodating space formed by the opening 133 can buffer the lateral stress of the insulating layer 140 squeezed and / or pushed by the support member, the risk of the insulating layer 140 being squeezed and broken by the support member can be reduced, and the water vapor passing through the broken insulating layer 140 to affect the flat layer 130 or the conductive layer can be reduced, thereby improving the reliability and / or performance of the electronic device 10.

[0019] In this embodiment, the electronic device 10 includes a first substrate 100, a second substrate 200 disposed opposite to the first substrate 100, and a plurality of support members disposed between the first substrate 100 and the second substrate 200. The first substrate 100 or the second substrate 200 may be a transparent substrate, such as a transparent plastic substrate or a glass substrate. For example, the material of the first substrate 100 or the second substrate 200 may include glass, quartz, sapphire, ceramic, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), fiberglass, ceramic, other suitable substrate materials, or a combination thereof, but not limited thereto. The material of the support member includes a photoresist material or other suitable material. The material of the support member may also include an inorganic material, an organic material, other suitable materials, or a combination thereof, but not limited thereto. The inorganic material may be, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials. The organic material mentioned above is, for example (but not limited to): a polymer material such as polyimide resin, epoxy resin or acrylic resin.

[0020] like Figure 1 and Figure 2 As described above, the electronic device 10 of this embodiment has a peripheral area 12. The peripheral area 12 can be defined as being disposed at the edge of the electronic device 10 and surrounding the working area (shown in FIG. Figure 3 and Figure 4 ), but the present embodiment is not limited thereto. In the present embodiment, the support member includes a plurality of first support members PS1 disposed on the first substrate 100 and / or the second substrate 200, and these first support members PS1 are disposed in the peripheral area 12, but the present embodiment is not limited thereto. In some embodiments, the support member may also be disposed in the working area. In the present embodiment, the support member may be disposed in the peripheral area 12 in an array manner or other suitable manner, but the present embodiment is not limited thereto.

[0021] In this embodiment, the first conductive layer M1 may be disposed on the first substrate 100, and then a plurality of traces, a plurality of electrodes or a plurality of pads may be formed through a patterning process. Figure 1 and Figure 2As shown, on the first substrate 100, the first conductive layer M1 can form a scan line, a gate line (not shown) or a gate G at least in the peripheral area 12, but not limited thereto. In some embodiments, the first conductive layer M1 can be disposed on the first substrate 100 and patterned at any position of the first substrate 100 as required. In the present embodiment, the material of the first conductive layer M1 includes a metal material, such as aluminum, molybdenum, copper, nickel, titanium, silver, other suitable metals, alloys of the above metals, or a combination of the above metals, but not limited thereto. In the present embodiment, the patterning process of the first conductive layer M1 includes photolithography, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or screen printing, but the present embodiment is not limited thereto.

[0022] The gate insulating layer 110 is disposed on the first substrate 100 and partially covers the first conductive layer M1. The material of the gate insulating layer 110 includes inorganic materials, organic materials, other suitable materials or a combination of the above materials, but is not limited thereto. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride or a stacked layer of at least two of the above materials. The above organic materials are, for example (but not limited to): polymer materials such as polyimide resins, epoxy resins or acrylic resins.

[0023] In this embodiment, a plurality of active devices T may be disposed on the first substrate 100. The active device T includes a gate G, a semiconductor layer CH, a source S, and a drain D. Figure 1 and Figure 2 As shown, the semiconductor layer CH is disposed on the gate insulating layer 110, and the source S and the drain D are electrically in contact with the semiconductor layer CH. The dielectric layer 120 is disposed on the gate insulating layer 110 and partially covers the semiconductor layer CH, the source S and the drain D, but the present embodiment is not limited thereto. The active device T includes a thin film transistor (TFT), such as a top gate thin film transistor, a bottom gate thin film transistor or other suitable thin film transistor, but not limited thereto. In the present embodiment, the gate G belongs to the first conductive layer M1, and the source S and the drain D belong to the second conductive layer M2. The material of the second conductive layer M2 may include molybdenum, aluminum, copper, nickel, titanium, silver, other suitable metals, alloys of the above metals, or combinations of the above metals, but not limited thereto. The semiconductor layer CH may include amorphous silicon, low temperature polysilicon, or metal oxide, but not limited thereto. In some embodiments, different active devices T may include different semiconductor layer CH materials, but not limited thereto.

[0024] In the present embodiment, the second conductive layer M2 may be disposed on the gate insulating layer 110, and may also be patterned to form a plurality of signal traces or a plurality of pads. The plurality of signal traces may be, for example, a data line (not shown), a common electrode line (not shown), a power line (not shown), a ground line (not shown) or other suitable lines, but the present embodiment is not limited thereto. In the present embodiment, a plurality of active elements T may be electrically connected to the first conductive layer M1 and the second conductive layer M2 in the gate insulating layer 110 and the dielectric layer 120 and applied as an active element array or a gate drive circuit (gate on array, GOA), but the present embodiment is not limited thereto.

[0025] The dielectric layer 120 is disposed on the gate insulating layer 110 and partially covers the second conductive layer M2. The material of the dielectric layer 120 includes inorganic materials, organic materials, other suitable materials or a combination of the above materials, but is not limited thereto. The above inorganic materials are, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride or a stacked layer of at least two of the above materials. The above organic materials are, for example (but not limited to): polymer materials such as polyimide resins, epoxy resins or acrylic resins.

[0026] The planar layer 130 is disposed on the dielectric layer 120. In the present embodiment, the planar layer 130 is, for example, disposed entirely on the dielectric layer 120, and is partially located in the peripheral area 12, and has a distance (not indicated) from the outer edge of the electronic device 10. In other words, the planar layer 130 is not flush with the edge of the first substrate 100. From another perspective, the planar layer 130 has a spacing distance from the edge of the first substrate 100. The planar layer 130 overlaps the first conductive layer M1, the second conductive layer M2 and / or a plurality of active components T in the normal direction N of the first substrate 100. The material of the planar layer 130 includes an organic material, but the present embodiment is not limited thereto. For example, the material of the planar layer 130 includes materials such as perfluoroalkoxy polymer resin (PFA), polymer film on array (PFA), fluoroelastomers, etc., but is not limited thereto. In some embodiments, the material of the planar layer 130 may also include inorganic materials, other suitable materials, or a combination of the above materials, but is not limited thereto.

[0027] In the present embodiment, the thickness of the planar layer 130 is, for example, 0.1 μm to 5 μm (0.1 μm ≤ thickness ≤ 5 μm), or 1.5 μm to 2.5 μm (1.5 μm ≤ thickness ≤ 2.5 μm), but the present disclosure is not limited thereto. In the present embodiment, the thickness of the planar layer 130 can be defined as the maximum thickness of the planar layer 130 in the normal direction N of the first substrate 100 after the cleavage. Under the above configuration, the planar layer 130 can have a sufficient thickness, so that the opening 133 of the peripheral region 12 can also have a sufficient thickness, so that the subsequent alignment layer 150 can flow into the opening 133 during the manufacturing process, so that the thickness of the alignment layer 151 on the planar layer 130 is reduced, and the thickness of the alignment layer 153 in the opening 133 is increased. The increase in the thickness of the alignment layer 153 can increase the anchoring energy of its alignment. In addition, the thickness of the alignment layer 151 on the first portion 131 is reduced, which can reduce the fragments that may be generated in subsequent processes, and can improve the reliability or performance of the electronic device 10, or improve the display quality of the electronic device 10.

[0028] The insulating layer 140 is disposed on the planar layer 130. In the present embodiment, the insulating layer 140 is, for example, disposed entirely on the first substrate 100 and partially covers the planar layer 130, and is partially located in the peripheral area 12. The material of the insulating layer 140 includes an inorganic material. The above-mentioned inorganic material is, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials. In some embodiments, the material of the insulating layer 140 also includes an organic material, other suitable materials, or a combination of the above-mentioned materials, but is not limited thereto. The above-mentioned organic material is, for example (but not limited to): a polymer material such as a polyimide resin, an epoxy resin, or an acrylic resin. In the present embodiment, the insulating layer 140 is an inorganic material and the planar layer 130 is an organic material, but is not limited thereto.

[0029] In the present embodiment, the thickness of the insulating layer 140 is, for example, 0.1 micrometer to 0.8 micrometer (0.1 micrometer ≤ thickness ≤ 0.8 micrometer), or 0.25 micrometer to 0.75 micrometer (0.25 micrometer ≤ thickness ≤ 0.75 micrometer), but the present disclosure is not limited thereto. In the present embodiment, the thickness of the insulating layer 140 can be defined as the maximum thickness of the insulating layer 140 in the normal direction N of the first substrate 100 after the splitting. It is worth noting that the thickness of the planar layer 130 divided by the thickness of the insulating layer 140 is greater than or equal to 1.5 and less than or equal to In the above configuration, the insulating layer 140 can protect the planar layer 130 from being affected by moisture, or the planar layer 130 can have a sufficient thickness to make the surface of the planar layer 130 contacting the insulating layer 140 planar, so as to improve the structural reliability of the electronic device 10 .

[0030] The alignment layer 150 is disposed on the insulating layer 140 on the planar layer 130. In the present embodiment, the alignment layer 150 is disposed on the first substrate 100, and a portion of the alignment layer 150 is located in the peripheral area 12. The alignment layer 150 may overlap a portion of the planar layer 130 or the insulating layer 140 in the normal direction N of the first substrate 100. From another perspective, the insulating layer 140 is disposed between the planar layer 130 and the alignment layer 150, but the present embodiment is not limited thereto. The material of the alignment layer 150 includes an organic material, such as polyimide, but the present disclosure is not limited thereto. In some embodiments, the material of the alignment layer 150 may also include an inorganic material. The above-mentioned inorganic material is, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above-mentioned materials.

[0031] In this embodiment, the thickness of the alignment layer 150 is, for example, 300 angstroms. The thickness of the alignment layer 150 may be 300 angstroms to 1500 angstroms (300 angstroms ≤ thickness ≤ 1500 angstroms), or 500 angstroms to 1200 angstroms (500 angstroms ≤ thickness ≤ 1200 angstroms), but the disclosure is not limited thereto. In the present embodiment, the thickness of the alignment layer 150 may be defined as the maximum thickness of the alignment layer 150 in the normal direction N of the first substrate 100 after the splitting.

[0032] The light shielding layer BM is disposed on the second substrate 200. In the present embodiment, the light shielding layer BM may be partially located in the peripheral area 12. The light shielding layer BM is, for example, a black matrix, but the present disclosure is not limited thereto. The light shielding layer BM may be patterned to have a plurality of patterned openings (not shown) corresponding to a plurality of pixel areas (not shown). For example, the light shielding layer BM may overlap the patterned wiring of the first conductive layer M1 (not shown) or the patterned signal wiring of the second conductive layer M2 (not shown) in the normal direction N of the first substrate 100, but the present disclosure is not limited thereto.

[0033] The filling layer 220 is disposed on the light shielding layer BM. In this embodiment, the filling layer 220 can be disposed on the light shielding layer BM and partially located in the peripheral area 12. The filling layer 220 is, for example, a transparent filling layer, but the present disclosure is not limited thereto.

[0034] It is worth noting that the light shielding layer BM of the present embodiment has a groove OP in the peripheral area 12, and the groove OP can surround the electronic device 10 in the peripheral area 12. The groove OP does not overlap with the planar layer 130 in the normal direction of the first substrate 100. In other words, the groove OP of the light shielding layer BM is located in the area where the light shielding layer BM does not overlap the planar layer 130. In the present embodiment, there is a distance K between the groove OP and the outer edge 11 of the electronic device 10, and the distance K can be, for example, 10 microns to 150 microns (10 microns ≤ distance K ≤ 150 microns), or 50 microns to 100 microns (50 microns ≤ distance K ≤ 100 microns). The above distance K can be defined as the shortest distance between the outer edge 11 of the electronic device 10 and the outer edge 211 of the groove OP in the local area in the normal direction N perpendicular to the first substrate 100. The width W of the groove OP can be 10 microns to 100 microns (10 microns ≤ width W ≤ 100 microns), or 15 microns to 25 microns (15 microns ≤ width W ≤ 25 microns). The width W of the groove OP may be defined as the maximum width of the groove OP in a local area in a normal direction N perpendicular to the first substrate 100 .

[0035] In the above configuration, the filling layer 220 can be filled into the groove OP to increase the contact area or adhesion strength between the filling layer 220 and the light shielding layer BM, thereby improving the reliability or performance of the electronic device 10 or improving the display quality of the electronic device 10 .

[0036] A plurality of support members are disposed on one of the first substrate 100 or the second substrate 200. In the present embodiment, the plurality of support members include a plurality of first support members PS1 disposed in the peripheral region 12. The first support member PS1 is disposed on the fill layer 220 on the second substrate 200 and is opposed to the flat layer 130 on the first substrate 100. Specifically, the first support member PS1 is opposed to the surface of the insulating layer 140 on the flat layer 130, but the present disclosure is not limited thereto. In some embodiments, the first support member PS1 may not contact the insulating layer 140. In some embodiments, the first support member PS1 may also contact the alignment layer 151. Due to the provision of the opening 133, the thickness of the alignment layer 151 on the first portion 131 of the flat layer 130 can be reduced, reducing the contact of the first support member PS1 with the alignment layer 151, reducing the fragmentation of the alignment layer 151 that may be caused by extrusion during contact, and improving the reliability or performance of the electronic device 10, or improving the display quality of the electronic device 10.

[0037] In the present embodiment, the electronic device 10 further includes an alignment layer 250. The alignment layer 250 may be disposed on the fill layer 220 and surround the first support member PS1. That is, the alignment layer 250 may be in direct contact with the first support member PS1, and in the normal direction N1 of the first substrate 100, the alignment layer 250 is not located between the first support member PS1 and the fill layer 220, but the present embodiment is not limited thereto. In some embodiments, the alignment layer 250 may be in direct contact with the side wall of the first support member PS1. In some embodiments, the alignment layer 250 may be in direct contact with the top surface of the first support member PS1. In other embodiments, the alignment layer 250 may not contact the first support member PS1. The material of the alignment layer 250 may be the same as or different from that of the alignment layer 150, including organic materials, such as polyimide, but the present disclosure is not limited thereto. In some embodiments, the material of the alignment layer 250 may also include inorganic materials. The inorganic material is, for example (but not limited to): silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials.

[0038] The packaging component 160 is disposed in the peripheral area 12 and is located between the first substrate 100 and the second substrate 200. In the present embodiment, the packaging component 160 is, for example, a sealant, which is disposed around the outer edge of the electronic device 10 and overlaps a portion of the peripheral area 12. For example, the packaging component 160 may overlap a portion of the wiring of the first conductive layer M1, a portion of the signal wiring of the second conductive layer M2, and the active component T in the normal direction N of the first substrate 100. The material of the packaging component 160 includes epoxy resin, polymethylmethacrylate (PMMA), light-curing adhesive, heat-curing adhesive, light-heat-curing adhesive, other suitable materials, or a combination of the above materials, but the present disclosure is not limited thereto.

[0039] The electronic device 10 of the present embodiment is a technology that applies the first support member PS1 to the packaging element 160. Under the above-mentioned setting, the packaging element 160 can directly contact the alignment layer 150 and the alignment layer 250, and the packaging element 160 surrounds the first support member PS1. In addition, the electronic device 10 of the present embodiment also includes a flat layer 130 disposed in the peripheral area 12, and the flat layer 130 partially overlaps the packaging element 160 in the normal direction N of the first substrate 100. Since the flat layer 130 can cover the first conductive layer M1, the second conductive layer M2 and / or the active element T in the peripheral area 12, the display medium layer (shown in FIG. 1 ) can be maintained. Figure 4 ) thickness consistency, so that the overall thickness of the electronic device 10 is consistent or similar, improving the structural reliability or performance. In addition, the planar layer 130 can also protect the wiring and / or active components T in the peripheral area 12, improving the display quality of the electronic device 10.

[0040] It is worth noting that the planar layer 130 has a first portion 131 and an opening 133. Figure 1 and Figure 2 As described above, the planar layer 130 may be patterned to form a plurality of openings 133 and openings 133A to surround a plurality of corresponding first portions 131. In other words, the first portions 131 may be disposed in the openings 133 and / or openings 133A to form, for example, an island shape. Figure 1 It can be known that the first portion 131 may be circular in the normal direction N of the first substrate 100 (for example, in the top view direction), and the opening 133 and the opening 133A surround the first portion 131 and have an arc edge in the normal direction N of the first substrate 100, for example, an arc shape, but the present embodiment is not limited thereto. In some embodiments, the first portion 131, the opening 133 and / or the opening 133A may also be elliptical, rectangular, triangular, irregular or other suitable shapes in the top view, but are not limited thereto. In the present embodiment, the distance W1 between the opening 133 and the opening 133A may be 5 microns to 50 microns (5 microns ≤ distance W1 ≤ 50 microns). The width W3 of the first portion 131 is 15 microns to 50 microns (15 microns ≤ width W3 ≤ 50 microns), or 25 microns to 30 microns (25 microns ≤ width W3 ≤ 30 microns). The distance W1 of the openings 133 and 133A may be defined as the minimum distance between the opening sidewalls of the openings 133 and 133A and the first portion 131 in the normal direction N perpendicular to the first substrate 100. The width W3 of the first portion 131 may be defined as the maximum width of the first portion 131 in the normal direction N perpendicular to the first substrate 100.

[0041] In the present embodiment, the opening 133 and the opening 133A are, for example, grooves formed by the planar layer 130 in the normal direction N of the first substrate 100. The opening 133 may penetrate the planar layer 130 in the normal direction N of the first substrate 100, but the present embodiment is not limited thereto. The insulating layer 140 may cover the planar layer 130 and fill the opening 133 and the opening 133A and / or cover the top surface and / or sidewall of the first portion 131 in the opening 133 and the opening 133A. The sidewall of the first portion 131 is not parallel to the normal direction N, but has an inclination angle. When viewed from a side direction, the first portion 131 is formed to be roughly trapezoidal in shape, which can increase the surface area of ​​the first portion 131. This inclination angle can allow the alignment layer to flow into the openings 133 and 133A in the subsequent process of making the alignment layer, so that the thickness of the alignment layer 151 on the first portion 131 is reduced, and the thickness of the alignment layer 153 in the openings 133 and 133A is increased, but not limited to this. In this way, the flat layer 130 can increase the surface in contact with the insulating layer 140 through the openings 133 and 133A, thereby increasing the adhesion or reliability between the flat layer 130 and the insulating layer 140.

[0042] In addition, the alignment layer 150 formed on the insulating layer 140 may partially overlap the first portion 131, the opening 133, the first portion 131, and the flat layer 130 outside the opening 133 in the normal direction N of the first substrate 100. For example, in the process of forming the alignment layer 150, the alignment layer 150 adjacent to the outer edge of the opening 133 may slide into the opening 133 along the surface of the insulating layer 140 and be formed in the accommodation space of the opening 133. In this way, the alignment layer 150 may include the alignment layer 151 overlapping the first portion 131 (for example, on the first portion 131) in the normal direction N of the first substrate 100 and the alignment layer 153 located in the opening 133. Under the above configuration, the surface area of ​​the alignment layer 150 may be increased. In this way, the area in which the package component 160 directly contacts the alignment layer 150 (including the alignment layer 151 on the first portion 121 and the alignment layer 153 in the opening 133) may be increased. Thereby, the adhesion or reliability between the packaging component 160 and the alignment layer 150 can be increased.

[0043] In the present embodiment, the alignment layer 151 on the first portion 131 has a first thickness H1, and the alignment layer 153 in the opening 133 has a second thickness H2. The first thickness H1 is greater than or equal to zero, and the first thickness H1 is less than the second thickness H2. For example, the first thickness H1 is greater than or equal to 0 angstroms and less than or equal to 500 angstroms, but the disclosure is not limited thereto. The second thickness is greater than 0 angstroms and less than or equal to 5000 angstroms. In some embodiments, the second thickness H2 may also be greater than or equal to 500 angstroms and less than or equal to 1200 angstroms, but the disclosure is not limited thereto. In the present embodiment, the first thickness H1 may be defined as the minimum thickness of the alignment layer 151 substantially located in the center area of ​​the first portion 131 in the normal direction N of the first substrate 100. The above minimum thickness may be defined as the minimum thickness in any cross-sectional image of the structure obtained by a scanning electron microscope. The second thickness H2 may be defined as the maximum thickness of the alignment layer 152 located in the opening 133 in the normal direction N of the first substrate 100.

[0044] In addition, the first support member PS1 overlaps the first portion 131 in the normal direction N of the first substrate 100, that is, the first support member PS1 is opposite to the first portion 131. In the present embodiment, the width W2 of the first support member PS1 is smaller than the width W3 of the first portion 131. In the present embodiment, the width W2 may be defined as the maximum width of the first support member PS1 in the normal direction N perpendicular to the first substrate 100. The width W3 may be defined as the maximum width of the first portion 131 in the normal direction N perpendicular to the first substrate 100. The width W2 of the first support member PS1 is 5 micrometers to 40 micrometers (5 micrometers ≤ width W2 ≤ 40 micrometers), or 9.5 micrometers to 15 micrometers (9.5 micrometers ≤ width W2 ≤ 15 micrometers), but the present embodiment is not limited thereto.

[0045] In some embodiments, the alignment layer 150 in the peripheral region 12 is not aligned with the outer edge of the first substrate 100, and the alignment layer 250 is not aligned with the outer edge of the second substrate 200, thereby exposing a portion of the inorganic material layer, such as (but not limited to) the insulating layer 140, the dielectric layer 120, the gate insulating layer 110, the first substrate 100 or the second substrate 200. In this way, the packaging component 160 can directly contact the inorganic material layer, which can increase the structural reliability or display quality of the electronic device 10.

[0046] In this embodiment, if Figure 2As shown, the first portion 131 located in the opening 133 can overlap with the first conductive layer M1 in the normal direction N of the first substrate 100. The first support member PS1 opposite to the first portion 131 can overlap with the first conductive layer M1 in the normal direction N of the first substrate 100, but the present embodiment is not limited thereto. In some embodiments, the flat layer 130 that does not overlap with the first support member PS1 can also overlap with the first conductive layer M1, the second wire layer M2 or the active element T in the normal direction N of the first substrate 100, but the present embodiment is not limited thereto. In the present embodiment, the insulating layer 140 is disposed between the first support member PS1 and the flat layer 130. In this way, when the first support member PS1 directly contacts and presses the insulating layer 140, the accommodation space formed by the opening 133 of the flat layer 130 can buffer the lateral stress of the insulating layer 140 pressed and / or pushed by the first support member PS1. Specifically, compared to the flat layer 130, the harder insulating layer 140 can move laterally through the opening 133 on the softer flat layer 130 to buffer the influence of stress on the insulating layer 140. Therefore, the risk of the insulating layer 140 being squeezed and broken by the first support member PS1 can be reduced. In addition, the phenomenon that moisture passes through the broken insulating layer 140 to make the flat layer 130 hygroscopic and swollen can be reduced, or the conductive layer covered by the insulating layer 140 can be reduced from being affected by moisture, thereby improving the reliability and / or performance or display quality of the electronic device 10.

[0047] In this embodiment, the package element 160 can also be filled into the opening 133. In this way, the contact area between the package element 160 and the insulating layer 140 or the package element 160 and the planar layer 130 can be increased. Thereby, the adhesion between the package element 160 and the insulating layer 140 or the planar layer 130 can be improved to increase the reliability of the electronic device 10.

[0048] In some embodiments, the plurality of openings 133 may correspond to or not correspond to the support members according to user needs. In addition, since the sizes of the plurality of support members may be set according to user needs, the sizes of the plurality of openings 133 must also be designed to correspond to the sizes of the corresponding support members. In other words, the distance W1 of the openings 133 may be the same or different, and the distance W1 of the openings 133 at different positions may be the same or different, and this embodiment is not limited thereto. For example, Figure 2The distance W1 of the opening 133 shown as being located near the outer edge 11 of the electronic device 10 may be greater than or equal to the distance W1 of the opening 133A located away from the outer edge 11, but the present embodiment is not limited thereto. For example, the distance W1 of the opening 133 near the outer edge 11 may be 10 microns, and the distance W1 of the opening 133A away from the outer edge 11 may be 6 microns, but the present embodiment is not limited thereto. In this way, the opening width may be adjusted according to the design requirements of the support member or according to the requirements of the different positions of the support member to increase the adhesion between the support member and the insulating layer 140. It should be noted that for the sake of clarity and convenience of description in the drawings, Figure 2 The distances W1 between different openings 133 and openings 133A and the distances W1 between different support members are schematically shown to be consistent, but those skilled in the art should understand that as long as the distance W1 of the opening 133 can overlap the conductive layer and allow the alignment layer 150 to fill the openings 133 and openings 133A, they can be mixed and matched without departing from the spirit and scope of the present disclosure.

[0049] In the present embodiment, part of the packaging element 160 may also overlap the insulating layer 140 and / or the dielectric layer 120 in the normal direction N of the first substrate 100, but not overlap the planar layer 130. That is, the outer edge of the packaging element 160 may be located between the outer edge of the first substrate 100 and the outer edge of the planar layer 130 in the normal direction of the first substrate 100, but the present embodiment is not limited thereto. In some embodiments, the outer edge of the packaging element 160 may also be flush with the outer edge of the planar layer 130. In some embodiments, the outer edge of the packaging element 160 may also be flush with the outer edge of the first substrate 100. In addition, the groove OP of the light shielding layer BM may not overlap the packaging element 160 in the normal direction N, but the present embodiment is not limited thereto.

[0050] In short, the electronic device 10 of an embodiment of the present disclosure can be provided with a flat layer 130 in the peripheral region 12, and the flat layer 130 has a plurality of openings 133 and a first portion 131 located in the openings 133. In this way, the contact area of ​​the flat layer 130 can be increased, and the alignment layer 150 on the flat layer 130 can flow into the plurality of openings 133 during the manufacturing process, which can reduce the thickness of the alignment layer 151 on the flat layer 130, and improve the adhesion between the package component 160 and the flat layer 130, so as to improve the structural reliability of the electronic device 10. In addition, the alignment layer 150 can flow into the openings 133, so that the thickness of the alignment layer 151 on the flat layer 130 is reduced, and the possible fragments of the alignment layer 151 can be reduced. In this way, the reliability or performance of the electronic device 10 can be improved. In addition, the first thickness H1 of the alignment layer 151 on the first portion 131 is smaller than the second thickness H2 of the alignment layer 153 in the opening 133, so that the adhesion between the alignment layer 150 and the insulating layer 140 can be increased, or the first support member PS1 can contact the insulating layer 140 to increase the adhesion between the first support member PS1 and the insulating layer 140. In addition, the adhesion between the package element 160 and the alignment layer 150 can also be improved. In addition, the opening 133 can also buffer the lateral stress of the insulating layer 140 squeezed and / or pushed by the first support member PS1, so that the risk of the insulating layer 140 being squeezed and broken by the first support member PS1 can be reduced, and the phenomenon that moisture passes through the broken insulating layer 140 to make the flat layer 130 hygroscopic and swollen can be reduced, thereby improving the reliability, performance or display quality of the electronic device 10. In addition, the planar layer 130 overlaps the first conductive layer M1 , the second conductive layer M2 or the active element T in the normal direction N of the first substrate 100 , and can also protect the above elements, reduce the direct impact of the external environment on the performance of the electronic elements, and improve the performance or display quality of the electronic device 10 .

[0051] Figure 3 This is a top view of an electronic device according to another embodiment of the present disclosure. For the sake of clarity and convenience of description, Figure 3 Several elements are omitted from illustration. Figure 4 for Figure 3 Schematic diagram of the cross section of the electronic device along the section line AA' and the section line CC'. For the sake of clarity and convenience of description, Figure 4 Some components are omitted from the illustration. The electronic device 10A of this embodiment is substantially similar to Figure 1 Therefore, the same and similar components in the two embodiments are not repeated here. The difference between the present embodiment and the electronic device 10 is that the electronic device 10A further has a working area 14.

[0052] Specifically, the working area 14 may be defined as an area in which the electronic device 10A has a signal adjustable function, such as an optical signal or an electromagnetic wave signal, but the present embodiment is not limited thereto. In the present embodiment, the working area 14 may be disposed adjacent to the peripheral area 12 and surrounded by the peripheral area 12, but the present embodiment is not limited thereto. The working area 14 may include a plurality of working electrodes (not shown) (such as pixel electrodes, common electrodes) and an active component array (not shown). Please refer to Figure 3 as well as Figure 4 In the working area 14, an active device T is disposed on the first substrate 100, and a planar layer 130 is disposed on the dielectric layer 120, and partially overlaps the first conductive layer M1, the second conductive layer M2 and the active device T in the normal direction N of the first substrate 100. In this embodiment, a display medium layer DM may also be disposed between the first substrate 100 and the second substrate 200. The material of the display medium layer DM includes a liquid crystal material, an electrowetting display material, an electrophoretic display material, etc., but the embodiment is not limited thereto. The active device T is electrically connected to the pixel electrode and is used to provide a driving electric field to drive the display medium layer DM to achieve the desired signal adjustable effect.

[0053] In the present embodiment, the planar layer 130 of the electronic device 10A further has a plurality of openings 134 disposed in the working area 14. The openings 134 in the working area 14 are substantially similar to the openings 133 in the peripheral area 12, and therefore will not be repeated. The width W4 of the openings 134 in the working area 14 and the distance W1 of the openings 133 in the peripheral area 12 may be the same or different, and the present embodiment is not limited thereto. For example, the distance W1 of the openings 133 in the peripheral area 12 may be greater than or equal to the width W4 of the openings 134 in the working area 14, or the width W4 of the openings 134 in the working area 14 may be greater than or equal to the distance W1 of the openings 133 in the peripheral area 12, but the present embodiment is not limited thereto.

[0054] In this embodiment, the alignment layer 150 further includes an alignment layer 152 disposed on the first portion 132 and an alignment layer 154 disposed in the opening 134. Figure 4 As shown, part of the alignment layer on the first portion 132 may slide into the opening 134 to become the alignment layer 154 formed in the accommodation space of the opening 134 .

[0055] like Figure 3 and Figure 4As shown, the electronic device 10A further includes a second support member PS2 disposed in the working area 14, and the second support member PS2 is disposed between the first substrate 100 and the second substrate 200. For example, the second support member PS2 can be disposed on the first portion 132 in the opening 134 in the working area 14. The second support member PS2 is substantially similar to the first support member PS1, and therefore will not be repeated. The second support member PS2 overlaps the first portion 132 in the normal direction N of the first substrate 100, that is, the second support member PS2 is aligned to the first portion 132. In addition, relative to the first support member PS1, the second support member PS2 can overlap the second conductive layer M2 in the normal direction N of the first substrate 100. In some embodiments, the second support member PS2 can overlap the first conductive layer M1 and the second conductive layer M2 in the normal direction N of the first substrate 100, but is not limited thereto. In some embodiments, the second support member PS2 is aligned to the surface of the insulating layer 140 on the flat layer 130, but the present embodiment is not limited thereto. In other embodiments, the second support member PS2 may also contact the alignment layer 152. Due to the setting of the opening 134, the thickness of the alignment layer 152 on the first part 132 of the flat layer 130 can be reduced, reducing the contact between the second support member PS2 and the alignment layer 152, and reducing the broken pieces of the alignment layer 152 that may be caused by contact. In this way, the reliability or performance of the electronic device 10A can be improved, or the display quality of the electronic device 10A can be improved.

[0056] In the present embodiment, the width of the second support member PS2 is less than the width of the first portion 132. The width of the second support member PS2 is 15 microns to 50 microns (15 microns ≤ width ≤ 50 microns), or 20 microns to 30 microns (20 microns ≤ width ≤ 30 microns). The width of the second support member PS2 can be defined as the maximum width of the first support member PS2 in the normal direction N perpendicular to the first substrate 100. In addition, the width of the first support member PS1 and the width of the second support member PS2 may be the same or different. In some embodiments, the width of the first support member PS1 may be greater than or equal to the width of the second support member PS2. In other embodiments, the width of the second support member PS2 may be greater than or equal to the width of the first support member PS1, but the present disclosure is not limited thereto.

[0057] It is worth noting that the height H3 of the first support member PS1 of the present embodiment is the same as the height H4 of the second support member PS2. For example, the height H3 of the first support member PS1 is 1 micron to 6 microns (1 micron ≤ height H3 ≤ 6 microns), or 2 microns to 4 microns (2 microns ≤ height H3 ≤ 4 microns). The height H4 of the second support member PS2 is 1 micron to 6 microns (1 micron ≤ height H4 ≤ 6 microns), or 2 microns to 4 microns (2 microns ≤ height H4 ≤ 4 microns). The height H3 of the first support member PS1 can be defined as the maximum height of the first support member PS1 located on the first portion 131 in the normal direction N of the first substrate 100. The height H4 of the second support member PS2 can be defined as the maximum height of the second support member PS2 located on the first portion 132 in the normal direction N of the first substrate 100. Under the above-mentioned setting, the thickness maintained by the second support member PS2 in the working area 14 and the thickness maintained by the first support member PS1 in the peripheral area 12 can be substantially consistent or similar. As a result, the overall thickness of the electronic device 10A can be substantially consistent or similar, so as to improve structural reliability or performance, or improve the display quality of the electronic device 10A.

[0058] In summary, the electronic device of the disclosed embodiment can be provided with a flat layer in the peripheral area and / or the working area, and the flat layer has a plurality of openings and a first portion located in the openings. In this way, the contact area of ​​the flat layer can be increased, and the alignment layer on the flat layer can flow into the plurality of openings during the manufacturing process, the thickness of the alignment layer on the flat layer can be reduced, the fragments that may be generated by the alignment layer can be reduced, or the first support member and / or the second support member can contact the insulating layer to increase the adhesion between the first support member and / or the second support member and the insulating layer respectively, and improve the adhesion between the package element and the flat layer, which can improve the reliability or performance of the electronic device, or improve the overall structural reliability of the electronic device. In addition, the opening can also buffer the lateral stress of the insulating layer squeezed and / or pushed by the support member (including the first support member or the second support member), so that the risk of the insulating layer being squeezed and broken by the support member can be reduced, and the phenomenon that water vapor passes through the broken insulating layer to make the flat layer hygroscopic and swollen can be reduced, thereby improving the reliability, performance or display quality of the electronic device. The planar layer overlaps the first conductive layer, the second conductive layer or the active element in the normal direction of the first substrate, which can protect the electronic elements in the electronic device, reduce the impact of the external environment on the performance of the electronic elements, and improve the performance or display quality of the electronic device.

[0059] In addition, the ratio of the thickness of the planar layer to the insulating layer can enhance the effect of the insulating layer protecting the planar layer from moisture. The planar layer has a sufficient thickness to increase the surface flatness of the planar layer contacting the insulating layer, thereby enhancing the structural reliability of the electronic device. The light shielding layer can be provided with a groove on the area that does not correspond to the overlapping planar layer, and the filling layer can be filled into the groove to increase the adhesive strength, thereby enhancing the reliability, performance or display quality of the electronic device.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure. Any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure also includes the combination of each claim and embodiment.

Claims

1. An electronic device having a peripheral area, characterized in that: The peripheral area of ​​the electronic device includes: a first substrate; a second substrate, arranged opposite to the first substrate; A plurality of first support members, disposed between the first substrate and the second substrate; The planar layer is disposed on the first substrate, and has a plurality of first portions and a plurality of openings, wherein the plurality of first portions have an island-shaped appearance in a top view, the plurality of openings respectively surround the plurality of first portions, and the plurality of first support members and the plurality of first portions respectively overlap in a normal direction of the first substrate; The light shielding layer is disposed between the second substrate and the plurality of first support members; a filling layer, disposed between the light shielding layer and the plurality of first support members; and The alignment layer is disposed on the planar layer. wherein the alignment layer on one of the plurality of first portions has a first thickness, the alignment layer in one of the plurality of openings has a second thickness, and the first thickness is greater than or equal to zero and less than the second thickness, The light shielding layer has a groove, and part of the filling layer fills the groove.

2. The electronic device according to claim 1, characterized in that: In a normal direction of the first substrate, one of the plurality of openings has an arc-shaped edge.

3. The electronic device according to claim 1, characterized in that: The first thickness is greater than or equal to 0 angstroms and less than or equal to 500 angstroms.

4. The electronic device according to claim 1, characterized in that: The invention also includes an insulating layer disposed on the planar layer, wherein the insulating layer is disposed between the plurality of first support members and the planar layer.

5. The electronic device according to claim 1, characterized in that: The invention also includes a packaging element disposed in the peripheral area, and the packaging element surrounds the plurality of first support members.

6. The electronic device according to claim 5, characterized in that: The packaging element is in direct contact with the alignment layer.

7. The electronic device according to claim 5, characterized in that: The packaging component overlaps with the planar layer in a normal direction of the first substrate.

8. The electronic device according to claim 1, characterized in that: The electronic device further comprises a working area disposed adjacent to the peripheral area, wherein the electronic device further comprises: The second support member is disposed in the working area and between the first substrate and the second substrate, and the height of the plurality of first support members is the same as the height of the second support member.

9. The electronic device according to claim 1, characterized in that: A first conductive layer is also included, and the plurality of first portions overlap the first conductive layer in a normal direction of the first substrate.

10. The electronic device according to claim 1, characterized in that: The groove does not overlap with the planar layer in a normal direction of the first substrate.

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