Organic light emitting display device

Abstract

An organic light-emitting display device may include: a substrate having a display area including a first sub-display area and a second sub-display area positioned at a first side of the first sub-display area, and a pad area positioned at a second side different from the first side of the first sub-display area; a plurality of right signal wirings arranged in the second sub-display area on the substrate; a plurality of right fan-out wirings, positioned in the pad area, the first sub-display area, and the second sub-display area on the right signal wiring, and respectively including bent portions; a plurality of dummy patterns, arranged in the first sub-display area and the second sub-display area on the right signal wiring, and arranged to be separated from the right fan-out wiring and have a grid shape; and a plurality of sub-pixel structures, arranged on the dummy patterns. Therefore, the visibility of the organic light-emitting display device can be relatively improved.

Description

Technical Field

[0001] Embodiments generally relate to an organic light emitting display device. More particularly, embodiments of the inventive concept relate to an organic light emitting display device including a fan-out wiring. Background Art

[0002] Flat panel display devices are used as display devices for replacing cathode ray tube display devices due to their light weight and thin characteristics. As representative examples of such flat panel display devices, there are liquid crystal display devices and organic light emitting display devices. Compared with liquid crystal display devices, organic light emitting display devices have the advantages of excellent brightness properties and viewing angle properties, and because a backlight unit is not required, an ultra-thin type can be achieved. The above-mentioned organic light emitting display device forms excitons after holes and electrons injected through positive electrodes and negative electrodes are recombined in an organic thin film, and utilizes a phenomenon in which light with a specific wavelength is generated by energy from the formed excitons.

[0003] An organic light-emitting display device may include a display area and a pad area. A pad electrode that receives a plurality of signals for displaying an image from an external device may be disposed in the pad area, and a plurality of signal wirings that transmit signals may be disposed in the display area. Recently, an organic light-emitting display device has been developed that has a pad area whose width in a horizontal direction is smaller than that of a display area in a horizontal direction. In this case, a signal may be transmitted to signal wirings disposed on both sides of the display area through a fan-out wiring. However, due to the fan-out wiring, spots are generated in the display area of ​​the organic light-emitting display device. Summary of the invention

[0004] Technical issues

[0005] Some embodiments provide an organic light emitting display device including a fan-out wiring.

[0006] However, the purpose of the inventive concept is not limited thereto. Therefore, the purpose of the inventive concept can be expanded without departing from the spirit and scope of the inventive concept.

[0007] Technical means

[0008] According to some embodiments, an organic light-emitting display device includes a substrate, a plurality of right signal wirings, a plurality of right fan-out wirings, a plurality of dummy patterns, and a plurality of sub-pixel structures. The substrate includes: i) a display area having a first sub-display area and a second sub-display area positioned on a first side portion of the first sub-display area; and ii) a pad area positioned on a second side portion of the first sub-display area different from the first side portion. The right signal wiring is arranged in the second sub-display area on the substrate. The right fan-out wiring is arranged in the pad area, the first sub-display area, and the second sub-display area on the right signal wiring, and the right fan-out wiring includes a bent portion. The dummy pattern is arranged in the first sub-display area and the second sub-display area on the right signal wiring, and is separated from the right fan-out wiring. The dummy pattern has a grid shape. The sub-pixel structure is arranged on the dummy pattern.

[0009] In an embodiment, each of the right fan-out wirings may include: a vertical extension portion disposed in the pad area and the first sub-display area and extending along a first direction; and a horizontal extension portion extending from a first end of the vertical extension portion positioned in the first sub-display area along a second direction orthogonal to the first direction.

[0010] In an embodiment, a second end of the vertical extension may be positioned in the pad region, and a first end of the vertical extension opposite the second end may be connected to the first end of the horizontal extension.

[0011] In an embodiment, a second end of the horizontal extension opposite to the first end may be connected to one of the right signal wirings through a contact hole.

[0012] In an embodiment, the bent portion may be defined by a first end of the vertically extending portion and a first end of the horizontally extending portion.

[0013] In an embodiment, the vertically extending portion and the horizontally extending portion may be formed integrally with each other.

[0014] In an embodiment, each of the right fan-out wirings may further include a sub-vertical extending portion extending from the second end of the horizontal extending portion along a fourth direction opposite to the first direction.

[0015] In an embodiment, a first end of the horizontal extension may be connected to a first end of the vertical extension, and a second end of the horizontal extension opposite to the first end may be connected to a first end of the sub-vertical extension.

[0016] In an embodiment, a second end of the sub-vertical extension opposite to the first end may be connected to one of the right signal wirings through a contact hole.

[0017] In an embodiment, the curved portion may be defined by i) a first end of the vertically extending portion and a first end of the horizontally extending portion and ii) a second end of the horizontally extending portion and a first end of the sub-vertically extending portion.

[0018] In an embodiment, the vertical extending portion, the horizontal extending portion, and the sub-vertical extending portion may be formed integrally with each other.

[0019] In an embodiment, the vertical extension may be parallel to the sub-vertical extension, and a length of the vertical extension in the first direction may be longer than a length of the sub-vertical extension in the first direction.

[0020] In an embodiment, the dummy pattern may include a plurality of vertical dummy patterns and a plurality of horizontal dummy patterns. The vertical dummy patterns may be spaced apart from the vertical extension portion in a first direction and may be arranged to be spaced apart from each other in the first direction. The horizontal dummy patterns may be spaced apart from the horizontal extension portion in a third direction opposite to the second direction and may be arranged to be spaced apart from each other in the third direction.

[0021] In an embodiment, the dummy pattern may further include a plurality of sub-vertical dummy patterns and a plurality of sub-horizontal dummy patterns. The sub-vertical dummy patterns may be separated from the vertical extension portion in the third direction and may be arranged to be separated from each other in the first direction. The sub-horizontal dummy patterns may be separated from the horizontal extension portion in the first direction and may be arranged to be separated from each other in the third direction.

[0022] In an embodiment, the display area may include a plurality of sub-pixel circuit areas, and at least one of the vertical dummy pattern, the horizontal dummy pattern, the sub-vertical dummy pattern, and the sub-horizontal dummy pattern may be provided in each of the sub-pixel circuit areas.

[0023] In an embodiment, the dummy pattern may have a grid shape in the display area by a vertical dummy pattern, a horizontal dummy pattern, a sub-vertical dummy pattern, and a sub-horizontal dummy pattern provided in each of the sub-pixel circuit regions.

[0024] In an embodiment, the organic light emitting display device may further include a plurality of power supply voltage wirings disposed in the display region on the substrate, and at least some of the dummy patterns may be electrically connected to at least some of the power supply voltage wirings.

[0025] In an embodiment, the right fan-out wiring may include first to M-th right fan-out wiring (where M is an integer of 1 or greater), wherein the first to M-th right fan-out wiring are sequentially arranged while being spaced apart from each other.

[0026] In an embodiment, the lengths of the first to Mth right fan-out wirings may be gradually reduced.

[0027] In an embodiment, the Kth right fan-out wiring from the first right fan-out wiring to the Mth right fan-out wiring (wherein K is an integer between 1 and M) may include: a vertical extension portion, which is arranged in the pad area and the first sub-display area and extends along a first direction; and a horizontal extension portion, which extends from a first end of the vertical extension portion positioned in the first sub-display area along a second direction orthogonal to the first direction.

[0028] In an embodiment, a second end of the vertical extension of the Kth right fan-out wiring may be positioned in the pad region, and a first end opposite to the second end of the vertical extension of the Kth right fan-out wiring may be connected to the first end of the horizontal extension.

[0029] In an embodiment, the right signal wiring may include a first right signal wiring to an Nth right signal wiring (where N is an integer of 1 or greater), wherein the first right signal wiring to the Nth right signal wiring are arranged in reverse order and are separated from each other.

[0030] In an embodiment, the Mth right fan-out wiring and the Nth right signal wiring are disposed adjacent to a boundary between the first sub display area and the second sub display area.

[0031] In an embodiment, a horizontal extension portion of the Kth right fan-out wiring among the first right fan-out wiring to the Mth right fan-out wiring can be connected to the Lth right signal wiring among the first right signal wiring to the Nth right signal wiring (where L is an integer between 1 and N) through a contact hole.

[0032] In an embodiment, the bent portion may be defined by a first end of a vertically extending portion of the K th right fan-out wiring and a first end of a horizontally extending portion of the K th right fan-out wiring.

[0033] In an embodiment, the vertical extension portion and the horizontal extension portion of the K-th right fan-out wiring may be integrally formed.

[0034] In an embodiment, the Kth right fan-out wiring may further include a sub-vertical extending portion extending from the second end of the horizontal extending portion along a fourth direction opposite to the first direction.

[0035] In an embodiment, a first end of the horizontal extending portion may be connected to the vertical extending portion, and a second end of the horizontal extending portion opposite to the first end may be connected to the first end of the sub-vertical extending portion.

[0036] In an embodiment, the right signal wiring may include a first right signal wiring to an Nth right signal wiring (where N is an integer of 1 or greater), wherein the first right signal wiring to the Nth right signal wiring are arranged in reverse order and are separated from each other.

[0037] In an embodiment, a sub-vertical extension of the Kth right fan-out wiring among the first right fan-out wiring to the Mth right fan-out wiring can be connected to the Lth right signal wiring among the first right signal wiring to the Nth right signal wiring (where L is an integer between 1 and N) through a contact hole.

[0038] In an embodiment, the bending portion may be defined by i) a first end of a vertical extension portion of the Kth right fan-out wiring and a first end of a horizontal extension portion of the Kth right fan-out wiring and ii) a second end of a horizontal extension portion of the Kth right fan-out wiring and a first end of a sub-vertical extension portion of the Kth right fan-out wiring.

[0039] In an embodiment, the vertical extending portion of the K th right fan-out wiring, the horizontal extending portion of the K th right fan-out wiring, and the sub-vertical extending portion of the K th right fan-out wiring may be integrally formed.

[0040] In an embodiment, the vertical extension of the K th right fan-out wiring may be parallel to the sub-vertical extension of the K th right fan-out wiring, and a length of the vertical extension in the first direction may be longer than a length of the sub-vertical extension in the first direction.

[0041] In an embodiment, an empty space may be formed inside the vertical extension portion of the Kth right fan-out wiring, the horizontal extension portion of the Kth right fan-out wiring, and the sub-vertical extension portion of the Kth right fan-out wiring, and may have a shape concave in the first direction. The K+1th right fan-out wiring among the first right fan-out wiring to the Mth right fan-out wiring may be disposed in the empty space.

[0042] In an embodiment, the dummy pattern may include a first dummy pattern to a Pth dummy pattern (wherein P is an integer of 1 or greater). The Jth dummy pattern among the first dummy pattern to the Pth dummy pattern (wherein J is an integer between 1 and N) may include a plurality of vertical dummy patterns and a plurality of horizontal dummy patterns. The vertical dummy pattern may be separated from the vertical extension of the Kth right fan-out wiring in the first direction, and may be arranged to be separated from each other in the first direction. The horizontal dummy pattern may be separated from the horizontal extension of the Kth right fan-out wiring in a third direction opposite to the second direction, and may be arranged to be separated from each other in the third direction.

[0043] In an embodiment, the Jth dummy pattern may further include a plurality of sub-vertical dummy patterns and a plurality of sub-horizontal dummy patterns. The sub-vertical dummy patterns may be separated from the vertical extension of the Kth right fan-out wiring in the third direction, and may be arranged to be separated from each other in the first direction. The sub-horizontal dummy patterns may be separated from the horizontal extension of the Kth right fan-out wiring in the first direction, and may be arranged to be separated from each other in the third direction.

[0044] In an embodiment, the display area may include a plurality of sub-pixel circuit areas, wherein at least one of the vertical dummy pattern, the horizontal dummy pattern, the sub-vertical dummy pattern, and the sub-horizontal dummy pattern may be provided in each of the sub-pixel circuit areas.

[0045] In an embodiment, the dummy pattern may have a grid shape in the display area by a vertical dummy pattern, a horizontal dummy pattern, a sub-vertical dummy pattern, and a sub-horizontal dummy pattern provided in each of the sub-pixel circuit regions.

[0046] In an embodiment, the substrate may further include a third sub-display area, wherein the third sub-display area is positioned on a third side portion, the third side portion is oriented to face the first side portion of the first sub-display area, the pad area and the first sub-display area are arranged in a first direction, and the third sub-display area, the first sub-display area and the second sub-display area may be arranged in a second direction orthogonal to the first direction.

[0047] In an embodiment, a width of the display region in the second direction may be greater than a width of the pad region in the second direction.

[0048] In an embodiment, the organic light emitting display device may further include a plurality of pad electrodes arranged along the second direction in the pad region.

[0049] In an embodiment, the organic light emitting display device may further include a plurality of left signal wirings and a plurality of left fan-out wirings. The left signal wirings may be arranged in the third sub-display area on the substrate. The left fan-out wirings may be arranged in the pad area, the first sub-display area, and the third sub-display area on the left signal wirings, and the left fan-out wirings may each include a bent portion.

[0050] In an embodiment, a dummy pattern may be disposed on the left signal wiring in the third sub display area and may be spaced apart from the left fan-out wiring. The dummy pattern may have a grid shape.

[0051] In an embodiment, the left fan-out wiring and the right fan-out wiring may be symmetrical to each other.

[0052] In an embodiment, the left signal wiring may be provided only in the third sub display area, and the data signal may be applied through the left fan-out wiring.

[0053] In an embodiment, the right signal wiring may be provided only in the second sub display area, and the data signal may be applied through the right fan-out wiring.

[0054] In an embodiment, each of the sub-pixel structures may include: a lower electrode disposed on the dummy pattern; a light emitting layer disposed on the lower electrode; and an upper electrode disposed on the light emitting layer.

[0055] In an embodiment, the organic light emitting display device may further include a plurality of central signal wirings disposed in the first sub display area on the substrate.

[0056] In an embodiment, a length of each of the center signal wirings in the first direction may be longer than a length of each of the right signal wirings in the first direction.

[0057] In an embodiment, the central signal wiring may be disposed only in the first sub display area, and the data signal may be applied through the central signal wiring.

[0058] Technical Effects

[0059] The organic light emitting display device according to an embodiment of the present invention includes a dummy pattern, so that the dummy pattern can have a grid pattern shape in the display area together with the right fan-out wiring and the left fan-out wiring. Therefore, the pattern and / or spot caused by the bending portion of the right fan-out wiring and the left fan-out wiring can not be visually recognized in the organic light emitting display device. In addition, when the dummy pattern is electrically connected to the high power supply voltage wiring through the contact hole, the wiring resistance of the high power supply voltage wiring can be reduced. In addition, a constant voltage is applied to the dummy pattern, so that the wiring with a varying voltage level can be shielded.

[0060] In the organic light-emitting display device according to an embodiment of the present invention, the contact hole of the right fan-out wiring is positioned at the lower end of the second sub-display area, and the contact hole of the left fan-out wiring is positioned at the lower end of the third sub-display area, so that the visibility of the organic light-emitting display device can be relatively improved.

[0061] However, the effects of the present invention are not limited thereto. Therefore, the effects of the present invention can be expanded without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 is a plan view illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

[0063] Figure 2 It is shown Figure 1 A plan view of a first sub-display area, a second sub-display area, and a third sub-display area of ​​an organic light emitting display device.

[0064] Figure 3 is shown electrically connected to Figure 1 A block diagram of external devices of an organic light emitting display device.

[0065] Figure 4 It is shown Figure 1 A plan view of an example of an organic light emitting display device.

[0066] Figure 5 It shows that the setting Figure 1 A circuit diagram of a sub-pixel circuit in a sub-pixel circuit area and an organic light emitting diode arranged on the sub-pixel circuit.

[0067] Figure 6 It shows that the Figure 2 A plan view of a center signal wiring, a right signal wiring, and a left signal wiring in the first to third sub display areas.

[0068] Figure 7 It is shown that the Figure 1 A plan view of fan-out wiring and dummy patterns in an organic light-emitting display device.

[0069] Figure 8 It is shown Figure 1 1 is an enlarged plan view of a region “A” of an organic light emitting display device.

[0070] Fig. 9 is a plan view illustrating an example of a fan-out wiring and a dummy pattern included in an organic light emitting display device according to an embodiment.

[0071] Fig.10 is a plan view illustrating another example of a fan-out wiring and a dummy pattern included in an organic light emitting display device according to an embodiment.

[0072] Fig.11 It is shown Figure 8 Floor plan of the fan-out routing and dummy pattern.

[0073] Fig.12 It is shown Fig.11 Layout diagram of area “B” of an organic light emitting display device.

[0074] Figures 13 to 15 It is shown Fig.12 Layout diagram of area "B".

[0075] Fig.16 It is along Fig.12 A cross-sectional view of an organic light emitting display device taken along line II'.

[0076] Fig.17 It is shown Fig.11 0 is an enlarged layout diagram of area “C” of an organic light emitting display device.

[0077] Fig.18 It is along Fig.17 A cross-sectional view of an organic light emitting display device taken along line II-II'.

[0078] Fig.19 It is shown Fig.11 0 is an enlarged layout diagram of region “D” of an organic light emitting display device.

[0079] Fig. 20 It is along Fig.19 A cross-sectional view of an organic light emitting display device taken along line III-III'.

[0080] Fig.21 It is shown Fig.11 1 is an enlarged layout diagram of area “E” of an organic light emitting display device.

[0081] Fig. 22 It is along Fig.21 A cross-sectional view of an organic light emitting display device taken along line IV-IV'.

[0082] Fig.23 is a plan view showing an organic light emitting display device according to an embodiment of the present invention.

[0083] Fig.24 It is shown Fig.23 1 is an enlarged plan view of a region “F” of an organic light emitting display device. DETAILED DESCRIPTION

[0084] Hereinafter, an organic light emitting display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals are used for the same or similar components.

[0085] Figure 1 is a plan view illustrating an organic light emitting display device according to an exemplary embodiment of the present invention. Figure 2 It is shown Figure 1 A plan view of a first sub-display area, a second sub-display area, and a third sub-display area of ​​an organic light emitting display device. Figure 3 is shown electrically connected to Figure 1 A block diagram of external devices of an organic light emitting display device. Figure 4 It is shown Figure 1 A plan view of an example of an organic light emitting display device.

[0086] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4, the organic light-emitting display device 100 may include a display area 40 capable of displaying an image and a pad (or "pad") area 60 capable of receiving a plurality of signals. The display area 40 may include a first sub-display area 10, a second sub-display area 20, and a third sub-display area 30. For example, the second sub-display area 20 may be positioned on a first side portion of the first sub-display area 10, the pad area 60 may be disposed on a second side portion of the first sub-display area 10 different from the first side portion, and the third sub-display area 30 may be positioned on a third side portion of the first sub-display area 10 facing the first side portion. The pad area 60 and the first sub-display area 10 may be arranged along a first direction D1 substantially parallel to an upper surface of the organic light-emitting display device 100, and the third sub-display area 30, the first sub-display area 10, and the second sub-display area 20 may be arranged along a second direction D2 substantially orthogonal to the first direction D1.

[0087] For example, the first sub-display region 10 may be positioned on the front surface of the organic light-emitting display device 100, and the second sub-display region 20 and the third sub-display region 30 may be bent around an axis in the vertical direction (e.g., around an axis in the first direction D1 and a fourth direction D4 opposite to the first direction D1) so as to be positioned on two side surfaces of the organic light-emitting display device 100. Optionally, a portion of the first sub-display region 10 adjacent to the pad region 60 may be bent around an axis in the horizontal direction (e.g., around an axis in the second direction D2 and a third direction D3 opposite to the second direction D2) so as to be positioned on the lower side surface of the organic light-emitting display device 100 (e.g., a surface positioned between the two side surfaces of the organic light-emitting display device 100). In addition, in other embodiments, such as Figure 4 As shown in , the second sub-display area 20 and the third sub-display area 30 can be bent around an axis in the vertical direction so as to be positioned on the two side surfaces of the organic light-emitting display device 100, the first portion of the first sub-display area 10 adjacent to the pad area 60 can be bent around an axis in the horizontal direction so as to be positioned on the lower side surface of the organic light-emitting display device 100, and the second portion of the first sub-display area 10 opposite to the first portion can be bent around an axis in the horizontal direction so as to be positioned on the upper side surface. In this case, the organic light-emitting display device 100 can display images not only on the front surface but also on the four side surfaces. However, for the above structure, the organic light-emitting display device 100 is required to include a flexible substrate (such as a polyimide substrate) as a lower substrate and a thin film encapsulation structure as an upper substrate.

[0088] In an embodiment, when viewed from a top view of the organic light-emitting display device 100, the width W1 of the display area 40 in the second direction D2 may be greater than the width W2 of the pad area 60 in the second direction D2. In addition, the width of the first sub-display area 10 in the first direction D1 (or a fourth direction D4 opposite to the first direction D1) may be greater than the width of each of the second sub-display area 20 and the third sub-display area 30 in the first direction D1. Alternatively, the width of the first sub-display area 10 in the first direction D1 may be less than or equal to the width of each of the second sub-display area 20 and the third sub-display area 30 in the first direction D1.

[0089] A plurality of sub-pixel circuit regions 50 may be arranged throughout the entire display region 40 , and a pad electrode 470 electrically connected to the external device 101 may be arranged in the pad region 60 along the second direction D2 (or a third direction D3 opposite to the second direction D2 ).

[0090] Sub-pixel circuits (e.g., Figure 5 A sub-pixel circuit SUB-PIXEL CIRCUIT) may be provided in each of the sub-pixel circuit regions 50 of the display region 40, and an organic light emitting diode (eg, Figure 5 An organic light emitting diode (OLED) may be disposed on the sub-pixel circuit. An image may be displayed on the display area 40 through the sub-pixel circuit and the organic light emitting diode.

[0091] The first sub-pixel circuit, the second sub-pixel circuit, and the third sub-pixel circuit may be disposed in the sub-pixel circuit region 50. For example, the first sub-pixel circuit may be connected to a first organic light emitting diode capable of emitting red light, the second sub-pixel circuit may be connected to a second organic light emitting diode capable of emitting green light, and the third sub-pixel circuit may be connected to a third organic light emitting diode capable of emitting blue light.

[0092] In an embodiment, the first organic light emitting diode may be arranged to overlap with the first sub-pixel circuit, the second organic light emitting diode may be arranged to overlap with the second sub-pixel circuit, and the third organic light emitting diode may be arranged to overlap with the third sub-pixel circuit. Alternatively, the first organic light emitting diode may be arranged to overlap with a portion of the first sub-pixel circuit and a portion of a sub-pixel circuit different from the first sub-pixel circuit, the second organic light emitting diode may be arranged to overlap with a portion of the second sub-pixel circuit and a portion of a sub-pixel circuit different from the second sub-pixel circuit, and the third organic light emitting diode may be arranged to overlap with a portion of the third sub-pixel circuit and a portion of a sub-pixel circuit different from the third sub-pixel circuit.

[0093] For example, the first to third organic light emitting diodes may be arranged using a scheme such as an RGB strip type in which rectangles having the same size are sequentially arranged, an S-stripe type including a blue organic light emitting diode having a relatively large area, a WRGB type also including a white organic light emitting diode, and a PenTile arranged in an RG-GB repeating pattern.

[0094] In addition, at least one driving transistor, at least one switching transistor, at least one capacitor, etc. may be disposed in each of the sub-pixel circuit regions 50. In an embodiment, one driving transistor, eight switching transistors, one storage capacitor, etc. may be disposed in each of the sub-pixel circuit regions 50.

[0095] Although the sub-pixel circuit region 50 of the present invention has been described as having a rectangular shape when viewed in a plan view, the shape is not limited thereto. For example, when viewed in a plan view, the sub-pixel circuit region 50 may have a triangular shape, a diamond shape, a polygonal shape, a circular shape, a track shape, or an elliptical shape.

[0096] The external device 101 may be electrically connected to the organic light-emitting display device 100 through a flexible printed circuit board. For example, one side of the flexible printed circuit board may be in direct contact with the pad electrode 470, and the other side of the flexible printed circuit board may be in direct contact with the external device 101. The external device 101 may provide a data signal, a scan signal, an emission control signal, a data initialization signal, an initialization voltage, a power voltage, etc. to the organic light-emitting display device 100. In addition, a driver integrated circuit may be mounted on the flexible printed circuit board. In other embodiments, the driver integrated circuit may be mounted on the organic light-emitting display device 100 so as to be adjacent to the pad electrode 470. Alternatively, when the organic light-emitting display device 100 includes a bending area, the pad electrode 470 may be electrically connected to the external device 101 through a printed circuit board. In this case, the bending area may be positioned between the display area 40 and the pad area 60 (for example, may be adjacent to the pad area 60). When the organic light-emitting display device 100 includes a bending area, the bending area may be bent around an axis in the horizontal direction, and the pad area 60 may be positioned on the rear surface of the organic light-emitting display device 100.

[0097] Figure 5 It shows that the setting Figure 1 A circuit diagram of a sub-pixel circuit in a sub-pixel circuit area and an organic light emitting diode arranged on the sub-pixel circuit.

[0098] Reference Figure 5, a sub-pixel circuit SUB-PIXEL CIRCUIT and an organic light emitting diode OLED may be provided in each of the sub-pixel circuit regions 50 of the organic light emitting display device 100. The sub-pixel circuit SUB-PIXEL CIRCUIT may include first to seventh transistors TR1, TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, TR6, and TR7, a storage capacitor CST, a high power supply voltage ELVDD wiring, a low power supply voltage ELVSS wiring, an initialization voltage VINT wiring, a data signal DATA wiring, a scan signal GW wiring, a data initialization signal GI wiring, an emission control signal EM wiring, a diode initialization signal GB wiring, and the like.

[0099] The organic light emitting diode OLED may output light based on the driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. In an embodiment, the second terminal of the organic light emitting diode OLED may be supplied with a low power supply voltage ELVSS. For example, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. Alternatively, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal.

[0100] The first transistor TR1 may include a gate terminal, a first terminal, and a second terminal. In an embodiment, the first terminal of the first transistor TR1 may be a source terminal, and the second terminal of the first transistor TR1 may be a drain terminal. Alternatively, the first terminal of the first transistor TR1 may be a drain terminal, and the second terminal of the first transistor TR1 may be a source terminal.

[0101] The first transistor TR1 may generate a driving current ID. In an embodiment, the first transistor TR1 may operate in a saturation region. In this case, the first transistor TR1 may generate a driving current ID based on a voltage difference between a gate terminal and a source terminal. In addition, a grayscale may be expressed based on the magnitude of the driving current ID supplied to the organic light emitting diode OLED. Alternatively, the first transistor TR1 may operate in a linear region. In this case, the grayscale may be expressed based on the sum of the time for supplying the driving current ID to the organic light emitting diode OLED within one frame.

[0102] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor TR2 may be supplied with a scan signal GW. The first terminal of the second transistor TR2 may be supplied with a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. In an embodiment, the first terminal of the second transistor TR2 may be a source terminal, and the second terminal of the second transistor TR2 may be a drain terminal. Alternatively, the first terminal of the second transistor TR2 may be a drain terminal, and the second terminal of the second transistor TR2 may be a source terminal.

[0103] The second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1 during the activation period of the scan signal GW. In this case, the second transistor TR2 may operate in a linear region.

[0104] Each of the third transistors TR3_1 and TR3_2 may include a gate terminal, a first terminal, and a second terminal. The third transistor TR3_1 and the third transistor TR3_2 may be connected in series and may be operated as a double transistor. For example, when the double transistor is turned off, the leakage current may be reduced. The gate terminal of each of the third transistors TR3_1 and TR3_2 may be supplied with a scan signal GW. The first terminal of each of the third transistors TR3_1 and TR3_2 may be connected to the gate terminal of the first transistor TR1. The second terminal of each of the third transistors TR3_1 and TR3_2 may be connected to the second terminal of the first transistor TR1. In an embodiment, the first terminal of each of the third transistors TR3_1 and TR3_2 may be a source terminal, and the second terminal of each of the third transistors TR3_1 and TR3_2 may be a drain terminal. Alternatively, the first terminal of each of the third transistors TR3_1 and TR3_2 may be a drain terminal, and the second terminal of each of the third transistors TR3_1 and TR3_2 may be a source terminal.

[0105] Each of the third transistors TR3_1 and TR3_2 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during the activation period of the scan signal GW. In this case, each of the third transistors TR3_1 and TR3_2 may operate in a linear region. In other words, each of the third transistors TR3_1 and TR3_2 may diode-connect the first transistor TR1 during the activation period of the scan signal GW. Because the first transistor TR1 is diode-connected, a voltage difference equal to the threshold voltage of the first transistor TR1 may occur between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1. As a result, a voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1 during the activation period of the scan signal GW. In other words, the data signal DATA may be compensated as much as the threshold voltage of the first transistor TR1, and the compensated data signal DATA may be supplied to the gate terminal of the first transistor TR1. When the threshold voltage compensation is performed, the problem of uneven drive current caused by the threshold voltage deviation of the first transistor TR1 may be solved.

[0106] An input terminal of the initialization voltage VINT may be connected to a first terminal of each of the fourth transistors TR4_1 and TR4_2 and a first terminal of the seventh transistor TR7 , and an output terminal of the initialization voltage VINT may be connected to a second terminal of each of the fourth transistors TR4_1 and TR4_2 and a first terminal of the storage capacitor CST.

[0107] Each of the fourth transistors TR4_1 and TR4_2 may include a gate terminal, a first terminal, and a second terminal. The fourth transistor TR4_1 and the fourth transistor TR4_2 may be connected in series and may be operated as a double transistor. For example, when the double transistor is turned off, the leakage current may be reduced. The gate terminal of each of the fourth transistors TR4_1 and TR4_2 may receive a data initialization signal GI. The first terminal of each of the fourth transistors TR4_1 and TR4_2 may be supplied with an initialization voltage VINT. The second terminal of each of the fourth transistors TR4_1 and TR4_2 may be connected to the gate terminal of the first transistor TR1. In an embodiment, the first terminal of each of the fourth transistors TR4_1 and TR4_2 may be a source terminal, and the second terminal of each of the fourth transistors TR4_1 and TR4_2 may be a drain terminal. Alternatively, the first terminal of each of the fourth transistors TR4_1 and TR4_2 may be a drain terminal, and the second terminal of each of the fourth transistors TR4_1 and TR4_2 may be a source terminal.

[0108] Each of the fourth transistors TR4_1 and TR4_2 may supply an initialization voltage VINT to a gate terminal of the first transistor TR1 during an activation period of the data initialization signal GI. In this case, each of the fourth transistors TR4_1 and TR4_2 may operate in a linear region. In other words, each of the fourth transistors TR4_1 and TR4_2 may initialize a gate terminal of the first transistor TR1 to an initialization voltage VINT during an activation period of the data initialization signal GI. In an embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than a voltage level of the data signal DATA held by the storage capacitor CST in a previous frame, and the initialization voltage VINT may be supplied to a gate terminal of the first transistor TR1 as a p-channel metal oxide semiconductor (PMOS) transistor. In other embodiments, the initialization voltage may have a voltage level sufficiently higher than a voltage level of the data signal held by the storage capacitor in a previous frame, and the initialization voltage may be supplied to a gate terminal of the first transistor TR1 as an n-channel metal oxide semiconductor (NMOS) transistor.

[0109] In an embodiment, the data initialization signal GI may be a signal substantially the same as the scan signal GW one horizontal time ago. For example, the data initialization signal GI supplied to the sub-pixels of the n-th row (where n is an integer of 2 or greater) among a plurality of sub-pixels (e.g., a sub-pixel circuit SUB-PIXEL CIRCUIT) and the organic light emitting diode OLED included in the organic light emitting display device 100 may be a signal substantially the same as the scan signal GW supplied to the sub-pixels of the n-1th row among the sub-pixels. In other words, the activated scan signal GW is supplied to the sub-pixels of the n-1th row among the sub-pixels, so that the activated data initialization signal GI may be supplied to the sub-pixels of the n-1th row among the sub-pixels. As a result, the data signal DATA may be supplied to the sub-pixels of the n-1th row among the sub-pixels, and the gate terminal of the first transistor TR1 included in the sub-pixel of the n-1th row among the sub-pixels may be initialized to the initialization voltage VINT.

[0110] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fifth transistor TR5 may be supplied with an emission control signal EM. The first terminal of the fifth transistor TR5 may be connected to the high power supply voltage ELVDD wiring. The second terminal of the fifth transistor TR5 may be connected to the first terminal of the first transistor TR1. In an embodiment, the first terminal of the fifth transistor TR5 may be a source terminal, and the second terminal of the fifth transistor TR5 may be a drain terminal. Alternatively, the first terminal of the fifth transistor TR5 may be a drain terminal, and the second terminal of the fifth transistor TR5 may be a source terminal.

[0111] The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the emission control signal EM. On the contrary, the fifth transistor TR5 may block the supply of the high power supply voltage ELVDD during the deactivation period of the emission control signal EM. In this case, the fifth transistor TR5 may operate in a linear region. The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the emission control signal EM, so that the first transistor TR1 may generate a driving current ID. In addition, the fifth transistor TR5 may block the supply of the high power supply voltage ELVDD during the deactivation period of the emission control signal EM, so that the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0112] The sixth transistor TR6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the sixth transistor TR6 may be supplied with an emission control signal EM. The first terminal of the sixth transistor TR6 may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 may be connected to the first terminal of the organic light emitting diode OLED. In an embodiment, the first terminal of the sixth transistor TR6 may be a source terminal, and the second terminal of the sixth transistor TR6 may be a drain terminal. Alternatively, the first terminal of the sixth transistor TR6 may be a drain terminal, and the second terminal of the sixth transistor TR6 may be a source terminal.

[0113] The sixth transistor TR6 can supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the emission control signal EM. In this case, the sixth transistor TR6 can operate in a linear region. In other words, the sixth transistor TR6 can supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the emission control signal EM, so that the organic light emitting diode OLED can output light. In addition, the sixth transistor TR6 electrically isolates the first transistor TR1 and the organic light emitting diode OLED from each other during the deactivation period of the emission control signal EM, so that the data signal DATA supplied to the second terminal of the first transistor TR1 (more precisely, the data signal compensated for the threshold voltage) can be supplied to the gate terminal of the first transistor TR1.

[0114] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the seventh transistor TR7 may be supplied with a diode initialization signal GB. The first terminal of the seventh transistor TR7 may be supplied with an initialization voltage VINT. The second terminal of the seventh transistor TR7 may be connected to a first terminal of the organic light emitting diode OLED. In an embodiment, the first terminal of the seventh transistor TR7 may be a source terminal, and the second terminal of the seventh transistor TR7 may be a drain terminal. Alternatively, the first terminal of the seventh transistor TR7 may be a drain terminal, and the second terminal of the seventh transistor TR7 may be a source terminal.

[0115] The seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during the activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 can operate in the linear region. In other words, the seventh transistor TR7 can initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0116] Alternatively, the data initialization signal GI may be substantially the same as the diode initialization signal GB. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may not affect each other. In other words, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may be independent of each other. Therefore, the diode initialization signal GB is not generated separately, so the economic efficiency of the process can be improved.

[0117] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the high power supply voltage ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power supply voltage ELVDD wiring. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the deactivation period of the scan signal GW. The deactivation period of the scan signal GW may include the activation period of the emission control signal EM, and the drive current ID generated by the first transistor TR1 during the activation period of the emission control signal EM may be supplied to the organic light emitting diode OLED. Therefore, based on the voltage level maintained by the storage capacitor CST, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED. Optionally, the sub-pixel circuit SUB-PIXEL CIRCUIT may include the first to seventh transistors TR1, TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, TR6, TR7 (for example, seven transistors), at least one storage capacitor CST, etc.

[0118] Figure 6 It shows that the Figure 2 A plan view of a center signal wiring, a right signal wiring, and a left signal wiring in the first to third sub display areas. Figure 7 It is shown that the Figure 1 A plan view of fan-out wiring and dummy patterns in an organic light-emitting display device. Figure 8 It is shown Figure 1 1 is an enlarged plan view of a region “A” of an organic light emitting display device. Fig. 9 is a plan view illustrating an example of a fan-out wiring and a dummy pattern included in an organic light emitting display device according to an embodiment. Fig.10 1 is a plan view showing another example of a fan-out wiring and a dummy pattern included in an organic light-emitting display device according to an embodiment. For example, for ease of description, Figure 6 The display area 40 of FIG. 4 shows only the center signal wiring 510 , the right signal wiring 520 , and the left signal wiring 530 . Figure 7 Only the right fan-out wiring 400 , the left fan-out wiring 500 , and the dummy pattern 600 in the display region 40 are shown.

[0119] Reference Figure 6 , Figure 7 and Figure 8, the organic light emitting display device 100 may include a substrate (not shown), a central signal wiring 510, a right signal wiring 520, a left signal wiring 530, a right fan-out wiring 400, a left fan-out wiring 500, a dummy pattern 600, a pad electrode 470, etc. Since the organic light emitting display device 100 includes a pad region 60 and a display region 40 including a first sub-display region 10, a second sub-display region 20, and a third sub-display region 30, the substrate may also be divided into the first sub-display region 10, the second sub-display region 20, the third sub-display region 30, and the pad region 60.

[0120] The central signal wiring 510 may be disposed on the substrate in the first sub display area 10, the right signal wiring 520 may be disposed on the substrate in the second sub display area 20, and the left signal wiring 530 may be disposed on the substrate in the third sub display area 30. Alternatively, the central signal wiring 510 may be disposed in a portion of the pad area 60. For example, the central signal wiring 510 may include a first central signal wiring to a thirteenth central signal wiring.

[0121] In an embodiment, the right signal wiring 520 may be disposed only in the second sub-display area 20, and the left signal wiring 530 may be disposed only in the third sub-display area 30. Figure 8 As shown in , the right signal wiring 520 may include the first right signal wiring to the fourth right signal wiring 521, 522, 523 and 524. In addition, the left signal wiring 530 may also include the first left signal wiring to the fourth left signal wiring. The fourth right signal wiring 524 and the fourth left signal wiring may be positioned adjacent to (or facing) each other, and the first right signal wiring 521 and the first left signal wiring may be arranged at the outermost side. In other words, the first right signal wiring to the fourth right signal wiring 521, 522, 523 and 524 may be arranged in the second sub-display area 20 along the second direction D2 according to the opposite order, and the first left signal wiring to the fourth left signal wiring may be arranged in the third sub-display area 30 along the third direction D3 according to the opposite order. In other words, the first right signal wiring to the fourth right signal wiring 521, 522, 523 and 524 may be symmetrical with the first left signal wiring to the fourth left signal wiring.

[0122] In an embodiment, each of the center signal wiring 510, the right signal wiring 520, and the left signal wiring 530 may be connected to a data signal wiring (eg, Figure 5In other words, the data signal may be applied from the external device 101 to the center signal wiring 510, the right signal wiring 520, and the left signal wiring 530. In addition, the center signal wiring 510 may be electrically connected to the pad electrode 470 without fan-out wiring, but the right signal wiring 520 and the left signal wiring 530 may be electrically connected to the pad electrode 470 through the right fan-out wiring 400 and the left fan-out wiring 500, respectively. In addition, the length of the center signal wiring 510 in the first direction D1 may be longer than the length of the right signal wiring 520 and the left signal wiring 530 in the first direction D1.

[0123] The right fan-out wiring 400 , the left fan-out wiring 500 , and the dummy pattern 600 may be disposed on the central signal wiring 510 , the right signal wiring 520 , and the left signal wiring 530 .

[0124] The right fan-out wiring 400 may be disposed on the substrate in a portion of the pad region 60, in the first sub-display region 10, and in the second sub-display region 20, and each of the right fan-out wirings 400 may include a bent portion. For example, each of the right fan-out wirings 400 may include a vertical extension portion and a horizontal extension portion. The vertical extension portion may be disposed in a portion of the pad region 60 and in the first sub-display region 10, and may extend in the first direction D1. In addition, the horizontal extension portion may extend from a first end of the vertical extension portion positioned in the first sub-display region 10 along a second direction D2. For example, a second end of the vertical extension portion may be positioned in the pad region 60, and a first end of the vertical extension portion opposite to the second end may be connected to the first end of the horizontal extension portion. The second end of the horizontal extension portion opposite to the first end may be connected to one of the right signal wirings 520 through a contact hole.

[0125] like Figure 8 As shown in , the right fan-out wiring 400 may include first to fourth right fan-out wirings 401, 402, 403, and 404. The first right fan-out wiring 401 may be connected to the first right signal wiring 521 through the first contact hole 721, the second right fan-out wiring 402 may be connected to the second right signal wiring 522 through the second contact hole 722, the third right fan-out wiring 403 may be connected to the third right signal wiring 523 through the third contact hole 723, and the fourth right fan-out wiring 404 may be connected to the fourth right signal wiring 524 through the fourth contact hole 724. The sizes of the first to fourth right fan-out wirings 401, 402, 403, and 404 may be sequentially reduced.

[0126] In an embodiment, in each of right fan-out wirings 400 , a bent portion may be defined by a first end of a vertical extension and a first end of a horizontal extension, and the vertical extension and the horizontal extension may be formed integrally with each other. Optionally, right fan-out wiring 400 may not be disposed in pad region 60 .

[0127] The left fan-out wiring 500 may be disposed on the substrate in a portion of the pad region 60, in the first sub-display region 10, and in the third sub-display region 30, and each of the left fan-out wirings 500 may include a bent portion. For example, each of the left fan-out wirings 500 may include a vertical extension portion and a horizontal extension portion. The vertical extension portion may be disposed in a portion of the pad region 60 and in the first sub-display region 10, and may extend in the first direction D1. In addition, the horizontal extension portion may extend along the third direction D3 from the first end of the vertical extension portion positioned in the first sub-display region 10. For example, the second end of the vertical extension portion may be positioned in the pad region 60, and the first end of the vertical extension portion opposite to the second end may be connected to the first end of the horizontal extension portion. The second end of the horizontal extension portion opposite to the first end may be connected to one of the left signal wirings 530 through a contact hole.

[0128] For example, the left fan-out wiring 500 may include first to fourth left fan-out wirings. The first left fan-out wiring may be connected to the first left signal wiring through a fifth contact hole, the second left fan-out wiring may be connected to the second left signal wiring through a sixth contact hole, the third left fan-out wiring may be connected to the third left signal wiring through a seventh contact hole, and the fourth left fan-out wiring may be connected to the fourth left signal wiring through an eighth contact hole. The sizes of the first to fourth left fan-out wirings may be sequentially reduced.

[0129] In an embodiment, in each of the left fan-out wirings 500, the bend may be defined by a first end of the vertical extension and a first end of the horizontal extension, and the vertical extension and the horizontal extension may be formed integrally with each other. In addition, the right fan-out wiring 400 may be symmetrical with the left fan-out wiring 500. Optionally, the left fan-out wiring 500 may not be disposed in the pad region 60.

[0130] The dummy pattern 600 may be separated from the right fan-out wiring 400 and the left fan-out wiring 500 in the first sub-display area 10, the second sub-display area 20, and the third sub-display area 30. The dummy pattern 600 may have a grid shape. The dummy pattern 600 may include a plurality of vertical dummy patterns, a plurality of horizontal dummy patterns, a plurality of sub-vertical dummy patterns, and a plurality of sub-horizontal dummy patterns.

[0131] The vertical dummy patterns of the dummy patterns 600 may be separated from the vertically extending portions of the right fan-out wiring 400 and the left fan-out wiring 500 in the first direction D1, and may be arranged to be separated from each other in the first direction D1. The horizontal dummy patterns of the dummy patterns 600 may be separated from the horizontally extending portions of the right fan-out wiring 400 in the third direction D3, and may be arranged to be separated from each other in the third direction D3. In addition, the horizontal dummy patterns of the dummy patterns 600 may be separated from the horizontally extending portions of the left fan-out wiring 500 in the second direction D2, and may be arranged to be separated from each other in the second direction D2.

[0132] For example, Figure 8 As shown in , the vertical dummy patterns may include first to fourth vertical dummy patterns 601 , 602 , 603 , and 604 , and the horizontal dummy patterns may include first to fourth horizontal dummy patterns 701 , 702 , 703 , and 704 .

[0133] The first vertical dummy patterns 601 may be spaced apart from the vertically extending portions of the first right fan-out wiring 401 in the first direction D1 , and may be arranged to be spaced apart from each other in the first direction D1 (eg, substantially the same direction in which the vertically extending portions extend).

[0134] The second vertical dummy patterns 602 may be spaced apart from the vertically extending portion of the second right fan-out wiring 402 in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertically extending portion extends). The second vertical dummy patterns 602 may be spaced apart from the horizontally extending portion of the first right fan-out wiring 401. In other words, the horizontally extending portion of the first right fan-out wiring 401 may be interposed between the second vertical dummy patterns 602.

[0135] The third vertical dummy pattern 603 may be spaced apart from the vertical extension of the third right fan-out wiring 403 in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertical extension extends). The third vertical dummy pattern 603 may be spaced apart from the horizontal extension of the first right fan-out wiring 401 and the horizontal extension of the second right fan-out wiring 402.

[0136] The fourth vertical dummy pattern 604 may be spaced apart from the vertical extension portion of the fourth right fan-out wiring 404 in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertical extension portion extends). The fourth vertical dummy pattern 604 may be spaced apart from the horizontal extension portion of the first right fan-out wiring 401, the horizontal extension portion of the second right fan-out wiring 402, and the horizontal extension portion of the third right fan-out wiring 403.

[0137] The first horizontal dummy patterns 701 may be spaced apart from the horizontally extending portion of the first right fan-out wiring 401 in the third direction D3 , and may be arranged to be spaced apart from each other in the third direction D3 . Fig. 9 One first horizontal dummy pattern 701 is shown in FIG. 4 , however, at least two first horizontal dummy patterns 701 may be disposed between the sub-vertical dummy pattern 801 and the first right fan-out wiring 401 .

[0138] The second horizontal dummy pattern 702 may be spaced apart from the horizontal extension portion of the second right fan-out wiring 402 in the third direction D3, and may be arranged to be spaced apart from each other in the third direction D3. The second horizontal dummy pattern 702 may be spaced apart from the vertical extension portion of the first right fan-out wiring 401. In other words, the vertical extension portion of the first right fan-out wiring 401 may be interposed between the second horizontal dummy patterns 702.

[0139] The third horizontal dummy pattern 703 may be separated from the horizontal extension portion of the third right fan-out wiring 403 in the third direction D3, and may be arranged to be separated from each other in the third direction D3. The third horizontal dummy pattern 703 may be separated from the vertical extension portion of the second right fan-out wiring 402 and the vertical extension portion of the first right fan-out wiring 401. In other words, the vertical extension portion of the second right fan-out wiring 402 and the vertical extension portion of the first right fan-out wiring 401 may be interposed between the third horizontal dummy pattern 703.

[0140] The fourth horizontal dummy pattern 704 may be separated from the horizontal extension portion of the fourth right fan-out wiring 404 in the third direction D3, and may be arranged to be separated from each other in the third direction D3. The fourth horizontal dummy pattern 704 may be separated from the vertical extension portion of the third right fan-out wiring 403, the vertical extension portion of the second right fan-out wiring 402, and the vertical extension portion of the first right fan-out wiring 401. In other words, the vertical extension portion of the third right fan-out wiring 403, the vertical extension portion of the second right fan-out wiring 402, and the vertical extension portion of the first right fan-out wiring 401 may be interposed between the fourth horizontal dummy pattern 704.

[0141] In addition, the vertical dummy patterns may further include fifth to eighth vertical dummy patterns, and the horizontal dummy patterns may further include fifth to eighth horizontal dummy patterns.

[0142] The fifth vertical dummy patterns may be spaced apart from the vertically extending portion of the first left fan-out wiring in the first direction D1 , and may be arranged to be spaced apart from each other in the first direction D1 .

[0143] The sixth vertical dummy pattern may be spaced apart from the vertical extension portion of the second left fan-out wiring in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1. The sixth vertical dummy pattern may be spaced apart from the horizontal extension portion of the first left fan-out wiring. In other words, the horizontal extension portion of the first left fan-out wiring may be interposed between the sixth vertical dummy patterns.

[0144] The seventh vertical dummy pattern may be spaced apart from the vertical extension of the third left fan-out wiring in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1. The seventh vertical dummy pattern may be spaced apart from the horizontal extension of the first left fan-out wiring and the horizontal extension of the second left fan-out wiring. In other words, the horizontal extension of the first left fan-out wiring and the horizontal extension of the second left fan-out wiring may be interposed between the seventh vertical dummy pattern.

[0145] The eighth vertical dummy pattern may be spaced apart from the vertical extension of the fourth left fan-out wiring in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1. The eighth vertical dummy pattern may be spaced apart from the horizontal extension of the first left fan-out wiring, the horizontal extension of the second left fan-out wiring, and the horizontal extension of the third left fan-out wiring. In other words, the horizontal extension of the first left fan-out wiring, the horizontal extension of the second left fan-out wiring, and the horizontal extension of the third left fan-out wiring may be interposed between the eighth vertical dummy pattern.

[0146] The fifth horizontal dummy pattern may be spaced apart from the horizontally extending portion of the first left fan-out wiring in the third direction D3 , and may be arranged to be spaced apart from each other in the third direction D3 . Figure 7 One fifth horizontal dummy pattern is shown in FIG. 8 , however, at least two fifth horizontal dummy patterns may be disposed between the sub-vertical dummy pattern 801 and the first left fan-out wiring.

[0147] The sixth horizontal dummy pattern may be spaced apart from the horizontal extension portion of the second left fan-out wiring in the third direction D3, and may be arranged to be spaced apart from each other in the third direction D3. The sixth horizontal dummy pattern may be spaced apart from the vertical extension portion of the first left fan-out wiring. In other words, the vertical extension portion of the first left fan-out wiring may be interposed between the sixth horizontal dummy patterns.

[0148] The seventh horizontal dummy pattern may be separated from the horizontal extension portion of the third left fan-out wiring in the third direction D3, and may be arranged to be separated from each other in the third direction D3. The seventh horizontal dummy pattern may be separated from the vertical extension portion of the second left fan-out wiring and the vertical extension portion of the first left fan-out wiring. In other words, the vertical extension portion of the second left fan-out wiring and the vertical extension portion of the first left fan-out wiring may be interposed between the seventh horizontal dummy pattern.

[0149] The eighth horizontal dummy pattern may be separated from the horizontal extension portion of the fourth left fan-out wiring in the third direction D3, and may be arranged to be separated from each other in the third direction D3. The eighth horizontal dummy pattern may be separated from the vertical extension portion of the third left fan-out wiring, the vertical extension portion of the second left fan-out wiring, and the vertical extension portion of the first left fan-out wiring. In other words, the vertical extension portion of the third left fan-out wiring, the vertical extension portion of the second left fan-out wiring, and the vertical extension portion of the first left fan-out wiring may be inserted between the eighth horizontal dummy pattern.

[0150] The sub-horizontal dummy patterns of the dummy pattern 600 may be spaced apart from the horizontally extending portions of the right and left fan-out wirings 400 and 500 in the first direction D1, and may be arranged to be spaced apart from each other in the third direction D3. The sub-horizontal dummy patterns arranged to be spaced apart from each other in the third direction D3 may be repeatedly spaced apart from each other in the first direction D1.

[0151] For example, Figure 8 As shown in , the sub-horizontal dummy patterns 901 may be spaced apart from the horizontally extending portion of the first right fan-out wiring 401 in the first direction D1, and may be arranged to be spaced apart from each other in the third direction D3. The sub-horizontal dummy patterns 901 arranged to be spaced apart from each other in the third direction D3 may be repeatedly spaced apart from each other in the first direction D1.

[0152] The sub vertical dummy pattern may be disposed between the right fan-out wiring 400 and the left fan-out wiring 500. In other words, the sub vertical dummy pattern may be spaced apart from the right fan-out wiring 400 in the third direction D3 or spaced apart from the left fan-out wiring 500 in the second direction D2.

[0153] For example, Figure 8 As shown in , the sub-vertical dummy pattern 801 may be disposed between the right fan-out wiring 400 and the left fan-out wiring 500, and may be arranged to be spaced apart from each other in the first direction D1. The dummy pattern 600 disposed on the left side of the sub-vertical dummy pattern 801 with respect to the sub-vertical dummy pattern 801 may be symmetrical with the dummy pattern 600 disposed on the right side of the sub-vertical dummy pattern 801. In addition, the right fan-out wiring 400 and the left fan-out wiring 500 may be symmetrical with each other with respect to the sub-vertical dummy pattern 801.

[0154] In addition, the dummy pattern 600 may further include sub-vertical dummy patterns between the first right signal wiring 521 and the second right signal wiring 522, between the second right signal wiring 522 and the third right signal wiring 523, and between the third right signal wiring 523 and the fourth right signal wiring 524. In addition, the dummy pattern 600 may further include sub-vertical dummy patterns between the first left signal wiring and the second left signal wiring, between the second left signal wiring and the third left signal wiring, and between the third left signal wiring and the fourth left signal wiring.

[0155] In other embodiments, Fig. 9 As shown in , the first right fan-out wiring 401 may be connected to the fourth right signal wiring 524 through the first contact hole 721, the second right fan-out wiring 402 may be connected to the third right signal wiring 523 through the second contact hole 722, the third right fan-out wiring 403 may be connected to the second right signal wiring 522 through the third contact hole 723, and the fourth right fan-out wiring 404 may be connected to the first right signal wiring 521 through the fourth contact hole 724, wherein the dummy pattern 600 may not be provided between the first right signal wiring 521 and the second right signal wiring 522, between the second right signal wiring 522 and the third right signal wiring 523, and between the third right signal wiring 523 and the fourth right signal wiring 524. In this case, the sizes of the first to fourth right fan-out wirings 401, 402, 403, and 404 may be the same as each other.

[0156] In other embodiments, Fig.10 As shown in , the sub-vertical dummy patterns may also be disposed between the fourth right signal wiring 524 and the third right signal wiring 523 , between the third right signal wiring 523 and the second right signal wiring 522 , and between the second right signal wiring 522 and the first right signal wiring 521 .

[0157] As described above, the dummy pattern 600 includes a plurality of vertical dummy patterns, a plurality of horizontal dummy patterns, a plurality of sub-vertical dummy patterns, and a plurality of sub-horizontal dummy patterns, so that the dummy pattern 600 may have a grid shape in the display region 40 .

[0158] For example, a conventional organic light-emitting display device may include right fan-out wiring and left fan-out wiring to provide data signals to right signal wiring and left signal wiring. When a conventional organic light-emitting display device includes right fan-out wiring and left fan-out wiring, patterns and / or spots may be visually recognized at a portion (such as a bent portion) in a display region of the conventional organic light-emitting display device where the right fan-out wiring and the left fan-out wiring are located. In other words, the visibility of the conventional organic light-emitting display device may be reduced.

[0159] The organic light-emitting display device 100 according to an embodiment of the present invention includes the dummy pattern 600, so that the dummy pattern 600 can realize a grid pattern shape throughout the entire display area 40 together with the right fan-out wiring 400 and the left fan-out wiring 500. In this case, the pattern and / or the spot will not be visually recognized on the organic light-emitting display device 100. Therefore, the visibility of the organic light-emitting display device 100 can be relatively improved.

[0160] Although it has been described in the embodiment that the center signal wiring 510 includes 13 wirings, and each of the right signal wiring 520 , the left signal wiring 530 , the right fan-out wiring 400 , and the left fan-out wiring 500 includes four wirings, the configuration of the present invention is not limited thereto.

[0161] For example, the right fan-out wiring 400 may include a first right fan-out wiring to an M-th right fan-out wiring (where M is an integer of 1 or greater), and the first right fan-out wiring to the M-th right fan-out wiring may be sequentially arranged while being separated from each other. The total length of the first right fan-out wiring to the M-th right fan-out wiring may be sequentially reduced. The K-th right fan-out wiring among the first right fan-out wiring to the M-th right fan-out wiring (where K is an integer between 1 and M) may include a vertical extension portion and a horizontal extension portion, the vertical extension portion being disposed in the pad area 60 and the first sub-display area 10 and extending along the first direction D1, and the horizontal extension portion extending from the first end of the vertical extension portion positioned in the first sub-display area 10 along the second direction D2.

[0162] A second end of the vertical extension of the Kth right fan-out wiring may be positioned in the pad area 60 , and a first end of the vertical extension of the Kth right fan-out wiring opposite to the second end may be connected to the first end of the horizontal extension.

[0163] The right signal wiring 520 may include a first right signal wiring to an Nth right signal wiring (where N is an integer of 1 or greater), and the first right signal wiring to the Nth right signal wiring may be arranged in reverse order and separated from each other. The Mth right fan-out wiring and the Nth right signal wiring may be disposed adjacent to a boundary between the first sub-display area 10 and the second sub-display area 20.

[0164] A horizontal extension portion of the Kth right fan-out wiring among the first right fan-out wiring to the Mth right fan-out wiring can be connected to the Lth right signal wiring among the first right signal wiring to the Nth right signal wiring (where L is an integer between 1 and N) through a contact hole, where K and L can be the same integer.

[0165] The bent portion may be defined by a first end of the vertically extending portion and a first end of the horizontally extending portion of the K-th right fan-out wiring, and the vertically extending portion and the horizontally extending portion of the K-th right fan-out wiring may be formed integrally with each other.

[0166] The dummy pattern 600 may include first to P-th dummy patterns (where P is an integer of 1 or more). A J-th dummy pattern (where J is an integer between 1 and N) among the first to P-th dummy patterns may be spaced apart from the vertical extension portion of the K-th right fan-out wiring in the first direction D1, and may include a plurality of vertical dummy patterns arranged to be spaced apart from each other in the first direction D1 and a plurality of horizontal dummy patterns spaced apart from the horizontal extension portion of the K-th right fan-out wiring in the third direction D3 and arranged to be spaced apart from each other in the third direction D3.

[0167] The Jth dummy pattern may further include a plurality of sub-vertical dummy patterns that are separated from the vertical extension portion of the Kth right fan-out wiring in the third direction D3 and are arranged to be separated from each other in the first direction D1, and a plurality of sub-horizontal dummy patterns that are separated from the horizontal extension portion of the Kth right fan-out wiring in the first direction D1 and are arranged to be separated from each other in the third direction D3.

[0168] Furthermore, in the embodiment, although the dummy patterns 600 have been described as being separated from each other, the configuration of the present invention is not limited thereto. For example, in other embodiments, at least two dummy patterns 600 positioned adjacent to each other among the dummy patterns 600 may be formed integrally with each other.

[0169] Fig.11 It is shown Figure 8 Floor plan of the fan-out routing and dummy pattern. Fig.12 It is shown Fig.11 Layout diagram of area “B” of an organic light emitting display device. Figures 13 to 15 It is shown Fig.12 Layout diagram of area "B". Fig.16 It is along Fig.12 A cross-sectional view of an organic light emitting display device taken along line II'. Fig.12 Previous description Figures 13 to 15 and Fig.16 For example, region "B" can be associated with Figure 1 Corresponding to one of the sub-pixel circuit regions 50 .

[0170] Reference Fig.13 and Fig.16 The organic light-emitting display device 100 may include a substrate 150, an active pattern 1100, a gate insulating layer 1160, a first gate electrode 1105, a first gate wiring 1110, a second gate wiring 1115, a third gate wiring 1120, and the like.

[0171] The substrate 150 may include a transparent or opaque material. For example, the substrate 150 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped (F-doped) quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. The substrate 150 may have a sub-pixel circuit area 50. Alternatively, the substrate 150 may be formed by a transparent resin substrate having flexibility. Examples of transparent resin substrates that can be used for the substrate 150 may include polyimide substrates. In this case, the polyimide substrate may be composed of a first polyimide layer, a barrier film layer, a second polyimide layer, etc. For example, the polyimide substrate may be constructed so that the first polyimide layer, the barrier film layer, and the second polyimide layer are stacked on a hard glass substrate. After an insulating layer (such as a buffer layer) is disposed on the second polyimide layer of the polyimide substrate, the sub-pixel circuit and the organic light emitting diode (e.g., an upper structure) may be disposed on the insulating layer. After the upper structure is disposed, the hard glass substrate may be removed. In other words, since the polyimide substrate is thin and flexible, it may be difficult to directly dispose the upper structure on the polyimide substrate. In view of the above difficulties, the polyimide substrate may be used as the substrate 150 by forming the upper structure using a hard glass substrate and then removing the glass substrate.

[0172] A buffer layer (not shown) may be disposed on the substrate 150. The buffer layer may be disposed over the entire substrate 150. The buffer layer may prevent metal atoms or impurities from diffusing to the transistor and the organic light emitting diode (e.g., the sub-pixel structure 1200), and may adjust the rate of heat transfer during a crystallization process for forming the active pattern 1100 so as to obtain a substantially uniform active pattern 1100. In addition, when the surface of the substrate 150 is uneven, the buffer layer may be used to improve the flatness of the surface of the substrate 150. Depending on the type of the substrate 150, at least two buffer layers may be disposed on the substrate 150, or no buffer layer may be disposed. For example, the buffer layer may include an organic material or an inorganic material.

[0173] The active pattern 1100 may be disposed on the substrate 150. The active pattern 1100 may include an oxide semiconductor, an inorganic semiconductor such as amorphous silicon and polycrystalline silicon, an organic semiconductor, or the like.

[0174] The active pattern 1100 may include a first region to a tenth region (a, b, c, d, e, f, g, h, i, j; for example, a region in which the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 do not overlap the active pattern 1100). In the step of forming a contact hole described below, the first region to the tenth region a, b, c, d, e, f, g, h, i, and j may be doped with ions and may have a relatively high conductivity. Boron (B) ions or phosphorus (P) ions may be used as the ions. The first region to the tenth region a, b, c, d, e, f, g, h, i, and j are used as regions for constituting source electrodes or drain electrodes of the first to seventh transistors TR1, TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, TR6, and TR7, and may not have boundaries clearly distinguished between regions, and may be electrically connected to each other. In an embodiment, the first transistor TR1 may correspond to a driving transistor, and the second to seventh transistors TR2, TR3_1, TR3_2, TR4_1, TR4_2, TR5, TR6, and TR7 may correspond to switching transistors.

[0175] The gate insulating layer 1160 may be disposed on the active pattern 1100. The gate insulating layer 1160 may cover the active pattern 1100 on the substrate 150, and may be disposed over the entire substrate 110. For example, the gate insulating layer 1160 may fully cover the active pattern 1100 on the substrate 150, and may have a substantially flat top surface without generating steps around the active pattern 1100. Alternatively, the gate insulating layer 1160 may cover the active pattern 1100 on the substrate 150, and be disposed to have a uniform thickness along the contour of the active pattern 1100. The gate insulating layer 1160 may include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 1160 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbonitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), titanium oxide (TiO x )wait.

[0176] The first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 may be disposed on the gate insulating layer 1160. In other words, the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 may be disposed on the same layer. Each of the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, each of the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), tungsten (W), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum, aluminum nitride (AlN), or the like. x ), alloys containing silver, tungsten nitride (WN x ), alloys containing copper, alloys containing molybdenum, titanium nitride (TiN x ), Tantalum Nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x )、Indium Tin Oxide (ITO), Tin Oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ), indium zinc oxide (IZO), etc. These may be used alone or in combination. The first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 may be formed simultaneously using the same material. Alternatively, each of the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 may be constructed as a multilayer structure including a plurality of layers.

[0177] The first gate electrode 1105 may constitute a first transistor TR1 together with the first region a and the second region b. In an embodiment, the first region a may be a source region and the second region b may be a drain region. Alternatively, the first region a may be a drain region and the second region b may be a source region. The first region a and the second region b may be doped with ions. In contrast, the region located below the first gate electrode 1105 in the active pattern 1100 may not be doped with ions. For example, the first region a and the second region b may operate as conductors. Therefore, the first transistor TR1 may generate Figure 5 is supplied to the sub-pixel structure 1200 (eg, with Figure 5The sub-pixel structure 1200 may output light based on the driving current ID corresponding to the organic light emitting diode OLED.

[0178] The first gate wiring 1110 may include a gate extension extending on the active pattern 1100 and the gate insulating layer 1160 in the second direction D2 and a gate protrusion protruding from the gate extension in the first direction D1. The gate protrusion may constitute a third transistor TR3_1 together with the fourth region d and the fifth region e. For example, the gate protrusion may be used as a gate electrode of the third transistor TR3_1. The first portion of the gate extension may constitute a third transistor TR3_2 together with the second region b and the fifth region e, and the second portion of the gate extension may constitute a second transistor TR2 together with the first region a and the third region c. The third transistor TR3_1 and the third transistor TR3_2 may be connected in series and may be operated as a dual-gate transistor. For example, when the dual-gate transistor is turned off, leakage current may be reduced. Therefore, the third transistor TR3_1 and the third transistor TR3_2 may be electrically connected to each other through the fifth region e. In addition, the first transistor TR1, the second transistor TR2, and the fifth transistor TR5 may be electrically connected to each other through the first region a, and the first transistor TR1, the third transistor TR3_2, and the sixth transistor TR6 may be electrically connected to each other through the second region b.

[0179] The first region a, the second region b, the third region c, the fourth region d, and the fifth region e may be doped with ions. In contrast, the region located below the first gate wiring 1110 in the active pattern 1100 may not be doped with ions. Therefore, the first region a, the second region b, the third region c, the fourth region d, and the fifth region e may operate as conductors, and the region located below the first gate wiring 1110 in the active pattern 1100 may operate as a channel of the second transistor TR2 and a channel of the third transistors TR3_1 and TR3_2, respectively. In an embodiment, the first gate wiring 1110 may be supplied with Figure 5 The scanning signal GW.

[0180] In an embodiment, each of the third region c of the second transistor TR2, the fourth region d of the third transistor TR3_1, and the fifth region e of the third transistor TR3_2 may be a source region, and each of the first region a of the second transistor TR2, the fifth region e of the third transistor TR3_1, and the second region b of the third transistor TR3_2 may be a drain region. Alternatively, each of the third region c of the second transistor TR2, the fourth region d of the third transistor TR3_1, and the fifth region e of the third transistor TR3_2 may be a drain region, and each of the first region a of the second transistor TR2, the fifth region e of the third transistor TR3_1, and the second region b of the third transistor TR3_2 may be a source region.

[0181] The second gate wiring 1115 may extend along the second direction D2 on the active pattern 1100 and the gate insulating layer 1160. The second gate wiring 1115 may constitute the seventh transistor TR7 together with the sixth region f and the tenth region j, may constitute the fourth transistor TR4_2 together with the sixth region f and the seventh region g, and may constitute the fourth transistor TR4_1 together with the seventh region g and the fourth region d. The fourth transistor TR4_1 and the fourth transistor TR4_2 may be connected in series and may operate as a dual-gate transistor. For example, when the dual-gate transistor is turned off, leakage current may be reduced. Therefore, the fourth transistor TR4_1 and the fourth transistor TR4_2 may be electrically connected to each other through the seventh region g. In addition, the seventh transistor TR7 and the fourth transistor TR4_2 may be electrically connected to each other through the sixth region f, and the tenth region j may be electrically connected to the ninth region i of the active pattern 1100 disposed in the sub-pixel circuit region 50 adjacent to each other along the first direction D1.

[0182] The fourth region d, the sixth region f, the seventh region g, and the tenth region j may be doped with ions. In contrast, the region located below the second gate wiring 1115 in the active pattern 1100 may not be doped with ions. Therefore, the fourth region d, the sixth region f, the seventh region g, and the tenth region j may operate as conductors, and the region located below the second gate wiring 1115 in the active pattern 1100 may operate as a channel of the fourth transistor TR4_1, a channel of the fourth transistor TR4_2, and a channel of the seventh transistor TR7, respectively. In an embodiment, the second gate wiring 1115 may be supplied with Figure 5 The sixth region f may be supplied with a data initialization signal GI. Figure 5 The initialization voltage VINT.

[0183] In an embodiment, each of the tenth region j of the seventh transistor TR7, the sixth region f of the fourth transistor TR4_2, and the seventh region g of the fourth transistor TR4_1 may be a source region, and each of the sixth region f of the seventh transistor TR7, the seventh region g of the fourth transistor TR4_2, and the fourth region d of the fourth transistor TR4_1 may be a drain region. Alternatively, each of the tenth region j of the seventh transistor TR7, the sixth region f of the fourth transistor TR4_2, and the seventh region g of the fourth transistor TR4_1 may be a drain region, and each of the sixth region f of the seventh transistor TR7, the seventh region g of the fourth transistor TR4_2, and the fourth region d of the fourth transistor TR4_1 may be a source region.

[0184] The third gate wiring 1120 may constitute a fifth transistor TR5 together with the first region a and the eighth region h, and may constitute a sixth transistor TR6 together with the second region b and the ninth region i. The first region a, the second region b, the eighth region h, and the ninth region i may be doped with ions. In contrast, the region located below the third gate wiring 1120 in the active pattern 1100 may not be doped with ions. Therefore, the first region a, the second region b, the eighth region h, and the ninth region i may operate as conductors, and the region located below the third gate wiring 1120 in the active pattern 1100 may operate as a channel of the fifth transistor TR5 and a channel of the sixth transistor TR6, respectively. In an embodiment, the third gate wiring 1120 may be supplied with Figure 5 The emission control signal EM.

[0185] In an embodiment, each of the eighth region h of the fifth transistor TR5 and the ninth region i of the sixth transistor TR6 may be a source region, and each of the first region a of the fifth transistor TR5 and the second region b of the sixth transistor TR6 may be a drain region. Alternatively, each of the eighth region h of the fifth transistor TR5 and the ninth region i of the sixth transistor TR6 may be a drain region, and each of the first region a of the fifth transistor TR5 and the second region b of the sixth transistor TR6 may be a source region.

[0186] Reference Fig.14 and Fig.16 The organic light-emitting display device 100 may further include a first interlayer insulating layer 1190 , a second gate electrode 1130 , a conductive pattern 1150 , and an initialization voltage wiring 1140 .

[0187] The first interlayer insulating layer 1190 may be disposed on the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120. The first interlayer insulating layer 1190 may cover the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 on the gate insulating layer 1160, and may be disposed over the entire gate insulating layer 1160. For example, the first interlayer insulating layer 1190 may sufficiently cover the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 on the gate insulating layer 1160, and may have a substantially flat top surface without generating steps around the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120. Alternatively, the first interlayer insulating layer 1190 may cover the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120 on the gate insulating layer 1160, and may be provided to have a uniform thickness along the contours of the first gate electrode 1105, the first gate wiring 1110, the second gate wiring 1115, and the third gate wiring 1120. The first interlayer insulating layer 1190 may include a silicon compound, a metal oxide, or the like.

[0188] The second gate electrode 1130, the conductive pattern 1150 and the initialization voltage wiring 1140 may be disposed on the first interlayer insulating layer 1190. In other words, the second gate electrode 1130, the conductive pattern 1150 and the initialization voltage wiring 1140 may be disposed on the same layer. Each of the second gate electrode 1130, the conductive pattern 1150 and the initialization voltage wiring 1140 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination. The second gate electrode 1130, the conductive pattern 1150 and the initialization voltage wiring 1140 may be formed simultaneously using the same material. Alternatively, each of the second gate electrode 1130, the conductive pattern 1150 and the initialization voltage wiring 1140 may be constructed as a multilayer structure including a plurality of layers.

[0189] The second gate electrode 1130 may extend along the second direction D2 on the first interlayer insulating layer 1190. The second gate electrode 1130 may overlap the first gate electrode 1105. Therefore, the second gate electrode 1130 may constitute a Figure 5 The second gate electrode 1130 may be supplied with Figure 5 In addition, the second gate electrode 1130 may have an opening exposing a portion of the first gate electrode 1105. The first gate electrode 1105 may be supplied with a first connection pattern 1230 described later through the opening. Figure 5 The initialization voltage VINT.

[0190] The initialization voltage wiring 1140 may extend in the second direction D2 on the first interlayer insulating layer 1190. The initialization voltage wiring 1140 may overlap the tenth region j, and may provide the initialization voltage VINT to the sixth region f through a second connection pattern 1430 described below.

[0191] The conductive pattern 1150 may be arranged to overlap at least a portion of the fourth region d and at least a portion of the third region c. For example, the conductive pattern 1150 may overlap the fourth region d of the sub-pixel circuit region 50 and the third region c of the sub-pixel circuit region 50 adjacently positioned along the second direction D2. In other words, when viewed from a top view of the organic light-emitting display device 100, the conductive pattern 1150 may be inserted between the first gate wiring 1110 and the second gate wiring 1115 and extend in the second direction D2, and the conductive pattern 1150 may not overlap the first gate wiring 1110 and the second gate wiring 1115. Therefore, the conductive pattern 1150 may constitute a parasitic capacitor together with at least a portion of the fourth region d and at least a portion of the third region c. In addition, the conductive pattern 1150 may be arranged to overlap at least a portion of the fifth region e. In other words, the conductive pattern 1150 may be arranged to overlap at least a portion of the third region c, at least a portion of the fourth region d, and at least a portion of the fifth region e. The conductive pattern 1150 may be supplied with a high power supply voltage through a high power supply voltage wiring 1290 described later. Figure 5 The high power supply voltage ELVDD.

[0192] Reference Fig.15 and Fig.16 The organic light-emitting display device 100 may further include a second interlayer insulating layer 1195, a high power supply voltage wiring 1290, a data wiring 1191, a first connection pattern 1230, a second connection pattern 1430 and a third connection pattern 1390, a first planarization layer 1270, and the like.

[0193] The second interlayer insulating layer 1195 may be disposed on the second gate electrode 1130, the conductive pattern 1150, and the initialization voltage wiring 1140. The second interlayer insulating layer 1195 may cover the second gate electrode 1130, the conductive pattern 1150, and the initialization voltage wiring 1140 on the first interlayer insulating layer 1190, and may be disposed over the entire first interlayer insulating layer 1190. For example, the second interlayer insulating layer 1195 may sufficiently cover the second gate electrode 1130, the conductive pattern 1150, and the initialization voltage wiring 1140 on the first interlayer insulating layer 1190, and may have a substantially flat top surface without generating steps around the second gate electrode 1130, the conductive pattern 1150, and the initialization voltage wiring 1140. Alternatively, the second interlayer insulating layer 1195 may cover the second gate electrode 1130, the conductive pattern 1150, and the initialization voltage wiring 1140 on the first interlayer insulating layer 1190, and may be provided to have a uniform thickness along the contours of the second gate electrode 1130 and the initialization voltage wiring 1140. The second interlayer insulating layer 1195 may include a silicon compound, a metal oxide, or the like.

[0194] The high power supply voltage wiring 1290, the data wiring 1191, the first connection pattern 1230, the second connection pattern 1430, and the third connection pattern 1390 may be disposed on the second interlayer insulating layer 1195. In other words, the high power supply voltage wiring 1290, the data wiring 1191, the first connection pattern 1230, the second connection pattern 1430, and the third connection pattern 1390 may be disposed on the same layer. Each of the high power supply voltage wiring 1290, the data wiring 1191, the first connection pattern 1230, the second connection pattern 1430, and the third connection pattern 1390 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination. The high power supply voltage wiring 1290, the data wiring 1191, the first connection pattern 1230, the second connection pattern 1430, and the third connection pattern 1390 may be formed simultaneously using the same material. Alternatively, each of the high power voltage wiring 1290 , the data wiring 1191 , the first connection pattern 1230 , the second connection pattern 1430 , and the third connection pattern 1390 may be configured as a multi-layer structure including a plurality of layers.

[0195] The data wiring 1191 may extend in the first direction D1 on the second interlayer insulating layer 1195 and may be connected to the third region c of the active pattern 1100 through the contact hole 1210. The data wiring 1191 may be supplied with Figure 5 Therefore, the data wiring 1191 may supply the data signal DATA to the third region c of the active pattern 1100 through the contact hole 1210. The voltage level of the data signal DATA may be changed to represent a gray scale.

[0196] The high power supply voltage wiring 1290 may extend in the first direction D1 on the second interlayer insulating layer 1195 while being separated from the data wiring 1191, may be connected to the eighth region h of the active pattern 1100 through the contact hole 1355, and may be connected to the second gate electrode 1130 through the contact hole 1360. The high power supply voltage wiring 1290 may be supplied with Figure 5 Therefore, the high power voltage wiring 1290 may supply the high power voltage ELVDD to the eighth region h of the active pattern 1100 through the contact hole 1355 , and supply the high power voltage ELVDD to the second gate electrode 1130 through the contact hole 1360 .

[0197] The first connection pattern 1230 may extend in the first direction D1 on the second interlayer insulating layer 1195, and may overlap a portion of the fourth region d of the active pattern 1100 and a portion of the first gate electrode 1105 exposed through the opening of the second gate electrode. The first connection pattern 1230 may be connected to the fourth region d of the active pattern 1100 through the contact hole 1250, and may be connected to the first gate electrode 1105 through the contact hole 1271. The fourth region d of the active pattern 1100 may be supplied with an initialization voltage VINT, and the initialization voltage VINT may be applied to the first gate electrode 1105 through the first connection pattern 1230.

[0198] The second connection pattern 1430 may be disposed on the second interlayer insulating layer 1195 to overlap a portion of the initialization voltage wiring 1140 and a portion of the sixth region f of the active pattern 1100. The second connection pattern 1430 may be connected to the initialization voltage wiring 1140 through the contact hole 1475, and may be connected to the sixth region f of the active pattern 1100 through the contact hole 1470. The initialization voltage VINT may be supplied to the sixth region f of the active pattern 1100 through the second connection pattern 1430.

[0199] The third connection pattern 1390 may be disposed on the second interlayer insulating layer 1195 to overlap the ninth region i of the active pattern 1100. The third connection pattern 1390 may be connected to the ninth region i of the active pattern 1100 through the contact hole 1410, may be electrically connected to the lower electrode 1291, and may supply a driving current ID to the lower electrode 1291.

[0200] The first planarization layer 1270 may be disposed on the second interlayer insulating layer 1195, the high power voltage wiring 1290, the data wiring 1191, the first connection pattern 1230, the second connection pattern 1430, and the third connection pattern 1390. The first planarization layer 1270 may have a contact hole exposing a portion of the third connection pattern 1390 connected to the sixth transistor TR6. The first planarization layer 1270 may be disposed to have a relatively thick thickness to sufficiently cover the high power voltage wiring 1290, the data wiring 1191, the first connection pattern 1230, the second connection pattern 1430, and the third connection pattern 1390 on the second interlayer insulating layer 1195. In this case, the first planarization layer 1270 may have a substantially flat top surface, and a planarization process may be added to the first planarization layer 1270 to achieve the above-mentioned flat top surface of the first planarization layer 1270. The first planarization layer 1270 may include an organic material or an inorganic material. In an embodiment, the first planarization layer 1270 may include an organic material. For example, the first planarization layer 1270 may include photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, or the like.

[0201] Reference Fig.12 and Fig.16 The organic light-emitting display device 100 may further include a first right fan-out wiring 401, a connecting electrode 1395, a first horizontal dummy pattern 701, a second planarization layer 1275, a pixel defining layer 1310, a sub-pixel structure 1200, a packaging substrate 1450, etc. The sub-pixel structure 1200 may further include a lower electrode 1291, a light-emitting layer 1330, and an upper electrode 1340.

[0202] The first right fan-out wiring 401, the connecting electrode 1395 and the first horizontal dummy pattern 701 can be arranged on the first planarization layer 1270. In other words, the first right fan-out wiring 401, the connecting electrode 1395 and the first horizontal dummy pattern 701 can be arranged on the same layer. Each of the first right fan-out wiring 401, the connecting electrode 1395 and the first horizontal dummy pattern 701 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination. The first right fan-out wiring 401, the connecting electrode 1395 and the first horizontal dummy pattern 701 can be formed simultaneously using the same material. Optionally, each of the first right fan-out wiring 401, the connecting electrode 1395 and the first horizontal dummy pattern 701 can be constructed as a multilayer structure including a plurality of layers.

[0203] When viewed from a top view of the organic light-emitting display device 100, the first right fan-out wiring 401 may include a vertical extension portion extending along the first direction D1 and a horizontal extension portion extending along the second direction D2 on the first planarization layer 1270. In an embodiment, the high power supply voltage wiring 1290 may be positioned below the vertical extension portion, and a portion of the first right fan-out wiring 401 (e.g., the vertical extension portion) may overlap the high power supply voltage wiring 1290. The first right fan-out wiring 401 may be supplied with Figure 5 The data signal DATA may be transmitted to the fourth right signal wiring 524.

[0204] When viewed from a top view of the organic light-emitting display device 100, the first horizontal dummy pattern 701 may be spaced apart from the horizontal extension portion of the first right fan-out wiring 401 along the third direction D3 on the first planarization layer 1270 so as to be disposed substantially parallel to the horizontal extension portion. The first horizontal dummy patterns 701 may be spaced apart from each other and arranged in the third direction D3. In other embodiments, at least two adjacent first horizontal dummy patterns 701 among the first horizontal dummy patterns 701 may be formed integrally with each other.

[0205] The connection electrode 1395 may be disposed on a portion of the first planarization layer 1270 under which the third connection pattern 1390 is positioned. The connection electrode 1395 may be connected to the third connection pattern 1390 through a contact hole formed by removing a portion of the first planarization layer 1270, and may electrically connect the lower electrode 1291 and the third connection pattern 1390.

[0206] The second planarization layer 1275 may be disposed on the first right fan-out wiring 401, the connection electrode 1395, and the first horizontal dummy pattern 701. The second planarization layer 1275 may have a contact hole exposing a portion of the connection electrode 1395. The second planarization layer 1275 may be disposed to have a relatively thick thickness to fully cover the first right fan-out wiring 401, the connection electrode 1395, and the first horizontal dummy pattern 701 on the first planarization layer 1270. In this case, the second planarization layer 1275 may have a substantially flat top surface, and a planarization process may be added to the second planarization layer 1275 to achieve the above-mentioned flat top surface of the second planarization layer 1275. The second planarization layer 1275 may include an organic material or an inorganic material. In an embodiment, the second planarization layer 1275 may include an organic material.

[0207] The lower electrode 1291 may be disposed on the second planarization layer 1275. The lower electrode 1291 may be in direct contact with the connection electrode 1395 through the contact hole of the second planarization layer 1275, and may be electrically connected to the sixth transistor TR6 through the connection electrode 1395. Figure 5 The driving current ID of the lower electrode 1291 is 0.0447W. In an embodiment, the lower electrode 1291 may be an anode electrode. Alternatively, the lower electrode 1291 may be a cathode electrode. The lower electrode 1291 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination. The lower electrode 1291 may have a multilayer structure including a plurality of layers.

[0208] The pixel defining layer 1310 may be disposed on a portion of the lower electrode 1291 and on the second planarization layer 1275. The pixel defining layer 1310 may cover both sides of the lower electrode 1291 and may have an opening exposing a portion of the upper surface of the lower electrode 1291. The pixel defining layer 1310 may be formed of an organic material or an inorganic material. In an embodiment, the pixel defining layer 1310 may include an organic material.

[0209] The light-emitting layer 1330 may be disposed on the lower electrode 1291 exposed by the pixel defining layer 1310. The light-emitting layer 1330 may be formed using at least one of the light-emitting materials, which can emit different colored light (such as red light, green light, and blue light) according to the sub-pixel. On the contrary, the light-emitting layer 1330 may be formed by stacking a plurality of light-emitting materials that can produce light of different colors (such as red light, green light, and blue light) so that white light can be emitted as a whole. In this case, a color filter may be disposed on the light-emitting layer 1330 (for example, disposed to overlap with the light-emitting layer 1330 on the upper surface of the encapsulation substrate 1450). The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Optionally, the color filter may also include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin, a color photoresist, and the like.

[0210] The upper electrode 1340 may be disposed on the pixel defining layer 1310 and the light emitting layer 1330. The upper electrode 1340 may be disposed over the entire substrate 150 while covering the pixel defining layer 1310 and the light emitting layer 1330. In an embodiment, the upper electrode 1340 may be a cathode electrode and may be supplied with Figure 5The low power supply voltage ELVSS of the upper electrode 1340 can be provided. Optionally, the upper electrode 1340 can be an anode electrode. The upper electrode 1340 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination. Optionally, the upper electrode 1340 can be constructed as a multilayer structure including a plurality of layers. Therefore, a sub-pixel structure 1200 including a lower electrode 1291, a light-emitting layer 1330, and an upper electrode 1340 can be provided.

[0211] The encapsulation substrate 1450 may be disposed on the upper electrode 1340. The encapsulation substrate 1450 may include a material substantially the same as that of the substrate 150. For example, the encapsulation substrate 1450 may include a quartz substrate, a synthetic quartz substrate, a fluorine-doped (F-doped) quartz substrate, a soda-lime glass substrate, an alkali-free glass substrate, etc. In other embodiments, the encapsulation substrate 1450 may be formed of a transparent inorganic material or a flexible plastic. For example, the encapsulation substrate 1450 may include a transparent resin substrate having flexibility. In this case, at least one inorganic layer and at least one organic layer may be alternately stacked to improve the flexibility of the organic light-emitting display device 100. The stacked structure may include a first inorganic layer, an organic layer, and a second inorganic layer. For example, a first inorganic layer having flexibility may be disposed along the contour of the upper electrode 1340, an organic layer having flexibility may be disposed on the first inorganic layer, and a second inorganic layer having flexibility may be disposed on the organic layer. In other words, the stacked structure may correspond to a thin film encapsulation structure that is in direct contact with the upper electrode 1340.

[0212] Fig.17 It is shown Fig.11 0 is an enlarged layout diagram of area “C” of an organic light emitting display device. Fig.18 It is along Fig.17 A cross-sectional view of an organic light emitting display device taken along line II-II'.

[0213] Reference Fig.11 , Fig.17 and Fig.18 The organic light emitting display device 100 may further include a sub-vertical dummy pattern 801 and a sub-horizontal dummy pattern 901 .

[0214] The sub-vertical dummy pattern 801 and the sub-horizontal dummy pattern 901 may be disposed on the first planarization layer 1270. In other words, the sub-vertical dummy pattern 801 and the sub-horizontal dummy pattern 901 may be disposed on the same layer. Each of the sub-vertical dummy pattern 801 and the sub-horizontal dummy pattern 901 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination. The sub-vertical dummy pattern 801 and the sub-horizontal dummy pattern 901 may be formed simultaneously using the same material. Optionally, each of the sub-vertical dummy pattern 801 and the sub-horizontal dummy pattern 901 may be constructed as a multilayer structure including a plurality of layers.

[0215] When viewed from a top view of the organic light-emitting display device 100, the sub-vertical dummy pattern 801 may be separated from the vertical extension portion of the first right fan-out wiring 401 along the third direction D3 on the first planarization layer 1270 so as to be arranged substantially parallel to the vertical extension portion. The sub-vertical dummy patterns 801 may be separated from each other and arranged in the first direction D1. In an embodiment, the high power supply voltage wiring 1290 may be positioned below the sub-vertical dummy pattern 801, and the sub-vertical dummy pattern 801 may overlap with the high power supply voltage wiring 1290. Optionally, the sub-vertical dummy pattern 801 may be electrically connected to the high power supply voltage wiring 1290 (or the initialization voltage wiring 1140) through a contact hole. In this case, Figure 5 The high power voltage ELVDD may be applied to the sub-vertical dummy patterns 801. In other embodiments, at least two adjacent sub-vertical dummy patterns 801 among the sub-vertical dummy patterns 801 may be formed integrally with each other.

[0216] When viewed from a top view of the organic light-emitting display device 100, the sub-horizontal dummy pattern 901 may be spaced apart from the horizontally extending portion of the first right fan-out wiring 401 along the first direction D1 on the first planarization layer 1270 so as to be disposed substantially parallel to the horizontally extending portion. The sub-horizontal dummy patterns 901 may be spaced apart from each other and arranged in the first direction D1. In other embodiments, at least two adjacent sub-horizontal dummy patterns 901 among the sub-horizontal dummy patterns 901 may be formed integrally with each other.

[0217] Fig.19 It is shown Fig.11 0 is an enlarged layout diagram of region “D” of an organic light emitting display device. Fig. 20 It is along Fig.19 A cross-sectional view of an organic light emitting display device taken along line III-III'.

[0218] Reference Fig.11 , Fig.19 and Fig. 20The organic light-emitting display device 100 may further include a second right fan-out wiring 402 and a third vertical dummy pattern 603 .

[0219] The second right fan-out wiring 402 and the third vertical dummy pattern 603 may be arranged on the first planarization layer 1270. In other words, the second right fan-out wiring 402 and the third vertical dummy pattern 603 may be arranged on the same layer. Each of the second right fan-out wiring 402 and the third vertical dummy pattern 603 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination. The second right fan-out wiring 402 and the third vertical dummy pattern 603 may be formed simultaneously using the same material. Optionally, each of the second right fan-out wiring 402 and the third vertical dummy pattern 603 may be constructed as a multilayer structure including a plurality of layers.

[0220] When viewed from a top view of the organic light-emitting display device 100, the second right fan-out wiring 402 may include a vertical extension portion extending along the first direction D1 and a horizontal extension portion extending along the second direction D2 on the first planarization layer 1270. Figure 5 The data signal DATA may be transmitted to the second right signal wiring 522 .

[0221] When observed from a top view of the organic light-emitting display device 100, the third vertical dummy pattern 603 can be separated from the vertical extension portion of the third right fan-out wiring 403 along the first direction D1 on the first planarization layer 1270 so as to be arranged in substantially the same direction as the vertical extension portion extends. The third vertical dummy patterns 603 can be separated from each other and arranged in the first direction D1. In an embodiment, the horizontal extension portion of the second right fan-out wiring 402 and the horizontal extension portion of the first right fan-out wiring 401 can be inserted between the third vertical dummy patterns 603. In addition, the high power supply voltage wiring 1290 can be positioned below the third vertical dummy pattern 603, and a portion of the first right fan-out wiring 401 (e.g., the vertical extension portion) can overlap with the high power supply voltage wiring 1290. Optionally, the third vertical dummy pattern 603 can be electrically connected to the high power supply voltage wiring 1290 (or the initialization voltage wiring 1140) through a contact hole. In this case, Figure 5 The high power supply voltage ELVDD may be applied to the third vertical dummy pattern 603. In other embodiments, at least two adjacent third vertical dummy patterns 603 among the third vertical dummy patterns 603 may be formed integrally with each other. Even when the third vertical dummy patterns 603 are formed integrally with each other, the third vertical dummy patterns 603 do not directly contact the right fan-out wiring 400.

[0222] Fig.21 It is shown Fig.11 1 is an enlarged layout diagram of area “E” of an organic light emitting display device. Fig. 22 It is along Fig.21 A cross-sectional view of an organic light emitting display device taken along line IV-IV'.

[0223] Reference Fig.11 , Fig.21 and Fig. 22 The organic light-emitting display device 100 may further include a third right fan-out wiring 403 and a fourth horizontal dummy pattern 704 .

[0224] The third right fan-out wiring 403 and the fourth horizontal dummy pattern 704 may be arranged on the first planarization layer 1270. In other words, the third right fan-out wiring 403 and the fourth horizontal dummy pattern 704 may be arranged on the same layer. Each of the third right fan-out wiring 403 and the fourth horizontal dummy pattern 704 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination. The third right fan-out wiring 403 and the fourth horizontal dummy pattern 704 may be formed simultaneously using the same material. Optionally, each of the third right fan-out wiring 403 and the fourth horizontal dummy pattern 704 may be constructed as a multilayer structure including a plurality of layers.

[0225] When viewed from a top view of the organic light-emitting display device 100, the third right fan-out wiring 403 may include a vertical extension portion extending along the first direction D1 and a horizontal extension portion extending along the second direction D2 on the first planarization layer 1270. In an embodiment, the high power supply voltage wiring 1290 may be positioned below the vertical extension portion, and a portion (e.g., the vertical extension portion) of the third right fan-out wiring 403 may overlap with the high power supply voltage wiring 1290. The third right fan-out wiring 403 may be supplied with Figure 5 The data signal DATA may be transmitted to the third right signal wiring 523 .

[0226] When viewed from a top view of the organic light-emitting display device 100, the fourth horizontal dummy pattern 704 may be spaced apart from the horizontally extending portion of the fourth right fan-out wiring 404 along the third direction D3 on the first planarization layer 1270 so as to be disposed substantially in the same direction as the horizontally extending portion extends. The fourth horizontal dummy patterns 704 may be spaced apart from each other and arranged in the third direction D3.

[0227] In an embodiment, the vertical extension portion of the first right fan-out wiring 401, the vertical extension portion of the second right fan-out wiring 402, and the vertical extension portion of the third right fan-out wiring 403 may be interposed between the fourth horizontal dummy patterns 704. In other embodiments, at least two adjacent fourth horizontal dummy patterns 704 among the fourth horizontal dummy patterns 704 may be formed integrally with each other. Even when the fourth horizontal dummy patterns 704 are formed integrally with each other, the fourth horizontal dummy patterns 704 do not directly contact the right fan-out wiring 400.

[0228] Therefore, at least one of the vertical dummy pattern, the horizontal dummy pattern, the sub vertical dummy pattern, and the sub horizontal dummy pattern may be provided in each of the sub pixel circuit regions 50. In addition, the dummy pattern 600 may have a grid shape in the display region 40 through the vertical dummy pattern, the horizontal dummy pattern, the sub vertical dummy pattern, and the sub horizontal dummy pattern in each of the sub pixel circuit regions 50.

[0229] The organic light-emitting display device 100 according to an embodiment of the present invention includes the dummy pattern 600, so that the dummy pattern 600 can have a grid pattern shape in the display area 40 together with the right fan-out wiring 400 and the left fan-out wiring 500. Therefore, the pattern and / or spot caused by the bent portion of the right fan-out wiring 400 and the bent portion of the left fan-out wiring 500 may not be visually recognized in the organic light-emitting display device 100. In addition, when the dummy pattern 600 is electrically connected to the high power supply voltage wiring 1290 through the contact hole, the wiring resistance of the high power supply voltage wiring 1290 can be reduced. In addition, a constant voltage is applied to the dummy pattern 600, so that the wiring with a varying voltage level can be shielded.

[0230] Fig.23 is a plan view showing an organic light emitting display device according to an embodiment of the present invention. Fig.24 It is shown Fig.23 In addition to the shape of the right fan-out wiring 400 and the shape of the left fan-out wiring 500, Fig.23 and Fig.24 The organic light emitting display device 900 shown in FIG. 1 may have the same Figures 1 to 22 The configuration of the organic light emitting display device 100 described above is substantially the same or similar. Fig.23 and Fig.24 In the Figures 1 to 22 The components described are substantially the same or similar components. For example, for ease of description, Fig.23 Only the right fan-out wiring 400, the left fan-out wiring 500 and the dummy pattern 600 are shown in the display area 40 of FIG. Fig.24Only the right fan-out wiring 400 and the dummy pattern 600 are shown in the display area 40 of FIG.

[0231] Reference Figure 6 , Fig.23 and Fig.24 , the right fan-out wiring 400 , the left fan-out wiring 500 , and the dummy pattern 600 may be disposed on the central signal wiring 510 , the right signal wiring 520 , and the left signal wiring 530 .

[0232] The right fan-out wiring 400 may be arranged on the substrate in a portion of the pad area 60, in the first sub-display area 10, and in the second sub-display area 20, and each of the right fan-out wirings 400 may include a bent portion. For example, each of the right fan-out wirings 400 may include a vertical extension, a horizontal extension, and a sub-vertical extension. The vertical extension may be arranged in a portion of the pad area 60 and in the first sub-display area 10, and may extend in the first direction D1. In addition, the horizontal extension may extend along the second direction D2 from the first end of the vertical extension positioned in the first sub-display area 10. For example, the second end of the vertical extension may be positioned in the pad area 60, and the first end of the vertical extension opposite to the second end may be connected to the first end of the horizontal extension. The second end of the horizontal extension opposite to the first end may be connected to the sub-vertical extension. The sub-vertical extension may extend along the fourth direction D4 from the second end of the horizontal extension positioned in the second sub-display area 20. For example, a first end of the sub-vertical extension may be connected to a second end of the horizontal extension, and a second end of the sub-vertical extension opposite to the first end may be connected to one of the right signal wirings 520 through a contact hole.

[0233] In an embodiment, the vertical extension portion may be substantially parallel to the sub-vertical extension portion, and the length of the vertical extension portion in the first direction D1 may be longer than the length of the sub-vertical extension portion in the first direction D1. In addition, the contact hole of the right fan-out wiring 400 may be positioned at the lower end of the second sub-display area 20 (e.g., a portion of the second sub-display area 20 adjacent to the pad area 60), and the contact hole of the left fan-out wiring 500 may be positioned at the lower end of the third sub-display area 30. The organic light-emitting display device 900 may also include a black matrix covering the contact hole disposed at the lower end of each of the second sub-display area 20 and the third sub-display area 30. In this case, the contact hole may not be visually recognized by a user of the organic light-emitting display device 900.

[0234] like Fig.24As shown in , the right fan-out wiring 400 may include first to fourth right fan-out wirings 401, 402, 403, and 404. The first right fan-out wiring 401 may be connected to the first right signal wiring 521 through the first contact hole 721, the second right fan-out wiring 402 may be connected to the second right signal wiring 522 through the second contact hole 722, the third right fan-out wiring 403 may be connected to the third right signal wiring 523 through the third contact hole 723, and the fourth right fan-out wiring 404 may be connected to the fourth right signal wiring 524 through the fourth contact hole 724. The sizes of the first to fourth right fan-out wirings 401, 402, 403, and 404 may be sequentially reduced.

[0235] In an embodiment, in each of the right fan-out wirings 400, a bend may be defined by a first end of a vertical extension and a first end of a horizontal extension, and a second end of a horizontal extension and a first end of a sub-vertical extension, and the vertical extension, the horizontal extension, and the sub-vertical extension may be formed integrally with each other. Optionally, the right fan-out wiring 400 may not be disposed in the pad region 60.

[0236] The left fan-out wiring 500 may be arranged on the substrate in a portion of the pad area 60, in the first sub-display area 10, and in the third sub-display area 30, and each of the left fan-out wirings 500 may include a bent portion. For example, each of the left fan-out wirings 500 may include a vertical extension, a horizontal extension, and a sub-vertical extension. The vertical extension may be arranged in a portion of the pad area 60 and in the first sub-display area 10, and may extend in the first direction D1. In addition, the horizontal extension may extend from the first end of the vertical extension positioned in the first sub-display area 10 along the third direction D3. For example, the second end of the vertical extension may be positioned in the pad area 60, and the first end of the vertical extension opposite to the second end may be connected to the first end of the horizontal extension. The second end of the horizontal extension opposite to the first end may be connected to the sub-vertical extension. The sub-vertical extension may extend from the second end of the horizontal extension positioned in the third sub-display area 30 along the fourth direction D4. For example, a first end of the sub-vertical extension may be connected to a second end of the horizontal extension, and a second end of the sub-vertical extension opposite to the first end may be connected to one of the left signal wirings 530 through a contact hole.

[0237] For example, the left fan-out wiring 500 may include first to fourth left fan-out wirings. The first left fan-out wiring may be connected to the first left signal wiring through a fifth contact hole, the second left fan-out wiring may be connected to the second left signal wiring through a sixth contact hole, the third left fan-out wiring may be connected to the third left signal wiring through a seventh contact hole, and the fourth left fan-out wiring may be connected to the fourth left signal wiring through an eighth contact hole. The sizes of the first to fourth left fan-out wirings may be sequentially reduced.

[0238] In an embodiment, in each of the left fan-out wirings 500, the bend may be defined by the first end of the vertical extension and the first end of the horizontal extension, and the second end of the horizontal extension and the first end of the sub-vertical extension, and the vertical extension, the horizontal extension, and the sub-vertical extension may be formed integrally with each other. In addition, the right fan-out wiring 400 may be symmetrical with the left fan-out wiring 500. Optionally, the left fan-out wiring 500 may not be provided in the pad area 60.

[0239] The dummy pattern 600 may be separated from the right fan-out wiring 400 and the left fan-out wiring 500 in the first sub-display area 10, the second sub-display area 20, and the third sub-display area 30. The dummy pattern 600 may have a grid shape. The dummy pattern 600 may include a plurality of vertical dummy patterns, a plurality of horizontal dummy patterns, a plurality of sub-vertical dummy patterns, and a plurality of sub-horizontal dummy patterns.

[0240] The vertical dummy patterns of the dummy patterns 600 may be separated from the vertical extension of the right fan-out wiring 400 and the vertical extension of the left fan-out wiring 500 in the first direction D1, and may be arranged to be separated from each other in the first direction D1. The horizontal dummy patterns of the dummy patterns 600 may be separated from the horizontal extension of the right fan-out wiring 400 in the third direction D3 and the second direction D2, and may be arranged to be separated from each other in the third direction D3 and the second direction D2. In addition, the horizontal dummy patterns of the dummy patterns 600 may be separated from the horizontal extension of the left fan-out wiring 500 in the second direction D2 and the third direction D3, and may be arranged to be separated from each other in the second direction D2 and the third direction D3.

[0241] For example, Fig.24 As shown in , the vertical dummy patterns may include first to eighth vertical dummy patterns 601 , 602 , 603 , 604 , 605 , 606 , 607 , and 608 , and the horizontal dummy patterns may include first to fourth horizontal dummy patterns 701 , 702 , 703 , and 704 .

[0242] The first vertical dummy patterns 601 may be spaced apart from the vertically extending portions of the first right fan-out wiring 401 in the first direction D1 , and may be arranged to be spaced apart from each other in the first direction D1 (eg, substantially the same direction in which the vertically extending portions extend).

[0243] The eighth vertical dummy pattern 608 may be spaced apart from the sub-vertical extension portion of the first right fan-out wiring 401 in the first direction D1 , and may be arranged to be spaced apart from each other in the first direction D1 (eg, substantially the same direction as the direction in which the sub-vertical extension portion extends).

[0244] The second vertical dummy patterns 602 may be spaced apart from the vertically extending portion of the second right fan-out wiring 402 in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertically extending portion extends). The second vertical dummy patterns 602 may be spaced apart from the horizontally extending portion of the first right fan-out wiring 401. In other words, the horizontally extending portion of the first right fan-out wiring 401 may be interposed between the second vertical dummy patterns 602.

[0245] The seventh vertical dummy pattern 607 may be spaced apart from the sub-vertical extension portion of the second right fan-out wiring 402 in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the sub-vertical extension portion extends). The seventh vertical dummy pattern 607 may be spaced apart from the horizontal extension portion of the first right fan-out wiring 401. In other words, the horizontal extension portion of the first right fan-out wiring 401 may be interposed between the seventh vertical dummy patterns 607.

[0246] The third vertical dummy pattern 603 may be separated from the vertical extension portion of the third right fan-out wiring 403 in the first direction D1, and may be arranged to be separated from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertical extension portion extends). The third vertical dummy pattern 603 may be separated from the horizontal extension portion of the first right fan-out wiring 401 and the horizontal extension portion of the second right fan-out wiring 402. In other words, the horizontal extension portion of the first right fan-out wiring 401 and the horizontal extension portion of the second right fan-out wiring 402 may be interposed between the third vertical dummy pattern 603.

[0247] The sixth vertical dummy pattern 606 may be separated from the sub-vertical extension portion of the third right fan-out wiring 403 in the first direction D1, and may be arranged to be separated from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the sub-vertical extension portion extends). The sixth vertical dummy pattern 606 may be separated from the horizontal extension portion of the first right fan-out wiring 401 and the horizontal extension portion of the second right fan-out wiring 402. In other words, the horizontal extension portion of the first right fan-out wiring 401 and the horizontal extension portion of the second right fan-out wiring 402 may be interposed between the sixth vertical dummy pattern 606.

[0248] The fourth vertical dummy pattern 604 may be separated from the vertical extension portion of the fourth right fan-out wiring 404 in the first direction D1, and may be arranged to be separated from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertical extension portion extends). The fourth vertical dummy pattern 604 may be separated from the horizontal extension portion of the first right fan-out wiring 401, the horizontal extension portion of the second right fan-out wiring 402, and the horizontal extension portion of the third right fan-out wiring 403. In other words, the horizontal extension portion of the first right fan-out wiring 401, the horizontal extension portion of the second right fan-out wiring 402, and the horizontal extension portion of the third right fan-out wiring 403 may be interposed between the fourth vertical dummy pattern 604.

[0249] The fifth vertical dummy pattern 605 may be separated from the sub-vertical extension portion of the fourth right fan-out wiring 404 in the first direction D1, and may be arranged to be separated from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the sub-vertical extension portion extends). The fifth vertical dummy pattern 605 may be separated from the horizontal extension portion of the first right fan-out wiring 401, the horizontal extension portion of the second right fan-out wiring 402, and the horizontal extension portion of the third right fan-out wiring 403. In other words, the horizontal extension portion of the first right fan-out wiring 401, the horizontal extension portion of the second right fan-out wiring 402, and the horizontal extension portion of the third right fan-out wiring 403 may be interposed between the fifth vertical dummy pattern 605.

[0250] The first horizontal dummy pattern 701 may be spaced apart from the horizontally extending portion of the first right fan-out wiring 401 in the third direction D3, and may be arranged to be spaced apart from each other in the third direction D3. Optionally, the first horizontal dummy pattern 701 may further include horizontal dummy patterns spaced apart from the horizontally extending portion of the first right fan-out wiring 401 in the second direction D2 and arranged to be spaced apart from each other in the second direction D2. Fig.24 One horizontal dummy pattern 701 is shown in FIG. 4 , however, at least two first horizontal dummy patterns 701 may be disposed between the sub-vertical dummy pattern 801 and the first right fan-out wiring 401 .

[0251] The second horizontal dummy pattern 702 may be separated from the horizontal extension portion of the second right fan-out wiring 402 in the third direction D3 and the second direction D2, and may be arranged to be separated from each other in the third direction D3 and the second direction D2. The second horizontal dummy pattern 702 may be separated from the vertical extension portion and the sub-vertical extension portion of the first right fan-out wiring 401. In other words, the vertical extension portion and the sub-vertical extension portion of the first right fan-out wiring 401 may be interposed between the second horizontal dummy patterns 702.

[0252] The third horizontal dummy pattern 703 may be separated from the horizontal extension portion of the third right fan-out wiring 403 in the third direction D3 and the second direction D2, and may be arranged to be separated from each other in the third direction D3 and the second direction D2. The third horizontal dummy pattern 703 may be separated from the vertical extension portion and the sub-vertical extension portion of the second right fan-out wiring 402 and the vertical extension portion and the sub-vertical extension portion of the first right fan-out wiring 401. In other words, the vertical extension portion and the sub-vertical extension portion of the second right fan-out wiring 402 and the vertical extension portion and the sub-vertical extension portion of the first right fan-out wiring 401 may be inserted between the third horizontal dummy pattern 703.

[0253] The fourth horizontal dummy pattern 704 may be separated from the horizontal extension portion of the fourth right fan-out wiring 404 in the third direction D3 and the second direction D2, and may be arranged to be separated from each other in the third direction D3 and the second direction D2. The fourth horizontal dummy pattern 704 may be separated from the vertical extension portion and the sub-vertical extension portion of the third right fan-out wiring 403, the vertical extension portion and the sub-vertical extension portion of the second right fan-out wiring 402, and the vertical extension portion and the sub-vertical extension portion of the first right fan-out wiring 401. In other words, the vertical extension portion and the sub-vertical extension portion of the third right fan-out wiring 403, the vertical extension portion and the sub-vertical extension portion of the second right fan-out wiring 402, and the vertical extension portion and the sub-vertical extension portion of the first right fan-out wiring 401 may be inserted between the fourth horizontal dummy pattern 704.

[0254] In addition, the vertical dummy patterns may further include ninth to sixteenth vertical dummy patterns, and the horizontal dummy patterns may further include fifth to eighth horizontal dummy patterns.

[0255] The ninth vertical dummy pattern may be spaced apart from the vertical extension portion of the first left fan-out wiring in the first direction D1 , and may be arranged to be spaced apart from each other in the first direction D1 (eg, substantially the same direction as the direction in which the vertical extension portion extends).

[0256] The sixteenth vertical dummy pattern may be spaced apart from the sub-vertical extension portion of the first left fan-out wiring in the first direction D1 , and may be arranged to be spaced apart from each other in the first direction D1 (eg, substantially the same direction as the sub-vertical extension portion extends).

[0257] The tenth vertical dummy pattern may be spaced apart from the vertical extension portion of the second left fan-out wiring in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertical extension portion extends). The tenth vertical dummy pattern may be spaced apart from the horizontal extension portion of the first left fan-out wiring. In other words, the horizontal extension portion of the first left fan-out wiring may be interposed between the tenth vertical dummy patterns.

[0258] The fifteenth vertical dummy pattern may be spaced apart from the sub-vertical extension portion of the second left fan-out wiring in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the sub-vertical extension portion extends). The fifteenth vertical dummy pattern may be spaced apart from the horizontal extension portion of the first left fan-out wiring. In other words, the horizontal extension portion of the first left fan-out wiring may be interposed between the fifteenth vertical dummy patterns.

[0259] The eleventh vertical dummy pattern may be spaced apart from the vertical extension portion of the third left fan-out wiring in the first direction D1, and may be arranged to be spaced apart from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertical extension portion extends). The eleventh vertical dummy pattern may be spaced apart from the horizontal extension portion of the first left fan-out wiring and the horizontal extension portion of the second left fan-out wiring. In other words, the horizontal extension portion of the first left fan-out wiring and the horizontal extension portion of the second left fan-out wiring may be interposed between the eleventh vertical dummy pattern.

[0260] The fourteenth vertical dummy pattern may be separated from the sub-vertical extension portion of the third left fan-out wiring in the first direction D1, and may be arranged to be separated from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the sub-vertical extension portion extends). The fourteenth vertical dummy pattern may be separated from the horizontal extension portion of the first left fan-out wiring and the horizontal extension portion of the second left fan-out wiring. In other words, the horizontal extension portion of the first left fan-out wiring and the horizontal extension portion of the second left fan-out wiring may be interposed between the fourteenth vertical dummy pattern.

[0261] The twelfth vertical dummy pattern may be separated from the vertical extension portion of the fourth left fan-out wiring in the first direction D1, and may be arranged to be separated from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the vertical extension portion extends). The twelfth vertical dummy pattern may be separated from the horizontal extension portion of the first left fan-out wiring, the horizontal extension portion of the second left fan-out wiring, and the horizontal extension portion of the third left fan-out wiring. In other words, the horizontal extension portion of the first left fan-out wiring, the horizontal extension portion of the second left fan-out wiring, and the horizontal extension portion of the third left fan-out wiring may be interposed between the twelfth vertical dummy pattern.

[0262] The thirteenth vertical dummy pattern may be separated from the sub-vertical extension portion of the fourth left fan-out wiring in the first direction D1, and may be arranged to be separated from each other in the first direction D1 (e.g., a direction substantially the same as the direction in which the sub-vertical extension portion extends). The thirteenth vertical dummy pattern may be separated from the horizontal extension portion of the first left fan-out wiring, the horizontal extension portion of the second left fan-out wiring, and the horizontal extension portion of the third left fan-out wiring. In other words, the horizontal extension portion of the first left fan-out wiring, the horizontal extension portion of the second left fan-out wiring, and the horizontal extension portion of the third left fan-out wiring may be interposed between the thirteenth vertical dummy pattern.

[0263] The fifth horizontal dummy pattern may be spaced apart from the horizontally extending portion of the first left fan-out wiring in the third direction D3, and may be arranged to be spaced apart from each other in the third direction D3. Optionally, the fifth horizontal dummy pattern may further include horizontal dummy patterns spaced apart from the horizontally extending portion of the first left fan-out wiring in the second direction D2 and arranged to be spaced apart from each other in the second direction D2. Fig.23 One fifth horizontal dummy pattern is shown in FIG. 8 , however, at least two fifth horizontal dummy patterns may be disposed between the sub-vertical dummy pattern 801 and the first left fan-out wiring.

[0264] The sixth horizontal dummy pattern may be spaced apart from the horizontal extension portion of the second left fan-out wiring in the second direction D2 and the third direction D3, and may be arranged to be spaced apart from each other in the second direction D2 and the third direction D3. The sixth horizontal dummy pattern may be spaced apart from the vertical extension portion and the sub-vertical extension portion of the first left fan-out wiring. In other words, the vertical extension portion and the sub-vertical extension portion of the first left fan-out wiring may be interposed between the sixth horizontal dummy patterns.

[0265] The seventh horizontal dummy pattern may be separated from the horizontal extension portion of the third left fan-out wiring in the second direction D2 and the third direction D3, and may be arranged to be separated from each other in the second direction D2 and the third direction D3. The seventh horizontal dummy pattern may be separated from the vertical extension portion and the sub-vertical extension portion of the second left fan-out wiring and the vertical extension portion and the sub-vertical extension portion of the first left fan-out wiring. In other words, the vertical extension portion and the sub-vertical extension portion of the second left fan-out wiring and the vertical extension portion and the sub-vertical extension portion of the first left fan-out wiring may be inserted between the seventh horizontal dummy pattern.

[0266] The eighth horizontal dummy pattern may be separated from the horizontal extension portion of the fourth left fan-out wiring in the second direction D2 and the third direction D3, and may be arranged to be separated from each other in the second direction D2 and the third direction D3. The eighth horizontal dummy pattern may be separated from the vertical extension portion and the sub-vertical extension portion of the third left fan-out wiring, the vertical extension portion and the sub-vertical extension portion of the second left fan-out wiring, and the vertical extension portion and the sub-vertical extension portion of the first left fan-out wiring. In other words, the vertical extension portion and the sub-vertical extension portion of the third left fan-out wiring, the vertical extension portion and the sub-vertical extension portion of the second left fan-out wiring, and the vertical extension portion and the sub-vertical extension portion of the first left fan-out wiring may be inserted between the eighth horizontal dummy pattern.

[0267] The sub-horizontal dummy patterns of the dummy pattern 600 may be spaced apart from the horizontally extending portions of the right fan-out wiring 400 and the left fan-out wiring 500 in the first direction D1, and may be arranged to be spaced apart from each other in the third direction D3. The sub-horizontal dummy patterns arranged to be spaced apart from each other in the third direction D3 may be repeatedly spaced apart from each other in the first direction D1.

[0268] For example, Fig.24 As shown in , the sub-horizontal dummy patterns 901 may be spaced apart from the horizontally extending portion of the first right fan-out wiring 401 in the first direction D1, and may be arranged to be spaced apart from each other in the third direction D3. The sub-horizontal dummy patterns 901 arranged to be spaced apart from each other in the third direction D3 may be repeatedly spaced apart from each other in the first direction D1.

[0269] The sub vertical dummy pattern may be disposed between the right fan-out wiring 400 and the left fan-out wiring 500. In other words, the sub vertical dummy pattern may be spaced apart from the right fan-out wiring 400 in the third direction D3 or spaced apart from the left fan-out wiring 500 in the second direction D2.

[0270] For example, Fig.24 As shown in , the sub-vertical dummy pattern 801 may be disposed between the right fan-out wiring 400 and the left fan-out wiring 500, and may be arranged to be spaced apart from each other in the first direction D1. The dummy pattern 600 disposed on the left side of the sub-vertical dummy pattern 801 with respect to the sub-vertical dummy pattern 801 may be symmetrical with the dummy pattern 600 disposed on the right side of the sub-vertical dummy pattern 801. In addition, the right fan-out wiring 400 and the left fan-out wiring 500 may be symmetrical with each other with respect to the sub-vertical dummy pattern 801.

[0271] As described above, the dummy pattern 600 includes a vertical dummy pattern, a horizontal dummy pattern, a sub-vertical dummy pattern, and a sub-horizontal dummy pattern, so that the dummy pattern 600 may have a grid shape in the display area 40 .

[0272] In the embodiment, although it has been described that the center signal wiring 510 includes 13 wirings, and each of the right signal wiring 520, the left signal wiring 530, the right fan-out wiring 400, and the left fan-out wiring 500 includes four wirings, the configuration of the present invention is not limited thereto.

[0273] For example, the right fan-out wiring 400 may include a first right fan-out wiring to an M-th right fan-out wiring (where M is an integer of 1 or greater), and the first right fan-out wiring to the M-th right fan-out wiring may be arranged sequentially while being separated from each other. The total length of the first right fan-out wiring to the M-th right fan-out wiring may be sequentially reduced. The K-th right fan-out wiring among the first right fan-out wiring to the M-th right fan-out wiring (where K is an integer between 1 and M) may include a vertical extension portion, a horizontal extension portion, and a sub-vertical extension portion, the vertical extension portion being arranged in the pad area 60 and the first sub-display area 10 and extending along the first direction D1, the horizontal extension portion extending from the first end of the vertical extension portion positioned in the first sub-display area 10 along the second direction D2, and the sub-vertical extension portion extending from the second end of the horizontal extension portion along a fourth direction D4 opposite to the first direction D1.

[0274] The second end of the vertical extension of the Kth right fan-out wiring may be positioned in the pad area 60, and the first end of the vertical extension of the Kth right fan-out wiring opposite to the second end may be connected to the first end of the horizontal extension. In addition, the first end of the horizontal extension may be connected to the first end of the vertical extension, and the second end of the horizontal extension opposite to the first end may be connected to the first end of the sub-vertical extension.

[0275] The right signal wiring 520 may include a first right signal wiring to an Nth right signal wiring (where N is an integer of 1 or greater), and the first right signal wiring to the Nth right signal wiring may be arranged in reverse order and separated from each other. The Mth right fan-out wiring and the Nth right signal wiring may be disposed adjacent to a boundary between the first sub-display area 10 and the second sub-display area 20.

[0276] The sub-vertical extension of the Kth right fan-out wiring among the first right fan-out wiring to the Mth right fan-out wiring may be connected to the Lth right signal wiring among the first right signal wiring to the Nth right signal wiring (where L is an integer between 1 and N) through a contact hole, where K and L may be the same integer, and the contact hole may be formed at the second end of the sub-vertical extension opposite to the first end. In other words, the contact hole may be positioned at the lower end of the second sub-display area 20.

[0277] The bending portion can be defined by the first end of the vertical extension portion and the first end of the horizontal extension portion of the Kth right fan-out wiring, and the second end of the horizontal extension portion and the first end of the sub-vertical extension portion, and the vertical extension portion, horizontal extension portion and sub-vertical extension portion of the Kth right fan-out wiring can be formed integrally with each other.

[0278] The vertical extension portion of the K th right fan-out wiring may be parallel to the sub-vertical extension portion of the K th right fan-out wiring, and a length of the vertical extension portion in the first direction D1 may be longer than a length of the sub-vertical extension portion in the first direction D1.

[0279] An empty space may be formed inside the vertical extension portion, the horizontal extension portion, and the sub-vertical extension portion of the Kth right fan-out wiring, and the empty space may have a shape concave in the first direction D1, and the K+1th right fan-out wiring from the first right fan-out wiring to the Mth right fan-out wiring may be disposed in the empty space.

[0280] The dummy pattern 600 may include first to P-th dummy patterns (where P is an integer of 1 or more). A J-th dummy pattern (where J is an integer between 1 and N) among the first to P-th dummy patterns may include a plurality of vertical dummy patterns that are spaced apart from the vertical extension of the K-th right fan-out wiring in the first direction D1 and are arranged to be spaced apart from each other in the first direction D1, and a plurality of horizontal dummy patterns that are spaced apart from the horizontal extension of the K-th right fan-out wiring in the third direction D3 and are arranged to be spaced apart from each other in the third direction D3.

[0281] The Jth dummy pattern may further include a plurality of sub-vertical dummy patterns that are separated from the vertical extension portion of the Kth right fan-out wiring in the third direction D3 and are arranged to be separated from each other in the first direction D1, and a plurality of sub-horizontal dummy patterns that are separated from the horizontal extension portion of the Kth right fan-out wiring in the first direction D1 and are arranged to be separated from each other in the third direction D3.

[0282] In addition, in the embodiment, although the dummy patterns 600 have been described as being separated from each other, the configuration of the present invention is not limited thereto. For example, in other embodiments, at least two dummy patterns 600 positioned adjacent to each other among the dummy patterns 600 may be formed integrally with each other.

[0283] The display area 40 may include a plurality of sub-pixel circuit areas 50 , and at least one of a vertical dummy pattern, a horizontal dummy pattern, a sub-vertical dummy pattern, and a sub-horizontal dummy pattern may be provided in each of the sub-pixel circuit areas 50 .

[0284] The dummy pattern 600 may have a grid shape in the display region 40 through a vertical dummy pattern, a horizontal dummy pattern, a sub-vertical dummy pattern, and a sub-horizontal dummy pattern in each of the sub-pixel circuit regions 50 .

[0285] The organic light-emitting display device 900 according to an embodiment of the present invention includes a dummy pattern 600, so that the dummy pattern 600 can realize a grid pattern shape throughout the entire display area 40 together with the right fan-out wiring 400 and the left fan-out wiring 500. In this case, the pattern and / or spot will not be visually recognized on the organic light-emitting display device 100. Therefore, the visibility of the organic light-emitting display device 100 can be relatively improved. In addition, the contact hole of the right fan-out wiring 400 is positioned at the lower end of the second sub-display area 20, and the contact hole of the left fan-out wiring 500 is positioned at the lower end of the third sub-display area 30, so that the visibility of the organic light-emitting display device 900 can be relatively improved.

[0286] The foregoing is an illustration of the embodiments and is not to be construed as limiting thereof. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Therefore, it will be understood that the foregoing is an illustration of various embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments as well as other embodiments are intended to be included within the scope of the appended claims.

[0287] Industrial Applicability

[0288] The present invention can be applied to various electronic devices including organic light-emitting display devices, for example, vehicle display devices, ship display devices, aircraft display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0289] Description of Reference Numerals

[0290] 10: First sub-display area

[0291] 20: Second sub-display area

[0292] 30: The third sub-display area

[0293] 40: Display area

[0294] 60: Pad area

[0295] 100, 900: Organic light-emitting display device

[0296] 101: External Devices

[0297] 150: Base

[0298] 400: Right fan-out routing

[0299] 401, 402, 403, 404: First right fan-out wiring to fourth right fan-out wiring

[0300] 470: Pad electrode

[0301] 500: Left fan-out routing

[0302] 510: Center signal wiring

[0303] 520: Right signal wiring

[0304] 530: Left signal wiring

[0305] 600: Fake pattern

[0306] 601, 602, 603, 604: first vertical dummy pattern to fourth vertical dummy pattern

[0307] 701, 702, 703, 704: first horizontal dummy pattern to fourth horizontal dummy pattern

[0308] 801: Sub-vertical dummy pattern

[0309] 901: Sub-level dummy pattern

[0310] 1100: Active pattern

[0311] 1105: First gate electrode

[0312] 1110: First gate wiring

[0313] 1115: Second gate wiring

[0314] 1120: Third gate wiring

[0315] 1130: Second gate electrode

[0316] 1140: Initialize voltage wiring

[0317] 1150: Conductive pattern

[0318] 1160: Gate insulation layer

[0319] 1190: First interlayer insulation layer

[0320] 1191: Data Cabling

[0321] 1195: Second interlayer insulation layer

[0322] 1200: Sub-pixel structure

[0323] 1230: First connection pattern

[0324] 1270: First planarization layer

[0325] 1275: Second planarization layer

[0326] 1290: High Supply Voltage Routing

[0327] 1291: Lower electrode

[0328] 1310: Pixel limiting layer

[0329] 1330: Luminous layer

[0330] 1340: Upper electrode

[0331] 1390: Third connection pattern

[0332] 1395: Connecting electrodes

[0333] 1430: Second connection pattern

[0334] 1475: Contact hole

Claims

1. An organic light-emitting display device, comprising: A substrate comprising: i) a display region having a first sub-display region and a second sub-display region positioned on a first side of the first sub-display region; and ii) a pad region positioned on a second side of the first sub-display region different from the first side; a plurality of right signal wirings, arranged in the second sub-display area on the substrate; a plurality of right fan-out wirings, arranged on the plurality of right signal wirings in the pad region, the first sub-display region, and the second sub-display region, the plurality of right fan-out wirings each comprising a bent portion; a plurality of dummy patterns disposed in the first sub-display region and the second sub-display region on the plurality of right signal wirings, the plurality of dummy patterns being separated from the plurality of right fan-out wirings, the plurality of dummy patterns having a grid shape; and A plurality of sub-pixel structures are arranged on the plurality of dummy patterns, The plurality of dummy patterns include a plurality of sub-horizontal dummy patterns and a plurality of sub-vertical dummy patterns, and the plurality of sub-horizontal dummy patterns and the plurality of sub-vertical dummy patterns are spaced apart from each other in a plan view.

2. The organic light emitting display device according to claim 1, wherein: Each of the plurality of right fan-out routings comprises: A vertical extension portion disposed in the pad area and the first sub-display area and extending along a first direction; and The horizontal extension portion extends from a first end of the vertical extension portion located in the first sub-display area along a second direction orthogonal to the first direction.

3. The organic light emitting display device according to claim 2, wherein: The second end of the vertical extension is positioned in the pad area, and the first end of the vertical extension opposite the second end is connected to the first end of the horizontal extension.

4. The organic light emitting display device according to claim 3, wherein: A second end of the horizontal extension portion opposite to the first end is connected to one of the plurality of right signal wirings through a contact hole.

5. The organic light emitting display device according to claim 4, wherein: The bent portion is defined by the first end of the vertically extending portion and the first end of the horizontally extending portion.

6. The organic light emitting display device according to claim 2, wherein: The vertically extending portion and the horizontally extending portion are formed integrally with each other.

7. The organic light emitting display device according to claim 4, wherein: Each of the plurality of right fan-out wirings further includes a sub-vertical extending portion extending from a second end of the horizontal extending portion in a fourth direction opposite to the first direction.

8. The organic light emitting display device according to claim 7, wherein: The first end of the horizontal extending portion is connected to the first end of the vertical extending portion, and the second end of the horizontal extending portion opposite to the first end is connected to the first end of the sub-vertical extending portion.

9. The organic light emitting display device according to claim 8, wherein: A second end of the sub-vertical extension, opposite to the first end, is connected to one of the plurality of right signal wires through a contact hole.

10. The organic light emitting display device according to claim 9, wherein: The bent portion is defined by i) the first end of the vertically extending portion and the first end of the horizontally extending portion and ii) the second end of the horizontally extending portion and the first end of the sub-vertically extending portion.

11. The organic light emitting display device according to claim 7, wherein: The vertical extending portion, the horizontal extending portion, and the sub-vertical extending portion are formed integrally with each other.

12. The organic light emitting display device according to claim 7, wherein: The vertical extension portion is parallel to the sub-vertical extension portion, and a length of the vertical extension portion in the first direction is longer than a length of the sub-vertical extension portion in the first direction.

13. The organic light emitting display device according to claim 7, wherein: The plurality of dummy patterns further include: a plurality of vertical dummy patterns spaced apart from the vertical extending portion in the first direction, the plurality of vertical dummy patterns being arranged to be spaced apart from each other in the first direction; and A plurality of horizontal dummy patterns are spaced apart from the horizontal extending portion in a third direction opposite to the second direction, and the plurality of horizontal dummy patterns are arranged to be spaced apart from each other in the third direction.

14. The organic light emitting display device according to claim 13, wherein: The plurality of sub-vertical dummy patterns are spaced apart from the vertical extending portion in the third direction, the plurality of sub-vertical dummy patterns are arranged to be spaced apart from each other in the first direction, and The plurality of sub-horizontal dummy patterns are spaced apart from the horizontal extending portion in the first direction, and the plurality of sub-horizontal dummy patterns are arranged to be spaced apart from each other in the third direction.

15. The organic light emitting display device according to claim 14, wherein: The display area includes a plurality of sub-pixel circuit areas, and at least one of the vertical dummy pattern, the horizontal dummy pattern, the sub-vertical dummy pattern, and the sub-horizontal dummy pattern is disposed in each of the sub-pixel circuit areas.

16. The organic light emitting display device according to claim 15, wherein: The plurality of dummy patterns have a grid shape in the display area by the vertical dummy pattern, the horizontal dummy pattern, the sub-vertical dummy pattern, and the sub-horizontal dummy pattern disposed in each of the sub-pixel circuit areas.

17. The organic light emitting display device according to claim 1, further comprising: A plurality of power supply voltage wirings are arranged on the substrate in the display area, wherein: At least some of the plurality of dummy patterns are electrically connected to at least some of the plurality of power supply voltage wirings.

18. The organic light emitting display device according to claim 1, wherein: The plurality of right fan-out wirings include a first right fan-out wiring to an Mth right fan-out wiring, wherein M is an integer of 1 or more, and wherein the first right fan-out wiring to the Mth right fan-out wiring are sequentially arranged while being spaced apart from each other.

19. The organic light emitting display device according to claim 18, wherein: Lengths of the first right fan-out wiring to the Mth right fan-out wiring gradually decrease.

20. The organic light emitting display device according to claim 18, wherein: The first right fan-out wiring to the Kth right fan-out wiring among the Mth right fan-out wiring include: A vertical extension portion disposed in the pad area and the first sub-display area and extending along a first direction; and a horizontal extending portion extending from a first end of the vertical extending portion located in the first sub-display area along a second direction orthogonal to the first direction, Here, K is an integer between 1 and M.

21. The organic light emitting display device according to claim 20, wherein: A second end of the vertical extension portion of the Kth right fan-out wiring is positioned in the pad region, and a first end of the vertical extension portion of the Kth right fan-out wiring opposite to the second end is connected to the first end of the horizontal extension portion.

22. The organic light emitting display device according to claim 21, wherein: The plurality of right signal wirings include a first right signal wiring to an Nth right signal wiring, wherein N is an integer of 1 or more, and wherein the first right signal wiring to the Nth right signal wiring are arranged in reverse order and are spaced apart from each other.

23. The organic light emitting display device according to claim 22, wherein: The Mth right fan-out wiring and the Nth right signal wiring are disposed adjacent to a boundary between the first sub display area and the second sub display area.

24. The organic light emitting display device according to claim 22, wherein: The horizontal extension portion of the Kth right fan-out wiring among the first right fan-out wiring to the Mth right fan-out wiring is connected to the Lth right signal wiring among the first right signal wiring to the Nth right signal wiring through a contact hole, where L is an integer between 1 and N.

25. The organic light emitting display device according to claim 24, wherein: The bent portion is defined by the first end of the vertically extending portion of the Kth right fan-out wiring and the first end of the horizontally extending portion of the Kth right fan-out wiring.

26. The organic light emitting display device according to claim 20, wherein: The vertical extending portion and the horizontal extending portion of the Kth right fan-out wiring are integrally formed.

27. The organic light emitting display device according to claim 26, wherein: The Kth right fan-out wiring further includes: The sub-vertical extension portion extends from the second end of the horizontal extension portion along a fourth direction opposite to the first direction.

28. The organic light emitting display device according to claim 27, wherein: A first end of the horizontal extending portion is connected to the vertical extending portion, and a second end of the horizontal extending portion opposite to the first end is connected to a first end of the sub-vertical extending portion.

29. The organic light emitting display device according to claim 28, wherein: The plurality of right signal wirings include a first right signal wiring to an Nth right signal wiring, wherein N is an integer of 1 or more, and wherein the first right signal wiring to the Nth right signal wiring are arranged in reverse order and are spaced apart from each other.

30. The organic light emitting display device according to claim 29, wherein: The sub-vertical extension of the Kth right fan-out wiring among the first right fan-out wiring to the Mth right fan-out wiring is connected to the Lth right signal wiring among the first right signal wiring to the Nth right signal wiring through a contact hole, where L is an integer between 1 and N.

31. The organic light emitting display device according to claim 30, wherein: The bent portion is defined by i) a first end of the vertical extension portion of the Kth right fan-out wiring and a first end of the horizontal extension portion of the Kth right fan-out wiring and ii) a second end of the horizontal extension portion of the Kth right fan-out wiring and a first end of the sub-vertical extension portion of the Kth right fan-out wiring.

32. The organic light emitting display device according to claim 27, wherein: The vertical extending portion of the Kth right fan-out wiring, the horizontal extending portion of the Kth right fan-out wiring, and the sub-vertical extending portion of the Kth right fan-out wiring are integrally formed.

33. The organic light emitting display device according to claim 27, wherein: The vertical extension portion of the Kth right fan-out wiring is parallel to the sub-vertical extension portion of the Kth right fan-out wiring, and a length of the vertical extension portion in the first direction is longer than a length of the sub-vertical extension portion in the first direction.

34. The organic light emitting display device according to claim 27, wherein: An empty space is formed inside the vertical extension portion of the Kth right fan-out wiring, the horizontal extension portion of the Kth right fan-out wiring, and the sub-vertical extension portion of the Kth right fan-out wiring, and the empty space has a shape concave in the first direction, and Among the above-mentioned first right fan-out wiring, the K+1th right fan-out wiring among the above-mentioned Mth right fan-out wiring is arranged in the above-mentioned empty space.

35. The organic light emitting display device according to claim 27, wherein: The plurality of right signal wirings include first to Nth right signal wirings, The plurality of dummy patterns include: The first dummy pattern to the Pth dummy pattern, wherein, The Jth dummy pattern among the first to Pth dummy patterns includes: a plurality of vertical dummy patterns spaced apart from the vertically extending portion of the Kth right fan-out wiring in the first direction and arranged to be spaced apart from each other in the first direction, and a plurality of horizontal dummy patterns spaced apart from the horizontally extending portion of the Kth right fan-out wiring in a third direction opposite to the second direction and arranged to be spaced apart from each other in the third direction, wherein N is an integer of 1 or more, P is an integer of 1 or more, and J is an integer between 1 and N.

36. The organic light emitting display device according to claim 35, wherein: The Jth dummy pattern also includes: a plurality of sub-vertical dummy patterns spaced apart from the vertically extending portion of the Kth right fan-out wiring in the third direction and arranged to be spaced apart from each other in the first direction; and A plurality of sub-horizontal dummy patterns are spaced apart from the horizontally extending portion of the Kth right fan-out wiring in the first direction and are arranged to be spaced apart from each other in the third direction.

37. The organic light emitting display device according to claim 36, wherein: The display area includes a plurality of sub-pixel circuit areas, wherein at least one of the vertical dummy pattern, the horizontal dummy pattern, the sub-vertical dummy pattern, and the sub-horizontal dummy pattern is disposed in each of the sub-pixel circuit areas.

38. The organic light emitting display device according to claim 37, wherein: The plurality of dummy patterns have a grid shape in the display area by the vertical dummy pattern, the horizontal dummy pattern, the sub-vertical dummy pattern, and the sub-horizontal dummy pattern disposed in each of the plurality of sub-pixel circuit areas.

39. The organic light emitting display device according to claim 1, wherein: The substrate also includes a third sub-display area, which is positioned on a third side, and the third side is oriented to face the first side of the first sub-display area, the pad area and the first sub-display area are arranged in a first direction, and the third sub-display area, the first sub-display area and the second sub-display area are arranged in a second direction orthogonal to the first direction.

40. The organic light emitting display device according to claim 39, wherein: A width of the display area in the second direction is greater than a width of the pad area in the second direction.

41. The organic light emitting display device according to claim 40, further comprising: A plurality of pad electrodes are arranged along the second direction in the pad region.

42. The organic light emitting display device according to claim 39, further comprising: A plurality of left signal wirings are arranged in the third sub-display area on the substrate; as well as A plurality of left fan-out wirings are arranged on the plurality of left signal wirings in the pad area, the first sub-display area, and the third sub-display area, and each of the plurality of left fan-out wirings includes a bent portion.

43. The organic light emitting display device according to claim 42, wherein: The plurality of dummy patterns are disposed in the third sub-display region on the plurality of left signal wirings and are separated from the plurality of left fan-out wirings, and Wherein, the plurality of dummy patterns have a grid shape.

44. The organic light emitting display device according to claim 42, wherein: The left fan-out wiring and the right fan-out wiring are symmetrical to each other.

45. The organic light emitting display device according to claim 42, wherein: The plurality of left signal wirings are disposed only in the third sub display area, and data signals are applied through the plurality of left fan-out wirings.

46. ​​The organic light emitting display device according to claim 1, wherein: The plurality of right signal wirings are disposed only in the second sub display area, and data signals are applied through the plurality of right fan-out wirings.

47. The organic light emitting display device according to claim 1, wherein: Each of the sub-pixel structures comprises: a lower electrode, disposed on the plurality of dummy patterns; a light-emitting layer, disposed on the lower electrode; and The upper electrode is arranged on the light-emitting layer.

48. The organic light emitting display device according to claim 1, further comprising: A plurality of central signal wirings are arranged in the first sub-display area on the substrate.

49. The organic light emitting display device according to claim 48, wherein: A length of each of the plurality of center signal wirings in the first direction is longer than a length of each of the plurality of right signal wirings in the first direction.

50. The organic light emitting display device according to claim 48, wherein: The plurality of central signal wirings are disposed only in the first sub display area, and data signals are applied through the plurality of central signal wirings.

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