Display device

Abstract

A display device is provided. The display device includes a display panel for driving a plurality of pixels. Each of the plurality of pixels includes: a light-emitting element; a driving transistor for controlling a driving current flowing through the light-emitting element; a first transistor for selectively applying a data voltage to a first node; a second transistor for receiving an emission signal from an emission control line to selectively apply a driving voltage to the first node; and a first capacitor connected between the first node and the emission control line. The first node is a source electrode of the driving transistor.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0132761, filed on October 24, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0003] With the development of an information-oriented society, various demands for display devices are constantly increasing. For example, display devices are being adopted by various electronic devices (such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs) (or display devices are being adopted in various electronic devices (such as smart phones, digital cameras, laptop computers, navigation devices and smart TVs)). The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device and an organic light emitting display device. Among such flat panel display devices, the organic light emitting display device includes a light emitting element so that each of the pixels of the display panel can emit light by itself (for example, so that each pixel can emit light independently). Therefore, the organic light emitting display device can display an image without a backlight unit that supplies light to the display panel (for example, the pixels of the organic light emitting display device can be self-emitting).

[0004] An organic light-emitting display device typically includes a display panel having data lines, scan lines, a plurality of pixels connected to the corresponding data lines and scan lines, a data driver for applying data signals to the data lines, and a scan driver having a shift register for applying scan signals to the scan lines. The scan driver can supply scan signals to the pixels according to a predetermined drive frequency. When the display device is turned on or driven, the scan driver may change the drive frequency. In doing so, flickering or ghosting may occur as the display device's drive frequency changes. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device that can avoid or substantially avoid flickering and / or ghosting that may be displayed when a driving frequency of the display device is changed by coupling a source electrode of a driving transistor using a gate-off voltage of an emission signal.

[0006] Aspects of the present disclosure also provide a display device that provides reduced power consumption by maintaining some of the multiple signals supplied to multiple pixels as high-speed drive (e.g., maintaining them in a high-speed drive state or maintaining them at a high drive frequency) while changing some other signals to low-speed drive (e.g., changing them to a low-speed drive state or changing them to a low drive frequency).

[0007] It should be noted that the aspects and features of the present disclosure are not limited to the above-mentioned aspects and features, and other aspects and features of the present disclosure will be apparent to those skilled in the art through the following description.

[0008] According to an embodiment of the present disclosure, a display device includes a display panel for driving a plurality of pixels. Each of the plurality of pixels includes: a light-emitting element; a driving transistor for controlling a driving current flowing through the light-emitting element; a first transistor for selectively applying a data voltage to a first node, the first node being a source electrode of the driving transistor; a second transistor for receiving an emission signal from an emission control line to selectively apply a driving voltage to the first node; and a first capacitor connected between the first node and the emission control line.

[0009] Each of the multiple pixels may also include: a third transistor for selectively connecting the second node to a third node, the second node being the drain electrode of the driving transistor and the third node being the anode electrode of the light-emitting element; and a fourth transistor for selectively applying the first initialization voltage to the third node.

[0010] The second transistor and the third transistor may be turned on in response to an emission signal having a first voltage level, and the fourth transistor may be turned on in response to an emission signal having a second voltage level higher than the first voltage level.

[0011] The driving transistor may include an active layer including a first material, and the fourth transistor may include an active layer including a second material different from the first material.

[0012] Each of the plurality of pixels may further include: a fifth transistor for selectively applying the second initialization voltage to a fourth node, the fourth node being a gate electrode of the driving transistor; and a sixth transistor for selectively connecting the second node and the fourth node.

[0013] Each of the driving transistor and the fourth transistor may include an active layer including a first material, and each of the fifth transistor and the sixth transistor may include an active layer including a second material different from the first material.

[0014] The display panel may include: a first active layer, located on the substrate and including a first material; a first gate layer, located on the first active layer; a second gate layer, located on the first gate layer; a second active layer, located on the second gate layer and including a second material different from the first material; a third gate layer, located on the second active layer; and a first source and drain layer, located on the third gate layer.

[0015] A first electrode of the first capacitor may be located in the first gate layer, and a second electrode of the first capacitor may be located in the second gate layer.

[0016] The display panel may further include a first connection electrode. The first connection electrode may be located in the first source-drain layer, may be connected to the second electrode of the first capacitor through a first contact opening, and may be connected to the first node through a second contact opening. The first node may also be a drain electrode of the second transistor.

[0017] The emission control line may include: a first emission control line located in the first gate layer; and a second emission control line located in the third gate layer. The first electrode of the first capacitor may be a portion of the first emission control line overlapping the second electrode.

[0018] A first electrode of the first capacitor may be located in the third gate layer, and a second electrode of the first capacitor may be located in the first source-drain layer.

[0019] The display panel may further include a second connection electrode. The second connection electrode may be located in the first source-drain layer and may be connected to the first node through the third contact opening. The first node may also be a drain electrode of the second transistor.

[0020] The emission control line may include: a first emission control line located in the first gate layer; and a second emission control line located in the third gate layer. The first electrode of the first capacitor may be a portion of the second emission control line overlapping the second electrode.

[0021] A first electrode of the first capacitor may be located in the first gate layer, and a second electrode of the first capacitor may be located in the second active layer.

[0022] The display panel may further include a third connection electrode. The third connection electrode may be located in the first source-drain layer, may be connected to the second electrode of the first capacitor through a fourth contact opening, and may be connected to the first node through a fifth contact opening. The first node may also be the drain electrode of the second transistor.

[0023] The emission control line may include: a first emission control line located in the first gate layer; and a second emission control line located in the third gate layer. The first electrode of the first capacitor may be a portion of the first emission control line overlapping the second electrode.

[0024] According to an embodiment of the present disclosure, a display device includes a display panel for driving a plurality of pixels. Each of the plurality of pixels includes: a light-emitting element; a driving transistor for controlling a driving current flowing through the light-emitting element; a first transistor for selectively applying a data voltage to a first node, the first node being a source electrode of the driving transistor; a second transistor for receiving an emission signal from an emission control line to selectively apply a driving voltage to the first node; a third transistor for receiving an emission signal to selectively connect a second node with a third node, the second node being a drain electrode of the driving transistor and the third node being an anode electrode of the light-emitting element; and a first capacitor connected between the second node and the emission control line.

[0025] Each of the multiple pixels may also include: a fourth transistor for selectively applying the first initialization voltage to the third node; a fifth transistor for selectively applying the second initialization voltage to the fourth node, the fourth node being the gate electrode of the driving transistor; and a sixth transistor for selectively connecting the second node to the fourth node.

[0026] The second transistor and the third transistor may be turned on in response to an emission signal having a first voltage level, and the fourth transistor may be turned on in response to an emission signal having a second voltage level higher than the first voltage level.

[0027] Each of the driving transistor and the fourth transistor may include an active layer including a first material, and each of the fifth transistor and the sixth transistor may include an active layer including a second material different from the first material.

[0028] According to an exemplary embodiment of the present disclosure, high-speed driving with a frequency that is a multiple of the frequency of the scanning signal can be achieved by driving the scanning signals so that they overlap with each other. In a display device according to an exemplary embodiment of the present disclosure, some of the multiple signals supplied to the multiple pixels driven at high speed can be maintained as high-speed driving, while some other signals can be changed to low-speed driving. Each of the multiple pixels may include a capacitor connected between the source electrode of the driving transistor and the emission control line. When the emission signal changes from a low level to a high level, the capacitor can couple the voltage of the source electrode of the driving transistor. Therefore, even when the driving frequency changes, by controlling the voltage at the source electrode of the driving transistor, the display device will not experience flickering and / or ghosting.

[0029] According to an exemplary embodiment of the present disclosure, each of the plurality of pixels may include a capacitor connected between the drain electrode of the drive transistor and the emission control line. When the emission signal transitions from a low level to a high level, the capacitor may couple the voltage of the drain electrode of the drive transistor. In such an embodiment, the drive transistor may be turned on in response to the gate-on voltage, and the voltage at the drain electrode of the drive transistor may be transmitted to the source electrode. Therefore, even when the driving frequency changes, by controlling the voltage at the source electrode of the drive transistor, the display device will not experience flickering and / or ghosting.

[0030] According to exemplary embodiments of the present disclosure, power consumption of a display device may be reduced by maintaining some of a plurality of signals supplied to a plurality of pixels at high-speed driving and changing some other signals to low-speed driving.

[0031] It should be noted that the present disclosure is not limited to the above-mentioned aspects and features, and other aspects and features of the present disclosure will be apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0033] Figure 1 is a perspective view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0034] Figure 2 yes Figure 1 An exploded perspective view of the display device shown in .

[0035] Figure 3 It shows Figure 1 and Figure 2 A plan view of the display panel is shown in FIG.

[0036] Figure 4 is a block diagram illustrating a display panel and a display driving circuit according to an exemplary embodiment of the present disclosure.

[0037] Figure 5 is a circuit diagram illustrating a sub-pixel according to an exemplary embodiment of the present disclosure.

[0038] Figure 6 is supplied to Figure 5 : The waveform diagram of the signal of the sub-pixel shown in FIG.

[0039] Figure 7 It shows Figure 5 A plan view of an example of a sub-pixel shown in FIG.

[0040] Figure 8 It shows Figure 7A plan view of some of the layers of the sub-pixel shown in FIG.

[0041] Figure 9 It shows Figure 7 A plan view of some other layers in the sub-pixel layers shown in FIG.

[0042] Figure 10 It is along Figure 7 A cross-sectional view taken along line II'.

[0043] Figure 11 It is along Figure 7 A sectional view taken along line II-II'.

[0044] Figure 12 It is along Figure 7 A cross-sectional view taken along line III-III'.

[0045] Figure 13 It shows Figure 5 A plan view of another example of a sub-pixel shown in .

[0046] Figure 14 It shows Figure 13 A plan view of some layers of the sub-pixel shown in FIG.

[0047] Figure 15 It shows Figure 13 A plan view of some other layers in the sub-pixel layers shown in FIG.

[0048] Figure 16 It is along Figure 13 A sectional view taken along line IV-IV'.

[0049] Figure 17 It shows Figure 5 A plan view of yet another example of a sub-pixel shown in .

[0050] Figure 18 It shows Figure 17 A plan view of some of the layers of the sub-pixel shown in FIG.

[0051] Figure 19 It shows Figure 17 A plan view of some other layers in the sub-pixel layers shown in FIG.

[0052] Figure 20 It is along Figure 17 A cross-sectional view taken along line V-V'.

[0053] Figure 21 is a circuit diagram illustrating a sub-pixel according to another exemplary embodiment of the present disclosure.

[0054] Figure 22 is supplied to Figure 21: The waveform diagram of the signal of the sub-pixel shown in FIG.

[0055] Figure 23 is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0056] Figure 24 is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In the following description, for the purpose of explanation, many details are set forth to provide a thorough understanding of the various exemplary embodiments (or implementations) of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of one or more devices or methods using the inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be implemented without these details or with one or more equivalent arrangements. In other cases, known structures and devices can be shown in block diagram form to avoid making various exemplary embodiments unnecessarily vague. In addition, various exemplary embodiments may be different, but do not have to be exclusive. For example, without departing from the inventive concepts, the specific shape, construction and characteristics of the exemplary embodiments can be used or implemented in another exemplary embodiment.

[0058] Unless otherwise indicated, the exemplary embodiments shown will be understood as providing exemplary (i.e., example) features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments (hereinafter, individually or collectively referred to as "elements" or "elements") may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0059] The use of cross hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. As such, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or need for the specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than described. For example, two successively described processes may be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0060] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. However, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element, there are no intervening elements. For this purpose, the term “connected” may refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements.

[0061] In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes (such as the x-axis, y-axis and z-axis) of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as any combination of only X, only Y, only Z or two of X, Y and Z or more, such as with XYZ, XYY, YZ and ZZ as an example. As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items.

[0062] Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be named the second element without departing from the teachings of the disclosure.

[0063] For descriptive purposes, spatially relative terms such as "under," "beneath," "beneath," "down," "over," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as "under" or "beneath" other elements would subsequently be positioned "over" the other elements. Thus, the exemplary term "under" can include both above and below orientations. Furthermore, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), with the spatially relative descriptors used herein interpreted accordingly.

[0064] The terms used herein are for the purpose of describing specific example embodiments, and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular "one" and "one (kind / person)" are also intended to include plural forms. In addition, when using the terms "comprise", "include" and / or their variations in this manual, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, and are so used to explain the measured values, calculated values ​​and / or the inherent deviation of the values ​​that will be recognized by those of ordinary skill in the art.

[0065] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic representations of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not be construed as being limited to the specific illustrated shapes of the regions, but rather include deviations in shape due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0066] As is customary in the art, some exemplary embodiments are described and shown in the accompanying drawings according to functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. such as logic circuits, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing certain functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0067] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0068] Figure 1 is a perspective view illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 2 yes Figure 1 An exploded perspective view of the display device shown in .

[0069] Reference Figure 1 and Figure 2 , the display device 10 according to an exemplary embodiment of the present disclosure may include a cover window 100 , a display panel 300 , a frame 600 , a main circuit board 700 , and a bottom cover 900 .

[0070] As used herein, the terms "above," "top," and "upper surface" refer to the upper side of the display device 10 (i.e., the side indicated by the arrow in the Z-axis direction), while the terms "below," "bottom," and "lower surface" refer to the lower side of the display device 10 (i.e., the opposite side in the Z-axis direction). As used herein, the terms "left," "right," "upper," and "lower" refer to relative positions when the display device 10 is viewed from the top. For example, the "left side" refers to the opposite direction indicated by the arrow of the X-axis (i.e., the -X direction), the "right side" refers to the direction indicated by the arrow of the X-axis, the "upper side" refers to the direction indicated by the arrow of the Y-axis, and the "lower side" refers to the opposite direction indicated by the arrow of the Y-axis (i.e., the -Y direction).

[0071] The display device 10 is configured to display video and / or still images. The display device 10 can be used as a display screen for portable electronic devices (such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)) and various products (such as televisions, laptop computers, monitors, billboards, and IoT devices).

[0072] When viewed from the top, the display device 10 may have a rectangular shape. Figure 1 and Figure 2When viewed from the top, the display device 10 may have a rectangular shape having a shorter side along a first direction (X-axis direction) and a longer side along a second direction (Y-axis direction). Each of the corners where the shorter side along the first direction (X-axis direction) intersects the longer side along the second direction (Y-axis direction) may be rounded with a certain curvature (e.g., a predetermined curvature) or may be a right angle. The shape of the display device 10 when viewed from the top is not limited to a rectangular shape, and the display device 10 may be formed in another shape, such as a polygonal shape, a circular shape, or an elliptical shape.

[0073] The display device 10 may include a first region DR1 formed flat and second regions DR2 extending from the right and left sides of the first region DR1, respectively. The second regions DR2 may be formed flat or may be curved. When the second regions DR2 are formed flat, the angle formed between the first region DR1 and each of the second regions DR2 may be an obtuse angle. When the second regions DR2 are formed as curved surfaces, they may have a constant curvature or a varying curvature.

[0074] Despite Figure 1 The second region DR2 extends from both the left and right sides of the first region DR1, respectively, but this is merely illustrative. For example, the second region DR2 may extend from only one of the right and left sides of the first region DR1. In other embodiments, the second region DR2 may extend from both the upper and lower sides and at least one of the left and right sides of the first region DR1. In the following description, the second region DR2 is provided at the left and right edges of the display device 10, respectively, as an example.

[0075] The cover window 100 may be disposed on the display panel 300 to cover an upper surface of the display panel 300. The cover window 100 may protect the upper surface of the display panel 300.

[0076] The cover window 100 may be provided in the first and second regions DR1 and DR2. The cover window 100 may include a first transmission portion DA1 and a second transmission portion DA2 covering the display panel 300, and a non-transmission portion NDA covering a portion other than the display panel 300, wherein the first transmission portion DA1 and the second transmission portion DA2 may be collectively referred to as a transmission portion DA. The second transmission portion DA2 may be provided on one side of the first transmission portion DA1, for example, as shown in FIG. Figure 1 and Figure 2 . The first and second transmissive portions DA1 and DA2 may be disposed in the first and second regions DR1 and DR2. The non-transmissive portion NDA may be opaque. In other embodiments, the non-transmissive portion NDA may be formed as a decorative layer having a pattern that may be displayed to a user (e.g., visible to a user) when no image is displayed.

[0077] The display panel 300 may be disposed under the cover window 100. The display panel 300 may be disposed in the first region DR1 and the second region DR2. Therefore, an image displayed by the display panel 300 may be viewed not only in the first region DR1 but also in the second region DR2 through the cover window 100. For example, an image displayed by the display panel 300 may be viewed from the upper surface and left and right edges of the display device 10 through the cover window 100.

[0078] The display panel 300 may be a light-emitting display panel including a light-emitting element. For example, the display panel 300 may be an organic light-emitting display panel including an organic light-emitting diode having an organic emission layer, a micro light-emitting diode display panel including micro-LEDs, a quantum dot light-emitting display panel including a quantum dot light-emitting diode having a quantum dot emission layer, or an inorganic light-emitting display panel including an inorganic light-emitting element containing an inorganic semiconductor. In the following description, the display panel 300 is described as an organic light-emitting display panel as an example.

[0079] The display panel 300 may include a main area MA and a protrusion area PA protruding from one side of the main area MA.

[0080] The main area MA may have a general area MDA, a sensor area SDA, and a non-display area NDA.

[0081] The general area MDA may be disposed to overlap the first transmission portion DA1 of the cover window 100. The sensor area SDA may be disposed to overlap the second transmission portion DA2 of the cover window 100. The sensor area SDA may be disposed on one side of the general area MDA, for example, as Figure 2 As shown in FIG, the sensor area SDA is disposed on the upper side, but is not limited thereto. As another example, the sensor area SDA may be disposed to be surrounded by the general area MDA (e.g., surrounded by the general area MDA along the periphery) and / or may be disposed adjacent to a corner of the display panel 300. In addition, although Figure 2 In the example shown in FIG, the display panel 300 includes one sensor area SDA, but this is merely illustrative. For example, the display panel 300 may include a plurality of sensor areas SDA.

[0082] Each of the normal area MDA and the sensor area SDA may include a plurality of pixels, scan lines and data lines connected to the plurality of pixels, and a power supply line. Hereinafter, a pixel may also be referred to as a sub-pixel.

[0083] The non-display area NDA may be defined as an edge area of ​​the display panel 300. The non-display area NDA may include a scan driver for applying a scan signal to the scan line and a link line connecting the data line with the display driving circuit 310.

[0084] The protruding area PA may protrude from one side of the main area MA. Figure 2 In the example shown in , the protruding area PA may protrude from the lower side of the main area MA. For example, the length of the protruding area PA in the first direction (X-axis direction) may be smaller than the length of the main area MA in the first direction (X-axis direction).

[0085] The protruding area PA may include a bending area and a pad area. The pad area may be provided on one side of the bending area, and the main area MA may be provided on the opposite side of the bending area. For example, the pad area may be provided on the lower side of the bending area, and the main area MA may be provided on the upper side of the bending area.

[0086] The display panel 300 (eg, the protruding area PA) may be formed to be flexible so that it can be bent, curved, folded, or rolled. For example, the display panel 300 (eg, the protruding area PA) may be bent at a bending area along a thickness direction (Z-axis direction).

[0087] The display panel 300 may include a display driving circuit 310 , a circuit board 320 , a power supply (unit) 330 , and a touch driving circuit 340 .

[0088] The display driving circuit 310 may output signals and voltages for driving the display panel 300. For example, the display driving circuit 310 may apply data voltages to the data lines. In addition, the display driving circuit 310 may apply driving voltages to the power lines and may apply scan control signals to the scan driver.

[0089] The circuit board 320 may be attached to the pad using an anisotropic conductive film (ACF). In addition, the leads of the circuit board 320 may be electrically connected to the pad of the display panel 300. For example, the circuit board 320 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0090] The power supply 330 may be provided on the circuit board 320 to apply a driving voltage to the display driving circuit 310 and the display panel 300. For example, the power supply 330 may generate a driving voltage to be applied to a driving voltage line, and may generate a low-level voltage to be applied to the cathode electrode of the light-emitting element of each sub-pixel. For example, the driving voltage may be a high-level voltage for driving a light-emitting element (e.g., an organic light-emitting diode), and the low-level voltage may be a low-level voltage for driving the organic light-emitting diode.

[0091] The touch drive circuit 340 can be provided on the circuit board 320 to measure the capacitance of the touch electrodes. For example, the touch drive circuit 340 can determine whether a user's touch is present and the location of the user's touch (if present) based on changes in the capacitance of the touch electrodes. As used herein, a user's touch refers to an object (such as a user's finger or a pen) contacting the surface of the display device 10 at a location where the touch sensing layer is provided. The touch drive circuit 340 can determine the location of the user's touch by distinguishing some of the touch electrodes where the user's touch occurs from other touch electrodes.

[0092] The frame 600 may be disposed below the display panel 300. The frame 600 may include plastic, metal, or a combination thereof. For example, the frame 600 may include a first camera opening (e.g., a first camera hole) CMH1 into which the first camera sensor 720 is inserted, a battery opening (e.g., a battery hole) BH into which the battery 790 is disposed, a cable opening (e.g., a cable hole) CAH through which a cable connected to the display driver circuit 310 or the circuit board 320 passes, and a sensor opening (e.g., a sensor hole) SH into which the sensor devices 740, 750, 760, and 770 are disposed. As another example, the frame 600 may not include a sensor opening SH and may not overlap with the sensor area SDA of the display panel 300.

[0093] The main circuit board 700 and the battery 790 may be disposed under the frame 600. The main circuit board 700 may be a printed circuit board (PCB) or a flexible printed circuit board.

[0094] The main circuit board 700 may include a main processor 710, a first camera sensor 720, a main connector 730, and sensor devices 740, 750, 760, and 770. The first camera sensor 720 may be provided on both the upper and lower surfaces of the main circuit board 700, the main processor 710 may be provided on the upper surface of the main circuit board 700, and the main connector 730 may be provided on the lower surface of the main circuit board 700. The sensor devices 740, 750, 760, and 770 may be provided on the upper surface of the main circuit board 700.

[0095] The main processor 710 may control all (or substantially all) functions of the display device 10. For example, the main processor 710 may apply digital video data to the display driver circuit 310 so that the display panel 300 displays an image. The main processor 710 may receive touch data from the touch driver circuit 340 to determine the coordinates of the user's touch and then execute an application indicated by an icon displayed at the coordinates of the user's touch.

[0096] The main processor 710 may control the display device 10 based on sensor signals input from the sensor devices 740, 750, 760, and 770. For example, the main processor 710 may determine whether an object is located near the upper surface of the display device 10 based on the proximity sensor signal input from the proximity sensor 740. In the call mode, even if the object approaches the upper surface of the display device 10 so that the user's touch is made, the main processor 710 may not execute the application indicated by the icon displayed at the coordinates of the user's touch.

[0097] The main processor 710 may determine the brightness of the upper surface of the display device 10 according to the illuminance sensor signal input from the illuminance sensor 750. The main processor 710 may adjust the brightness of the image displayed by the display panel 300 according to the brightness of the upper surface of the display device 10.

[0098] The main processor 710 may determine whether the user's iris image is identical to an iris image previously stored in the memory based on the iris sensor signal input from the iris sensor 760. When it is determined that the user's iris image is identical (or substantially identical) to an iris image previously stored in the memory, the main processor 710 may unlock the display device 10 to display the home screen on the display panel 300.

[0099] The first camera sensor 720 can process image frames (such as still images and videos obtained by the image sensor) and can output them to the main processor 710. For example, the first camera sensor 720 can be, but is not limited to, a CMOS image sensor or a CCD sensor. The first camera sensor 720 can be exposed to the lower surface of the bottom cover 900 through a second camera opening (e.g., a second camera hole) CMH2 and can capture an object or background below the display device 10.

[0100] The cable having passed through the cable opening CAH of the frame 600 may be connected to the main connector 730. Thus, the main circuit board 700 may be electrically connected to the display driving circuit 310 and / or the circuit board 320.

[0101] The sensor device may include a proximity sensor 740 , an illumination sensor 750 , an iris sensor 760 , and a second camera sensor 770 .

[0102] The proximity sensor 740 can detect whether an object is approaching the upper surface of the display device 10. For example, the proximity sensor 740 may include a light source that outputs light and a light receiver that receives light reflected by the object. The proximity sensor 740 is configured to determine whether an object is approaching the upper surface of the display device 10 based on the amount of light reflected by the object. The proximity sensor 740 overlaps the sensor opening SH, the sensor area SDA of the display panel 300, and the second transmissive portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300. Therefore, when an object approaches the upper surface of the display device 10, a proximity sensor signal can be generated and output to the main processor 710.

[0103] The illuminance sensor 750 is configured to detect the brightness of the upper surface of the display device 10. The illuminance sensor 750 may include a resistor whose resistance changes according to the brightness of incident light. The illuminance sensor 750 may determine the brightness of the upper surface of the display device 10 based on the resistance of the resistor. The illuminance sensor 750 overlaps the sensor opening SH, the sensor area SDA of the display panel 300, and the second transmissive portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300. Therefore, an illuminance sensor signal may be generated according to the brightness of the upper surface of the display device 10 and output to the main processor 710.

[0104] The iris sensor 760 is configured to determine whether the captured image of the user's iris is identical (or substantially identical) to an iris image previously stored in the memory. The iris sensor 760 may generate an iris sensor signal based on whether the image of the user's iris is identical to an iris image previously stored in the memory and output the iris sensor signal to the main processor 710.

[0105] The second camera sensor 770 can process image frames (such as still images and videos obtained by the image sensor) and can output them to the main processor 710. For example, the second camera sensor 770 can be, but is not limited to, a CMOS image sensor or a CCD sensor. The number of pixels of the second camera sensor 770 can be smaller than the number of pixels of the first camera sensor 720, and the size of the second camera sensor 770 can be smaller than the size of the first camera sensor 720. The second camera sensor 770 overlaps the sensor opening SH, the sensor area SDA of the display panel 300, and the second transmissive portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300. Therefore, the second camera sensor 770 can capture an object or background above the display device 10.

[0106] The battery 790 may be disposed so as not to overlap the main circuit board 700 in the third direction (Z-axis direction). The battery 790 may overlap the battery opening BH of the frame 600.

[0107] The main circuit board 700 may also include a mobile communication module configured to transmit / receive wireless signals to / from at least one of a base station, an external terminal, and a server via a mobile communication network. The wireless signals may include various types of data, such as voice signals, video call signals, or text / multimedia message transmission / reception.

[0108] The bottom cover 900 may be disposed under the main circuit board 700 and the battery 790. The bottom cover 900 may be fastened and fixed to the frame 600. The bottom cover 900 may form an exterior appearance of the lower surface of the display device 10. The bottom cover 900 may be made of plastic, metal, or a combination thereof.

[0109] The bottom cover 900 may include a second camera opening CMH2 through which the lower surface of the first camera sensor 720 is exposed. The position of the first camera sensor 720 and the positions of the first camera opening CMH1 and the second camera opening CMH2 corresponding to the first camera sensor 720 are not limited to the positions according to Figure 2 The locations of the exemplary embodiments are shown in FIG.

[0110] Figure 3 It shows Figure 1 and Figure 2 The plan view of the display panel shown in FIG. Figure 4 is a block diagram illustrating a display panel and a display driving circuit according to an exemplary embodiment of the present disclosure.

[0111] Reference Figure 3 and Figure 4 , the display panel 300 may include a normal area MDA, a sensor area SDA, and a non-display area NDA.

[0112] The normal area MDA may include a first sub-pixel SP1 , a driving voltage line VDDL connected to the first sub-pixel SP1 , a scan line GL, an emission control line EML, and a data line DL.

[0113] Each first sub-pixel SP1 may be connected to at least one scan line GL, at least one data line DL, at least one emission control line EML, and at least one driving voltage line VDDL. Figure 3 and Figure 4In the example shown in FIG, each first subpixel SP1 is shown as being connected to two scan lines GL, one data line DL, one emission control line EML, and one driving voltage line VDDL, but the present disclosure is not limited thereto. For example, each first subpixel SP1 may be connected to three or more scan lines GL.

[0114] Each first sub-pixel SP1 may include a driving transistor, a switching transistor, a light emitting element, and a capacitor.

[0115] The first sub-pixel SP1 may receive a driving voltage through a driving voltage line VDDL. The driving voltage may be a high-level voltage for driving the light emitting element of the first sub-pixel SP1.

[0116] The scan lines GL and the emission control lines EML may extend in a first direction (X-axis direction) and may be spaced apart from each other in a second direction (Y-axis direction) crossing (eg, perpendicular to) the first direction (X-axis direction).

[0117] The data lines DL may extend in the second direction (Y-axis direction) and may be spaced apart from each other in the first direction (X-axis direction).

[0118] The sensor area SDA may include the second sub-pixel SP2 , a driving voltage line VDDL connected to the second sub-pixel SP2 , a scan line GL, an emission control line EML, and a data line DL.

[0119] Each second sub-pixel SP2 may be connected to at least one scan line GL, at least one data line DL, at least one emission control line EML, and at least one driving voltage line VDDL. Figure 3 and Figure 4 In the example shown in FIG, each second subpixel SP2 is shown as being connected to two scan lines GL, one data line DL, one emission control line EML, and one driving voltage line VDDL, but the present disclosure is not limited thereto. For example, each second subpixel SP2 may be connected to three or more scan lines GL.

[0120] Each second sub-pixel SP2 may include a driving transistor, a switching transistor, a light emitting element, and a capacitor.

[0121] The second sub-pixel SP2 may receive a driving voltage through a driving voltage line VDDL. The driving voltage may be a high-level voltage for driving the light emitting element of the second sub-pixel SP2.

[0122] For example, the number of first subpixels SP1 per unit area in the normal area MDA can be greater than the number of second subpixels SP2 per unit area in the sensor area SDA. The normal area MDA is used to display images, which is the primary function of the display device 10, and the first subpixels SP1 can be densely arranged in the normal area MDA. The sensor area SDA may include a pixel area in which the second subpixels SP2 are disposed and a transmissive area that transmits light. Therefore, as the area of ​​the transmissive area of ​​the sensor area SDA increases, the number of second subpixels SP2 per unit area can be less than the number of first subpixels SP1 per unit area.

[0123] The non-display area NDA may be defined as the remaining area of ​​the display panel 300 excluding the normal area MDA and the sensor area SDA. The non-display area NDA may include a scan driver 410 for applying scan signals to the scan lines GL, fan-out lines FL connecting the data lines DL to the display driver circuit 310, and pads DP connected to the circuit board 320. The display driver circuit 310 and the pads DP may be disposed in the pad area of ​​the display panel 300. The pads DP may be disposed closer to one edge of the pad area than the display driver circuit 310.

[0124] like Figure 4 As shown in , the display driving circuit 310 may include a timing controller 311 and a data driver 312 .

[0125] The timing controller 311 can receive digital video data DATA and timing signals from the circuit board 320. Based on the timing signals, the timing controller 311 can generate a scan control signal SCS to control the operation timing of the scan driver 410, an emission control signal ECS to control the operation timing of the emission control driver 420, and a data control signal DCS to control the operation timing of the data driver 312. The timing controller 311 can output the scan control signal SCS to the scan driver 410 via a first scan control line SCL1. The timing controller 311 can output the emission control signal ECS to the emission control driver 420 via a second scan control line SCL2. The timing controller 311 can output the digital video data DATA and the data control signal DCS to the data driver 312.

[0126] The data driver 312 may convert the digital video data DATA into analog positive / negative data voltages and supply them to the data lines DL through the fan-out lines FL. The scan signals of the scan driver 410 may be used to select the sub-pixels SP1 and SP2 to which the data voltages are applied, and the selected sub-pixels SP1 and SP2 may receive the data voltages through the data lines DL.

[0127] exist Figure 3In the embodiment, the scan driver 410 may be disposed on the outer sides of the normal area MDA and the sensor area SDA, or on one side of the non-display area NDA. The emission control driver 420 may be disposed on the other outer sides of the normal area MDA and the sensor area SDA, or on the opposite side of the non-display area NDA. For another example, both the scan driver 410 and the emission control driver 420 may be disposed on the outer sides of the normal area MDA and the sensor area SDA.

[0128] The scan driver 410 may include a plurality of thin film transistors for generating scan signals based on the scan control signal SCS, and the emission control driver 420 may include a plurality of thin film transistors for generating emission signals based on the emission control signal ECS. For example, the thin film transistors of the scan driver 410 and the thin film transistors of the emission control driver 420 may be formed on the same layer as the thin film transistors of each of the first sub-pixel SP1 and the second sub-pixel SP2.

[0129] Figure 5 is a circuit diagram illustrating a sub-pixel according to an exemplary embodiment of the present disclosure, Figure 6 is supplied to Figure 5 : The waveform diagram of the signal of the sub-pixel shown in FIG. Figure 5 The sub-pixels shown in the figure can be Figure 3 and Figure 4 The first sub-pixel SP1 or the second sub-pixel SP2 shown in FIG.

[0130] Reference Figure 5 and Figure 6The display panel 300 may include a plurality of subpixels arranged along p rows and q columns, where p and q are natural numbers. The subpixel arranged in the nth row and mth column may be connected to a first scan line GLa(n), a second scan line GLb(n), and a third scan line GLc(n), an emission control line EML(n), a data line DL, a drive voltage line VDDL, and a first initialization voltage line VIL1 and a second initialization voltage line VIL2, where n is a natural number equal to or less than p, and m is a natural number equal to or less than q. For example, the emission control line EML(n) may include a first emission control line and a second emission control line. The first emission control line may supply an emission signal EM(n) to a second transistor ST2 and a third transistor ST3, each of which includes an active layer including (or made of) a first material. The second emission control line may supply an emission signal EM(n) to a fourth transistor ST4, which includes an active layer including (or made of) a second material different from the first material. The second transistor ST2 and the third transistor ST3 may be turned on by the emission signal EM(n) at a first voltage level, and the fourth transistor ST4 may be turned on by the emission signal EM(n) at a second voltage level higher than the first voltage level.

[0131] The sub-pixel may include a driving transistor DT, a light emitting element EL, a plurality of switching elements, and first and second capacitors C1 and C2. The switching elements may include first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0132] The driving transistor DT may include a gate electrode, a source electrode, and a drain electrode. The driving transistor DT may control a source-drain current Isd (hereinafter, referred to as "driving current") according to a data voltage applied to the gate electrode. The driving current Isd flowing through the channel of the driving transistor DT may be proportional to the square of the difference between the threshold voltage Vth of the driving transistor DT and the voltage Vsg between the source electrode and the gate electrode of the driving transistor DT (Isd=k'×(Vsg-Vth)). 2 ), where k' represents a proportionality coefficient determined by the structure and physical properties of the driving transistor DT, Vsg represents a source-gate voltage of the driving transistor DT, and Vth represents a threshold voltage of the driving transistor DT.

[0133] The light emitting element EL may receive a driving current to emit light. The amount of light or brightness emitted from the light emitting element EL may be proportional to the magnitude of the driving current.

[0134] The light-emitting element EL may be an organic light-emitting diode including an anode electrode, a cathode electrode, and an organic emission layer disposed between the anode electrode and the cathode electrode. In other embodiments, the light-emitting element EL may be an inorganic light-emitting element including an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. In other embodiments, the light-emitting element EL may be a quantum dot light-emitting element including an anode electrode, a cathode electrode, and a quantum dot emission layer disposed between the anode electrode and the cathode electrode. In other embodiments, the light-emitting element EL may be a micro light-emitting diode.

[0135] The anode electrode of the light-emitting element EL may be connected to the third node N3. The anode electrode of the light-emitting element EL may be connected to the drain electrode of the third transistor ST3 and the source electrode of the fourth transistor ST4 via the third node N3. The cathode electrode of the light-emitting element EL may be connected to the low-level line VSSL. A parasitic capacitor Cel may be formed between the anode electrode and the cathode electrode of the light-emitting element EL.

[0136] The first transistor ST1 can be turned on by the third scan signal Gc(n) of the third scan line GLc(n) and can connect the data line DL to the first node N1 (i.e., the source electrode of the drive transistor DT). The first transistor ST1 can be turned on based on the third scan signal Gc(n), thereby applying a data voltage to the first node N1. The gate electrode of the first transistor ST1 can be connected to the third scan line GLc(n), its source electrode can be connected to the data line DL, and its drain electrode can be connected to the first node N1. The drain electrode of the first transistor ST1 can be electrically connected to the source electrode of the drive transistor DT, the drain electrode of the second transistor ST2, and the second electrode of the first capacitor C1 through the first node N1.

[0137] The second transistor ST2 can be turned on by the emission signal EM(n) of the emission control line EML(n) and can connect the drive voltage line VDDL to the first node N1 (i.e., the source electrode of the drive transistor DT). The gate electrode of the second transistor ST2 can be connected to the emission control line EML(n), its source electrode can be connected to the drive voltage line VDDL, and its drain electrode can be connected to the first node N1. The drain electrode of the second transistor ST2 can be electrically connected to the source electrode of the drive transistor DT, the drain electrode of the first transistor ST1, and the second electrode of the first capacitor C1 through the first node N1.

[0138] The third transistor ST3 can be turned on by the emission signal EM(n) of the emission control line EML(n) to connect the second node N2 (i.e., the drain electrode of the drive transistor DT) to the third node N3 (i.e., the anode electrode of the light-emitting element EL). The gate electrode of the third transistor ST3 can be connected to the emission control line EML(n), its source electrode can be connected to the second node N2, and its drain electrode can be connected to the third node N3. The source electrode of the third transistor ST3 can be connected to the drain electrode of the drive transistor DT and the drain electrode of the sixth transistor ST6 through the second node N2. The drain electrode of the third transistor ST3 can be connected to the anode electrode of the light-emitting element EL and the source electrode of the fourth transistor ST4 through the third node N3.

[0139] When the second transistor ST2 , the driving transistor DT, and the third transistor ST3 are all turned on, a driving current may be supplied to the light emitting element EL.

[0140] The fourth transistor ST4 can be turned on by the emission signal EM(n) of the emission control line EML(n) to connect the first initialization voltage line VIL1 to the third node N3 (i.e., the anode electrode of the light-emitting element EL). The fourth transistor ST4 can be turned on based on the emission signal EM(n) to discharge the anode electrode of the light-emitting element EL to the first initialization voltage. The gate electrode of the fourth transistor ST4 can be connected to the emission control line EML(n), the drain electrode thereof can be connected to the first initialization voltage line VIL1, and the source electrode thereof can be connected to the third node N3. The source electrode of the fourth transistor ST4 can be connected to the anode electrode of the light-emitting element EL and the drain electrode of the third transistor ST3 via the third node N3.

[0141] The fifth transistor ST5 can be turned on by the first scan signal Ga(n) of the first scan line GLa(n) and can connect the second initialization voltage line VIL2 to the fourth node N4 (i.e., the gate electrode of the drive transistor DT). The fifth transistor ST5 can be turned on based on the first scan signal Ga(n), thereby discharging the gate electrode of the drive transistor DT to the second initialization voltage. The gate electrode of the fifth transistor ST5 can be connected to the first scan line GLa(n), the drain electrode thereof can be connected to the second initialization voltage line VIL2, and the source electrode thereof can be connected to the fourth node N4. The source electrode of the fifth transistor ST5 can be connected to the gate electrode of the drive transistor DT, the source electrode of the sixth transistor ST6, and the first electrode of the second capacitor C2 through the fourth node N4.

[0142] The sixth transistor ST6 can be turned on by the second scan signal Gb(n) of the second scan line GLb(n) to connect the second node N2 (i.e., the drain electrode of the drive transistor DT) to the fourth node N4 (i.e., the gate electrode of the drive transistor DT). The gate electrode of the sixth transistor ST6 can be connected to the second scan line GLb(n), its drain electrode can be connected to the second node N2, and its source electrode can be connected to the fourth node N4. The drain electrode of the sixth transistor ST6 can be connected to the drain electrode of the drive transistor DT and the source electrode of the third transistor ST3 through the second node N2. The source electrode of the sixth transistor ST6 can be electrically connected to the gate electrode of the drive transistor DT, the source electrode of the fifth transistor ST5, and the first electrode of the second capacitor C2 through the fourth node N4.

[0143] Each of the driving transistor DT, the first transistor ST1, the second transistor ST2, and the third transistor ST3 may include a silicon-based active layer. For example, each of the driving transistor DT, the first transistor ST1, the second transistor ST2, and the third transistor ST3 may include an active layer comprising (or made of) low-temperature polycrystalline silicon (LTPS). The active layer made of low-temperature polycrystalline silicon may have high electron mobility and excellent conduction characteristics. Therefore, the display device 10 includes the driving transistor DT, the first transistor ST1, the second transistor ST2, and the third transistor ST3 having excellent conduction characteristics, so that multiple sub-pixels can be stably and efficiently driven.

[0144] Each of the driving transistor DT, the first transistor ST1, the second transistor ST2, and the third transistor ST3 may be a p-type transistor. For example, each of the driving transistor DT, the first transistor ST1, the second transistor ST2, and the third transistor ST3 may output a current flowing into a source electrode to a drain electrode based on a gate low voltage applied to the gate electrode.

[0145] Each of the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may include an oxide-based active layer. For example, each of the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may have a coplanar structure in which a gate electrode is disposed above the oxide-based active layer. Transistors having such a coplanar structure have excellent leakage current characteristics and allow low-frequency driving, thereby reducing power consumption. Therefore, the display device 10 includes the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 having excellent leakage current characteristics, so that leakage current can be prevented from flowing within the sub-pixel and the voltage within the sub-pixel can be maintained stable.

[0146] Each of the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be an n-type transistor. For example, each of the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may output current flowing into the source electrode to the drain electrode based on the gate high voltage applied to the gate electrode.

[0147] The first capacitor C1 may be connected between the emission control line EML(n) and the first node N1. For example, the first electrode of the first capacitor C1 may be connected to the emission control line EML(n), and the second electrode of the first capacitor C1 may be connected to the first node N1 (i.e., the source electrode of the drive transistor DT). The first capacitor C1 stores the voltage difference between the emission control line EML(n) and the source electrode of the drive transistor DT, so that the source electrode of the drive transistor DT can control the voltage.

[0148] The first capacitor C1 can be coupled to the source electrode of the drive transistor DT using the gate-off voltage of the emission signal EM(n). For example, when the emission signal EM(n) provided from the emission control line EML(n) rises, the first capacitor C1 can increase the voltage at the first node N1, and when the emission signal EM(n) falls, the first capacitor C1 can decrease the voltage at the first node N1. Therefore, the first capacitor C1 can control the voltage at the source electrode of the drive transistor DT in synchronization with the rising or falling edge of the emission signal EM(n).

[0149] The second capacitor C2 may be connected between the fourth node N4 (i.e., the gate electrode of the driving transistor DT) and the driving voltage line VDDL. For example, a first electrode of the second capacitor C2 is connected to the fourth node N4, and a second electrode of the second capacitor C2 is connected to the driving voltage line VDDL, so that a potential difference between the driving voltage line VDDL and the gate electrode of the driving transistor DT is maintained (or stored) by the second capacitor C2.

[0150] exist Figure 6 In the embodiment of the present invention, a plurality of sub-pixels may be driven according to a driving frequency (e.g., a predetermined driving frequency). The plurality of sub-pixels may display an image that changes (e.g., refreshes) relatively quickly in a high-speed driving mode, and may display an image that changes (e.g., refreshes) relatively slowly in a low-speed driving mode. It will be understood here that the high-speed driving mode and the low-speed driving mode are relative expressions, and the driving frequency of each of the high-speed driving mode and the low-speed driving mode is not limited to a specific value.

[0151] When the display device 10 is turned on or driven, the display device 10 can change the driving frequency. For example, the display device 10 can supply multiple scan signals to multiple sub-pixels based on a 240 Hz driving frequency. In this case, the scan driver 410 can supply the first to third scan signals Ga(n), Gb(n), and Gc(n) having a driving frequency of 240 Hz to the multiple pixels through the first to third scan lines GLa(n), GLb(n), and GLc(n), respectively, and the emission control driver 420 can apply the emission signal EM(n) having a driving frequency of 240 Hz to the multiple pixels through the emission control line EML(n).

[0152] For example, the display device 10 may change the driving frequency from 240 Hz to 120 Hz. In this case, the emission control driver 420 may supply the emission signal EM(n) having the driving frequency of 240 Hz to the plurality of pixels through the emission control line EML(n), and the scan driver 410 may supply the first to third scan signals Ga(n), Gb(n), and Gc(n) having the driving frequency of 120 Hz to the plurality of pixels through the first to third scan lines GLa(n), GLb(n), and GLc(n).

[0153] When the display device 10 changes from a 240 Hz driving frequency to a 120 Hz driving frequency, the emission signal EM(n) may still have a gate-on voltage and a gate-off voltage according to the 240 Hz driving frequency. For example, the emission signal EM(n) may have a gate-on voltage and a gate-off voltage in each of the first frame period Frame1 and the second frame period Frame2.

[0154] In addition, when the display device 10 changes from a driving frequency of 240 Hz to a driving frequency of 120 Hz, each of the first to third scan signals Ga(n), Gb(n), and Gc(n) may have a gate-on voltage and a gate-off voltage according to the driving frequency of 120 Hz. For example, each of the first to third scan signals Ga(n), Gb(n), and Gc(n) may have a gate-on voltage and a gate-off voltage in the first frame period Frame1, but may maintain the gate-off voltage in the second frame period Frame2.

[0155] As another example, the display device 10 may change the driving frequency from 240 Hz to 80 Hz. In this case, the emission control driver 420 may supply an emission signal EM(n) having a driving frequency of 240 Hz to a plurality of pixels through the emission control line EML(n), and the scan driver 410 may supply first to third scan signals Ga(n), Gb(n), and Gc(n) having a driving frequency of 80 Hz to the plurality of pixels through the first to third scan lines GLa(n), GLb(n), and GLc(n).

[0156] Therefore, the power consumption of the display device 10 can be reduced by maintaining some signals requiring high-speed driving among a plurality of signals supplied to a plurality of pixels at high-speed driving while changing some other signals to low-speed driving.

[0157] Combine Figure 5 For reference Figure 6 When the display device 10 is driven at a driving frequency of 120 Hz, the emission signal EM(n) may have a gate-on voltage and a gate-off voltage in each of the first frame period Frame1 and the second frame period Frame2, and each of the first to third scan signals Ga(n), Gb(n), and Gc(n) may have a gate-on voltage and a gate-off voltage in the first frame period Frame1, and may maintain the gate-off voltage in the second frame period Frame2. Therefore, when the display device 10 changes from a driving frequency of 240 Hz to a driving frequency of 120 Hz, the emission signal EM(n) may still be driven at a driving frequency of 240 Hz, and the first to third scan signals Ga(n), Gb(n), and Gc(n) may be driven at a driving frequency of 120 Hz.

[0158] When the display device 10 is driven at a driving frequency of 120 Hz, the first frame period Frame1 may include first to fourth periods t1 to t4.

[0159] The fourth transistor ST4 may receive the emission signal EM(n) at a high level during the first period t1. The fourth transistor ST4 may be turned on based on the emission signal EM(n) at a high level and may apply a first initialization voltage (hereinafter referred to as "VI1") to the third node N3 (i.e., the anode electrode of the light emitting element EL). Therefore, the fourth transistor ST4 may initialize the anode electrode of the light emitting element EL during the first period t1.

[0160] The fifth transistor ST5 may receive the first scan signal Ga(n) at a high level during the second period t2. The fifth transistor ST5 may be turned on based on the first scan signal Ga(n) at a high level and may apply a second initialization voltage (hereinafter referred to as "VI2") to the fourth node N4 (i.e., the gate electrode of the driving transistor DT). Therefore, the fifth transistor ST5 may initialize the gate electrode of the driving transistor DT during the second period t2.

[0161] The sixth transistor ST6 may receive the second scan signal Gb(n) at a high level during the third period t3 . The sixth transistor ST6 may be turned on based on the second scan signal Gb(n) at a high level and may connect the second node N2 with the fourth node N4 .

[0162] The first transistor ST1 may receive the third scan signal Gc(n) at a low level during the fourth period t4. The first transistor ST1 may be turned on based on the third scan signal Gc(n) at a low level and may apply a data voltage (hereinafter, referred to as "Vdata") to the first node N1 (i.e., the source electrode of the driving transistor DT).

[0163] When the source electrode of the driving transistor DT receives the data voltage Vdata, the source-gate voltage Vsg of the driving transistor DT may be equal to (or substantially equal to) the voltage difference (Vdata-VI2) between the data voltage Vdata and the second initialization voltage VI2, and the source-gate voltage Vsg becomes greater than the threshold voltage (hereinafter, referred to as "Vth") (Vdata-VI2>Vth), and thus the driving transistor DT may be turned on. Therefore, at the moment when the driving transistor DT is turned on in the fourth period t4, the source-drain current Isd of the driving transistor DT may be determined based on the data voltage Vdata, the second initialization voltage VI2, and the threshold voltage Vth of the driving transistor DT (Isd=k×(Vdata-VI2-Vth) 2 ). The driving transistor DT may supply the source-drain current Isd to the second node N2 until the source-gate voltage Vsg reaches the threshold voltage Vth of the driving transistor DT. The sixth transistor ST6 may be turned on during the third period t3 to supply the voltage at the second node N2 to the fourth node N4. In this manner, while the driving transistor DT is turned on, the voltage at the fourth node N4 and the source-drain current Isd of the driving transistor DT may change, and the voltage at the fourth node N4 may eventually converge to the voltage difference Vdata-Vth between the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0164] When the emission signal EM(n) transitions from a low level to a high level, the first capacitor C1 can couple to the source electrode of the drive transistor DT. For example, when the emission signal EM(n) provided by the emission control line EML(n) rises, the first capacitor C1 can increase the voltage at the first node N1. Therefore, the first capacitor C1 controls the voltage at the source electrode of the drive transistor DT in synchronization with the rising edge of the emission signal EM(n). Therefore, even when the driving frequency changes, the display device 10 can prevent (or substantially prevent) flicker and / or ghosting by controlling the voltage at the source electrode of the drive transistor DT.

[0165] During the second frame period Frame2, the emission signal EM(n) may have a gate-on voltage and a gate-off voltage. When the emission signal EM(n) has a high level, the fourth transistor ST4 may be turned on to initialize the anode electrode of the light-emitting element EL, and the second transistor ST2 and the third transistor ST3 may be turned off. When the emission signal EM(n) has a low level, the fourth transistor ST4 may be turned off, and the second transistor ST2 and the third transistor ST3 may be turned on to supply a drive current to the light-emitting element EL.

[0166] Each of the first to third scan signals Ga(n), Gb(n), and Gc(n) may maintain a gate-off voltage during the second frame period Frame2. The first scan signal Ga(n) and the second scan signal Gb(n) may have a low level, and the third scan signal Gc(n) may have a high level. Therefore, the first transistor ST1, the fifth transistor ST5, and the sixth transistor ST6 may be turned off.

[0167] Figure 7 It shows Figure 5 A plan view of an example of a sub-pixel shown in FIG. Figure 8 It shows Figure 7 A plan view of some of the layers of the sub-pixel shown in FIG. Figure 9 It shows Figure 7 A plan view of some other layers in the sub-pixel layers shown in FIG. Figure 7 shows the stacking of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in this order according to an embodiment of the present disclosure, Figure 8 shows the stacking of a first active layer, a first gate layer, and a second gate layer in this order, Figure 9 The second active layer, the third gate layer, the first source and drain layer, and the second source and drain layer are stacked in this order. Figures 10 to 12 Detailed description Figures 7 to 9 The stacking relationship of the layers shown in .

[0168] The driving transistor DT may include an active layer DT_ACT, a gate electrode DT_G, a source electrode DT_S, and a drain electrode DT_D. The active layer DT_ACT of the driving transistor DT may overlap the gate electrode DT_G of the driving transistor DT. For example, the active layer DT_ACT of the driving transistor DT may be made of low-temperature polysilicon (LTPS).

[0169] The gate electrode DT_G of the driving transistor DT may be connected to the fifth connection electrode BE5 through a ninth contact opening (e.g., a ninth contact hole) CNT9, and the fifth connection electrode BE5 may be connected to the source electrode S5 of the fifth transistor ST5 and the source electrode S6 of the sixth transistor ST6 through a sixteenth contact opening (e.g., a sixteenth contact hole) CNT16. A portion of the gate electrode DT_G of the driving transistor DT overlapping the second electrode CE22 of the second capacitor C2 may be the first electrode CE21 of the second capacitor C2.

[0170] The source electrode DT_S of the driving transistor DT may be connected to the drain electrode D1 of the first transistor ST1 and the drain electrode D2 of the second transistor ST2. The source electrode DT_S of the driving transistor DT may be connected to the first connection electrode BE1 through a second contact opening (e.g., a second contact hole) CNT2, and the first connection electrode BE1 may be connected to the second electrode CE12 of the first capacitor C1 through a first contact opening (e.g., a first contact hole) CNT1.

[0171] The drain electrode DT_D of the driving transistor DT may be connected to the source electrode S3 of the third transistor ST3. The drain electrode DT_D of the driving transistor DT may be connected to the eighth connection electrode BE8 through an eighteenth contact opening (e.g., an eighteenth contact hole) CNT18, and the eighth connection electrode BE8 may be connected to the drain electrode D6 of the sixth transistor ST6 through a seventeenth contact opening (e.g., a seventeenth contact hole) CNT17.

[0172] The first transistor ST1 may include an active layer ACT1, a gate electrode G1, a source electrode S1, and a drain electrode D1. The active layer ACT1 of the first transistor ST1 may overlap with the gate electrode G1 of the first transistor ST1. For example, the active layer ACT1 of the first transistor ST1 may be made of low-temperature polycrystalline silicon (LTPS). The gate electrode G1 of the first transistor ST1 may be a portion of the third scan line GLc(n) that overlaps with the active layer ACT1.

[0173] The source electrode S1 of the first transistor ST1 may be connected to the seventh link electrode BE7 through a twelfth contact opening (eg, a twelfth contact hole) CNT12 , and the seventh link electrode BE7 may be connected to the data line DL through a thirteenth contact opening (eg, a thirteenth contact hole) CNT13 .

[0174] The drain electrode D1 of the first transistor ST1 can be connected to the source electrode DT_S of the driving transistor DT and the drain electrode D2 of the second transistor ST2. The drain electrode D1 of the first transistor ST1 can be connected to the first connection electrode BE1 through the second contact opening CNT2, and the first connection electrode BE1 can be connected to the second electrode CE12 of the first capacitor C1 through the first contact opening CNT1.

[0175] The second transistor ST2 may include an active layer ACT2, a gate electrode G2, a source electrode S2, and a drain electrode D2. The active layer ACT2 of the second transistor ST2 may overlap with the gate electrode G2 of the second transistor ST2. For example, the active layer ACT2 of the second transistor ST2 may be made of low-temperature polycrystalline silicon (LTPS). The gate electrode G2 of the second transistor ST2 may be a portion of the first emission control line EML1(n) that overlaps with the active layer ACT2.

[0176] The source electrode S2 of the second transistor ST2 may be connected to the fourth connection electrode BE4 through a seventh contact opening (e.g., a seventh contact hole) CNT7, and the fourth connection electrode BE4 may be connected to the driving voltage line VDDL through an eighth contact opening (e.g., an eighth contact hole) CNT8. In addition, the fourth connection electrode BE4 may be connected to the second electrode CE22 of the second capacitor C2 through a sixth contact opening (e.g., a sixth contact hole) CNT6.

[0177] The drain electrode D2 of the second transistor ST2 can be connected to the source electrode DT_S of the driving transistor DT and the drain electrode D1 of the first transistor ST1. The drain electrode D2 of the second transistor ST2 can be connected to the first connection electrode BE1 through the second contact opening CNT2, and the first connection electrode BE1 can be connected to the second electrode CE12 of the first capacitor C1 through the first contact opening CNT1.

[0178] The third transistor ST3 may include an active layer ACT3, a gate electrode G3, a source electrode S3, and a drain electrode D3. The active layer ACT3 of the third transistor ST3 may overlap with the gate electrode G3 of the third transistor ST3. For example, the active layer ACT3 of the third transistor ST3 may be made of low-temperature polycrystalline silicon (LTPS). The gate electrode G3 of the third transistor ST3 may be a portion of the first emission control line EML1(n) that overlaps with the active layer ACT3.

[0179] The source electrode S3 of the third transistor ST3 can be connected to the drain electrode DT_D of the driving transistor DT. The source electrode S3 of the third transistor ST3 can be connected to the eighth connection electrode BE8 through the eighteenth contact opening CNT18, and the eighth connection electrode BE8 can be connected to the drain electrode D6 of the sixth transistor ST6 through the seventeenth contact opening CNT17.

[0180] The drain electrode D3 of the third transistor ST3 can be connected to the sixth connection electrode BE6 through a tenth contact opening (e.g., a tenth contact hole) CNT10. The sixth connection electrode BE6 can be connected to the first anode connection electrode ANDE1 through a fourteenth contact opening (e.g., a fourteenth contact hole) CNT14, and the first anode connection electrode ANDE1 can be connected to the anode electrode of the light emitting element EL through the second anode connection electrode ANDE2. The sixth connection electrode BE6 can be connected to the source electrode S4 of the fourth transistor ST4 through an eleventh contact opening (e.g., an eleventh contact hole) CNT11.

[0181] The fourth transistor ST4 may include an active layer ACT4, a gate electrode G4, a drain electrode D4, and a source electrode S4. The active layer ACT4 of the fourth transistor ST4 may overlap with the gate electrode G4 of the fourth transistor ST4. For example, the active layer ACT4 of the fourth transistor ST4 may include an oxide-based active layer. The gate electrode G4 of the fourth transistor ST4 may be a portion of the second emission control line EML2(n) that overlaps with the active layer ACT4.

[0182] The drain electrode D4 of the fourth transistor ST4 may be connected to the first initialization voltage line VIL1 to receive the first initialization voltage VI1.

[0183] The source electrode S4 of the fourth transistor ST4 may be connected to the sixth connection electrode BE6 through the eleventh contact opening CNT11. The sixth connection electrode BE6 may be connected to the drain electrode D3 of the third transistor ST3 through the tenth contact opening CNT10 and to the first anode connection electrode ANDE1 through the fourteenth contact opening CNT14.

[0184] The fifth transistor ST5 may include an active layer ACT5, a gate electrode G5, a drain electrode D5, and a source electrode S5. The active layer ACT5 of the fifth transistor ST5 may overlap the gate electrode G5 of the fifth transistor ST5. For example, the active layer ACT5 of the fifth transistor ST5 may include an oxide-based active layer. The gate electrode G5 of the fifth transistor ST5 may be a portion of the first scan line GLa(n) that overlaps the active layer ACT5.

[0185] The drain electrode D5 of the fifth transistor ST5 may be connected to the second initialization voltage line VIL2 through a fifteenth contact opening (eg, a fifteenth contact hole) CNT15 to receive the second initialization voltage VI2.

[0186] The source electrode S5 of the fifth transistor ST5 can be connected to the source electrode S6 of the sixth transistor ST6. The source electrode S5 of the fifth transistor ST5 can be connected to the fifth connection electrode BE5 through the sixteenth contact opening CNT16, and the fifth connection electrode BE5 can be connected to the gate electrode DT_G of the drive transistor DT through the ninth contact opening CNT9. The portion of the gate electrode DT_G of the drive transistor DT that overlaps with the second electrode CE22 of the second capacitor C2 can be the first electrode CE21 of the second capacitor C2.

[0187] The sixth transistor ST6 may include an active layer ACT6, a gate electrode G6, a drain electrode D6, and a source electrode S6. The active layer ACT6 of the sixth transistor ST6 may overlap with the gate electrode G6 of the sixth transistor ST6. For example, the active layer ACT6 of the sixth transistor ST6 may include an oxide-based active layer. The gate electrode G6 of the sixth transistor ST6 may be a portion of the second scan line GLb(n) that overlaps with the active layer ACT6.

[0188] The drain electrode D6 of the sixth transistor ST6 may be connected to the eighth link electrode BE8 through the seventeenth contact opening CNT17. The eighth link electrode BE8 may be connected to the drain electrode DT_D of the driving transistor DT and the source electrode S3 of the third transistor ST3.

[0189] The source electrode S6 of the sixth transistor ST6 can be connected to the source electrode S5 of the fifth transistor ST5. The source electrode S6 of the sixth transistor ST6 can be connected to the fifth connection electrode BE5 through the sixteenth contact opening CNT16, and the fifth connection electrode BE5 can be connected to the gate electrode DT_G of the drive transistor DT through the ninth contact opening CNT9. The portion of the gate electrode DT_G of the drive transistor DT that overlaps with the second electrode CE22 of the second capacitor C2 can be the first electrode CE21 of the second capacitor C2.

[0190] The first capacitor C1 may include a first electrode CE11 and a second electrode CE12. The first electrode CE11 of the first capacitor C1 may be a portion of the first emission control line EML1(n) that overlaps with the second electrode CE12 of the first capacitor C1. The second electrode CE12 of the first capacitor C1 may be connected to the first connection electrode BE1 through a first contact opening CNT1. The first connection electrode BE1 may be connected to the source electrode DT_S of the drive transistor DT through a second contact opening CNT2. Therefore, the first capacitor C1 stores a voltage difference between the emission control line EML(n) and the source electrode DT_S of the drive transistor DT. Therefore, the voltage at the source electrode DT_S of the drive transistor DT may be controlled, thereby preventing (or substantially reducing) flickering and / or ghosting.

[0191] The second capacitor C2 may include a first electrode CE21 and a second electrode CE22. The first electrode CE21 of the second capacitor C2 may be a portion of the gate electrode DT_G of the driving transistor DT that overlaps with the second electrode CE22 of the second capacitor C2. The second electrode CE22 of the second capacitor C2 may be connected to the fourth connection electrode BE4 through a sixth contact opening CNT6, and the fourth connection electrode BE4 may be connected to the driving voltage line VDDL through an eighth contact opening CNT8.

[0192] Figure 10 It is along Figure 7 A cross-sectional view taken along line II' of Figure 11 It is along Figure 7 A cross-sectional view taken along line II-II', Figure 12 It is along Figure 7 A cross-sectional view taken along line III-III'.

[0193] Reference Figures 10 to 12 The display panel 300 may include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a first interlayer dielectric layer ILD1, a second gate layer GTL2, a second interlayer dielectric layer ILD2, a second active layer ACTL2, a second gate insulating layer GI2, a third gate layer GTL3, a third interlayer dielectric layer ILD3, a first source and drain layer SDL1, a fourth interlayer dielectric layer ILD4, a second source and drain layer SDL2, a passivation layer PAS, a first planarization layer OC1, a second planarization layer OC2, a light emitting element EL, a pixel defining layer PDL and a thin film encapsulation layer TFE.

[0194] The substrate SUB may be a base substrate and may include (or may be made of) an insulating material such as a polymer resin. For example, the substrate SUB may be a flexible substrate that may be bent, folded, or rolled.

[0195] The third light blocking layer BML3 may be disposed on the substrate SUB and may overlap the driving transistor DT. The third light blocking layer BML3 may block light incident on the driving transistor DT and the light emitting element EL.

[0196] The buffer layer BF may be disposed on the substrate SUB to cover the third light blocking layer BML3. For example, the buffer layer BF may include a plurality of inorganic layers and may be formed on the entire upper surface of the substrate SUB to block moisture from penetrating into the light emitting element EL through the substrate SUB.

[0197] The first active layer ACTL1 may be disposed on the buffer layer BF. The first active layer ACTL1 may include (or may be made of) a silicon-based material. For example, the first active layer ACTL1 may be made of low-temperature polycrystalline silicon (LTPS). The active layers DT_ACT, ACT1, ACT2, and ACT3, the source electrodes DT_S, S1, S2, and S3, and the drain electrodes DT_D, D1, D2, and D3 of the driving transistor DT, the first transistor ST1, the second transistor ST2, and the third transistor ST3 may be disposed in the first active layer ACTL1, respectively.

[0198] The first gate insulating layer GI1 may cover the buffer layer BF and the first active layer ACTL1 , and may insulate the first active layer ACTL1 from the first gate layer GTL1 .

[0199] The first gate layer GTL1 may be disposed on the first gate insulating layer GI1. The gate electrode DT_G of the driving transistor DT, the first emission control line EML1(n), and the third scan line GLc(n) may be disposed in the first gate layer GTL1.

[0200] A portion of the gate electrode DT_G may overlap the second electrode CE22 of the second capacitor C2 to form a first electrode CE21 of the second capacitor C2.

[0201] A portion of the first emission control line EML1(n) may overlap the active layer ACT2 of the second transistor ST2 to form a gate electrode G2 of the second transistor ST2. Another portion of the first emission control line EML1(n) may overlap the active layer ACT3 of the third transistor ST3 to form a gate electrode G3 of the third transistor ST3. Still another portion of the first emission control line EML1(n) may overlap the second electrode CE12 of the first capacitor C1 to form a first electrode CE11 of the first capacitor C1.

[0202] A portion of the third scan line GLc(n) may overlap the active layer ACT1 of the first transistor ST1 to form the gate electrode G1 of the first transistor ST1.

[0203] The first interlayer dielectric layer ILD1 may cover the first gate layer GTL1 and the first gate insulating layer GI1 . The first interlayer dielectric layer ILD1 may insulate the first gate layer GTL1 from the second gate layer GTL2 .

[0204] The second gate layer GTL2 may be disposed on the first interlayer dielectric layer ILD1. The first and second light blocking layers BML1 and BML2, the second electrodes CE12 and CE22 of the first and second capacitors C1 and C2 may be disposed in the second gate layer GTL2.

[0205] The first light blocking layer BML1 may be disposed to overlap the fifth transistor ST5 to block light incident thereon. The second light blocking layer BML2 may be disposed to overlap the sixth transistor ST6 to block light incident thereon.

[0206] The second electrode CE12 of the first capacitor C1 can be connected to the first connection electrode BE1 of the first source-drain layer SDL1 through the first contact opening CNT1, and the first connection electrode BE1 can be connected to the drain electrode D2 of the second transistor ST2 and the source electrode DT_S of the drive transistor DT in the first active layer ACTL1 through the second contact opening CNT2. Therefore, the first capacitor C1 stores the voltage difference between the emission control line EML(n) and the source electrode DT_S of the drive transistor DT, and thus, the voltage at the source electrode DT_S of the drive transistor DT can be controlled, thereby preventing (or substantially preventing) flicker and / or ghosting.

[0207] The second electrode CE22 of the second capacitor C2 can be connected to the fourth connection electrode BE4 of the first source-drain layer SDL1 through the sixth contact opening CNT6, and the fourth connection electrode BE4 can be connected to the driving voltage line VDDL of the second source-drain layer SDL2 through the eighth contact opening CNT8. Therefore, the second capacitor C2 can maintain the potential difference between the driving voltage line VDDL and the gate electrode DT_G of the driving transistor DT.

[0208] The second interlayer dielectric layer ILD2 may cover the second gate layer GTL2 and the first interlayer dielectric layer ILD1. The second interlayer dielectric layer ILD2 may insulate the second gate layer GTL2 from the second active layer ACTL2.

[0209] The second active layer ACTL2 may be disposed on the second interlayer dielectric layer ILD2. For example, the second active layer ACTL2 may be formed of an oxide-based material. The active layers ACT4, ACT5, and ACT6 of the fourth to sixth transistors ST4, ST5, and ST6, as well as the drain electrodes D4, D5, and D6 and the source electrodes S4, S5, and S6 may be disposed in the second active layer ACTL2, respectively.

[0210] The second gate insulating layer GI2 may cover the second interlayer dielectric layer ILD2 and the second active layer ACTL2 and may insulate the second active layer ACTL2 from the third gate layer GTL3 .

[0211] The third gate layer GTL3 may be disposed on the second gate insulating layer GI2. The second emission control line EML2(n), the first scan line GLa(n), and the second scan line GLb(n) may be disposed in the third gate layer GTL3.

[0212] A portion of the second emission control line EML2(n) may overlap the active layer ACT4 of the fourth transistor ST4 to form a gate electrode G4 of the fourth transistor ST4. A portion of the first scan line GLa(n) may overlap the active layer ACT5 of the fifth transistor ST5 to form a gate electrode G5 of the fifth transistor ST5. A portion of the second scan line GLb(n) may overlap the active layer ACT6 of the sixth transistor ST6 to form a gate electrode G6 of the sixth transistor ST6.

[0213] The third interlayer dielectric layer ILD3 may cover the third gate layer GTL3 and the second gate insulating layer GI2 , and may insulate the third gate layer GTL3 from the first source / drain layer SDL1 .

[0214] The first source drain layer SDL1 may be disposed on the third interlayer dielectric layer ILD3 , and the first and fourth to eighth connection electrodes BE1 , BE4 , BE5 , BE6 , BE7 , and BE8 may be disposed in the first source drain layer SDL1 .

[0215] The first connection electrode BE1 may be connected to the second electrode CE12 of the first capacitor C1 through the first contact opening CNT1 and may be connected to the drain electrode D2 of the second transistor ST2 and the source electrode DT_S of the driving transistor DT through the second contact opening CNT2 .

[0216] The fourth connection electrode BE4 can be connected to the second electrode CE22 of the second capacitor C2 through the sixth contact opening CNT6, can be connected to the source electrode S2 of the second transistor ST2 through the seventh contact opening CNT7, and can be connected to the driving voltage line VDDL of the second source and drain layer SDL2 through the eighth contact opening CNT8.

[0217] The fifth connection electrode BE5 may be connected to the gate electrode DT_G of the driving transistor DT through the ninth contact opening CNT9 and may be connected to the source electrode S5 of the fifth transistor ST5 through the sixteenth contact opening CNT16 .

[0218] The sixth connection electrode BE6 may be connected to the drain electrode D3 of the third transistor ST3 through the tenth contact opening CNT10 , to the source electrode S4 of the fourth transistor ST4 through the eleventh contact opening CNT11 , and to the first anode connection electrode ANDE1 through the fourteenth contact opening CNT14 .

[0219] The seventh link electrode BE7 may be connected to the source electrode S1 of the first transistor ST1 through the twelfth contact opening CNT12 and may be connected to the data line DL through the thirteenth contact opening CNT13 .

[0220] The eighth connection electrode BE8 may be connected to the drain electrode D6 of the sixth transistor ST6 through the seventeenth contact opening CNT17 and may be connected to the source electrode S3 of the third transistor ST3 through the eighteenth contact opening CNT18 .

[0221] The fourth interlayer dielectric layer ILD4 may cover the first source / drain layer SDL1 and the third interlayer dielectric layer ILD3 , and may insulate the first source / drain layer SDL1 from the second source / drain layer SDL2 .

[0222] The second source and drain layer SDL2 may be disposed on the fourth interlayer dielectric layer ILD4. The data line DL, the driving voltage line VDDL, and the first anode connection electrode ANDE1 may be disposed in the second source and drain layer SDL2.

[0223] A passivation layer PAS may be disposed on the second source / drain layer SDL2 to protect a plurality of transistors of the sub-pixel.

[0224] A first planarization layer OC1 may be disposed on the passivation layer PAS to provide a flat surface throughout the sub-pixels.

[0225] The second anode connection electrode ANDE2 may be disposed on the first planarization layer OC1. The second anode connection electrode ANDE2 may connect the first anode connection electrode ANDE1 to the anode electrode E1 of the light emitting element EL.

[0226] The second planarization layer OC2 may cover the second anode connection electrode ANDE2 and the first planarization layer OC1.

[0227] The light-emitting element EL may be disposed on the second planarization layer OC2. The light-emitting element EL may include an anode electrode E1, an emission layer E, and a cathode electrode E2. The anode electrode E1 may be disposed on the second planarization layer OC2. For example, the anode electrode E1 may be disposed so as to overlap with an opening area EA defined by (or within) the pixel-defining layer PDL.

[0228] The emission layer E may be provided on the anode electrode E1. The emission layer E may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron blocking layer, an electron transport layer, an electron injection layer, etc. For example, the emission layer E may be, but is not limited to, an organic emission layer including (or made of) an organic material.

[0229] The cathode electrode E2 may be disposed on the emission layer E. For example, the cathode electrode E2 may be implemented in the form of a common electrode extending across (eg, covering) all sub-pixels.

[0230] A thin film encapsulation layer TFE may be disposed on the light emitting element EL and the pixel defining layer PDL to cover the plurality of sub-pixels. The thin film encapsulation layer TFE may prevent (or substantially prevent) oxygen or moisture from penetrating into the light emitting element EL.

[0231] Figure 13 It shows Figure 5 A plan view of another example of a sub-pixel shown in FIG. Figure 14 It shows Figure 13 A plan view of some layers of the sub-pixel shown in, Figure 15 It shows Figure 13 A plan view of some other layers in the sub-pixel layer shown in FIG. Figure 16 It is along Figure 13 A sectional view taken along line IV-IV'. Figure 13 The stacking of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in this order is shown. Figure 14 The stacking of the first active layer, the first gate layer, and the second gate layer in this order is shown. Figure 15 The second active layer, the third gate layer, the first source drain layer, and the second source drain layer are stacked in this order. In addition to the layout of the first electrode CE11 and the second electrode CE12 of the first capacitor C1, Figures 13 to 16 The sub-pixels shown in are substantially the same as the sub-pixels described above; therefore, redundant descriptions of the features will be omitted.

[0232] Reference Figures 13 to 16 , the first capacitor C1 may be connected between the emission control line EML(n) and the source electrode DT_S of the driving transistor DT. The first capacitor C1 may include a first electrode CE11 and a second electrode CE12. The first electrode CE11 of the first capacitor C1 may be a portion of the second emission control line EML2(n) disposed in the third gate layer GTL3 that overlaps with the second electrode CE12 of the first capacitor C1.

[0233] The second electrode CE12 of the first capacitor C1 may be a portion of the second connection electrode BE2 disposed in the first source / drain layer SDL1 overlapping the first electrode CE11 of the first capacitor C1. The second connection electrode BE2 may be connected to the source electrode DT_S of the driving transistor DT and the drain electrode D2 of the second transistor ST2 disposed in the first active layer ACTL1 through a third contact opening CNT3.

[0234] Therefore, the first capacitor C1 stores the voltage difference between the emission control line EML(n) and the source electrode DT_S of the driving transistor DT, and thus, even when the driving frequency changes, the voltage at the source electrode DT_S of the driving transistor DT can be controlled, thereby preventing (or substantially preventing) flickering and / or ghosting.

[0235] Figure 17 It shows Figure 5 A plan view of yet another example of a sub-pixel shown in FIG. Figure 18 It shows Figure 17 A plan view of some of the layers of the sub-pixel shown in FIG. Figure 19 It shows Figure 17 A plan view of some other layers in the sub-pixel layer shown in FIG. Figure 20 It is along Figure 17 A cross-sectional view taken along line V-V'. Figure 17 The stacking of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer in this order is shown. Figure 18 The stacking of the first active layer, the first gate layer, the second gate layer, and the second active layer in this order is shown. Figure 19 The second active layer, the third gate layer, the first source drain layer, and the second source drain layer are stacked in this order. In addition to the layout of the first electrode CE11 and the second electrode CE12 of the first capacitor C1, Figures 17 to 20 The sub-pixels shown in FIG are the same as those described above. Figure 7 The sub-pixels described are substantially the same; therefore, redundant descriptions of the features will be omitted.

[0236] Reference Figures 17 to 20 , the first capacitor C1 may be connected between the emission control line EML(n) and the source electrode DT_S of the driving transistor DT. The first capacitor C1 may include a first electrode CE11 and a second electrode CE12. The first electrode CE11 of the first capacitor C1 may be a portion of the first emission control line EML1(n) disposed in the first gate layer GTL1 that overlaps with the second electrode CE12 of the first capacitor C1.

[0237] The second electrode CE12 of the first capacitor C1 may be disposed in the second active layer ACTL2. The second electrode CE12 of the first capacitor C1 may be connected to the third connection electrode BE3 of the first source / drain layer SDL1 through a fourth contact opening CNT4. The third connection electrode BE3 may be connected to the source electrode DT_S of the driving transistor DT and the drain electrode D2 of the second transistor ST2 disposed in the first active layer ACTL1 through a fifth contact opening CNT5.

[0238] Therefore, the first capacitor C1 stores a voltage difference between the emission control line EML(n) and the source electrode DT_S of the driving transistor DT, and thus may control the voltage at the source electrode DT_S of the driving transistor DT, thereby preventing (or substantially preventing) flickering and / or ghosting.

[0239] Figure 21is a circuit diagram illustrating a sub-pixel according to another exemplary embodiment of the present disclosure, Figure 22 is supplied to Figure 21 Except that a different signal is applied to the gate electrode G4 of the fourth transistor ST4, Figure 21 and Figure 22 The described sub-pixels are substantially the same as those described above; therefore, redundant descriptions of the features will be omitted.

[0240] Reference Figure 21 and Figure 22 , the display panel 300 may include a plurality of sub-pixels arranged along p rows and q columns, where p and q are natural numbers. The sub-pixel arranged in the n-th row and m-th column may be connected to a first scan line GLa(n), a second scan line GLb(n), and a third scan line GLc(n), an emission control line EML(n), a data line DL, a driving voltage line VDDL, and a first initialization voltage line VIL1 and a second initialization voltage line VIL2, where n is a natural number equal to or less than p, and m is a natural number equal to or less than q.

[0241] The sub-pixel may include a driving transistor DT, a light emitting element EL, a plurality of switching elements, and first and second capacitors C1 and C2. The switching elements may include first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0242] The light-emitting element EL may receive a driving current to emit light. The amount of light emitted from the light-emitting element EL, or brightness, may be proportional to the magnitude of the driving current. The anode electrode of the light-emitting element EL may be connected to a third node N3. The anode electrode of the light-emitting element EL may be connected to the drain electrode of the third transistor ST3 and the source electrode of the fourth transistor ST4 via the third node N3. The cathode electrode of the light-emitting element EL may be connected to a low-level line VSSL.

[0243] The first transistor ST1 may be turned on by the third scan signal Gc(n) of the third scan line GLc(n) and may supply the data voltage Vdata to the first node N1 (ie, the source electrode of the driving transistor DT).

[0244] The second transistor ST2 may be turned on by the emission signal EM(n) of the emission control line EML(n) and may apply the driving voltage of the driving voltage line VDDL to the first node N1 (ie, the source electrode of the driving transistor DT).

[0245] The third transistor ST3 may be turned on by the emission signal EM(n) of the emission control line EML(n) to connect the second node N2 (ie, the drain electrode of the driving transistor DT) with the third node N3 (ie, the anode electrode of the light emitting element EL).

[0246] The fourth transistor ST4 may be turned on by the fourth scan signal Gc(n+1) of the fourth scan line GLc(n+1) and may supply the first initialization voltage VI1 to the third node N3 (ie, the anode electrode of the light emitting element EL).

[0247] The fifth transistor ST5 may be turned on by the first scan signal Ga(n) of the first scan line GLa(n) and may apply the second initialization voltage VI2 of the second initialization voltage line VIL2 to the fourth node N4 (ie, the gate electrode of the driving transistor DT).

[0248] The sixth transistor ST6 may be turned on by the second scan signal Gb(n) of the second scan line GLb(n) to connect the second node N2 (ie, the drain electrode of the driving transistor DT) with the fourth node N4 (ie, the gate electrode of the driving transistor DT).

[0249] Each of the driving transistor DT and the first to fourth transistors ST1, ST2, ST3, and ST4 may include a silicon-based active layer. For example, the driving transistor DT and the first to fourth transistors ST1, ST2, ST3, and ST4 may include an active layer made of low-temperature polysilicon (LTPS).

[0250] Each of the fifth transistor ST5 and the sixth transistor ST6 may include an oxide-based active layer. For example, each of the fifth transistor ST5 and the sixth transistor ST6 may have a coplanar structure in which a gate electrode is disposed above the oxide-based active layer.

[0251] The first capacitor C1 may be connected between the emission control line EML(n) and the first node N1. For example, the first electrode CE11 of the first capacitor C1 may be connected to the emission control line EML(n), and the second electrode CE12 of the first capacitor C1 may be connected to the first node N1 (i.e., the source electrode of the drive transistor DT). The first capacitor C1 stores the voltage difference between the emission control line EML(n) and the source electrode of the drive transistor DT, so that the source electrode of the drive transistor DT controls the voltage.

[0252] The first capacitor C1 can be coupled to the source electrode of the drive transistor DT using the gate-off voltage of the emission signal EM(n). For example, when the emission signal EM(n) provided from the emission control line EML(n) rises, the first capacitor C1 can increase the voltage at the first node N1, and when the emission signal EM(n) falls, the first capacitor C1 can decrease the voltage at the first node N1. Therefore, the first capacitor C1 controls the voltage at the source electrode of the drive transistor DT in synchronization with the rising or falling edge of the emission signal EM(n).

[0253] Figure 23 is a circuit diagram showing a sub-pixel according to yet another exemplary embodiment of the present disclosure. Except that the first capacitor C1 is connected to a different position, Figure 23 The sub-pixels shown in Figure 5 The sub-pixels shown in are substantially the same; therefore, redundant descriptions of the features will be omitted.

[0254] Reference Figure 23 The sub-pixel may include a driving transistor DT, a light emitting element EL, a plurality of switching elements, and a first capacitor C1 and a second capacitor C2. The switching elements may include first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0255] The light-emitting element EL may receive a driving current to emit light. The amount of light emitted from the light-emitting element EL, or brightness, may be proportional to the magnitude of the driving current. The anode electrode of the light-emitting element EL may be connected to a third node N3. The anode electrode of the light-emitting element EL may be connected to the drain electrode of the third transistor ST3 and the source electrode of the fourth transistor ST4 via the third node N3. The cathode electrode of the light-emitting element EL may be connected to a low-level line VSSL.

[0256] The first transistor ST1 may be turned on by the third scan signal Gc(n) of the third scan line GLc(n) and may supply the data voltage Vdata to the first node N1 (ie, the source electrode of the driving transistor DT).

[0257] The second transistor ST2 may be turned on by the emission signal EM(n) of the emission control line EML(n) and may apply the driving voltage of the driving voltage line VDDL to the first node N1 (ie, the source electrode of the driving transistor DT).

[0258] The third transistor ST3 may be turned on by the emission signal EM(n) of the emission control line EML(n) to connect the second node N2 (ie, the drain electrode of the driving transistor DT) with the third node N3 (ie, the anode electrode of the light emitting element EL).

[0259] The fourth transistor ST4 may be turned on by the emission signal EM(n) of the emission control line EML(n) to apply the first initialization voltage VI1 of the first initialization voltage line VIL1 to the third node N3 (ie, the anode electrode of the light emitting element EL).

[0260] The fifth transistor ST5 may be turned on by the first scan signal Ga(n) of the first scan line GLa(n) and may apply the second initialization voltage VI2 of the second initialization voltage line VIL2 to the fourth node N4 (ie, the gate electrode of the driving transistor DT).

[0261] The sixth transistor ST6 may be turned on by the second scan signal Gb(n) of the second scan line GLb(n) to connect the second node N2 (ie, the drain electrode of the driving transistor DT) with the fourth node N4 (ie, the gate electrode of the driving transistor DT).

[0262] The first capacitor C1 may be connected between the emission control line EML(n) and the second node N2. For example, a first electrode CE11 of the first capacitor C1 may be connected to the emission control line EML(n), and a second electrode CE12 of the first capacitor C1 may be connected to the second node N2 (i.e., the drain electrode of the drive transistor DT). The first capacitor C1 stores a voltage difference between the emission control line EML(n) and the drain electrode of the drive transistor DT, so that the drain electrode of the drive transistor DT controls the voltage.

[0263] The first capacitor C1 can couple the drain electrode of the drive transistor DT using the gate-off voltage of the emission signal EM(n). For example, when the emission signal EM(n) provided by the emission control line EML(n) rises, the first capacitor C1 can increase the voltage at the second node N2, and when the emission signal EM(n) falls, the first capacitor C1 can decrease the voltage at the second node N2. In this case, the drive transistor DT can be turned on by receiving the gate-on voltage, and the voltage at the drain electrode of the drive transistor DT can be transmitted to the source electrode. Therefore, the first capacitor C1 can control the voltages at the drain and source electrodes of the drive transistor DT in synchronization with the rising or falling edge of the emission signal EM(n).

[0264] Therefore, even when the driving frequency changes, the display device can prevent flicker and / or ghosting by controlling the voltage at the source electrode of the driving transistor.

[0265] Figure 24 is a circuit diagram showing a sub-pixel according to yet another exemplary embodiment of the present disclosure. In addition to different signals being applied to the gate electrode G4 of the fourth transistor ST4, Figure 24 The sub-pixel and Figure 23 The sub-pixels shown in are substantially the same; therefore, redundant descriptions of the features will be omitted.

[0266] The sub-pixel may include a driving transistor DT, a light emitting element EL, a plurality of switching elements, and first and second capacitors C1 and C2. The switching elements may include first to sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0267] The fourth transistor ST4 may be turned on by the fourth scan signal Gc(n+1) of the fourth scan line GLc(n+1) and may supply the first initialization voltage VI1 to the third node N3 (ie, the anode electrode of the light emitting element EL).

[0268] Each of the driving transistor DT and the first to fourth transistors ST1, ST2, ST3, and ST4 may include a silicon-based active layer. For example, the driving transistor DT and the first to fourth transistors ST1, ST2, ST3, and ST4 may include an active layer made of low-temperature polysilicon (LTPS).

[0269] Each of the fifth transistor ST5 and the sixth transistor ST6 may include an oxide-based active layer. For example, each of the fifth transistor ST5 and the sixth transistor ST6 may have a coplanar structure in which a gate electrode is disposed above the oxide-based active layer.

[0270] The present disclosure is not limited to the above-described aspects, features, and exemplary (ie, example) embodiments, and various other aspects, features, and embodiments are included in this description.

[0271] Although the exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications and changes may be made therein without departing from the spirit or essential features of the present disclosure. Therefore, the above embodiments are to be considered illustrative rather than restrictive. The present disclosure is to be defined based on the appended claims and their equivalents.

Claims

1. A display device comprising a display panel for driving a plurality of pixels, each of the plurality of pixels comprising: Light-emitting element; a driving transistor for controlling a driving current flowing through the light-emitting element; a first transistor for selectively applying a data voltage to a first node, the first node being a source electrode of the driving transistor; a second transistor configured to receive an emission signal from an emission control line to selectively apply a driving voltage to the first node; as well as a first capacitor connected between the first node or the second node and the emission control line, wherein the second node is the drain electrode of the driving transistor; Wherein, the display panel includes: a first active layer located on the substrate and comprising a first material; a first gate layer, located on the first active layer; a second gate layer, located on the first gate layer; a second active layer located on the second gate layer and comprising a second material different from the first material; a third gate layer, located on the second active layer; and The first source and drain layer is located on the third gate layer.

2. The display device according to claim 1, wherein A first electrode of the first capacitor is located in the first gate layer, and The second electrode of the first capacitor is located in the second gate layer.

3. The display device according to claim 1, wherein A first electrode of the first capacitor is located in the third gate layer, and The second electrode of the first capacitor is located in the first source-drain layer.

4. The display device according to claim 1, wherein A first electrode of the first capacitor is located in the first gate layer, and The second electrode of the first capacitor is located in the second active layer.

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