voltage converter

Abstract

This disclosure relates to a voltage converter. In one embodiment, the voltage converter includes: a first transistor coupled between a first rail and a first node, the first rail being configured to receive a power supply voltage; and an inductor coupled between the first node and a second node, the second node being configured to deliver an output voltage, wherein in each operating cycle of the converter, the first transistor is held in an on state for a first time period, the first time period being proportional to the reciprocal of the voltage difference between the power supply voltage and the output voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of French patent application No. 1911933, filed on October 24, 2019, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to an electronic system and method, and in a particular embodiment, to a voltage converter. Background Technology

[0004] In a switching power converter, the DC voltage used to power the converter is chopped by a switching switch to achieve a power storage phase in the inductor and a discharge phase in which the power stored in the inductor is directed toward a load connected to the converter output.

[0005] In a pulse frequency modulation (PFM) type switching converter, each operating cycle of the converter includes a power storage phase in the inductor, followed by a power transfer phase to the load connected to the converter. During the power storage phase (charging phase), the current flowing through the inductor increases. During the power transfer phase (discharging phase), the current flowing through the inductor decreases. For each operating cycle, the current flowing through the inductor is zero at the beginning of the power storage phase and at the end of the power transfer phase.

[0006] PFM-type switching converters have various drawbacks. Summary of the Invention

[0007] Some embodiments relate to a switching power supply type DC / DC voltage converter that converts a DC supply voltage to a DC output voltage. Some embodiments particularly relate to a buck DC / DC voltage converter where the DC output voltage has a lower value than the DC supply voltage.

[0008] Some embodiments involve PFM-type switching converters.

[0009] The embodiments overcome all or some of the disadvantages of known switching converters (especially PFM types).

[0010] An embodiment provides a voltage converter comprising:

[0011] A first MOS transistor is connected between a first rail and a first node, the first rail being configured to receive a power supply potential; and

[0012] An inductor is connected between a first node and a second node, the second node being configured to transmit the output potential, wherein in each operating cycle of the converter, a first MOS transistor remains in the on state for a first time period, which is proportional to the reciprocal of the potential difference between the power supply potential and the output potential.

[0013] According to an embodiment, the converter further includes a second MOS transistor connected between a first node and a second rail, the second rail being configured to receive a reference potential.

[0014] According to an embodiment, the converter further includes control circuitry configured to continuously perform the following control in each operating cycle:

[0015] Set the first transistor to the ON state;

[0016] Set the first transistor to the off state and the second transistor to the on state; and

[0017] Set the second transistor to the off state.

[0018] The control circuit is configured to keep the first transistor in the on state for a first time period during each operating cycle.

[0019] According to an embodiment, the control circuit is further configured to start an operating cycle when the output potential is lower than the potential setpoint.

[0020] According to an embodiment, the control circuit further includes a ramp generator configured to transmit a potential ramp having a slope proportional to the potential difference, the first time period being determined based on a comparison of the potential ramp with an output potential or a potential setpoint.

[0021] According to the embodiment, the potential ramp increases from the reference potential, and the first time period corresponds to the time it takes for the potential ramp to increase from the reference potential to the output potential or the potential setpoint.

[0022] According to an embodiment, the control circuit further includes a comparator configured to compare a potential ramp with an output potential or a potential setpoint.

[0023] According to an embodiment, the ramp generator includes:

[0024] A capacitor is connected between the second rail and the third node, the third node being configured as a potential ramp; and

[0025] A current source having a first terminal connected to a first rail and a second terminal connected to a third node, the current source being configured to transmit a current having a value proportional to the potential difference.

[0026] According to an embodiment, the current source includes:

[0027] The third MOS transistor is connected between the second rail and the fourth node;

[0028] The resistor is connected between the first rail and the fourth node;

[0029] The fourth MOS transistor is connected between the second rail and the fifth node;

[0030] The fifth MOS transistor is connected between the first rail and the fifth node;

[0031] The sixth MOS transistor, mirror-assembled with the fifth transistor, is connected between the first rail and the second terminal of the current source; and

[0032] An operational amplifier having a first input configured to receive an output potential, preferably inverted, a second input connected to a fourth node, preferably non-inverted, and an output connected to the control terminals of a third transistor and a fourth transistor.

[0033] According to an embodiment, the ramp generator further includes a switch connected in parallel with a capacitor.

[0034] According to an embodiment, the control circuit is further configured to control the switch to turn off at the beginning of the converter's operating cycle.

[0035] According to an embodiment, in each operating cycle of the converter, the control circuit is configured to keep the second MOS transistor in the on state for a second time period.

[0036] According to an embodiment, in each operating cycle of the converter, the control circuit is configured to keep the second MOS transistor in the on state for a second time period. The control circuit further includes another ramp generator configured to transmit another potential ramp having a slope proportional to the potential difference. The second time period is determined based on a comparison of the other potential ramp with the output potential or a potential setpoint.

[0037] According to an embodiment, another potential ramp decreases from the power supply potential, and the second time period corresponds to the time taken for the other potential ramp to decrease from the power supply potential to the output potential or the potential setpoint.

[0038] According to an embodiment, the control circuit includes a state machine. Attached Figure Description

[0039] The above and other features and advantages will be discussed in detail in conjunction with the accompanying drawings in the following non-limiting description of specific embodiments.

[0040] Figure 1 An embodiment of a DC / DC voltage converter is shown very schematically;

[0041] Figure 2 The illustration is shown. Figure 1 Timing diagram of the converter's operation;

[0042] Figure 3 It shows Figure 1 More detailed embodiments of the converter;

[0043] Figure 4 The illustration shows an embodiment. Figure 3 Timing diagram of the converter's operation;

[0044] Figure 5 It is shown in the form of a circuit. Figure 3 An embodiment of a converter;

[0045] Figure 6 It is shown in the form of a circuit. Figure 3 Alternative embodiments of the converter portion; and

[0046] Figure 7 It is shown in the form of a circuit. Figure 3 Another alternative embodiment of the converter portion. Detailed Implementation

[0047] The same components are designated using the same reference numerals in different drawings. Specifically, structural and / or functional elements common to different embodiments can be designated using the same reference numerals and can have the same structure, size, and material properties.

[0048] For clarity, only those steps and elements useful for understanding the described embodiments are shown and detailed. Specifically, common applications that can provide a DC / DC converter are not yet detailed, and the described embodiments are compatible with such common applications.

[0049] Throughout this disclosure, the term "connection" is used to specify a direct electrical connection between circuit elements that have no intermediate elements other than conductors, while the term "coupling" is used to specify an electrical connection between circuit elements that may be direct or may be via one or more other elements.

[0050] In the following description, when a term modifying absolute position (such as the terms "in front", "behind", "top", "bottom", "left", "right", etc.) or a term modifying relative position (such as the terms "above", "below", "above", "below", etc.) or a term modifying direction (such as the terms "horizontal", "vertical", etc.) is used, it refers to the orientation of the figure unless otherwise stated.

[0051] In this document, the terms “about,” “approximately,” “generally,” and “about” are used to specify a tolerance of ±10% for the relevant value, preferably ±5%.

[0052] Figure 1 An embodiment of the DC / DC voltage converter 1 is shown in a very schematic manner.

[0053] Converter 1 is configured to deliver a DC output potential Vout referenced to a reference potential (typically ground GND). The converter includes an output node 2 on which the potential Vout is available.

[0054] The converter 1 is powered by a DC power supply potential Vbat with reference potential GND. The converter 1 is then connected between a first conductive rail or rail 3 set to potential Vbat and a second conductive rail or rail 5 set to reference potential GND.

[0055] Converter 1 is configured to transmit a potential Vout equal to a setpoint value. For this purpose, converter 1 receives a DC potential setpoint Vref at input node 7 with reference to potential GND, the DC potential setpoint Vref having a setpoint value representing potential Vout, preferably equal to the setpoint value of potential Vout.

[0056] In this example, the potentials Vout, Vbat, and Vref are positive.

[0057] In this example, converter 1 is a step-down type, meaning the setpoint value of potential Vout is less than the value of potential Vbat. In other words, the value of potential Vout is less than the value of potential Vbat.

[0058] The converter 1 includes a first MOS ("metal-oxide-semiconductor") transistor 9, preferably a PMOS transistor (P-channel MOS transistor). The MOS transistor 9 is connected between rail 3 and (first) node 11. In other words, the first conductive terminal (e.g., its source) of the transistor 9 is connected to rail 3, and the second conductive terminal (e.g., its drain) of the transistor 9 is connected to node 11.

[0059] The converter 1 further includes a second MOS transistor 13, preferably an NMOS transistor (N-channel MOS transistor). Transistor 13 is connected between node 11 and rail 5. In other words, the first conductive terminal (e.g., its source) of transistor 13 is connected to rail 5, and the second conductive terminal (e.g., its drain) of transistor 13 is connected to node 11.

[0060] Therefore, transistors 9 and 13 are connected in series between rails 3 and 5, and are connected to each other at the level of internal node 11.

[0061] The converter 1 includes an inductor element or inductor 15. Inductor 15 is connected between node 11 and (second) node 2.

[0062] The converter 1 includes a control circuit 17. The circuit 17 is configured to implement or control the operating cycle of the converter 1 to adjust the potential Vout such that the value of the potential Vout is equal to the setpoint value Vref.

[0063] For this purpose, circuit 17 includes:

[0064] Terminal 171 is coupled (preferably connected) to node 7;

[0065] Terminal 172 is coupled (preferably connected) to node 2;

[0066] Terminal 173 is coupled (preferably connected) to guide rail 3;

[0067] Terminal 174 is coupled (preferably connected) to guide rail 5;

[0068] Terminal 175 is coupled (preferably connected) to the control terminal or gate of transistor 9; and

[0069] Terminal 177 is coupled (preferably connected) to the control terminal or gate of transistor 13.

[0070] Converter 1 includes an output capacitor (not shown) connected between node 2 and rail 5. As an example, this capacitor is between approximately 2.2 μF and 20 MF, or even larger. This output capacitor acts as a filter. In other words, the converter output capacitor smooths the current present at node 2 and stores the power supplied to node 2 by the converter.

[0071] Although not shown here, in operation, the load is connected between node 2 and rail 5, which is powered by the standby potential Vout of rail 5. The load typically includes an input capacitor between node 2 and rail 5.

[0072] According to an embodiment, converter 1 is configured to operate in pulse frequency modulation (discontinuous conduction mode). In this embodiment, circuit 17 is then configured to begin the operating cycle of converter 1 when the value of potential Vout is less than the setpoint value Vref and both transistors 9 and 13 are in the off state. More specifically, at the beginning of each operating cycle, when both transistors 9 and 13 are in the off state and node current IL flows through inductor 15, the circuit is configured to control transistor 9 to be turned on and transistor 13 to be turned off. During a first time period Ton during which circuit 17 keeps transistor 8 in the on state, power is then stored in inductor 15. At the end of time period Ton, circuit 17 is configured to control transistor 9 to be turned off and transistor 13 to be turned on. For a second time period Toff during which circuit 17 keeps 13 in the on state, power is then transferred back to the load connected to the converter output by inductor 15. At the end of time period Toff, circuit 17 is configured to control transistor 13 to be turned off. The time period Toff is determined such that the time when the transistor 13 is set to the off state by the control of circuit 17 corresponds to the time when the current flowing through the inductor becomes zero.

[0073] Figure 2 The illustration shows an embodiment. Figure 1 A timing diagram of the operation of converter 1, wherein converter 1 (e.g., its control circuit 17) is configured to operate in pulse frequency modulation mode.

[0074] Figure 2 The timing diagram at the top shows the change of potential Vout (in volts V) over time t. Figure 2 The timing diagram at the bottom shows the change of the current IL flowing through inductor 15 with time t.

[0075] At time t0, transistors 9 and 13 are in the off state, the current IL is zero, and the value of potential Vout is greater than its setpoint value, which in this example is the value of potential Vref.

[0076] Between time t0 and the subsequent time t2, for example, the potential Vout decreases due to the fact that the load connected to converter 1 consumes current.

[0077] During time t1, between time t0 and time t2, the potential Vout becomes less than its setpoint value Vref. This is detected by circuit 17 of converter 1, which then controls the transistor 9 to be turned on. Transistor 9 turns on at time t2.

[0078] Therefore, starting from time t2, inductor 15 has a terminal connected to node 2 and a terminal coupled to rail 3 via transistor 9. The current IL flowing through inductor 15 increases with the increase of slope A1, which is defined by the following relationship (1):

[0079] A1 = (Vbat - Vout) / L

[0080] L is the value of inductance 15.

[0081] As a result, starting from time t2, current IL is transferred to node 2, and the capacitor between node 2 and rail 5 ( Figure 1 (Not shown in the image) Charging. The potential Vout increases and becomes greater than its setpoint value Vref again.

[0082] At the next time t3 (which equals t2 + Ton), circuit 17 controls transistor 13 to be in the on state and controls transistor 9 to be in the off state.

[0083] Therefore, starting from time t3, inductor 15 has a terminal connected to node 2 and a terminal coupled to rail 5 via transistor 13. The current IL flowing through inductor 15 decreases as the slope A2 decreases, which is defined by the following relationship (2):

[0084] A2 = -Vout / L.

[0085] Although the current IL decreases from time t3, as long as the current IL is not zero, if the current generated by the load is less than the current IL supplied to node 2, the capacitor between node 2 and rail 5 will continue to charge, and the potential Vout will continue to increase.

[0086] At the next time t4 (which is equal to t3 + Toff), circuit 17 controls transistor 13 to be in the off state, and the current IL is zero at time t4.

[0087] Starting at time t4, the current IL is zero and the potential Vout decreases, similar to what happens at time t0.

[0088] Although not shown in this document, when the value of potential Vout falls below the setpoint value of potential Vout at some time after time t4, circuit 17 implements a new operating cycle, such as that described with respect to the following times t2, t3 and t4.

[0089] During the operation cycle of converter 1, at time t3, that is, at the end of time period Ton and the beginning of time period Toff, or in other words, when circuit 17 controls transistor 9 to be turned on and transistor 13 is turned on after transistor 9 has been turned off for time period Ton, the current IL through inductor 15 reaches its maximum value ILp. The value ILp is defined by the following relationship (3):

[0090] ILp=((Vbat-Vout)*Ton) / L.

[0091] The power consumed by converter 1 depends on the value ILp. The value ILp is preferably determined to minimize the power consumed by the converter, while the potential Vout can be adjusted to its setpoint value when the power consumed by the load connected to converter 1 does not exceed a given maximum value and the value of potential Vbat is greater than or equal to a given minimum value.

[0092] Furthermore, converter 1 is configured to operate using different potential Vbat values. For example, the value of potential Vbat is different between two different applications providing converter 1, and can vary depending on the operation in a given application.

[0093] In some embodiments, to avoid the power consumed by converter 1 depending on the value of potential Vbat, the inventors here assume, for example, that in converter 1, the time period Ton is proportional to the reciprocal of the potential difference between potential Vbat and potential Vout. In other words, converter 1 is configured such that the time period Ton verifies the following relationship (4):

[0094] Ton = A3 / (Vbat - Vout),

[0095] A3 is a proportionality coefficient, which is different from zero and independent of Vbat.

[0096] Therefore, the maximum value ILp of the current IL passing through inductor 15 is independent of the value of potential Vbat, which is particularly advantageous in some embodiments.

[0097] Figure 3 It shows Figure 1 A more detailed embodiment of converter 1 is described below. Only the following is emphasized here. Figure 1 Details not shown, such as details of circuit 17 concerning converter 1, are in Figure 3 The area is delimited by a dashed box.

[0098] Circuit 17 includes a state machine 300. State machine 300 is configured to transmit control signals from transistors 9 and 13 to corresponding terminals 175 and 177 to achieve [the desired action / function]. Figure 1 and Figure 2The described operation. To determine the control signals for transistors 9 and 13, state machine 300 receives multiple signals. In fact, state machine 300 is implemented in hardware and corresponds to a circuit. Circuit 300 is powered by a potential Vbat and connected between rails 3 and 5. To avoid overload, these connections are... Figure 3 The details were not provided.

[0099] Circuit 17 includes a comparator 302 configured to deliver a signal START at its output, representing a comparison of the value of potential Vout with its setpoint value. The output of comparator 302 is connected to circuit 300. The signal START is in a first state, such as a high state, when the value of potential Vout is less than its setpoint value, and in a second state, such as a low state, when the value of potential Vout is greater than its setpoint value. Comparator 302 includes a first input (e.g., an inverting (-)) and a second input (e.g., a non-inverting (+)), the first input being configured to receive a potential whose value represents the value of potential Vout, and the second input being configured to receive a potential whose value represents the setpoint value of potential Vout.

[0100] In this example, where the value of potential Vref is equal to the setpoint value of potential Vout, comparator 302 is configured to compare potential Vref with potential Vout. The first input of comparator 302 is connected to node 2, and the second input of comparator 302 is connected to terminal 171 of circuit 17.

[0101] In this embodiment, the time period Ton is determined by comparing the potential ramp RP with either potential Vref or potential Vout, where potential Vout can be considered equal to potential Vref. Therefore, circuit 17 includes a ramp generator 304 configured to transmit the potential ramp RP; and a comparator 306 configured to compare ramp RP with potential Vref or Vout, in this example comparing ramp RP with potential Vref. Potential RP is referenced to a reference potential GND.

[0102] Generator 304 is powered by a potential Vbat and is connected between rails 3 and 5. To avoid overload, these connections are... Figure 3 It is not shown in the text.

[0103] Generator 304 is controlled by circuit 300 via signal cmdP. More specifically, when signal START is in its first state (which indicates that the value of potential Vout is less than its setpoint value), and if both transistors 9 and 13 are in the on state, circuit 300 controls transistor 9 to the on state, and simultaneously controls the start or initiation of potential ramp RP via signal cmdP. As an example, signal cmdP is determined based on, or even equal to, the control signal transmitted from circuit 300 to transistor 9.

[0104] The ramp generator 304 is configured such that the slope of each potential ramp RP is proportional to the difference between potentials Vbat and Vout.

[0105] According to an embodiment, each potential ramp RP is a ramp added from the reference potential GND.

[0106] The ramp RP is sent to the first input (e.g., non-inverting (+)) of comparator 306, the second input (e.g., inverting (-)) of comparator 306 to receive the potential Vref, and the output of comparator 306 transmits the signal COMP to circuit 300.

[0107] according to Figure 3 In the illustrated embodiment, the potential ramp RP is sent to comparator 306 via selection circuit 308 (e.g., a multiplexer), which includes two inputs, one output, and a control terminal. The control terminal of circuit 308 receives a signal sel from circuit 300. Depending on the state of signal sel, circuit 308 sends a signal at its output that is present on one or the other of its inputs.

[0108] More specifically, when circuit 300 controls the transistor 9 to be turned on and controls the start of the potential ramp RP, circuit 300 sets the signal sel to the first state, so that comparator 306 receives the potential ramp RP.

[0109] Therefore, as long as the signal sel remains in its first state, the signal COMP remains in its first state, such as the low state. As soon as the potential RP is less than the potential Vref, and the potential RP becomes greater than the potential Vref, it switches to the second state, such as the high state.

[0110] The switching of the signal COMP from its first state to its second state marks the end of the time period Ton. Circuit 300 then controls transistor 9 to the off state and controls transistor 13 to the on state. Preferably, circuit 300 simultaneously controls the end of the potential ramp RP via the signal cmdP.

[0111] In this embodiment, the time period Toff is determined by comparing the potential slope RN with the potential Vref or the potential Vout, and more specifically, in this example, by comparing the potential slope RN with the potential Vref. Therefore, circuit 17 includes a slope generator 310 configured to transmit the potential slope RN.

[0112] Generator 310 is powered by a potential Vbat and is connected between rails 3 and 5. To avoid overload, these connections are... Figure 3 Not shown in the diagram. Generator 310 is controlled by circuit 300 via signal cmdN.

[0113] More specifically, at the end of time period Ton, when circuit 300 controls transistor 9 to the off state and transistor 13 to the on state, circuit 300 also controls the start of the potential ramp RN via signal cmdN. As an example, signal cmdN is determined based on, or even equal to, the control signal transmitted from circuit 300 to transistor 13.

[0114] According to the embodiment, each potential ramp RN is a ramp that decreases from the power supply potential Vbat.

[0115] according to Figure 3 In the illustrated embodiment, the comparison between the ramp RN and the potential Vref is implemented by comparator 306. The ramp RN is then sent to the second input of circuit 308. Further, circuit 300 is configured to switch the signal sel to its second state, while simultaneously controlling transistor 9 to be turned off and transistor 13 to be turned on, so as to send the ramp RN to comparator 306.

[0116] Therefore, in each embodiment where the ramp RN decreases from the potential Vbat, the signal COMP remains in its second state, such as the high state, as long as the signal sel remains in its second state, and switches to its first state, such as the low state, as long as the potential RN is greater than the potential Vref, and as long as the potential RN becomes less than the potential Vref.

[0117] The switching of the signal COMP from its second state to its first state marks the end of the time period Toff. Circuit 300 then controls the transistor 13 to be set to the off state. Preferably, circuit 300 simultaneously controls the end of the potential ramp RN via the signal cmdN.

[0118] In relation to Figure 3 In the described converter 1, due to the fact that the slope of the potential ramp RP is proportional to the difference between the potentials Vbat and Vout, and that the potential ramp equals Vref at the end of the time period Ton, the time period Ton verifies the following relationship (5):

[0119] Ton=(A4*Vref) / (Vbat-Vout),

[0120] A4 is a proportionality coefficient, for example, positive for an increased slope RP, and (Vbat-Vout) / A4 is the slope of slope RP.

[0121] By substituting relation (5) into relation (3), we obtain the following relation (6):

[0122] ILp = (A4 * Vref) / L.

[0123] Therefore, in converter 1, the maximum value of current ILp is effectively independent of the value of potential Vbat.

[0124] In an alternative embodiment (not shown), the comparison of the potential slope RP with the potential Vref is implemented by comparator 306, and the comparison of the potential slope RN with the potential Vref is implemented by an additional comparator disposed in circuit 17. The additional comparator then receives the potential slope RN at a first input (e.g., a non-inverting (+)) and the potential Vref at a second input (e.g., an inverting (-)), and the output of the additional comparator transmits a signal representing the comparison of the potential slope RN with the potential Vref to circuit 300. In this variation, circuit 308 is omitted, and circuit 300 does not generate the signal sel. Those skilled in the art will be able to... Figure 3 The above description of converter 1 applies to this alternative embodiment.

[0125] Figure 4 The diagram illustrates the implementation patterns. Figure 3 The timing diagram for the operation of converter 1. More specifically, Figure 4 It shows in Figure 3 The changes in potential ramps RN and RP (in volts (V)) with time t during the operating cycle of converter 1 Figure 4 The times t0, t1, t2, t3, and t4 shown are related to... Figure 2 The times described are the same.

[0126] In this embodiment, the potential ramp RP increases from the reference potential GND and is compared with the potential Vref to determine the time period Ton, and the ramp RP decreases from the power supply potential Vbat and is compared with the potential Vref to determine the time period Toff.

[0127] At time t0, potential RP equals potential GND, potential RN equals potential Vbat, and signal COMP is in its first state. Further, signal START is in its second state, indicating that potential Vout is greater than potential Vref.

[0128] At time t1, the potential Vout becomes less than the potential Vref( Figure 2 ), and although this is not shown in this article, it will cause the START signal to switch to its first state.

[0129] In response to the switching of the signal START, at time t2, the circuit controls the switching of transistor 9 to the on state via the signal cmdP and controls the start of the ramp RP.

[0130] Time t2 marks the beginning of time interval Ton.

[0131] Starting at time t2, the potential RP increases so that it becomes equal to the potential Vref at time t3.

[0132] Therefore, although this is not shown in this document, at time t3, the signal COMP switches from its first state to its second state. In response to the switching of the signal COMP, circuit 300 controls the switching of transistor 9 to the off state, the switching of transistor 13 to the on state, and the start of the potential ramp RN via the control signal cmdN. In this example, at time t3, circuit 300 also controls the end of the potential ramp RP via the signal cmdP, and the potential RP then switches back to the potential GND.

[0133] Time t3 marks the end of time interval Ton and the beginning of time interval Toff.

[0134] Starting at time t3, the potential RN decreases so that it becomes equal to the potential Vref at time t4.

[0135] Therefore, at time t4, the signal COMP switches from its second state to its first state. In response to the switching of the signal COMP, circuit 300 controls the switching of transistor 13 to the off state. At time t4, in this example, circuit 300 also controls the end of the potential ramp RN via the signal cmdN, and the potential RN then switches back to the potential Vbat.

[0136] Time t4 marks the end of the time interval Toff.

[0137] Although the above has already covered... Figure 3 and Figure 4 The description describes the case where potential ramps RP and RN are compared with potential Vref, but those skilled in the art will be able to make the description applicable to the case where potential ramps RN and RP are compared with potential Vout, which are implemented by a single comparator 306 and selection circuit 308 or by using two different comparators.

[0138] Furthermore, based on the functional indications given above, the actual implementation of state machine 300 is within the capabilities of those skilled in the art.

[0139] Those skilled in the art will also be able to determine the slope of the potential ramp RN, for example, based on the time period Ton, such that the end of the time period Toff corresponds to the time when the current IL through inductor 15 becomes zero. Specifically, according to the embodiment, it can be assumed that, like the slope of the potential ramp RP, the slope of the ramp RN is proportional to the difference between potentials Vbat and Vout.

[0140] Figure 5 It is shown in the form of a circuit. Figure 3 An embodiment of the converter. More specifically, Figure 5 An embodiment of the ramp generator 304 is shown.

[0141] The ramp generator 304 includes a capacitor C1 connected between the rail 5 and the (third) node 500, which is configured to transmit a potential ramp RP.

[0142] The ramp generator 304 further includes a current source 502, which in Figure 5 The area is delimited by a dashed box. The first terminal of current source 502 is connected to rail 3, and the second terminal of current source 502 is connected to node 500. Current source 502 is configured to transmit current I1, which has a value proportional to the difference between potentials Vbat and Vout.

[0143] The current source 502 includes a (third) MOS transistor 504, preferably an NMOS transistor, which is connected between rail 5 and (fourth) node 506. In other words, a conductive terminal of transistor 504 (e.g., its source) is connected to rail 5, and another conductive terminal of transistor 504 (e.g., its drain) is connected to node 506.

[0144] The current source 502 further includes a resistor R connected between the rail 3 and the node 506.

[0145] The current source 502 also includes an operational amplifier 508 having an input configured to receive a potential Vout (i.e., its inverting input (-)), another input connected to node 506 (i.e., its non-inverting input (+)), and an output connected to the control terminal of transistor 504.

[0146] Transistor 504 is then controlled by an amplifier, causing node 506 to be at potential Vout. Therefore, the current I2 flowing through transistor 504 is defined by the following relationship (7):

[0147] I2 = (Vbat - Vout) / R,

[0148] The current source 502 includes a (fourth) MOS transistor 510, preferably an NMOS transistor, which is connected between rail 5 and (fifth) node 512. In other words, a conductive terminal of transistor 510 (e.g., its source) is connected to rail 5, and another conductive terminal of transistor 510 (e.g., its drain) is connected to node 512.

[0149] The control terminal of transistor 510 is connected to the control terminal of transistor 504, thereby connecting to the output of operational amplifier 508. Therefore, a current I3 proportional to (preferably equal to) current I2 flows through transistor 510.

[0150] The current source 502 includes a (fifth) MOS transistor 514, preferably a PMOS transistor, which is connected between rail 3 and node 512. In other words, one conductive terminal of transistor 514 (e.g., its source) is connected to rail 3, and another conductive terminal of transistor 514 (e.g., its drain) is connected to node 512.

[0151] Current source 502 includes a (sixth) MOS transistor 516, preferably a PMOS transistor, which is mirror-assembled with transistor 514 and connected between rail 3 and node 500. In other words, a conductive terminal of transistor 516 (e.g., its source) is connected to rail 3, another conductive terminal of transistor 516 (e.g., its drain) is connected to node 500, and a control terminal of transistor 516 is connected to the control terminal of transistor 514, whose drain and gate are connected to each other. The conductive terminal of transistor 516 connected to node 500 corresponds to the second terminal of current source 502.

[0152] Therefore, the current I1 flowing through transistor 516 is proportional to, preferably equal to, the current I3 flowing through transistor 514, and thus proportional to, preferably equal to, the current I2. Thus, current source 502 effectively transmits the current I1, which is proportional to the difference between potentials Vbat and Vout.

[0153] As an example, when transistors 504, 510, 514, and 516 are designed to make currents I1, I2, and I3 equal, source 502 carries current I1, which is defined by the following relationship (8):

[0154] I1 = (Vbat - Vout) / R.

[0155] The ramp generator 304 includes circuit 518 (here, a switch), which is controlled by the signal cmdP ( Figure 3 It controls and is configured to start or stop the potential ramp RP based on the state of the signal cmdP.

[0156] More specifically, in Figure 5 In the illustrated embodiment, switch 518, implemented for example by a MOS transistor (preferably an NMOS transistor), is connected in parallel with capacitor C1, i.e., between node 500 and rail 5.

[0157] When the signal cmdP is in the first state (e.g., high state), switch 518 is turned on, and the potential RP is equal to the reference potential GND.

[0158] When the signal cmdP switches from its first state to its second state (e.g., low state), switch 518 is closed. According to the following relationship (9), capacitor C1 is charged by current I1 and its potential RP increases with time t:

[0159] RP = (t*I1) / C1,

[0160] I1 is proportional to the difference between potentials Vbat and Vout, or in other words, proportional to Vbat - Vout.

[0161] Therefore, the slope of the potential ramp RP is effectively proportional to the difference Vbat - Vout.

[0162] As an example, when transistors 504, 510, 514, and 516 are designed to make currents I1, I2, and I3 equal, current I1 verifies the above relationship (8), and potential RP thus verifies the following relationship (10):

[0163] RP=(t*(Vbat-Vout)) / (R*C1),

[0164] Therefore, the time period Ton is defined by the following relation (11):

[0165] Ton=(Vref*(R*C1) / (Vbat-Vout)),

[0166] When the slope RP is compared with the potential Vref to define the time period Ton.

[0167] Figure 6 It is shown in the form of a circuit. Figure 3 An alternative embodiment of the converter. More specifically, in this variation, the slope of the potential ramp RN is proportional to the difference between potentials Vbat and Vout. Figure 6 Ramp generators 304 and 310 are shown.

[0168] Figure 6 The ramp generator 304 and Figure 5 The ramp generator is the same.

[0169] The ramp generator 310 includes a capacitor C2 connected between the rail 3 and the (sixth) node 600, which is configured to transmit a potential ramp RN.

[0170] The ramp generator 310 further includes a current source 602, which in Figure 6 The area is delimited by a dashed box. The first terminal of current source 602 is connected to rail 5, and the second terminal of current source 602 is connected to node 600. Current source 602 is configured to transmit current I4, which has a value proportional to the difference between potentials Vbat and Vout.

[0171] Current source 602 includes current source 502 (with ramp generator 304) Figure 5 The components are the same, namely amplifier 508, resistor R, and transistor 504. In fact, the advantage comes from the fact that the current I2 generated by amplifier 508, resistor R, and transistor 504 generates current I4.

[0172] The current source 602 further includes a (sixth) MOS transistor 604, preferably an NMOS transistor, which is connected between rail 5 and node 600. In other words, a conductive terminal (e.g., its source) of transistor 604 is connected to rail 5, and another conductive terminal (e.g., its drain) of transistor 604 is connected to node 600 and corresponds to the second terminal of current source 602.

[0173] The control terminal of transistor 604 is connected to the control terminal of transistor 504, and therefore to the output of operational amplifier 508, although this connection is made in order to avoid overload. Figure 6 It is not shown in the text.

[0174] Therefore, the current I4 flowing through transistor 604 is proportional to, and preferably equal to, current I2. Current I4 is effectively proportional to the difference between potentials Vbat and Vout.

[0175] The ramp generator 310 includes circuit 606 (here, a switch), which is controlled by the signal cmdN ( Figure 3 It controls and is configured to start or stop the potential ramp RN based on the state of the signal cmdN.

[0176] More specifically, in Figure 6 In the embodiment shown, switch 606, implemented for example by a MOS transistor (preferably a PMOS transistor), is connected in parallel with capacitor C2, i.e., switch 606 is between rail 3 and node 600.

[0177] When signal cmdN is in the first state (e.g., low state), switch 606 is turned on, and potential RN is equal to potential Vbat.

[0178] When the signal cmdN switches from its first state to its second state (e.g., high state), switch 606 is closed. According to the following relationship (12), capacitor C2 is charged by current I4 and its potential RN decreases with time t:

[0179] RN = Vbat - (t*I4) / C2,

[0180] I4 is proportional to the difference between potentials Vbat and Vout.

[0181] Therefore, similar to the slope of the potential slope RP, the slope of the potential slope RN is proportional to the difference between potentials Vbat and Vout.

[0182] As an example, when the transistors 504 and 604 are designed to make the currents I2 and I4 equal, the potential slope RN verifies the following relationship (13):

[0183] RN=Vbat-(t*(Vbat-Vout)) / (R*C2),

[0184] Therefore, the time period Toff is defined by the following relation (14):

[0185] Toff=((Vbat-Vref)*(R*C2) / (Vbat-Vout)),

[0186] When the ramp RN is compared with the potential Vref to define the time period Toff.

[0187] In fact, the potential Vout can be considered equal to its setpoint value, that is, the potential Vref in this example. Therefore, the time period Toff can be considered equal to the product of the resistance R and the capacitance C2.

[0188] Although Figure 6 The circuit has been described as corresponding to a ramp generator 304 configured to transmit a ramp RP and a ramp generator 310 configured to transmit a ramp RN, but such a circuit can also be regarded as a single ramp generator including two outputs 500 and 600 configured to transmit potential ramps (RP and RN, respectively), and the single generator is then controlled by two signals cmdP and cmdN.

[0189] Furthermore, regarding the case where the potential Vbat decreases from each ramp RN... Figure 3 and Figure 5An embodiment of the ramp generator 310 has been described; in other embodiments, each ramp RN increases from a reference potential.

[0190] In each embodiment where the ramp RN increases from the reference potential, as long as the signal sel( Figure 3 When the potential RN is in its second state, the signal COMP is in its first state, such as a low state, as long as the potential RN is less than the potential Vref; and as soon as the potential RN becomes greater than the potential Vref, it switches to its second state, such as a high state. The switching of the signal COMP from its first state to its second state marks the end of the time period Toff, and the circuit 300 then controls the transistor 13 to be set to the off state. Preferably, the circuit 300 simultaneously controls the end of the potential ramp RN via the signal cmdN. The above operation also applies to the case where the potential RN is compared with the potential Vout to define the time period Toff, rather than being compared with the potential Vref.

[0191] Figure 7 It is shown in the form of a circuit. Figure 3 Another alternative embodiment of the converter portion. More specifically, in this variation, each ramp RN increases from the reference potential GND, and the time period Toff corresponds to the time taken for each ramp RN to reach the potential Vref or Vout.

[0192] The ramp generator RN is a MOS transistor 700, preferably an NMOS transistor. A conductive terminal of transistor 700 (e.g., its source) is connected to node 702, which is coupled to rail 5 via resistor R1. Another conductive terminal of transistor 700 (e.g., its drain) is connected to node 704, which is coupled to rail 3.

[0193] The ramp generator RN further includes an operational amplifier 706 having an input configured to receive a potential Vout (i.e., its non-inverting input (+)), another input connected to node 702 (i.e., the inverting input (-)), and an output connected to the control terminal of transistor 700.

[0194] Transistor 700 is then controlled by amplifier 706, causing node 702 to be at potential Vout. Therefore, the current I6 flowing through transistor 700 is defined by the following relationship (15):

[0195] I6 = Vout / R1.

[0196] The ramp generator RN further includes a capacitor C3 connected between the guide rail 5 and the output node 708 of the ramp generator. The ramp RN is available at node 708.

[0197] The current mirror 710 of the ramp generator is capable of delivering a current I7 proportional to (preferably equal to) the current I6 to node 708. More specifically, the current mirror 710 includes a first branch coupling node 704 to rail 3 and a second branch coupling node 708 to rail 3. Each branch of the current mirror 710 includes a MOS transistor, preferably a PMOS transistor.

[0198] The ramp generator RN includes circuit 712 (which is a switch in this case), which is controlled by the signal cmdN ( Figure 3 It is controlled and configured to start or stop the potential ramp RN according to the state of the signal cmdN.

[0199] More specifically, in Figure 7 In the embodiment shown, switch 712, implemented for example by a MOS transistor (preferably an NMOS transistor), is connected in parallel with capacitor C3, i.e., switch 712 is between node 708 and rail 5.

[0200] When the signal cmdN is in the first state (e.g., high state), switch 712 is turned on, and the potential RN is equal to the reference potential GND.

[0201] When the signal cmdN switches from its first state to its second state (e.g., low state), switch 712 is turned off. According to the following relationship (16), capacitor C3 is charged by current I7 and its potential RN increases with time t:

[0202] RN=(t*I7) / C3

[0203] Therefore, when the slope RN is compared with the potential Vref to define the time period Toff, the time period Toff is defined by the following relation (17):

[0204] Toff = Vref * C3 / I7

[0205] As an example, when current I7 equals current I6 and ramp RN is compared with potential Vref to define time period Toff, time period Toff is defined by the following relation (18):

[0206] Toff = Vref * C3 * R1 / Vout

[0207] In fact, the potential Vout can be considered equal to its setpoint value, i.e., the potential Vref in this example. Therefore, in the example where currents I6 and I7 are equal, the time period Toff can be considered equal to the product of resistor R1 and capacitor C3. Those skilled in the art will be able to determine the values ​​of resistor R1 and capacitor C3 so that at the end of the time period Toff, the current IL in inductor 15 ( Figure 1 and Figure 3 The value is zero.

[0208] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of the various embodiments and variations can be combined, and other variations will occur to them. Specifically, the converter 1, whose time period Ton is proportional to the reciprocal of the potential difference Vbat – Vout, can utilize a ramp generator 304 (such as regarding…). Figures 3 to 6 This can be achieved in a manner other than those described. Furthermore, those skilled in the art will be able to apply the above description to situations where, for at least the described signal, the high and low states of the signal are reversed.

[0209] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0210] Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the invention. Therefore, the above description is merely illustrative and not intended to be limiting. The invention is limited to what is defined by the following claims and their equivalents.

Claims

1. A voltage converter, comprising: A first transistor is coupled between a first rail and a first node, the first rail being configured to receive a power supply voltage. A second transistor is coupled between the first node and a second rail, the second rail being configured to receive a reference voltage. An inductor is coupled between the first node and the second node, the second node being configured to transmit the output voltage. A first ramp generator is configured to transmit a first voltage ramp, the first voltage ramp having a slope proportional to a first voltage difference between the power supply voltage and the output voltage; A second ramp generator is configured to transmit a second voltage ramp, the second voltage ramp having a slope proportional to the first voltage difference. In each operating cycle of the voltage converter: The first transistor is kept in the on state for a first time period, the first time period being determined based on a comparison between the first voltage ramp and the output voltage or voltage set point, and The second transistor is kept in the on state for a second time period, the second time period being determined by comparing the second voltage ramp with the output voltage or the voltage setpoint.

2. The voltage converter according to claim 1, wherein the reference voltage is ground.

3. The voltage converter of claim 1, further comprising a control circuit configured to continuously control the following during each operating cycle of the voltage converter: Set the first transistor to the on state; Set the first transistor to the off state and the second transistor to the on state; as well as The second transistor is set to the off state, and the control circuit is configured to keep the first transistor in the on state for the first time period during each operating cycle.

4. The voltage converter according to claim 3, wherein the control circuit includes a state machine.

5. The voltage converter of claim 3, wherein in each operating cycle of the voltage converter, the control circuit is configured to keep the second transistor in the on state for the second time period.

6. The voltage converter of claim 3, wherein the control circuit is further configured to start an operating cycle when the output voltage is less than the voltage setpoint.

7. The voltage converter of claim 3, wherein the first time period is proportional to the reciprocal of the first voltage difference between the power supply voltage and the output voltage.

8. The voltage converter of claim 1, wherein the second voltage ramp is configured to decrease from the power supply voltage, and the second time period corresponds to the time taken for the second voltage ramp to decrease from the power supply voltage to the output voltage or the voltage setpoint.

9. The voltage converter of claim 1, wherein the first voltage ramp is configured to increase from the reference voltage, and the first time period corresponds to the time taken for the first voltage ramp to increase from the reference voltage to the output voltage or the voltage setpoint.

10. The voltage converter of claim 3, wherein the control circuitry further includes a comparator configured to compare the first voltage ramp with the output voltage or the voltage setpoint.

11. The voltage converter of claim 3, wherein the first ramp generator comprises: A capacitor is coupled between the second rail and a third node, the third node being configured to transmit the first voltage ramp. as well as A current source having a first terminal coupled to the first rail and a second terminal coupled to the third node, the current source being configured to deliver a current having a value proportional to the first voltage difference.

12. The voltage converter of claim 11, wherein the current source comprises: The third transistor is coupled between the second rail and the fourth node; A resistor is coupled between the first guide rail and the fourth node; The fourth transistor is coupled between the second rail and the fifth node; The fifth transistor is coupled between the first guide rail and the fifth node; The sixth transistor is assembled as a mirror image of the fifth transistor and is coupled between the first rail and the second terminal of the current source; as well as An operational amplifier having a first input configured to receive the output voltage, a second input coupled to the fourth node, and an output coupled to the control terminals of the third transistor and the fourth transistor.

13. The voltage converter of claim 12, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are metal-oxide-semiconductor (MOS) transistors.

14. The voltage converter of claim 12, wherein the first input of the operational amplifier is an inverting input and the second input of the operational amplifier is a non-inverting input.

15. The voltage converter of claim 11, wherein the first ramp generator further comprises a switch coupled in parallel with the capacitor.

16. The voltage converter of claim 15, wherein the control circuit is further configured to control the switching off at the beginning of each operating cycle of the voltage converter.

17. A method of operating a voltage converter, the method comprising: The power supply voltage is received on the first track; The reference voltage is received in the second track; The regulated output voltage is transmitted at the first node; A first voltage slope is transmitted at the output of the first slope generator, the first voltage slope having a slope proportional to a first voltage difference between the power supply voltage and the regulated output voltage; A second voltage ramp is transmitted at the output of the second ramp generator. This second voltage ramp has a slope proportional to the first voltage difference. In each operating cycle of the voltage converter, continuously: The first transistor is set to the on state and is coupled between the first track and the second node that is coupled to the first node through an inductor; The first transistor is set to the off state, and the second transistor is set to the on state, the second transistor being coupled between the second node and the second track; as well as The second transistor is set to the off state, wherein, in each operating cycle of the voltage converter: The first transistor is held in the on state for a first time period, the first time period being determined based on a comparison between the first voltage ramp and the regulated output voltage or voltage setpoint. The second transistor is kept in the on state for a second time period, which is determined by comparing the second voltage ramp with the regulated output voltage or the voltage setpoint.

18. A circuit, the circuit comprising: The first power terminal is configured to receive power supply voltage; The second power supply terminal is configured to receive a reference voltage; The first transistor is coupled between the first power terminal and the first node; The second transistor is coupled between the first node and the second power supply terminal; The third terminal is configured to be coupled to the first node via an inductor; A first ramp generator is configured to transmit a first voltage ramp, the first voltage ramp having a slope proportional to a first voltage difference between the power supply voltage and the output voltage. A second ramp generator is configured to transmit a second voltage ramp, the second voltage ramp having a slope proportional to the first voltage difference; as well as The control circuit is configured to continuously perform the following in each operating cycle: Set the first transistor to the ON state. Set the first transistor to the off state and the second transistor to the on state, and The second transistor is set to the off state, wherein in each operating cycle: The first transistor is held in the on state for a first time period, the first time period being determined based on a comparison between the first voltage ramp and the output voltage or voltage setpoint. The second transistor is kept in the on state for a second time period, the second time period being determined by comparing the second voltage ramp with the output voltage or the voltage setpoint.

19. The circuit of claim 18, wherein the control circuit comprises: A state machine having a first output coupled to the control terminal of the first transistor, a second output coupled to the control terminal of the second transistor, and a first input coupled to the third terminal; as well as The selection circuit has a first input coupled to the output of the first ramp generator, a second input coupled to the second ramp generator, and an output coupled to the second input of the state machine.

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