Method and system for offloading lookup operations to a nand offload device

Abstract

A method and system of offloading lookup operations to a NAND offload device is disclosed. The method includes receiving, by the NAND offload device from a key-value solid-state drive (KV SSD) NAND interface, a NAND read command, wherein the NAND offload device is connected between the KV SSD NAND interface and a NAND device using a NAND bus; determining, by the NAND offload device, whether the NAND read command includes an information element that indicates an indirect read operation; based on determining that the NAND read command includes the information element, performing, by the NAND offload device, the indirect read operation; and based on determining that the NAND read command does not include the information element: passing, by the NAND offload device, the NAND read command to the NAND device over the NAND bus, and configuring, by the NAND offload device, a switch to pass a response message from the NAND device to the KV SSD NAND interface at an output gate.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Indian application 201941041568, filed on 14 October 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to memory systems, and more specifically, to a method and memory system for offloading lookup operations to a NAND offloading device. Background Technology

[0004] Typically, enterprise solid-state drives (SSDs) that support <key, value>-based access (often called key-value (KV) SSDs) perform multi-level lookups based on the key to locate the location in the NAND memory where the value corresponding to the key is stored. In the example, the key and value can be terms used in a database. The key could be an employee ID, and the value could be an employee name, address, etc. The <key> is used to perform a lookup in the NAND memory. Each level of lookup may involve transfers with the NAND and processing within the SSD controller to search for the key, before the next level of lookup is performed in the NAND memory. Because the SSD may also be performing other operations in parallel, such as garbage collection (GC) or input / output (I / O) with other NAND chips, latency may be introduced between the levels of lookups.

[0005] Figure 1A This illustrates an example scenario for KV read operations. For example... Figure 1A As shown, a <key, value> lookup method can be described based on hashing. In operation S102, the KV SSD can receive a read request from the processor (100) based on the key and calculate the hash of the key. In operation S104, the KV SSD can perform a lookup in a first-level table in RAM based on the hash value. In an embodiment, first level can refer to, for example, a first-level lookup or a level 1 lookup. In operation S106, based on the NAND address found in the first-level table lookup, the KV SSD can perform a NAND read operation on a page (which may be, for example, a second-level entry) and a binary search on the key within the page. In an embodiment, second level can refer to, for example, a second-level lookup or a level 2 lookup. In operation S108, the KV SSD can perform a NAND read operation at the page address and offset identified at operation S106 and transfer the <value>. Depending on the load in the SSD, the processing of the second-level entry at operation S106 may be delayed, resulting in a delay in the overall <key, value> read.

[0006] Figure 1BThis is a schematic diagram of a NAND device (200). The NAND device (200) may include a controller (202), a voltage selector (204), a NAND memory array (206), a latch (208), a column decoder (210), a NAND bus (212), and a row decoder (214). The controller (202) may include read circuitry (202a), programming circuitry (204a), and erase circuitry (206a). The row decoder (214) and column decoder (210) can be used to select a single row and at least one column of the NAND memory array (206) based on an address applied to the NAND device (200).

[0007] A voltage selector (204) can be connected to a column line corresponding to a column of the NAND memory array (206) to supply a voltage level on the addressed column line corresponding to the data value stored in the NAND device (200). The NAND device (200) may be able to perform write operations, thereby using programming circuitry (204a) and erase circuitry (206a) to write (e.g., program to or erase from) memory cells selected by write addresses applied to the row decoder and column decoder (214 and 210) during a write operation in the NAND device (200). By using read circuitry (206a), a read operation can be used during a read operation in the NAND device (210) to retrieve data previously written to the NAND memory array (206) selected by read addresses applied to the row decoder and column decoder (214 and 210). The latch (208) can sense data from the NAND memory array (206) of the selected row during a read operation and latch n bits of data on the NAND bus (212) via the column decoder (210) during a programming operation.

[0008] Therefore, it is hoped that the above-mentioned shortcomings or other deficiencies can be addressed or at least a useful alternative can be provided. Summary of the Invention

[0009] A method and memory system are provided for offloading lookup operations to a NAND offloading device.

[0010] A method is also provided for receiving NAND read commands from the NAND interface of a key-value solid-state drive (KV SSD) by a NAND offloading device.

[0011] It also provides a NAND offloading device on the NAND bus placed between the KV SSD NAND interface and the NAND device.

[0012] A method is also provided for determining whether a NAND read command includes information elements indicating an indirect read operation by a NAND unloading device.

[0013] A method is also provided in which an indirect read operation is performed by the NAND unloading device if the NAND read command includes the information element.

[0014] A method is also provided in which, if the NAND read command does not include the information element, the NAND read command is passed to the NAND device via the NAND bus by the NAND offloading device, and the NAND offloading device configures a switch to pass the response from the NAND device to the KV SSD NAND interface at the output gate.

[0015] According to an embodiment, a method for offloading a lookup operation to a NAND offloading device includes: receiving a NAND read command from a key-value solid-state drive (KV SSD) NAND interface by the NAND offloading device, wherein the NAND offloading device is connected between the KV SSD NAND interface and the NAND device using a NAND bus; determining whether the NAND read command includes an information element indicating an indirect read operation by the NAND offloading device; performing the indirect read operation by the NAND offloading device based on the determination that the NAND read command includes the information element; and transmitting the NAND read command to the NAND device via the NAND bus by the NAND offloading device based on the determination that the NAND read command does not include the information element, and configuring a switch by the NAND offloading device to transmit a response message from the NAND device to the KV SSD NAND interface at an output gate.

[0016] According to an embodiment, a NAND offloading device connected between a key-value solid-state drive (KV SSD) NAND interface and a NAND device via a NAND bus includes: a NAND offloading controller; a key size register connected to the NAND offloading controller and configured to store the size of a key to be used for lookup; a low-density parity-checking (LDPC) engine connected to the NAND offloading controller and configured to pull data from at least one NAND device; and a buffer RAM configured to store the data pulled by the LDPC engine, wherein the NAND offloading controller is configured to pass input / output (IO) commands received from the KV SSD NAND interface to the NAND device and to copy response messages received from the NAND device to the KV SSD NAND interface.

[0017] According to an embodiment, a memory system for offloading lookup operations to a NAND offloading device includes: a key-value solid-state drive (KV SSD) NAND interface; a NAND device; a NAND bus disposed between the KV SSD NAND interface and the NAND device; and a NAND offloading device disposed on the NAND bus, wherein the NAND offloading device includes a NAND offloading controller configured to pass input / output (IO) commands from the KV SSD NAND interface to the NAND device and to copy at least one response message received from the NAND device to the KV SSD NAND interface. Attached Figure Description

[0018] The accompanying drawings illustrate embodiments, and similar reference numerals indicate corresponding parts throughout the various figures. A better understanding of the embodiments will be achieved from the following detailed description with reference to the accompanying drawings, in which:

[0019] Figure 1A This is an example scenario illustrating KV read operations;

[0020] Figure 1B This is a schematic diagram of an example of a NAND device;

[0021] Figure 2 This is a schematic diagram of a memory system for offloading a lookup operation to a NAND offloading device according to an embodiment;

[0022] Figure 3 This is an example flowchart illustrating a method for a NAND unloading controller to process indirect read operations according to an embodiment;

[0023] Figure 4 This is an example flowchart illustrating a method for processing indirect read operations for a NAND unloading controller according to an embodiment;

[0024] Figure 5 This is a timing diagram illustrating a KV read operation on a NAND device according to an embodiment;

[0025] Figure 6 This represents the first-level table according to the embodiment;

[0026] Figure 7 This is a flowchart illustrating various operations performed in a first-level table according to an embodiment, and determining whether to issue an indirect read or a normal read;

[0027] Figure 8 This is a flowchart illustrating a method for a <key, value> insertion operation during a write operation according to an embodiment. Detailed Implementation

[0028] The embodiments herein, along with their various features and advantageous details, are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted to avoid unnecessarily obscuring the embodiments herein. Furthermore, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. Unless otherwise indicated, the term "or" as used herein means non-exclusive or. The examples used herein are intended only to facilitate understanding of how the embodiments herein can be practiced and are also intended to enable those skilled in the art to practice the embodiments herein. Therefore, the examples should not be construed as limiting the scope of the embodiments.

[0029] In the art, embodiments are conventionally described and illustrated in terms of blocks that perform the described functions or multiple functions. These blocks (which may be referred to herein as units or modules, etc.) are physically implemented by analog or digital circuitry such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc., and optionally, may be driven by firmware and software. For example, the circuitry may be specifically implemented in one or more semiconductor chips or specifically implemented on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Without departing from the scope of the invention, the various blocks of an embodiment may be physically separated into two or more interactive and discrete blocks. Similarly, without departing from the scope of the invention, the blocks of an embodiment may be physically combined into more complex blocks.

[0030] The accompanying drawings are used to aid in the easy understanding of the various technical features. It should be understood that the embodiments presented herein are not limited to the drawings. Therefore, this disclosure should be construed as extending to any modifications, equivalents, and substitutions, except for those specifically illustrated in the drawings. Although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are generally used only to distinguish one element from another.

[0031] Therefore, embodiments herein disclose a method for offloading a lookup operation to a NAND offloading device. The method may include receiving a NAND read command from a KV SSD NAND interface by the NAND offloading device. The NAND offloading device may be located on a NAND bus between the KV SSD NAND interface and the NAND device. Furthermore, the method includes determining whether the NAND read command includes an information element indicating an indirect read operation. Additionally, the method may include performing an indirect read operation by the NAND offloading device in response to determining that the NAND read command includes the information element. Furthermore, the method may include transmitting the NAND read command to the NAND device via the NAND bus in response to determining that the NAND read command does not include the information element, and configuring a switch by the NAND offloading device to transmit a response from the NAND device to the KV SSD NAND interface at an output gate.

[0032] These examples can be used to improve the latency of <key, value> lookups in KV implementations in host machines or SSDs. The examples are scalable to implement multi-level lookups. These examples can be used to offload lookup operations to NAND offloading devices without any overhead. These examples can be used to optimize lookup operations and improve <key, value> lookup latency by transparently offloading lookup operations to NAND offloading devices on the NAND bus. In the examples, the key and value can be terms used in a database. The key could be an employee ID, and the value could be an employee name, address, etc. The key can be used to perform lookups within the NAND device.

[0033] Figure 2 This is a schematic diagram of a memory system (1000) according to an embodiment for offloading a lookup operation to a NAND offloading device (400). In this embodiment, the memory system (1000) includes a NAND device (200), a KV SSD NAND interface (300), and a NAND offloading device (400). The operation and function of the NAND device (200) are as described above. Figure 1B The similarities described.

[0034] In this embodiment, the memory system (1000) includes a NAND bus positioned between the KV SSD NAND interface (300) and the NAND device (200). A NAND offloading device (400) is positioned on the NAND bus. The NAND offloading device (400) includes a NAND offloading controller (402), a buffer RAM (404), a low-density parity-checking (LDPC) engine (406), and a key-size register (408). The NAND offloading controller (402) transmits input / output (IO) commands from the KV SSD NAND interface (300) to the NAND device (200) and copies at least one response received from the NAND device (200) back to the KV SSD NAND interface (300).

[0035] A key size register (408) is connected to the NAND offload controller (402). The key size register (408) stores the size of the key to be used during lookup. An LDPC engine (406) is connected to the NAND offload controller (402), where the LDPC engine (406) pulls data from the NAND device (200). A buffer RAM (404) stores the data pulled by the LDPC engine (406). The NAND offload controller (402) passes input / output (IO) commands received from the KV SSD NAND interface (300) to the NAND device (200) and copies the responses received from the NAND device (200) back to the KV SSD NAND interface (300).

[0036] In this embodiment, the NAND offload controller (402) is configured to receive a NAND read command from the KV SSD NAND interface (300). After receiving the NAND read command from the KV SSD NAND interface (300), the NAND offload controller (402) is configured to determine whether the NAND read command includes an information element indicating an indirect read operation. In this embodiment, the information element is a bit of information configured in a first-level table in RAM to indicate whether the location of the information element is at the NAND device (200) storing a second-level entry. In this embodiment, the first level may refer to, for example, a first-level lookup or a level 1 lookup, and the second level may refer to, for example, a second-level lookup or a level 2 lookup.

[0037] In this embodiment, the NAND unloading controller (402) is configured to calculate a hash value based on the key associated with the NAND read command and perform a lookup of the second-level NAND page address corresponding to the hash value in a first-level table in the buffer RAM (404). Based on the lookup of the second-level NAND page address corresponding to the hash value in the first-level table in the buffer RAM (404), the NAND unloading controller (402) is configured to determine whether the NAND read command includes an information element based on the NAND page address.

[0038] In an embodiment, if the NAND read command includes an information element, the NAND unloading controller (402) is configured to perform an indirect read operation.

[0039] In an embodiment, if the NAND read command does not include an information element, the NAND unloading controller (402) is configured to pass the NAND read command to the NAND device (200) via the NAND bus and is configured to switch to pass the response from the NAND device (200) to the KV SSD NAND interface (300) via an output gate.

[0040] In this embodiment, the NAND read command is transmitted to the NAND device (200) via the NANS bus by using the Flash Translation Layer (FTL) module (302) to read the NAND page containing the mapping information of the key associated with the NAND read command, using the FTL module (302) to read the NAND page containing the value corresponding to the key, and transmitting the NAND read command to the NAND device (200) via the NAND bus based on the value corresponding to the key.

[0041] In this embodiment, the NAND offloading controller (402) is configured to receive a NAND read command from the KV SSD NAND interface (300). Furthermore, the NAND offloading controller (402) is configured to determine that the NAND read command is an indirect read command. Based on this determination, the NAND offloading controller (402) is configured to modify the NAND read command into a normal NAND read command and send the normal read command to the NAND device (200). Based on the normal read command, the NAND offloading controller (402) is configured to receive a response message from the NAND device (200). Furthermore, the NAND offloading controller (402) is configured to store the response message in a buffer RAM (404). Furthermore, the NAND offloading controller (402) is configured to search for a key for the next-level mapping within the NAND pages stored in the buffer RAM (404). Furthermore, the NAND offloading controller (402) is configured to send the NAND read command to the NAND device (200) at a location identified by the next-level mapping. In addition, the NAND offload controller (402) is configured to forward response messages from the NAND device (200) to the KV SSD NAND interface (300).

[0042] In this embodiment, the NAND offload controller is configured to program keys and values ​​to an additional point of the FTL module (302) in an open block. Furthermore, the NAND offload controller is configured to calculate a hash value based on the key and determine the page address of the second-level table. Furthermore, the NAND offload controller is configured to update the entries of the second-level table to the additional point of the NAND block holding the entries of the second-level table. Furthermore, the NAND offload controller is configured to determine whether the NAND wafer programmed with the keys and values ​​is the same as the NAND wafer programmed with the second-level table. Furthermore, the NAND offload controller is configured to determine whether the bit to be set is in the same NAND wafer. If the bit to be set is in the same NAND wafer, the NAND offload controller is configured to set a first-level entry for the hash value corresponding to the key. Furthermore, if both the second-level entry and the <key, value> mapping are in the same NAND wafer, when setting the bit IndRead in the first-level table, the NAND offload controller is configured to update the page address of the second-level entry in the first-level entry for the hash value. The first-level table can be updated to point to the second-level entry.

[0043] According to an embodiment, the indirect read command can be processed by the unloading controller as described below.

[0044] In this embodiment, the NAND offload controller (402) is located on the NAND bus between the KV SSD NAND interface (300) and the NAND device (200). All NAND devices (which may be, for example, NAND chips) on a given NAND channel can be connected to a single NAND offload controller. For simplicity, it will be described that one NAND device (200) is managed by one NAND offload controller. All NAND IO operations on the NAND device pass through the NAND offload controller (402), which transmits commands to the NAND device (200) and copies responses from the NAND device (200) back to the KV SSD NAND interface (300).

[0045] although Figure 2 Various hardware components of the memory system (1000) are shown, but it will be understood that other embodiments are not limited thereto. In other embodiments, the memory system (1000) may include fewer or more components. Furthermore, the labels or names of the components are for illustrative purposes only and do not limit the scope of the invention. One or more components may be combined together to perform the same or substantially similar functions to offload lookup operations to the NAND offloading device (400).

[0046] Figure 3 This is an example flowchart illustrating a method (S300) for an offloading controller to process an indirect read according to an embodiment. Operations (S302-S308) are performed by a NAND offloading device (400). In operation S302, the method includes receiving a NAND read command from a KV SSD NAND interface (300). In operation S304, the method includes determining whether the NAND read command includes an information element indicating an indirect read operation. If the NAND read command includes an information element indicating an indirect read operation, then in operation S306, the method includes performing the indirect read operation. If the NAND read command does not include an information element indicating an indirect read operation, then in operation S308, the method includes transmitting the NAND read command to a NAND device (200) via a NAND bus and configuring a switch to transmit a response from the NAND device (200) to the KV SSD NAND interface (300) at an output gate.

[0047] Figure 4 This is an example flowchart illustrating a method (S400) for processing indirect read operations by a NAND offloading controller (402) according to an embodiment. The steps and operations can be compared with... Figure 2 Similar to those described in [the document]. In an embodiment, if LDPC decoding fails or the key is not found during a binary search in the key latch, the NAND unloading controller (402) can cause the sensing operation to fail.

[0048] In operation S402, the method includes determining whether the incoming command is an indirect read command. If the incoming command is not an indirect read command, then in operation S404, the method includes passing DQ bus data from the KV SSD NAND interface (300) to the NAND device (200). In operation S406, the method includes configuring a switch to pass a NAND response from the NAND device (200) to the KV SSD NAND interface (300).

[0049] If the incoming command is an indirect read command, then in operation S408, the method includes performing a NAND read against the second-level entry. In operation S410, the method includes pulling the NAND device response to buffer RAM (404) via the LDPC engine (406). In operation S412, the method includes determining whether LDPC decoding was successful. If LDPC decoding was unsuccessful, then in operation S418, the method includes causing the sensing operation to fail. If LDPC decoding was successful, then in operation S414, the method includes reading the key size. In operation S416, the method includes determining whether the key was found using a binary search. If the key was not found using a binary search, then in operation S418, the method includes causing the sensing operation to fail.

[0050] If the key is found using a binary search, then in operation S420, the method includes issuing a NAND read for the value. In operation S422, the method includes configuring a switch to pass a NAND response from the NAND device (200) to the KV SSD NAND interface (300). In operation S424, the method includes transferring the value from the NAND device (200) to the KV SSD NAND interface (300).

[0051] Figure 5 This is a timing diagram indicating the KV read operation on the NAND device (200) according to the embodiment. Figure 5The diagram shows the transactions seen by the KV SSD NAND interface (300). After issuing an indirect read operation command, the KV SSD NAND interface detects that the NAND device (200) (which may be, for example, a NAND chip) is busy. During this period, the NAND unloading controller (402) can perform an intermediate-level lookup. When ready, a signal is used to notify that a value is available in the NAND latch and can be pulled. Additionally, DQ<7:0>: indicates the data bus, which is used to transfer NAND commands + addresses from the processor (100) to the NAND device (200) and to transfer data between the processor (100) and the NAND device (200). Furthermore, R / B: is a signal from the NAND device (200) to the processor (100) indicating whether the NAND device (200) is currently busy. When the NAND device (200) is busy, the processor (100) should not send new commands.

[0052] The command phase shown is not a single signal. Transmission on the DQ bus is divided into multiple phases. The command phase indicates the transmission status. First, the processor (100) sends command and address information to the NAND device (200). The address information consists of the row and column numbers of the NAND memory cells. The command and address are transmitted via the DQ bus. Once the NAND device (200) receives the command, it indicates a busy signal to the processor (100). When the busy signal is off, the processor (100) can retrieve the data and display it. <dout>.

[0053] Figure 7 This is a flowchart illustrating a method (S700) for performing a lookup operation in a first-level table and determining whether to issue an indirect read or a normal read according to an embodiment. The operation (S702-710) can be performed by a flash translation layer (FTL) module (302) running in the KV SSD NAND interface (300).

[0054] Method S700 can be used to introduce whether the location of the indicator value in the first-level table is a bit (IndRead) in the same NAND chip where a second-level entry is stored. For example... Figure 7 As shown, the presence of this bit indicates whether an indirect read operation can be performed.

[0055] In operation S702, the method includes calculating a hash. In operation S704, the method includes providing a first-level table in RAM for the entry corresponding to the hash. In operation S706, the method includes determining whether IndRead is 1. If IndRead is 1, then in operation S712, the method includes performing an indirect read of the NAND page holding the value corresponding to the key. If IndRead is not equal to 1, then in operation S708, the method includes reading the NAND page holding the mapping information of the key. In operation S710, the method includes reading the NAND page holding the value corresponding to the key.

[0056] Figure 8 This is a flowchart illustrating a method (S800) for performing a <key, value> insertion operation during a write operation according to an embodiment. In this embodiment, the IndRead bit may be included in a level 1 table, such as, for example... Figure 6 As shown. This bit can be set if the level 2 entry and value are in the same chip. This can be identified during the <key, value> insertion operation. Figure 8 Show reference Figure 8 The insertion process. In order to benefit from indirect read operations, the FTL module (302) can maintain open blocks to store values ​​and corresponding Level 2 entries (which may correspond to, for example, metadata) in the same NAND chip as much as possible.

[0057] In operation S802, the method includes programming <key, value> to an additional point of the FTL module (302) in the open block. During this operation, the NAND chip used (e.g., chip D1) can be noted. In operation S804, the method includes calculating a hash (H) based on the key from a first-level entry of a given hash and finding a second-level page address. In operation S806, the method includes updating the second-level entry to an additional point of the NAND block holding the second-level entry. During this operation, the NAND chip used (e.g., chip D2) can be noted. In operation S808, the method includes determining whether D1 == D2. If D1 == D2, then in operation S810, the method includes setting IndRead for the hash (H) in the first-level entry. In operation S812, the method includes updating the page address of the second-level entry for the hash (H) in the first-level entry.

[0058] The various actions, behaviors, blocks, steps, etc. discussed above (e.g., methods (S300, S400, S700, and S800)) can be executed in the presented order, in a different order, or simultaneously. Furthermore, in some embodiments, without departing from the scope of the invention, some actions, behaviors, blocks, steps, etc., can be omitted, added, modified, skipped, etc.

[0059] The embodiments disclosed herein can be implemented using at least one software program that runs on at least one hardware device and performs network management functions to control elements.

[0060] The above description of specific embodiments will so fully reveal the general nature of the embodiments herein that others can readily modify and / or adapt these specific embodiments for various applications by applying present knowledge without departing from the general concept. Therefore, such modifications and adaptations should and are intended to be understood as being within the meaning and equivalents of the disclosed embodiments. It will be understood that the wording or terminology used herein is for descriptive purposes and not for limitation. Thus, although the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modifications within the spirit and scope of the embodiments described herein.< / dout>

Claims

1. A method for offloading a lookup operation to a NAND unmount device, comprising: The NAND offloading device receives a NAND read command from the NAND interface of the key-value solid-state drive, wherein the NAND offloading device is connected between the NAND interface of the key-value solid-state drive and the NAND device using a NAND bus; The NAND unloading device determines whether the NAND read command includes an information element indicating an indirect read operation; Based on the determination that the NAND read command includes the information element, the indirect read operation is performed by the NAND offloading device; and Based on the determination that the NAND read command does not include the information element: The NAND unloading device transmits the NAND read command to the NAND device via the NAND bus, and The NAND offloading device is configured to pass a response message from the NAND device to the NAND interface of the key-value solid-state driver at the output gate. The information element includes a one-bit information contained in the first-level table of the random access memory, and The information element indicates whether the information element is located at a NAND device storing a second-level entry.

2. The method according to claim 1, further comprising: The NAND offloading device calculates a hash value based on the key associated with the NAND read command; The NAND offloading device performs a lookup of the second-level NAND page address corresponding to the hash value in the first-level table of the random access memory; as well as The NAND offloading device determines whether the NAND read command includes the information element based on the second-level NAND page address.

3. The method according to claim 1, further comprising: The NAND page containing mapping information of the key associated with the NAND read command is read by the flash translation layer module included in the NAND interface of the key-value solid-state driver; The flash memory conversion layer module reads the NAND page holding the value corresponding to the key; as well as The flash memory conversion layer module transmits the NAND read command to the NAND device via the NAND bus based on the value corresponding to the key.

4. The method according to claim 1, further comprising: The NAND offloading device receives the NAND read command from the NAND interface of the key-value solid-state driver; The NAND unloading device determines that the NAND read command is an indirect read command; The NAND unloading device modifies the NAND read command into a normal read command; The normal read command is sent to the NAND device by the NAND offloading device; The NAND unloading device receives the response message from the NAND device based on the normal read command; The response message is stored in a buffered random access memory by the NAND offloading device; The NAND offloading device searches for a key for the next level mapping within the NAND pages stored in the buffer random access memory; The NAND offloading device sends the NAND read command to the NAND device at the location identified by the next-level mapping. as well as The response message is forwarded from the NAND device to the NAND interface of the key-value solid-state driver by the NAND offloading device.

5. The method according to claim 1, further comprising: Additional points in the flash translation layer module within the open block are used to program keys and values. Calculate the hash value based on the key programmed to the additional point; Determine the page address of the second-level table; Update the entries of the second-level table to the additional point of the NAND block that holds the entries of the second-level table; Determine whether the key and value programmed to the additional point are included in the same wafer as the second-level table; The key and the value programmed to the additional point are included in the same chip as the second-level table, with bits set for the hash value in the entry of the first-level table; as well as Based on the fact that the key and value programmed to the additional point are not included in the same wafer as the second-level table, the page address of the second-level table is updated in the entry of the first-level table.

6. A NAND offloading device, the NAND offloading device being connected between a key-value solid-state driver NAND interface including a flash conversion layer and a NAND device via a NAND bus, the NAND offloading device comprising: NAND offload controller; A key size register, which is connected to the NAND offload controller, is configured to store the size of the key to be used for lookup; A low-density parity check engine is connected to the NAND offload controller and is configured to pull data from at least one NAND device; as well as A buffered random access memory is configured to store data pulled by the low-density parity engine. The NAND offload controller is configured to pass input / output commands received from the NAND interface of the key-value solid-state drive to the NAND device, and to copy response messages received from the NAND device to the NAND interface of the key-value solid-state drive.

7. The NAND offloading device according to claim 6, wherein, The NAND offload controller is also configured to: Receive NAND read commands from the NAND interface of the key-value solid-state driver; Determine whether the NAND read command includes an information element indicating an indirect read operation; Based on the determination that the NAND read command includes the information element, the indirect read operation is performed, and Based on the determination that the NAND read command does not include the information element, the NAND read command is transmitted to the NAND device via the NAND bus, and a switch is configured to transmit the response message from the NAND device to the key-value solid-state driver NAND interface at the output gate. The information element includes a bit of information included in a first-level table in the random access memory, and The information element indicates whether the information element is located at a NAND device storing a second-level entry.

8. The NAND offloading device according to claim 7, wherein, The NAND offload controller is also configured to: Calculate the hash value based on the key associated with the NAND read command; A lookup of the second-level NAND page address corresponding to the hash value is performed in the first-level table of the random access memory; and The NAND read command is determined based on the second-level NAND page address to determine whether it includes the information element.

9. The NAND offloading device according to claim 7, wherein, The NAND offload controller is also configured to: Read the NAND page that holds mapping information of the key associated with the NAND read command; Read the NAND page that holds the value corresponding to the key associated with the NAND read command; and The NAND read command is transmitted to the NAND device via the NAND bus based on the value of the key associated with the NAND read command.

10. The NAND offloading device according to claim 7, wherein, The NAND offload controller is also configured to: Receive the NAND read command from the NAND interface of the key-value solid-state driver; It is determined that the NAND read command is an indirect read command; Modify the NAND read command to a normal NAND read command; Send the normal NAND read command to the NAND device; Receive the response message from the NAND device based on the normal NAND read command; The response message is stored in the buffered random access memory; Search for the key for the next level mapping within the NAND pages stored in the buffered random access memory; The NAND read command is sent to the NAND device at the location identified by the next-level mapping; and The response message is forwarded from the NAND device to the NAND interface of the key-value solid-state driver.

11. The NAND offloading device according to claim 7, wherein, The NAND offload controller is also configured to: The keys and values ​​are programmed into additional points of the flash conversion layer module in the open block; Calculate the hash value based on the key programmed to the additional point; Determine the page address of the second-level table; Update the entries of the second-level table to the additional point of the NAND block that holds the entries of the second-level table; Determine whether the key and value programmed to the additional point are included in the same wafer as the second-level table; The key and the value, based on the programming to the additional point, are included in the same chip as the second-level table, with bits set for the hash value in the entry of the first-level table; as well as Based on the fact that the key and value programmed to the additional point are not included in the same wafer as the second-level table, the page address of the second-level table is updated in the entry of the first-level table.

12. A memory system for offloading a lookup operation to a NAND offloading device, comprising: A key-value solid-state drive NAND interface, which includes a flash memory conversion layer; NAND devices; A NAND bus positioned between the NAND interface of the key-value solid-state driver and the NAND device; as well as A NAND offloading device disposed on the NAND bus, wherein the NAND offloading device includes a NAND offloading controller configured to transmit input / output commands from the NAND interface of the key-value solid-state drive to the NAND device, and to copy at least one response message received from the NAND device to the NAND interface of the key-value solid-state drive.

13. The memory system according to claim 12, wherein, The NAND offload controller is configured as follows: Receive NAND read commands from the NAND interface of the key-value solid-state driver; Determine whether the NAND read command includes an information element indicating an indirect read operation; Based on the determination that the NAND read command includes the information element, an indirect read operation is performed, and Based on the determination that the NAND read command does not include the information element, the NAND read command is transmitted to the NAND device via the NAND bus, and a switch is configured to transmit the response message from the NAND device to the key-value solid-state driver NAND interface at the output gate. The information element includes a bit of information included in a first-level table in the random access memory, and The information element indicates whether the information element is located at a NAND device storing a second-level entry.

14. The memory system according to claim 13, wherein, The NAND offload controller is also configured to: Calculate the hash value based on the key associated with the NAND read command; A lookup of the second-level NAND page address corresponding to the hash value is performed in the first-level table of the random access memory; and The NAND read command is determined based on the second-level NAND page address to determine whether it includes the information element.

15. The memory system according to claim 13, wherein, The NAND offload controller is also configured to: Read the NAND page that holds mapping information of the key associated with the NAND read command; Read the NAND page holding the value corresponding to the key; and The NAND read command is transmitted to the NAND device via the NAND bus based on the value corresponding to the key.

16. The memory system according to claim 13, wherein, The NAND offload controller is also configured to: Receive the NAND read command from the NAND interface of the key-value solid-state driver; It is determined that the NAND read command is an indirect read command; Modify the NAND read command to a normal NAND read command; Send the normal NAND read command to the NAND device; The response message is received from the NAND device based on the normal NAND read command; and The response message is stored in a buffered random access memory; Search for the key for the next level mapping within the NAND pages stored in the buffered random access memory; The NAND read command is sent to the NAND device at the location identified by the next-level mapping; and The response message is forwarded from the NAND device to the NAND interface of the key-value solid-state driver.

17. The memory system according to claim 13, wherein, The NAND offload controller is also configured to: Additional points in the flash translation layer module within the open block are used to program keys and values. Calculate the hash value based on the key programmed to the additional point; Determine the page address of the second-level table; Update the entries of the second-level table to the additional point of the NAND block that holds the entries of the second-level table; Determine whether the key and value programmed to the additional point are included in the same wafer as the second-level table; The key and the value, based on the programming to the additional point, are included in the same chip as the second-level table, with bits set for the hash value in the entry of the first-level table; as well as Based on the fact that the key and value programmed to the additional point are not included in the same wafer as the second-level table, the page address update of the second-level table is updated in the entry of the first-level table.

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