The circuit architecture of high order MUX is derived from low order MUX design

Abstract

A circuit architecture to derive a high order MUX from a low order MUX design. Various implementations described herein are directed to implementations of a high order multiplexer using low order multiplexers. In embodiments, the implementation requires some modifications to an existing circuit design of a low order multiplexer. Multiple multiplexers can be coupled to each other to form a common input port and output port. Using an enable signal, only one of the coupled multiplexers can be enabled at a time while the rest are switched off. Thus, upon receiving a select signal indicative of an address of a memory cell, the low order multiplexers coupled together function as a high order multiplexer in selecting the appropriate column corresponding to the memory cell.

Description

The circuit architecture for deriving high-level MUXs from low-level MUX designs.

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of Indian Patent Application No. 201941041459, filed on October 14, 2019, entitled “Circuit Architecture for Deriving High-Order MUX from Low-Order MUX Design”, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to a circuit architecture for deriving high-order MUXs from low-order MUX designs. Background Technology

[0004] This section aims to provide information relevant to understanding the various techniques described herein. As the section title suggests, this is a discussion of prior art and should in no way imply that it is prior art. Generally, the relevant techniques may or may not be considered prior art. Therefore, it should be understood that any statements in this section should be taken as such and not as an endorsement of prior art.

[0005] In memory circuit design, multiplexers are typically used to select a specific address within a memory cell array. Based on the values ​​of one or more input selector signals, a multiplexer facilitates the transfer of content from one of multiple input data lines to an output line. The size of a multiplexer is determined by the number of input data lines. For example, a multiplexer capable of selecting one output from 32 input data lines is called a 32:1 multiplexer. A higher-order multiplexer (also called a higher-order mux) is simply a multiplexer that receives a large number of input data lines compared to another multiplexer. For example, a 64:1 multiplexer is a higher-order multiplexer than a 32:1 multiplexer. The size of a multiplexer can also indicate the required number of input selector lines: Number of input data lines = 2 输入选择器线 Therefore, a 32:1 multiplexer requires 5 input selector lines.

[0006] Larger-sized multiplexers are often desired in circuit designs. Conventionally, low-order multiplexers are combined to derive higher-order multiplexers. However, this traditional approach requires redesigning the circuit, necessitating new manufacturing, verification, and packaging processes. This leads to inefficient development and expensive products. Therefore, an improved circuit design is needed that allows for the derivation of higher-order multiplexers from low-order multiplexers without substantially altering the baseline circuit design of the low-order multiplexers. Summary of the Invention

[0007] According to a first aspect of the present invention, a memory circuit includes: an array of memory cells arranged in a plurality of columns and a plurality of rows. A first cell has a first pair of multiplexers, a first sense amplifier, and a first write driver corresponding to a first set of columns. A second cell has a second pair of multiplexers, a second sense amplifier, and a second write driver corresponding to a second set of columns. A write enable signal is configured to enable one of the first and second write drivers. A read enable signal is configured to enable one of the first and second sense amplifiers.

[0008] According to a second aspect of the invention, a memory circuit includes: a memory array having a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a row selector configured to identify a selected row associated with a particular memory cell; and a column selector configured to identify a selected column associated with the particular memory cell, wherein the column selector includes: a plurality of multiplexers, each multiplexer corresponding to a subset of the plurality of columns; an enable signal for switching one of the plurality of multiplexers at a time; and a selection signal for selecting a column from the subset of the plurality of columns corresponding to the one of the plurality of multiplexers enabled by the enable signal.

[0009] A method for implementing a multiplexer according to a third aspect of the present invention includes: providing an array of memory cells arranged in a plurality of columns and a plurality of rows; coupling a pair of multiplexers to the plurality of columns, wherein each of the multiplexers in the pair corresponds to a subset of the plurality of columns; forming a common output port by coupling the output ports of the pair of multiplexers together; receiving a selection signal by the pair of multiplexers, wherein each of the multiplexers in the pair translates the selection signal into an address of a specific column; and generating an output on the common output port in response to a read enable signal. Attached Figure Description

[0010] This document describes various implementations of the techniques with reference to the accompanying drawings. However, it should be understood that the drawings are for illustrative purposes only, and that the various implementations described herein are not intended to limit the embodiments of the techniques described herein.

[0011] Figures 1A and 1B show prior art circuits that use low-order multiplexers to implement high-order multiplexers.

[0012] Figure 2 shows a diagram of a memory circuit using a low-order multiplexer according to various implementations described herein.

[0013] Figure 3 shows a memory circuit that uses a low-order multiplexer to implement a high-order multiplexer according to an embodiment of the invention described herein.

[0014] Figure 4 shows a memory circuit diagram of a high-order multiplexer implemented using a low-order multiplexer according to another embodiment of the invention described herein.

[0015] Figure 5 shows a memory circuit diagram of a high-order multiplexer implemented using more than two low-order multiplexers according to another embodiment of the invention described herein.

[0016] Figure 6 shows a memory circuit diagram of a high-order multiplexer implemented using a low-order multiplexer with a specified selection signal, according to yet another embodiment of the invention described herein.

[0017] Figure 7 shows a flowchart of a method for deriving a high-order multiplexer from a low-order multiplexer according to an embodiment of the invention described herein. Detailed Implementation

[0018] The various implementations described in this paper target integrated circuit (IC) architectures that enable the implementation of high-order multiplexers using low-order multiplexers. The various schemes and techniques described in this paper can provide optimized circuit designs to achieve high-order multiplexers with limited modifications to the low-order multiplexer circuitry.

[0019] Figures 1A and 1B illustrate prior art circuits that implement high-order multiplexers using low-order multiplexers. More specifically, Figure 1A shows a circuit 1000 including a pair of multiplexers 1010 and 1020. Multiplexers 1010 and 1020 receive input data 1011 and 1021 to generate outputs 1013 and 1023 based on selection signals 1012 and 1022, respectively. The number of input data lines depends on the size of the multiplexer. Each of the input data 1011, 1021 may include multiple input data lines. For example, multiplexers 1010 and 1020 may be 32:1 multiplexers. In such an embodiment, input data 1011 and 1021 include 32 input data lines. Furthermore, each of multiplexers 1010 and 1020 requires a 5-bit address to be passed by each of selection signals 1012 and 1022 to generate outputs 1013 and 1023. For example, when selection signal 1012 receives the address

[00000] , the first input data line of the 32 input lines from input data 1011 is connected to output line 1013. Multiplexer 1020 has a similar function.

[0020] Referring to Figure 1B, a conventional method for implementing a high-order multiplexer from multiple low-order multiplexers is shown. More specifically, circuit 1100 includes a first-stage and a second-stage multiplexer. Compared to circuit 1000 of Figure 1A, an additional layer of multiplexer 1130 is added to multiplexers 1110 and 1120. Thus, each of the first-stage multiplexers 1110 and 1120 selects one output from data inputs 1111 and 1121. Then, one of the two outputs 1113 and 1123 generated by multiplexers 1110 and 1120 is selected as the final output 1133 of circuit 1100. Therefore, in addition to the first selection signal 1112, a second selection signal 1122 is also needed to determine the output of the third multiplexer 1130.

[0021] In the conventional design of circuit 1100, two low-order multiplexers are used to implement a high-order multiplexer. For example, multiplexers 1110 and 1120 could be 32:1 multiplexers implementing a 64:1 multiplexer in circuit 1100. More specifically, each of the two multiplexers 1110 and 1120 receives 32 input data lines, resulting in 64 input data lines together. In the first stage of circuit 1100, two outputs 1113 and 1123 are selected based on selection signal 1112. Then, in the second stage of circuit 1100, the final output 1133 is selected based on selection signal 1122. Thus, one output is generated from 64 data input lines.

[0022] However, the conventional approach to deriving high-order multiplexers from the aforementioned low-order multiplexers faces the challenge of requiring substantial changes to the existing circuit design of the low-order multiplexers. Such modifications incur significant costs due to the design, fabrication, and verification of the high-order multiplexer circuitry. Furthermore, the circuitry necessitates additional levels of multiplexing, which consumes more power and slows down operation. The subject matter described in this invention aims to address these drawbacks.

[0023] Figure 2 illustrates a memory circuit 200 with multiple multiplexers according to various implementations described herein. The memory circuit 200 can be implemented as a system or device having various circuit components arranged and coupled together to provide a combination or assembly of components for physical circuit design and related structures. Furthermore, methods for designing, providing, and constructing the memory circuit 200 can involve using the various circuit components described herein, thereby enabling various multiplexer designs and associated techniques.

[0024] As shown in Figure 2, the memory circuit 200 may include various components, including a column address decoder 201, a row address decoder 202, a clock generator 203, a memory array 204, and a dummy word line (DWL) 205. The memory circuit 200 also includes multiple column selector cells 210A to 210Z (here, 210 represents multiple column selector cells). The memory array 204 includes multiple row word lines (i.e., row 0, row 1, row 2, ..., row n) and multiple columns (i.e., CL 1, CL 2, ..., CL n). The memory array 204 may be formed by multiple memory cells at the intersections of memory columns and rows. In one embodiment, the columns correspond to the bit lines of the memory array. In another embodiment, half of the column is a source line and the other half is a bit line, wherein each memory cell is connected to both the bit line and the source line at the intersection with the word line. In yet another embodiment, the memory cells are connected to complementary bit lines (BL and NBL).

[0025] Column selector unit 210 can be coupled via columns (CL1, CL2, ..., CLn) to each memory cell in each of the rows (i.e., row 1, row 2, row 3, ..., row n). Memory circuitry 200 may also include a plurality of inverted word lines (e.g., nwl1, nwl2, nwl3, ..., nwln) coupled between row address decoder 202 and the corresponding row of the memory cell (i.e., row 1, row 2, row 3, ..., row n) for accessing each of the memory cells based on a selected word line (e.g., wl1, wl2, wl3, ..., wl_n). Each of the inverted word lines (nwl_0, nwl_1, nwl_2, ..., nwl_n) has a corresponding word line driver (e.g., inverters i1, i2, ..., in) coupled thereto to provide a word line signal to the memory cell of the corresponding row.

[0026] Memory circuit 200 can receive a clock signal CLK and an address signal Addr. Clock signal generator 203 can receive the clock signal CLK and thus generate one or more internal clock signals. For example, a first internal clock signal i_clk1 is provided by clock signal generator 203 to row address decoder 102. Therefore, row address decoder 202 can also receive address signal Addr to access at least one word line (e.g., wl1, wl2, wl3, ..., wln). A second internal clock signal i_clk2 generated by clock signal generator 203 can be provided to a pseudo-word line driver (e.g., inverter id) via pseudo-word line 205 (DWL). After passing through multiple delay circuits 207, the signal is then returned to clock signal generator 203.

[0027] Finally, the clock signal generator 203 provides a third internal clock signal i_clk3 to the plurality of column selector units 210. In an embodiment, the NOR gate 206 receives the address signal Addr decoded by the column address decoder 201 and the clock signal i_clk3 generated by the clock signal generator 203 to generate a selection signal SLCT. The selection signal SLCT is passed to each of the column selector units 210. The column selector unit 210 includes a pair of multiplexers, which includes first multiplexers 211A, 211B, ..., 211Z (211 herein represents a plurality of first multiplexers) and second multiplexers 212A, 212B, ..., 212Z (212 herein represents a plurality of second multiplexers). The column selector unit 210 also includes sense amplifiers 213A, 213B, ..., 213Z (213 herein represents multiple sense amplifiers) that generate read output signals RD / OUT A, RD / OUT B, ..., and RD / OUT Z (RD / OUT herein represents multiple read output signals). The column selector unit 210 also includes write drivers 214A, 214B, ..., 214Z (214 herein represents multiple write drivers) that receive write input signals WR / IN A, WR / IN B, ..., and WR / IN Z (WR / IN herein represents multiple write input signals).

[0028] In this embodiment, each pair of multiplexers 211 and 212 within column selector unit 210 corresponds to a subset of columns in memory array 204. The selection signal SLCT received by multiplexers 211 and 212 can provide the address of one column from the subset of columns for each of multiplexers 211 and 212. For example, CL1 indicates the subset of columns received by multiplexer 211A, while (0:N) indicates the number of data input lines (i.e., N is a number such as 4, 8, 16, 32, etc.). Column CL1A is the selection of multiplexer 211A from subset CL1 (0:N) based on the selection signal SLCT. Column CL2A is the selection of multiplexer 212A from subset CL2 (0:N) based on the selection signal SLCT. Similarly, the remaining multiplexers 211B, 212B, ..., 211Z and 212Z generate columns CL3B, CL4B, ..., CLmz and CLnz as outputs based on the selection signal SLCT.

[0029] During a read operation, the read enable signal RD / ENB controls the read operation by passing an enable signal to the sense amplifier 213. The enabled sense amplifier receives selection from the corresponding multiplexer and thus generates an output on the read output signal RD / OUT. Similarly, during a write operation, the write enable signal WR / ENB controls the write operation by passing an enable signal to the write driver 214. The enabled write driver receives input from the write input signal WR / IN and is stored by the multiplexer in the memory cell corresponding to the selected column.

[0030] For example, multiplexers 211 and 212 of column selector unit 210 can be 32:1 multiplexers. Thus, in this embodiment, each of the multiplexers is connected to 32 columns (i.e., CL 1(0:31)) of memory array 204. The select signal SLCT can transmit a 5-bit address such that the first column is selected by address

[00000] and the last column is selected by address

[11111] . Therefore, during a read operation enabled by the read enable signal RD / ENB, the read output signal RD / OUT can generate data stored in the memory cell corresponding to the column selected by the select signal SLCT. Similarly, during a write operation enabled by the write enable signal WR / ENB, the write input signal WR / IN can receive data to be stored in the memory cell corresponding to the column selected by the select signal SLCT.

[0031] In various implementations, each memory cell in memory array 204 may be referred to as a bit cell, and each bit cell may be configured to store at least one data bit value (e.g., a data value associated with logic '0' or '1'). Each row of bit cells row_1, row_2, ..., row_n in memory array 204 may include any number of bit cells (or memory cells) arranged in various configurations, such as, for example, a two-dimensional (2D) memory array having multiple bit cells arranged in an indexed 2D grid pattern with any number of columns (N columns) and rows (N rows). Each bit cell may be implemented using any type of memory, including, for example, dual-port memory, single-port memory, static random access memory (SRAM), magnetoresistive RAM (MRAM), and / or any other type of memory. For example, each bit cell may include a multi-transistor static RAM (SRAM) cell, including various types of SRAM cells, such as, for example, 6T CMOS SRAM and / or any other type of complementary MOS (CMOS) SRAM cell, such as, for example, 4T, 8T, 10T, or more transistors per bit. In other cases, such as when tracing is required on the relevant CLK2Q path, each bit cell may include a multi-layer MRAM bit cell with a free layer and a fixed layer.

[0032] The memory circuitry 200, including each bit cell in the memory array 204, can be implemented as an integrated circuit (IC) with various types of memory circuitry, such as, for example, dual-port, single-port, SRAM, MRAM, and / or any other type of memory, including any type of volatile and non-volatile memory. The memory circuitry 200 can be implemented as an IC with a single-track and / or dual-track memory architecture, and the memory circuitry 200 can be integrated with computing circuitry and various related components on a single chip. Furthermore, the memory circuitry 200 can be implemented in embedded systems for electronic applications, mobile applications, biometric applications, and / or IoT (Internet of Things) applications.

[0033] The memory circuit system 200 comprises multiple leaf cells (unit cells), the basic structure of an integrated circuit, repeated and interconnected in a manner that forms the desired circuit. Such a design requires extensive verification processes for performance testing. Furthermore, the development of a manufacturing process for this specific design is quite time-consuming and expensive. To obtain a higher-order multiplexer from the lower-order multiplexer present in the memory circuit 200 based on the conventional methods described with respect to Figures 1A and 1B, the entire design and manufacturing process must be altered. Thus, it is desirable to obtain a higher-order multiplexer with minimal modifications to the basic design presented in Figure 2.

[0034] This article will describe in detail, with reference to Figures 3 to 6, the various implementation methods of the derived high-order multiplexer design.

[0035] Figure 3 illustrates a memory circuit that uses a low-order multiplexer to implement a high-order multiplexer according to an embodiment of the invention described herein. As shown in Figure 3, the basic design of memory circuit 300 is very similar to that of memory circuit 200 in Figure 2. In fact, for simplicity, many redundant elements, such as the clock signal generator, row address decoder, memory array, and pseudo-word lines, have been omitted from Figure 3. Otherwise, these omitted elements are present in the design of memory circuit 300 and function essentially in the same manner as in memory circuit 200.

[0036] Furthermore, like the memory circuit 200 of Figure 2, the memory circuit 300 includes a plurality of column selector units 310. Column selector units 310 may include two multiplexers 311 and 312 (one for bit lines and the other for source lines), a sense amplifier 313, and a write driver 314. In other embodiments, only a single multiplexer is required in each column selector unit. A subset of columns may be assigned to each of the multiplexers 311 and 312. In embodiments, the multiplexers are coupled together to implement a higher-order multiplexer. For example, multiplexers 311A ​​and 312A in column selector unit 310A may be paired with multiplexers 311C and 312C in column selector unit 310C. Similarly, multiplexers 311B and 312B in column selector unit 310B may be paired with multiplexers 311D and 312D in column selector unit 310D. In other cases, two or more column selector units can be coupled together to form a higher-order multiplexer.

[0037] In an embodiment, coupled column selector units 310A and 310C, and 310B and 310D, are connected to enable signals such that only one of the coupled column selector units, such as 310A or 310C, is enabled at a time. In the case of a coupled pair of multiplexers, the enable signals are required to carry a single bit size. For example, one of the column selector units 310A may be connected to enable signals RD / ENB and WR / ENB, while the other 310C may be connected to an inverted enable signal N_WR / ENB or N_RD / ENB. In an embodiment, the enable signals include a write enable signal WR / ENB and a read enable signal RD / ENB. For example, the sense amplifier 313A of column selector unit 310A is connected to the read enable signal RD / ENB, while the sense amplifier 313C of column selector unit 310C is connected to the inverted read enable signal N_RD / ENB. Thus, during a read operation, only one of the column selector units 310A and 310C in the pair can be enabled at a time. Similarly, in other embodiments, the write driver 314A of column selector unit 310A is connected to the write enable signal WR / ENB, while the write driver 314C of column selector unit 310C is connected to the inverted write enable signal N_WR / ENB. Thus, during a write operation, only one of the column selector units in the pair is enabled. Column selector units 310B and 310D are paired in the same manner as described above with respect to column selector units 310A and 310C to form a high-order multiplexer.

[0038] In this embodiment, the input and output ports of the column selector units are coupled together. For example, the read output signal RD / OUT AC is coupled to the output ports RD / OUT A and RD / OUT C of the two sense amplifiers 313A and 313C of column selector units 310A and 310C. Similarly, the write input signal WR / IN AC is coupled to the input ports RD / OUT A and RD / OUT C of the write drivers 314A and 314C of column selector units 310A and 310C. In this embodiment, in the same manner as described above with respect to column selector units 310A and 310C, the read output signal RD / OUT BD can be connected to the output ports RD / OUT B and RD / OUT D of the other column selector units 310B and 310D, while the write input signal WR / IN BD can be connected to the input ports WR / OUT B and WR / OUT D.

[0039] In this example, multiplexers 311 and 312 can be 32:1 multiplexers. Thus, each of the multiplexers can select one column from a subset of 32 columns, and therefore, as previously mentioned, they may require a 5-bit address passed by the select signal SLCT. In an embodiment of the invention, two 32:1 multiplexers are combined together without substantially modifying the memory circuitry to implement a 64:1 multiplexer using a single-bit state passed by the enable signals RD / ENB and WR / ENB.

[0040] For example, during a write operation, the write input signal WR / IN can receive a value to be stored in a memory cell corresponding to one of the 64 columns of the memory array. The write input signal WR / IN AC is connected to write drivers 314A and 314C. However, since one of the write drivers 314A and 314C is coupled to the write enable signal WR / ENB, and the other is connected to the inverted write enable signal N_WR / ENB, only one driver will be enabled at a time. For example, if write driver 314C is enabled, the input value received by the write input signal WR / IN AC is stored in the memory cell associated with columns CL5C and CL6C, selected by multiplexers 311C and 312C, respectively. The column address is passed to multiplexers 311C and 312C via the select signal SLCT to select the bit line from CL5 (0:N) and the source line from CL6 (0:N).

[0041] In another example, during a read operation, the read output signal RD / OUT can generate a value stored in the memory corresponding to one of the 64 columns of the memory array. The read output signal RD / OUT is connected to two sense amplifiers 313A and 313C. However, since one of the sense amplifiers 313A and 313C is coupled to the read enable signal RD / ENB, and the other is connected to the inverting read enable signal N_RD / ENB, only one sense amplifier is enabled at a time. For example, if sense amplifier 313A is enabled, the output value generated by the read output signal RD / OUT AC is based on the value stored in the memory cell associated with the columns CL1A and CL2A selected by multiplexers 311A ​​and 312A. The column address is passed to multiplexers 311A ​​and 312A via the selection signal SLCT to select the bit line from CL1 (0:N) and the source line from CL2 (0:N).

[0042] Figure 4 illustrates a memory circuit using a low-order multiplexer to implement a high-order multiplexer according to another embodiment of the invention described herein. Memory circuit system 400 is an alternative implementation of memory circuit system 300. In this embodiment, instead of every other column selector cell, adjacent cells are formed into a pair to implement the high-order multiplexer. For example, column selector cells 410A and 410B can form a first pair, while column selector cells 410C and 410D can form a second pair of multiplexers. In this embodiment, although the write driver of the first column selector cell (i.e., 414A and 414C) of the pair is connected to the write enable signal WR / ENB, the write driver of the second column selector cell (i.e., 414B and 414D) of the pair is connected to the inverted write enable signal N_WR / ENB. Similarly, in other embodiments, while the sense amplifiers of the first column selector units (i.e., 413A and 413C) of the pair are connected to the read enable signal RD / ENB, the sense amplifiers of the second column selector units (i.e., 413B and 413D) of the pair are connected to the inverting read enable signal N_RD / ENB.

[0043] In this embodiment, each pair of column selector units generates one output and receives one input. For example, the output ports RD / OUT A and RD / OUT B of the first pair of column selector units 410A and 410B are coupled to the read output signal RD / OUT AB. Alternatively, in another embodiment, the input ports WR / IN A and WR / IN B of the first pair of column selector units 410A and 410B are coupled to the write input signal WR / IN AB. In this embodiment, in the same manner as described above with respect to column selector units 310A and 310B, the read output signal RD / OUT CD can be connected to the output ports RD / OUT C and RD / OUT D of the other column selector units 310C and 310D, while the write input signal WR / IN CD can be connected to the input ports WR / IN C and WR / IN D.

[0044] In one embodiment, depending on the select signal and the enable signal, each of the first pair of column selector units 410A and 410B selects memory cells corresponding to columns (e.g., bit lines) CL1A and CL3B selected from subsets of columns CL1 and CL3, and columns (e.g., source lines) CL2A and CL4B selected from columns CL2 and CL4. Similarly, in another embodiment, depending on the select signal and the enable signal, the second pair of column selector units 410C and 410D selects memory cells corresponding to columns (e.g., bit lines) CL5C and CL7D selected from columns CL5 and CL7, and columns (e.g., source lines) CL6C and CL8D selected from columns CL6 and CL8.

[0045] Figure 5 illustrates a memory circuit diagram of implementing a high-order multiplexer using more than two low-order multiplexers according to another embodiment of the invention described herein. While the earlier embodiments described with reference to Figures 3 and 4 show the use of a pair of low-order multiplexers to form a high-order multiplexer, the memory circuit 500 of Figure 5 depicts an embodiment in which multiple multiplexers (two or more) are used to form a high-order multiplexer. For example, four multiplexers in a 4:1 sequence can be combined according to the disclosed method to implement a 16:1 multiplexer.

[0046] In this embodiment, the circuit design for memory circuit 500 is based on the same memory circuit described previously with reference to Figures 2 through 4. Memory circuit 500 includes multiple column selector units 510. Each column selector unit 510 includes multiple pairs of multiplexers 511 and 512, a sense amplifier 513, and a write driver 514. In this embodiment, memory circuit 500 includes only one read output signal RD / OUT and only one write input signal WR / IN. In this embodiment, the read output signal RD / OUT is coupled to output ports RD / OUT A, RD / OUT B, RD / OUT C, and RD / OUT D corresponding to all sense amplifiers 513, while the write input signal WR / IN is connected to input ports WR / IN A, WR / IN B, WR / IN C, and WR / IN D corresponding to all write drivers 514.

[0047] In this embodiment, the size of the selection signal SLCT depends on the order of multiplexers 511 and 512. The invention is not limited to a specific size of multiplexer, thus the size of the selection signal can be as large as required by the design. For example, if the size of the subset of columns allocated to each multiplexer is 4, the size of the selection signal SLCT can be at least 2 bits. On the other hand, the size of the enable signals (write enable signal and read enable signal) depends on the number of column selector units or the number of multiplexers. The invention is also not limited to a specific number of column selector units, thus the size of the enable signals can be as large as required by the design. For example, in the case of 4 column selector units, the enable signals can be at least two bits.

[0048] In this embodiment, the read enable signal RD / ENB is connected to each of the sense amplifiers 513 in the column selector unit 510 to control the read operation. In this embodiment, only one of the column selector units 510 can be activated for a read operation at a time. In this embodiment, when one of the column selector units 510 is enabled for a read operation, the remaining column selector units 510 are disabled. Similarly, the write enable signal is connected to each of the write drivers 514 in the column selector unit 510 to control the write operation. In this embodiment, only one of the column selector units 510 is activated for a write operation at a time. In this embodiment, when one of the column selector units 510 is enabled for a write operation, the remaining column selector units 510 are disabled.

[0049] In an embodiment, the pair of multiplexers 511 and 512 within column selector unit 510 receive selection of a specific column. For example, the select signal SCLT can pass a two-bit address, such as address

[00] , to multiplexers 511 and 512, which have four input data lines (i.e., columns). This address indicates that the first column CL(0) of the four columns CL(0:3) is selected by each of multiplexers 511 and 512. However, during a read operation, only one of the sense amplifiers 513 can be turned on by the read enable signal RD / ENB. For example, sense amplifier 513B of column selector unit 510B can be turned on by the read enable signal RD / ENB B. In this case, all the remaining read enable signals RD / ENB A, RD / ENB C, and RD / ENB D turn off their corresponding sense amplifiers 513A, 513C, and 513D, respectively. Therefore, the values ​​of the memory cells corresponding to the selected columns CL3B and CL4B are transmitted to the read output signal (RD / OUT) via the output port RD / OUT B through multiplexers 511B and 512B.

[0050] Similarly, in another embodiment, during a write operation, the select signal SCLT can pass a two-bit address, such as address

[10] , to multiplexers 511 and 512, which have four input data lines (i.e., columns). This address indicates that the third column CL(2) of the four columns CL(0:3) is selected by each of multiplexers 511 and 512. However, during a write operation, only one of the write drivers 514 is turned on by the write enable signal WR / ENB. For example, the write driver 514C of the column selector unit 510C can be turned on by the write enable signal WR / ENB C. In this case, all the remaining write enable signals WD / ENB A, WD / ENB B, and WR / ENB D turn off their corresponding write drivers 514A, 514B, and 514D, respectively. Therefore, the value received by the write input signal WR / IN is passed through multiplexers 511C and 512C via the input port WR / IN C to the memory cell corresponding to the selected columns CL5C and CL6C.

[0051] Figure 6 illustrates a memory circuit that implements a high-order multiplexer using a low-order multiplexer with a specified select signal, according to yet another embodiment of the invention described herein. Memory circuit 600 is another implementation of memory circuit 300. Referring back to Figure 3, the select signal SLCT is passed to all multiplexers 311 and 312 within column selector unit 310, regardless of whether they are enabled. For example, although the write enable signal WR / ENB may only have column selector units 310A and 310B enabled, the select signal SLCT is still passed to all four column selector units, even those that are disabled, such as 310C and 310D. Such a design can place a large load on the select signal SLCT, thus causing slow communication.

[0052] Referring back to Figure 6, in this embodiment, a designated selection signal is defined based on the currently enabled multiplexer. In this embodiment, the designated selection signal includes selection signals for read and write operations. For example, when enabled by the read enable signal RD / ENB, the selection signal SLCT RD AB passes the column address to each of the multiplexers in column selector units 610A and 610B. Similarly, when enabled by the write enable signal WR / ENB, the selection signal SLCT WR AB passes the column address to each of the multiplexers in column selector units 610A and 610B. For column selector units 610C and 610D, the selection signals SLCT RD CD and SLCT WR CD function in the same manner.

[0053] For example, when implementing a 64:1 multiplexer using a pair of 32:1 multiplexers, there may be four selection signals. In Figure 6, considering only column selector units 610A and 610C, a first selection signal SLCT RD AB is specified to provide a column address during a read operation on a memory cell selected by the pair of multiplexers 611A and 612A. A second selection signal SLCT WR AB is specified to provide a column address during a write operation on a memory cell selected by the pair of multiplexers 611A and 612A. A third selection signal SLCT RD CD is specified to provide a column address during a read operation on a memory cell selected by the pair of multiplexers 611C and 612C. A fourth selection signal SLCT WR CD is specified to provide a column address during a write operation on a memory cell selected by the pair of multiplexers 611C and 612D.

[0054] In this embodiment, the select signal provides the column's 5-bit address to the multiplexer. However, the select signal is strobed by an enable signal, such that the select signal is only transmitted if the corresponding multiplexer is enabled by the enable signal.

[0055] Figure 7 shows a flowchart of a method 700 for providing memory circuitry according to various implementations described herein.

[0056] It should be understood that even though method 700 can indicate a specific order of operation execution, in some cases, specific parts of the operation may be executed in different orders on different systems. In other cases, additional operations and / or steps may be added to method 700 and / or omitted from method 700. Furthermore, method 700 can be implemented in hardware and / or software. If implemented in hardware, method 700 can be implemented using various circuit elements, such as those described herein with reference to Figures 3 to 6. If implemented in software, method 700 can be implemented as a program and / or software instruction process that can be configured to provide high-order multiplexer design techniques as described herein. Additionally, if implemented in software, instructions related to implementing method 700 can be stored in memory and / or a database. For example, a computer or various other types of computing devices having a processor and memory can be configured to execute method 700.

[0057] As described and illustrated with reference to Figure 7, method 700 can be used to fabricate and / or manufacture or enable the fabrication and / or manufacture of an integrated circuit (IC) that implements the high-order multiplexer design schemes and techniques described herein, which relate to providing high-order multiplexer architectures and / or various related systems, devices, components, circuits and related architectures.

[0058] At block 701, method 700 may provide a memory circuit with an array of bit cells arranged in columns and rows. Each bit cell may be connected to one row of word lines and two columns of bit lines and source lines. A series of multiplexers may be used to select the column associated with the desired bit cell. In an embodiment, a subset of multiple columns is assigned to each multiplexer. The number of columns assigned to each multiplexer depends on the size of the multiplexer.

[0059] At block 702, multiple multiplexers are specified to form a higher-order multiplexer. For example, two 32:1 multiplexers can be selected to form a 64:1 multiplexer. In other cases, four 4:1 multiplexers can be selected to form a 16:1 multiplexer. In embodiments of the invention, a higher-order multiplexer can be implemented using a basic circuit design with multiple lower-order multiplexers with minimal modifications.

[0060] At block 703, input and output ports corresponding to multiple low-order multiplexers used to implement the high-order multiplexer are coupled together. A common input port can be used to write data into the bit cells selected by the high-order multiplexer, while a common output port can be used to generate data stored in the bit cells selected by the high-order multiplexer.

[0061] At block 704, a selection signal indicating the address of a specific column is received from a subset of the columns of the allocated multiplexer. In one embodiment, all multiplexers forming a higher-order multiplexer receive the selection signal and select a column. In the case where the memory circuitry includes bit lines and source lines, this selection of the pair of multiplexers corresponds to the same memory cell. In another embodiment, the selection signal is specified such that those multiplexers that are not enabled do not receive the signal. The magnitude of the selection signal depends on the size of the multiplexers combined to form the higher-order multiplexer.

[0062] At block 705, the multiplexer receives an enable signal to turn on a specific multiplexer among a plurality of multiplexers while turning off the others. In an embodiment, the enable signal includes a write enable signal and a write enable signal. The number of bits transmitted through the enable signal depends on the number of multiplexers coupled together to form a higher-order multiplexer. The read enable signal can be transmitted to the sensor amplifier, while the write enable signal can be transmitted to the write driver corresponding to the multiplexer.

[0063] At block 706, data is received at a common input port to store it in selected memory cells. A selection signal selects a column at each of the multiplexers. A write enable signal activates one of the multiplexers. Thus, data is stored in the memory cell corresponding to the column selected based on the selection signal by the multiplexer enabled based on the write enable signal.

[0064] At box 707, data stored in a specific memory cell is generated at a common output port. A selection signal selects a column at each of the multiplexers. A read enable signal activates one of the multiplexers. Therefore, data is generated at the output port in the memory cell corresponding to the column selected by the selection signal by the multiplexer enabled by the read enable signal.

[0065] This document describes various implementations of a memory circuit. The memory circuit can be an array of memory cells arranged in multiple columns and rows. The memory circuit may include a first cell, a first sense amplifier, and a first write driver, the first cell having a first pair of multiplexers corresponding to a first group of multiple columns. The memory circuit may also include a second cell, a second sense amplifier, and a second write driver, the second cell having a second pair of multiplexers corresponding to a second group of multiple columns. A write enable signal can be configured to enable either the first driver or the second write driver. A read enable signal can be configured to enable either the first sense amplifier or the second sense amplifier.

[0066] This document describes various implementations of a memory circuit. The memory circuit may include a memory array having multiple memory cells arranged in multiple rows and multiple columns. The memory circuit may further include: a row selector configured to identify a selected row associated with a particular memory cell; and a column selector configured to identify a selected column associated with a particular memory cell. The column selector may include multiple multiplexers, each multiplexer corresponding to a subset of multiple columns. The column selector may also include an enable signal to switch one of the multiple multiplexers at a time. Finally, the column selector may also include a selection signal to select one column from a subset of multiple columns corresponding to one of the multiple multiplexers enabled by the enable signal.

[0067] This document describes various methods for implementing multiplexers. The method may include providing an array of memory cells arranged in multiple columns and multiple rows, coupling a pair of multiplexers to the multiple columns, wherein each of the multiplexers in the pair corresponds to a subset of the multiple columns, forming an output port by coupling the output paths of the pair of multiplexers together, and forming an input port by coupling the input paths of the pair of multiplexers together. The method also includes receiving a selection signal through the pair of multiplexers, wherein the selection signal is converted to a specific column by each of the multiplexers in the pair, generating an output at the output port in response to a read enable signal, and receiving an input at the input port in response to a write enable signal.

[0068] The subject matter of the claims is intended to be limited to the implementations and descriptions provided herein, but includes modifications of those implementations, including portions of the implementations and combinations of elements of different implementations according to the claims. It should be understood that in the development of any such implementation, for example in any engineering or design project, many implementation-specific decisions will be made to achieve the developer's specific objectives, such as compliance with system-related constraints and business-related constraints, which may differ from one implementation to another. Furthermore, it should be understood that such development work may be complex and time-consuming, but will still be routine work of design, fabrication, and manufacturing for those skilled in the art who benefit from this invention.

[0069] Various implementations have been described in detail, with examples illustrated in the accompanying drawings and diagrams. Numerous specific details are set forth in the following detailed description to provide a thorough understanding of the inventive content provided herein. However, the inventive content provided herein can be practiced without these specific details. In some other instances, well-known methods, processes, components, circuits, and networks have not been described in detail to avoid unnecessarily obscuring the details of the embodiments.

[0070] It should also be understood that although the terms first, second, etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The first element and the second element are both elements, but they should not be considered the same element.

[0071] The terminology used in the description of the invention provided herein is for the purpose of describing particular implementations and is not intended to limit the scope of the invention. As used in the description of the invention and the appended claims, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. The term “and / or” as used herein refers to and covers any and all possible combinations of one or more of the associated listed items. When used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups.

[0072] As used herein, depending on the context, the term "if" can be interpreted as "when," "at," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if [statement condition or event] is detected" can be interpreted as "when determination" or "in response to determination," "when [statement condition or event] is detected," or "in response to detection of [statement condition or event]." The terms "above" and "below"; "upper" and "lower"; "upward" and "downward"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in conjunction with some implementations of the various techniques described herein.

[0073] While the foregoing describes various implementations of the techniques described herein, other and further implementations can be designed based on the inventive content herein, as determined by the appended claims.

[0074] Although the subject matter has been described using language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms for implementing the claims.

Claims

1. A memory circuit, comprising: An array of memory cells arranged in multiple columns and multiple rows; The first unit has a first pair of multiplexers, a first sense amplifier, and a first write driver corresponding to a first group of multiple columns; The second unit has a second pair of multiplexers, a second sense amplifier, and a second write driver corresponding to the second group of multiple columns; The write enable signal is configured to enable one of the first write driver and the second write driver; And a read enable signal, configured to enable one of the first and second read amplifiers.

2. The memory circuit according to claim 1, further comprising: An input signal is coupled to the first write driver and the second write driver, wherein during a write operation, the input signal is connected to one of the multiple columns from the first set of multiple columns and the second set of multiple columns.

3. The memory circuit according to claim 1 further includes: An output signal is coupled to the first and second sense amplifiers, wherein during a read operation, the output signal is connected to one of the plurality of columns from the first set of plurality of columns and the second set of plurality of columns.

4. The memory circuit according to claim 1, wherein each of the first pair of multiplexers and the second pair of multiplexers is a 32:1 multiplexer.

5. The memory circuit according to claim 4, wherein the first group of multiple columns and the second group of multiple columns correspond to 64 bit lines and 64 source lines.

6. The memory circuit according to claim 2, further comprising: The selection signal received by the first pair of multiplexers and the second pair of multiplexers, wherein the selection signal corresponds to a different column in each of the first pair of multiplexers and the second pair of multiplexers.

7. The memory circuit of claim 6, wherein the write enable signal enables the first write driver during the write operation and writes the value transmitted from the input signal to a specific memory cell, wherein the specific memory cell corresponds to the first group of multiple columns.

8. A memory circuit, comprising: A memory array having multiple memory cells arranged in multiple rows and multiple columns; A row selector is configured to identify a selected row associated with a specific memory cell; A column selector comprising multiple units is configured to identify a selected column associated with a particular memory unit, wherein the column selector comprises: a plurality of multiplexers, each multiplexer corresponding to a subset of the plurality of columns, wherein each of the plurality of units comprises a pair of multiplexers; an enable signal for switching one of the multiplexers at a time; and a selection signal for selecting a column from the subset of the plurality of columns corresponding to the one of the multiplexers enabled by the enable signal.

9. The memory circuit of claim 8, wherein the enable signal includes a write enable signal for a write operation and a read enable signal for a read operation.

10. The memory circuit of claim 9, wherein the input ports of the plurality of multiplexers are coupled together to receive input data during the write operation.

11. The memory circuit of claim 9, wherein the output ports of the plurality of multiplexers are coupled together to generate an output data during the read operation.

12. The memory circuit of claim 9, wherein the plurality of multiplexers comprises four 4:1 multiplexers, and wherein the plurality of columns is 16.

13. The memory circuit of claim 12, wherein the select signal comprises 2 bits and the enable signal comprises 4 bits.

14. The memory circuit of claim 12, wherein the enable signal enables one of the plurality of multiplexers and disables the remaining multiplexers.

15. A method for implementing a multiplexer, comprising: Provides an array of memory cells arranged in multiple columns and multiple rows; A pair of multiplexers is coupled to the plurality of columns, wherein each of the multiplexers in the pair of multiplexers corresponds to a different subset of the plurality of columns; and the output ports of the pair of multiplexers are coupled together to form a common output port; The selection signal is received by the pair of multiplexers, wherein each of the pair of multiplexers converts the selection signal into an address for a specific column; and an output is generated on the common output port in response to a read enable signal.

16. The method of claim 15, further comprising: By coupling the input ports of the pair of multiplexers together to form a common input port; And in response to a write enable signal, receive input on the common input port.

17. The method of claim 16, wherein the read enable signal enables one of the multiplexers in the pair of multiplexers; and the output is based on the specific column corresponding to the selection signal converted by the enabled multiplexer.

18. The method of claim 16, wherein the write enable signal enables one of the multiplexers in the pair of multiplexers; and the input is written to the specific column corresponding to the selection signal converted by the enabled multiplexer.

19. The method of claim 16, wherein the write enable signal and the read enable signal enable one of the multiplexers in the pair of multiplexers and disable the other multiplexer in the pair of multiplexers.

20. The method of claim 15, wherein each of the multiplexers in the pair of multiplexers is a 32:1 multiplexer, wherein the selection signal is a 1-bit signal, and the plurality of columns are 64 columns.

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