Semiconductor memory device

Abstract

A semiconductor memory device is provided, which may include: a bit line extending in a first direction; a first conductive pattern extending in a second direction intersecting the first direction; a semiconductor pattern connecting the bit line to the first conductive pattern; a second conductive pattern including an insertion portion located in the first conductive pattern; and a dielectric layer located between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width that increases as the distance from the semiconductor pattern increases.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0134616 filed on October 28, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the inventive concepts relate to a semiconductor memory device, and more particularly, to a three-dimensional (3D) semiconductor memory device having improved integration density. Background Art

[0003] Semiconductor devices have been highly integrated to provide improved performance and / or lower manufacturing costs. The integration density of semiconductor devices affects the cost of semiconductor devices, resulting in a demand for more highly integrated semiconductor devices. The integration density of a typical two-dimensional (2D) or planar semiconductor device can be determined primarily by the area occupied by a unit memory cell. Therefore, the integration density of a typical 2D semiconductor device is affected by the technology for forming fine patterns. However, because more expensive equipment is required to form finer patterns, although the integration density of 2D semiconductor devices continues to increase, it is still limited. Therefore, a three-dimensional (3D) semiconductor memory device has been developed. A 3D semiconductor memory device may include memory cells arranged three-dimensionally. Summary of the invention

[0004] Example embodiments of the inventive concepts may provide a semiconductor memory device capable of improving electrical characteristics and / or reliability.

[0005] In one aspect, a semiconductor memory device may include: a bit line extending in a first direction; a first conductive pattern extending in a second direction intersecting the first direction; a semiconductor pattern connecting the bit line to the first conductive pattern; a second conductive pattern including an insertion portion located in the first conductive pattern; and a dielectric layer located between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width that increases as the distance from the semiconductor pattern increases.

[0006] In one aspect, a semiconductor memory device may include: first insulating patterns vertically stacked on a substrate; semiconductor patterns located between the first insulating patterns and arranged along a first direction, the semiconductor patterns extending in a second direction intersecting the first direction; bit lines electrically connected to first ends of the semiconductor patterns; first conductive patterns respectively located on second ends of the semiconductor patterns; second conductive patterns including portions located in the first conductive patterns; and a dielectric layer located between the first conductive patterns and the second conductive patterns. Each first conductive pattern may have a width in the first direction that increases as the distance from the corresponding semiconductor pattern increases.

[0007] In one aspect, a semiconductor memory device may include: a stacked structure including a plurality of layers stacked vertically on a substrate, each layer including a bit line extending in a first direction, a semiconductor pattern extending from the bit line in a second direction intersecting the first direction, and a first insulating pattern located below the semiconductor pattern; a gate electrode extending in a third direction intersecting the first direction and the second direction and on both side surfaces of the semiconductor pattern; a second insulating pattern filling a space between the semiconductor patterns and covering the gate electrode; first conductive patterns electrically connected to the semiconductor patterns, respectively; and second conductive patterns spaced apart from the first conductive patterns and having a dielectric layer between the second conductive patterns and the first conductive patterns. Each first conductive pattern may have a width that increases as the distance from the corresponding semiconductor pattern increases.

[0008] In one aspect, a method for manufacturing a semiconductor memory device may include: forming a stacked structure on a substrate, the stacked structure including a semiconductor pattern extending in a first direction and an insulating pattern surrounding the semiconductor pattern, the stacked structure having a first surface including an end of the semiconductor pattern; reducing the length of the semiconductor pattern in the first direction to form a recessed region recessed from the first surface in the first direction; and forming a first conductive pattern, a second conductive pattern, and a dielectric layer located between the first conductive pattern and the second conductive pattern in each recessed region. The formation of the recessed region may include repeatedly performing a first etching process for etching the semiconductor pattern and a second etching process for etching the insulating pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The inventive concept will become more apparent in view of the accompanying drawings and accompanying detailed description.

[0010] Figure 1 is a schematic circuit diagram illustrating a cell array of a semiconductor memory device according to some example embodiments of the inventive concept.

[0011] Figure 2 is a plan view illustrating a semiconductor memory device according to some example embodiments of the inventive concept.

[0012] Figure 3 is with Figure 2 A portion 'A' of FIG. 1 corresponds to a perspective view illustrating a semiconductor memory device according to some example embodiments of the inventive concepts.

[0013] Figure 4A , Figure 4B , Figure 4C and Figure 4D are respectively along Figure 3 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0014] FIG. 5A to FIG. 5D is with Figure 4A A portion 'A' of FIG. 1 corresponds to an enlarged view showing a semiconductor memory device according to some example embodiments of the inventive concepts.

[0015] Figures 6 to 9 are respectively Figure 3 Line AA′, line BB′, line CC′, and line DD′ correspond to illustrate cross-sectional views of semiconductor memory devices according to some example embodiments of the inventive concepts.

[0016] Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig.21 are plan views illustrating a method for manufacturing a semiconductor memory device according to some example embodiments of the inventive concept.

[0017] Fig.11 , Fig.13A , Fig.15 , Fig.17 , Fig.19A and Fig.22A are respectively along Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig.21 A cross-sectional view taken along line AA'.

[0018] Fig. 13B , Fig.19B and Fig. 22B are respectively along Fig.12 , Fig.18 and Fig.21 A cross-sectional view taken along line BB'.

[0019] Fig. 13C It is along Fig.12 A cross-sectional view taken along line CC'.

[0020] FIG. 20A to FIG. 20D is with Fig.16 A portion 'B' of FIG. 1 corresponds to an enlarged view illustrating a method of forming a recess region according to some example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0021] Figure 1 is a schematic circuit diagram illustrating a cell array of a semiconductor memory device according to some example embodiments of the inventive concept.

[0022] Reference Figure 1, a memory cell array of a semiconductor memory device according to some example embodiments of the inventive concepts may include a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged along the second direction D2.

[0023] Each subcell array SCA may include a plurality of bit lines BL, a plurality of word lines WL, and / or a plurality of memory cell transistors MCT. Each memory cell transistor MCT may be connected between a corresponding one of the word lines WL and a corresponding one of the bit lines BL.

[0024] The bit lines BL may be conductive patterns (eg, metal lines) vertically spaced apart from the substrate. The bit lines BL may extend in the first direction D1. The bit lines BL in each subcell array SCA may be spaced apart from each other in the vertical direction (eg, third direction D3).

[0025] The word lines WL may be conductive patterns (eg, metal lines) extending from a substrate in a vertical direction (eg, a third direction D3 ). The word lines WL in each subcell array SCA may be spaced apart from each other in the first direction D1 .

[0026] The gate of the memory cell transistor MCT may be connected to the word line WL, and the source of the memory cell transistor MCT may be connected to the bit line BL. A data storage element DS may be connected to each memory cell transistor MCT. For example, the data storage element DS may be a capacitor, and the drain of the memory cell transistor MCT may be connected to the capacitor.

[0027] Figure 2 is a plan view illustrating a semiconductor memory device according to some example embodiments of the inventive concept.

[0028] Reference Figure 1 and Figure 2 , the semiconductor memory device may include a memory cell region CR and a peripheral circuit region PR. Figure 1 The described memory cell array may be disposed in the memory cell region CR. The peripheral transistor PTR may be disposed in the peripheral circuit region PR. The peripheral transistor PTR may be connected to the memory cell array through a bit line BL. The peripheral transistor PTR may include, for example, a sense amplifier.

[0029] The bit lines BL may extend from the memory cell region CR to the peripheral circuit region PR. The bit lines BL may extend in the first direction D1 and may have different lengths. For example, the bit lines BL may have a step structure in the peripheral circuit region PR. Each bit line BL may be disposed on an end portion of the semiconductor pattern SP disposed at the same level. The bit lines BL may be reference Figure 1 The bit line BL is described.

[0030] The semiconductor pattern SP may extend in the second direction D2. For example, the semiconductor pattern SP may include silicon, germanium, or silicon-germanium. Each semiconductor pattern SP may include a source region / drain region and a channel region between the source region / drain region. The gate electrode GE may be disposed on a side surface of the semiconductor pattern SP. The semiconductor pattern SP and the gate electrode GE may constitute a reference Figure 1 A memory cell transistor MCT is described.

[0031] The data storage element DS may be connected to the other end of the semiconductor pattern SP, respectively. The data storage element DS may include a first conductive pattern EL1 and a second conductive pattern EL2 located on the first conductive pattern EL1. The first conductive pattern may extend in the second direction and may be arranged in the first direction and the third direction. It will be understood that when an element or layer is referred to as being arranged / stacked in a certain direction or in multiple directions, the element or layer may be arranged in the certain direction or in the multiple directions. The second conductive pattern EL2 may be adjacent to the first conductive pattern EL1. A dielectric layer may be provided between the first conductive pattern EL1 and the second conductive pattern EL2. The data storage element DS may be a capacitor and may be used as a memory element capable of storing data.

[0032] Figure 3 is with Figure 2 A portion 'A' of FIG. 1 corresponds to a perspective view illustrating a semiconductor memory device according to some example embodiments of the inventive concepts. Figure 4A , Figure 4B , Figure 4C and Figure 4D are respectively along Figure 3 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′. FIG. 5A to FIG. 5D is with Figure 4A A portion 'A' of FIG. 1 corresponds to an enlarged view showing a semiconductor memory device according to some example embodiments of the inventive concepts.

[0033] Refer to the detailed Figure 3 as well as FIG. 4A to FIG. 4D , the stacked structure SS may be disposed on the substrate SUB. In some example embodiments, the stacked structure SS may include a plurality of layers L1, L2, L3, and L4 stacked on the substrate SUB. Hereinafter, a semiconductor memory device including four layers will be described as an example. However, in some example embodiments, the semiconductor memory device may include layers whose number is greater than or less than four. As an example, the third layer L3 and the fourth layer L4 among the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may be omitted. As another example, other layers may be stacked on the fourth layer L4.

[0034] The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 of the stacked structure SS may be stacked in a direction (e.g., a third direction D3) perpendicular to the substrate SUB. Each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include a bit line BL, a first insulating pattern IP1, a semiconductor pattern SP, and a data storage element DS.

[0035] The first insulating pattern IP1 may be stacked to be spaced apart from each other in the third direction. The semiconductor pattern SP and the bit line BL may be disposed on each first insulating pattern IP1. The semiconductor pattern SP and the bit line BL may be disposed side by side on the first insulating pattern IP1. The first insulating pattern IP1 may vertically separate the semiconductor pattern SP and the bit line BL disposed on the first insulating pattern IP1 from the semiconductor pattern SP and the bit line BL disposed under the first insulating pattern IP1. The first insulating pattern IP1 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon. For example, the first insulating pattern IP1 may include silicon nitride (SiN). The first insulating pattern IP1 may extend in the second direction D2.

[0036] The bit line BL of each of the first layer L1 to the fourth layer L4 may extend in the first direction D1. The bit line BL may be located at the same level as the semiconductor pattern SP. One side surface of the bit line BL may face one end of the semiconductor pattern SP. Each bit line BL may have a line shape or a bar shape extending in the first direction D1. The bit lines BL may be stacked along the third direction D3 and may be spaced apart from each other in the third direction D3. The bit line BL may include a conductive material. For example, the conductive material may include at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium or tantalum), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide or titanium silicide).

[0037] The semiconductor pattern SP may be provided in plurality in each of the first to fourth layers L1 to L4. The plurality of semiconductor patterns SP in each of the layers L1 to L4 may be arranged along the first direction D1. Each semiconductor pattern SP may have a line shape, a bar shape, or a column shape extending in the second direction D2. For example, the semiconductor pattern SP may include silicon, germanium, or silicon-germanium. Each semiconductor pattern SP may include a channel region CH, a first dopant region SD1, and a second dopant region SD2. The channel region CH may be provided between the first dopant region SD1 and the second dopant region SD2. The bit line BL may be electrically connected to the first dopant region SD1 of the semiconductor pattern SP.

[0038] The channel region CH may be disposed between the first dopant region SD1 and the second dopant region SD2. Figure 1 The first dopant region SD1 and the second dopant region SD2 may correspond to the channel of the memory cell transistor MCT described above. Figure 1 The source and drain of the memory cell transistor MCT are described to correspond.

[0039] The first dopant region SD1 and the second dopant region SD2 may be regions of the semiconductor pattern SP doped with dopants. Therefore, the first dopant region SD1 and the second dopant region SD2 may have an N-type conductivity type or a P-type conductivity type. The first dopant region SD1 may be one of a source region and a drain region, and the second dopant region SD2 may be the other of the source region and the drain region. In some example embodiments, the first dopant region SD1 may be formed in an upper portion of the semiconductor pattern SP.

[0040] A hole HO penetrating the stack structure SS may be defined. The hole HO may be located between the semiconductor patterns SP. A vertically extending gate electrode GE may be disposed in the hole HO penetrating the stack structure SS. In other words, the gate electrode GE may penetrate the stack structure SS. The gate electrode GE may be adjacent to the channel region CH of the semiconductor pattern SP. The gate electrode GE may be disposed on a side surface of the channel region CH and may extend in a third direction D3. The gate electrode GE may include a conductive material, and the conductive material may include at least one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound. The gate electrode GE may be a reference Figure 1 Described word line WL.

[0041] The gate insulating layer GI may be disposed between the gate electrode GE and the channel region CH. The gate insulating layer GI may include at least one of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. For example, the high-k dielectric layer may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0042] The gate electrode GE may include a first gate electrode GEa and a second gate electrode GEb respectively disposed at both sides of the channel region CH of the semiconductor pattern SP. In some example embodiments, the first gate electrode GEa and the second gate electrode GEb may constitute a single word line WL. In some example embodiments, the first gate electrode GEa may be the word line WL, and the second gate electrode GEb may be a back gate.

[0043] The gate insulating layer GI may be disposed between each gate electrode GE and a corresponding one of the semiconductor patterns SP. The gate insulating layer GI may include at least one of a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0044] The second insulating pattern IP2 may be provided to fill each hole HO. The second insulating pattern IP2 may cover the gate electrode GE. For example, the second insulating pattern IP2 may be provided between a pair of gate electrodes GE adjacent to each other in the hole HO. The second insulating pattern IP2 may be provided between a pair of semiconductor patterns SP adjacent to each other. The second insulating pattern IP2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the second insulating pattern IP2 may include silicon oxide having an etching selectivity relative to the first insulating pattern IP1.

[0045] The data storage elements DS may be connected to the other ends of the semiconductor pattern SP, respectively. In other words, the semiconductor pattern SP may connect the bit line BL to the data storage elements DS. The data storage elements DS may be connected to the second dopant regions SD2 of the semiconductor pattern SP, respectively.

[0046] In detail, the data storage element DS may include a first conductive pattern EL1 extending in the second direction D2, a second conductive pattern EL2 adjacent to the first conductive pattern EL1, and a dielectric layer DL. The dielectric layer DL may be disposed between the first conductive pattern EL1 and the second conductive pattern EL2. The first conductive pattern EL1 and the second conductive pattern EL2 may be spaced apart from each other using the dielectric layer DL disposed therebetween, and may constitute a capacitor. The data storage element DS in the stacked structure SS may share a single dielectric layer DL and a single second conductive pattern EL2. In other words, the first conductive pattern EL1 may be disposed in plurality in the stacked structure SS, and the single dielectric layer DL may cover the surface of the first conductive pattern EL1. The single second conductive pattern EL2 may be disposed on the single dielectric layer DL.

[0047] The first conductive pattern EL1 may have a width that increases as the distance from the semiconductor pattern SP increases in the first direction D1. Figure 5A , the first conductive pattern EL1 may include first to third portions EL1a, EL1b, and EL1c. The first portion EL1a of the first conductive pattern EL1 may be electrically connected to the other end of the semiconductor pattern SP. The semiconductor pattern SP may have a first width w1 in the first direction D1. The first portion EL1a of the first conductive pattern EL1 may have a second width w2 equal to the first width W1. For example, a side surface of the semiconductor pattern SP may be coplanar with a side surface of the first portion EL1a of the first conductive pattern EL1.

[0048] The second portion EL1b of the first conductive pattern EL1 may have a third width w3 greater than the second width w2, and the third portion EL1c of the first conductive pattern EL1 may have a fourth width w4 greater than the third width w3. Each of the first to third portions EL1a, EL1b, and EL1c of the first conductive pattern EL1 may extend in the second direction D2 and may have a substantially constant width in the first direction D1. The first to third portions EL1a, EL1b, and EL1c of the first conductive pattern EL1 may be parallel to each other. The first conductive pattern EL1 may include a step portion ST respectively disposed between the first portion EL1a and the second portion EL1b and between the second portion EL1b and the third portion EL1c. The width of the first conductive pattern EL1 in the first direction D1 may be nonlinearly changed at the step portion ST. Each first conductive pattern EL1 may have a barrel shape with one end thereof opened.

[0049] Each of the first to third portions EL1a, EL1b, and EL1c of the first conductive pattern EL1 may have two side walls facing each other in the first direction D1. Each of the two side walls may have a constant thickness in the first direction D1 and may extend in the second direction D2. The two side walls may be parallel to each other. The first portion EL1a of the first conductive pattern EL1 may include a connection portion connecting the two side walls. The connection portion may be adjacent to the semiconductor pattern SP.

[0050] The insertion portion EL2a of the second conductive pattern EL2 inserted into the first conductive pattern EL1 may have a width WD1 that increases with an increasing distance from the semiconductor pattern SP in the first direction D1. Figure 4D As shown in , the width WD3 of the insertion portion EL2a in the third direction D3 may be constant.

[0051] The second conductive pattern EL2 may be disposed adjacent to the first conductive pattern EL1. Each second conductive pattern may have a surface facing the surface of the first conductive pattern. The second conductive pattern EL2 may include insertion portions EL2a respectively inserted into the first conductive pattern EL1 and an outer portion EL2b surrounding at least a portion of the first conductive pattern EL1. The width WD1 of the insertion portion EL2a in the first direction D1 may increase as the distance from the semiconductor pattern SP increases. The outer portion EL2b may connect the insertion portion EL2a.

[0052] Each of the first conductive pattern EL1 and the second conductive pattern EL2 may include at least one of a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a doped semiconductor material (e.g., doped silicon or doped germanium). The dielectric layer DL may include a high-k dielectric material, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or any combination thereof.

[0053] In some example embodiments, Figure 5B As shown in , the width of the first conductive pattern EL1 in the first direction D1 may gradually increase as the distance from the semiconductor pattern SP increases.

[0054] In some example embodiments, Figure 5C and Figure 5D As shown in FIG. 1 , the minimum width of the first conductive pattern EL1 in the first direction D1 may be greater than the width of the semiconductor pattern SP in the first direction D1. Figure 5A and Figure 5B Unlike the illustration of FIG. 1 , the side surface of the semiconductor pattern SP may not be aligned with the side surface of the first conductive pattern EL1.

[0055] The first silicide pattern SC1 may be disposed between the bit line BL and the semiconductor pattern SP. The second silicide pattern SC2 may be disposed between the semiconductor pattern SP and the first conductive pattern EL1. The bit line BL may be electrically connected to the first dopant region SD1 through the first silicide pattern SC1. The first conductive pattern EL1 may be electrically connected to the second dopant region SD2 through the second silicide pattern SC2. The first silicide pattern SC1 and the second silicide pattern SC2 may include metal silicide (e.g., cobalt silicide).

[0056] Figures 6 to 9 are respectively Figure 3 The lines A-A', B-B', CC' and D-D' correspond to each other to show a cross-sectional view of a semiconductor memory device according to some example embodiments of the inventive concept. Hereinafter, for the purpose of ease and convenience of explanation, the reference to FIG. 4A to FIG. 4D A detailed description of components that are the same as those in the example embodiments.

[0057] Reference Figures 6 to 9, the insertion portion EL2a of the first conductive pattern EL1 and the second conductive pattern EL2 may have a constant width in the first direction D1. The width of the first conductive pattern EL1 in the first direction D1 may be substantially equal to the width of the semiconductor pattern SP in the first direction D1. The side surface of the first conductive pattern EL1 may be aligned with the side surface of the semiconductor pattern SP and the side surface of the first insulating pattern IP1. The width of the first conductive pattern EL1 in the third direction D3 may increase as the distance from the semiconductor pattern SP increases. In addition, the insertion portion EL2a of the second conductive pattern EL2 may have a width WD3 that increases as the distance from the semiconductor pattern SP increases in the third direction D3. The insertion portion EL2a of the second conductive pattern EL2 may have a constant width WD1 in the first direction D1. The width of the first insulating pattern IP1 in the third direction D3 may decrease as the distance from the semiconductor pattern SP increases.

[0058] Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig.21 are plan views illustrating a method for manufacturing a semiconductor memory device according to some example embodiments of the inventive concept. Fig.11 , Fig.13A , Fig.15 , Fig.17 , Fig.19A and Fig.22A are respectively along Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 and Fig.21 A cross-sectional view taken along line AA'. Fig. 13B , Fig.19B and Fig. 22B are respectively along Fig.12 , Fig.18 and Fig.21 A cross-sectional view taken along line BB'. Fig. 13C It is along Fig.12 A cross-sectional view taken along line CC'.

[0059] Reference Fig.10 and Fig.11 , a stack structure SS may be formed on the substrate SUB. The forming of the stack structure SS may include forming first to fourth layers L1, L2, L3, and L4 that are sequentially stacked.

[0060] Each of the first to fourth layers L1, L2, L3, and L4 may include a first insulating pattern IP1 and a semiconductor layer SL. In other words, the first insulating pattern IP1 and the semiconductor layer SL may be alternately formed. The semiconductor layer SL may include a semiconductor material such as silicon, germanium, or silicon-germanium. The first insulating pattern IP1 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon. For example, the first insulating pattern IP1 may be formed of silicon nitride (SiN).

[0061] The stacked structure SS may be patterned to form holes HO penetrating the stacked structure SS. Each hole HO may have a line shape or a strip shape extending in the second direction D2. The holes HO may be arranged along the first direction D1 and may be spaced apart from each other. A semiconductor pattern SP may be defined in each semiconductor layer SL by the holes HO. For example, the semiconductor pattern SP may be defined between a pair of holes HO adjacent to each other. The semiconductor pattern SP may have a strip shape extending in the second direction D2.

[0062] Reference Fig.12 as well as FIG. 13A to FIG. 13C , a gate insulating layer GI and a gate electrode GE may be formed in each hole HO. For example, a gate insulating layer and a gate electrode layer may be formed in the hole HO, and then the gate insulating layer and the gate electrode layer may be patterned to form the gate insulating layer GI and the gate electrode GE. The gate electrode GE and the gate insulating layer GI may extend in the third direction D3 along the inner side surface of the stacked structure SS exposed by the hole HO. The gate electrode GE may include a first gate electrode GEa and a second gate electrode GEb respectively disposed at both sides of the semiconductor pattern SP.

[0063] After forming the gate electrode GE, a second insulating pattern IP2 may be formed to fill each hole HO. The second insulating pattern IP2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating pattern IP2 may have an etching selectivity relative to the first insulating pattern IP1. For example, when the first insulating pattern IP1 includes silicon nitride (SiN), the second insulating pattern IP2 may include silicon oxide (SiO).

[0064] Reference Fig.14 and Fig.15, a portion of the semiconductor layer SL other than the semiconductor pattern SP may be replaced by a bit line BL. A wet etching process for selectively etching the semiconductor layer SL may be performed on one side surface of the stacked structure SS. A portion of the semiconductor layer SL may be removed by the wet etching process. The bit line BL may be formed by forming a conductive material in a space formed by removing the semiconductor layer SL. The bit line BL may partially fill the space formed by removing the semiconductor layer SL, and a remaining area of ​​the space formed by removing the semiconductor layer SL may be filled with the insulating layer IL. The bit line BL may extend in a first direction D1. The bit line BL may be electrically connected to the semiconductor pattern SP.

[0065] A first silicide pattern SC1 may be formed between the bit line BL and each of the semiconductor patterns SP. The formation of the first silicide pattern SC1 may include performing a silicidation process on the semiconductor pattern SP exposed by removing a portion of the semiconductor layer SL before forming the bit line BL.

[0066] First dopant regions SD1 may be formed in the semiconductor patterns SP, respectively. The formation of the first dopant regions SD1 may include implanting a dopant into the semiconductor pattern SP through one end portion of the semiconductor pattern SP exposed by removing a portion of the semiconductor layer SL before forming the bit line BL.

[0067] Reference Fig.16 and Fig.17 , a portion of the stacked structure SS may be removed to form a first surface SW exposing an end surface (e.g., a side surface) of the semiconductor pattern SP. The first surface SW may include a side surface of the semiconductor pattern SP, a side surface of the first insulating pattern IP1, and a side surface of the second insulating pattern IP2. The side surfaces of the semiconductor pattern SP, the first insulating pattern IP1, and the second insulating pattern IP2 may be coplanar with each other.

[0068] In detail, a trench TR extending in the first direction D1 may be formed in the stacked structure SS. The formation of the trench TR may include forming a mask pattern (not shown) defining the trench TR on the stacked structure SS, and etching the stacked structure SS using the mask pattern as an etching mask. Since the trench TR is formed, the lengths of the semiconductor pattern SP, the first insulating pattern IP1, and the second insulating pattern IP2 in the second direction D2 may be shortened.

[0069] Reference Fig.18 , Fig.19A and Fig.19B, the length of the semiconductor pattern SP in the second direction D2 can be reduced. The length of the semiconductor pattern SP in the second direction D2 can be shortened compared to the length of the first insulation pattern IP1 and the second insulation pattern IP2 in the second direction D2. For example, the reduction of the length of the semiconductor pattern SP in the second direction D2 may include performing a wet etching process that selectively etches the semiconductor pattern SP. Because the length of the semiconductor pattern SP in the second direction D2 is shorter than the length of the first insulation pattern IP1 and the second insulation pattern IP2 in the second direction D2, a recessed region RS recessed from the first surface SW in a direction opposite to the second direction D2 may be formed. While reducing or shortening the length of the semiconductor pattern SP in the second direction D2, a portion of the second insulation pattern IP2 may also be removed. In addition, the recessed region RS may have a width that increases as the distance from the semiconductor pattern SP increases. The recessed region RS may be defined by the top and bottom surfaces of the first insulation pattern IP1, the inner side surface of the second insulation pattern IP2, and the recessed side surface of the semiconductor pattern SP.

[0070] FIG. 20A to FIG. 20D is with Fig.16 The portion 'B' corresponds to an enlarged view showing a method of forming a recessed area according to some example embodiments of the inventive concept. FIG. 20A to FIG. 20D The process of forming the recess region RS is described in more detail.

[0071] Reference Fig. 20A A first etching process for etching the semiconductor pattern SP may be performed on the first surface SW of the stacked structure SS. The first etching process may be a wet etching process for selectively etching the semiconductor pattern SP among the semiconductor pattern SP, the first insulating pattern IP1, and the second insulating pattern IP2.

[0072] A portion of the semiconductor pattern SP may be removed by the first etching process. A recessed region RS may be formed in the region from which the semiconductor pattern SP is removed. Since the recessed region RS is formed, the top surface of the first insulating pattern IP1 and the inner side surface IP2s of the second insulating pattern IP2 may be exposed.

[0073] Reference Fig. 20B, a second etching process for etching the second insulating pattern IP2 may be performed. The second etching process may be a wet etching process for selectively etching the second insulating pattern IP2 among the semiconductor pattern SP, the first insulating pattern IP1, and the second insulating pattern IP2. A portion of the second insulating pattern IP2 may be removed by the second etching process. Therefore, the distance between the inner side surfaces IP2s of the second insulating pattern IP2 exposed by the recessed region RS may be increased. After performing the second etching process, the distance between the inner side surfaces IP2s of the second insulating pattern IP2 may be greater than the width of the semiconductor pattern SP in the first direction D1.

[0074] Reference Fig. 20C , the first etching process and the second etching process may be alternately performed to increase the width of the recessed region RS in the first direction D1 and the second direction D2. The length of the semiconductor pattern SP in the second direction D2 may be reduced by repeatedly performing the first etching process, and the distance between the inner side surfaces IP2s of the second insulating pattern IP2 may be increased by repeatedly performing the second etching process. Since the first etching process and the second etching process are alternately performed, the inner side surface IP2s of the second insulating pattern IP2 may have a step shape.

[0075] Reference Fig.20D , the first etching process may be performed again to partially remove the semiconductor pattern SP. A distance between inner side surfaces IP2s of the second insulation pattern IP2 adjacent to the semiconductor pattern SP may be equal to a width of the semiconductor pattern SP in the first direction D1.

[0076] Refer again Fig.18 , Fig.19A and Fig.19B , second dopant regions SD2 may be formed in the semiconductor patterns SP, respectively. The formation of the second dopant regions SD2 may include implanting dopants into the semiconductor patterns SP through the exposed side surfaces SPs of the semiconductor patterns SP after forming the recess regions RS.

[0077] The second silicide pattern SC2 may be formed on the exposed side surface SPs of each semiconductor pattern SP. The formation of the second silicide pattern SC2 may include performing a silicidation process on the exposed side surface SPs of the semiconductor pattern SP after forming the second dopant region SD2.

[0078] Reference Fig.21 , Fig.22A and Fig. 22B, the first conductive patterns EL1 may be formed in the recessed regions RS, respectively. For example, the formation of the first conductive patterns EL1 may include: conformally forming a first electrode layer in the recessed regions RS, and wet-etching the first electrode layer to divide the first electrode layer into a plurality of first conductive patterns EL1. Therefore, each of the first conductive patterns EL1 may have a barrel shape with one end thereof opened.

[0079] In detail, each first conductive pattern EL1 may conformally cover the top surface of the first insulating pattern IP1 disposed thereunder, the bottom surface of the first insulating pattern IP1 disposed thereon, the inner side surface of the second insulating pattern IP2, and the end of the semiconductor pattern SP. Since the recessed region RS has a width that increases as the distance from the semiconductor pattern SP increases in the first direction D1, the first conductive pattern EL1 may have a width that increases as the distance from the semiconductor pattern SP increases in the first direction D1. The top surface of the first insulating pattern IP1 and the bottom surface of the first insulating pattern IP1 facing each other may be parallel to each other. The width of the first conductive pattern EL1 in the third direction D3 may be constant.

[0080] Refer again Figure 3 as well as FIG. 4A to FIG. 4D , a portion of the second insulating pattern IP2 may be removed to expose the side surface of the first conductive pattern EL1, and then a dielectric layer DL may be conformally formed on the first conductive pattern EL1. The dielectric layer DL may cover the exposed surface of the first conductive pattern EL1. A second conductive pattern EL2 may be formed on the dielectric layer DL. The second conductive pattern EL2 may be formed to completely fill the trench TR and the recessed region RS.

[0081] In a semiconductor memory device according to some example embodiments of the inventive concept, a conductive pattern constituting a data storage element may have a width that increases as the distance from the semiconductor pattern increases. Thus, process defects may be prevented or minimized, and the reliability of the semiconductor memory device may be improved.

[0082] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above example embodiments are not restrictive, but illustrative. Therefore, the scope of the inventive concept will be determined by the broadest permissible interpretation of the claims and their equivalents, and should not be restricted or limited by the foregoing description.

Claims

1. A semiconductor memory device, comprising: A bit line extending in a first direction; A first conductive pattern extending in a second direction intersecting the first direction; a semiconductor pattern connecting the bit line to the first conductive pattern; a second conductive pattern including an insertion portion located in the first conductive pattern; as well as a dielectric layer, located between the first conductive pattern and the second conductive pattern, The insertion portion of the second conductive pattern has a width that increases as the distance from the semiconductor pattern increases.

2. The semiconductor memory device according to claim 1, wherein The first conductive pattern includes: a first portion adjacent to the semiconductor pattern; a second portion having a width greater than that of the first portion; and a step portion connecting the first portion and the second portion.

3. The semiconductor memory device according to claim 1, further comprising: The gate electrode is located on the semiconductor pattern and extends in a third direction intersecting the first direction and the second direction.

4. The semiconductor memory device according to claim 1, further comprising: a first silicide pattern located between the semiconductor pattern and the bit line; as well as The second silicide pattern is located between the semiconductor pattern and the first conductive pattern.

5. The semiconductor memory device according to claim 1, wherein: Semiconductor patterns include: a first dopant region electrically connected to the bit line; a second dopant region electrically connected to the first conductive pattern; and The channel region is located between the first dopant region and the second dopant region.

6. The semiconductor memory device according to claim 1, wherein: The first conductive pattern includes a first portion and a second portion, the first portion being adjacent to the semiconductor pattern, the second portion having a width greater than that of the first portion; And a width of the first portion in the first direction is substantially equal to a width of the semiconductor pattern in the first direction.

7. The semiconductor memory device according to claim 1, wherein: The second conductive pattern also includes an outer portion surrounding at least a portion of the first conductive pattern.

8. The semiconductor memory device according to claim 1, wherein The first conductive pattern has a width in the first direction that increases with increasing distance from the semiconductor pattern.

9. The semiconductor memory device according to claim 8, wherein: The first conductive pattern has a constant width in a third direction intersecting the first direction and the second direction.

10. The semiconductor memory device according to claim 1, wherein The insertion portion has a width in the first direction that increases as a distance from the semiconductor pattern increases.

11. A semiconductor memory device, comprising: a first insulating pattern vertically stacked on the substrate; A semiconductor pattern located between the first insulating patterns and arranged along a first direction, the semiconductor pattern extending in a second direction intersecting the first direction; a bit line electrically connected to a first end portion of the semiconductor pattern; first conductive patterns, respectively located on the second end portions of the semiconductor patterns; a second conductive pattern including a portion located in the first conductive pattern; as well as The dielectric layer is located between the first conductive patterns and the second conductive patterns, wherein each of the first conductive patterns has a width in the first direction that increases with increasing distance from the corresponding semiconductor pattern.

12. The semiconductor memory device according to claim 11, wherein The first conductive pattern includes a first portion and a second portion, the first portion being adjacent to the semiconductor pattern, the second portion having a width greater than that of the first portion; And a width of the first portion in the first direction is substantially equal to a width of the semiconductor pattern in the first direction.

13. The semiconductor memory device according to claim 11, further comprising: The gate electrode is located on the semiconductor pattern and extends in a third direction intersecting the first direction and the second direction.

14. The semiconductor memory device according to claim 11, further comprising: a first silicide pattern located between each semiconductor pattern and the bit line; as well as The second silicide pattern is located between each semiconductor pattern and the corresponding first conductive pattern.

15. The semiconductor memory device according to claim 11, wherein Each semiconductor pattern includes: a first dopant region electrically connected to the bit line; a second dopant region electrically connected to the first conductive pattern; and The channel region is located between the first dopant region and the second dopant region.

16. A semiconductor memory device, comprising: A stacked structure comprising a plurality of layers vertically stacked on a substrate, wherein each of the plurality of layers comprises: a bit line extending in a first direction; a semiconductor pattern extending from the bit line in a second direction intersecting the first direction; and a first insulating pattern located below the semiconductor pattern; a gate electrode extending in a third direction intersecting the first direction and the second direction and on both side surfaces of the semiconductor pattern; a second insulating pattern filling the space between the semiconductor patterns and covering the gate electrode; first conductive patterns electrically connected to the semiconductor patterns, respectively; and a second conductive pattern spaced apart from the first conductive pattern and having a dielectric layer between the second conductive pattern and the first conductive pattern, Each of the first conductive patterns has a width that increases as a distance from the corresponding semiconductor pattern increases.

17. The semiconductor memory device according to claim 16, wherein: The first insulating pattern has an etch selectivity with respect to the second insulating pattern.

18. The semiconductor memory device according to claim 16, further comprising: The gate insulating layer is located between the semiconductor pattern and the gate electrode.

19. The semiconductor memory device according to claim 16, further comprising: a first silicide pattern located between each semiconductor pattern and the bit line; as well as The second silicide pattern is located between each semiconductor pattern and the corresponding first conductive pattern.

20. The semiconductor memory device according to claim 16, wherein Each semiconductor pattern includes: a first dopant region electrically connected to the bit line; a second dopant region electrically connected to the first conductive pattern; and The channel region is located between the first dopant region and the second dopant region and is adjacent to the gate electrode.

Images