Organic Light-Emitting Diode Display

Abstract

An embodiment of the present invention relates to an organic light-emitting diode display, comprising: a substrate; a semiconductor pattern disposed on the substrate; a first conductive layer disposed on the semiconductor pattern and including a first gate electrode having an island structure, a second gate electrode having an island structure, and a third gate electrode having an island structure; and a second conductive layer disposed on the first conductive layer and including a first initialization voltage line overlapping with the first gate electrode, a scan line overlapping with the second gate electrode, and a control signal line overlapping with the third gate electrode, wherein the control signal line is electrically connected to the third gate electrode, the scan line is electrically connected to the second gate electrode, and the first initialization voltage line, the scan line, and the control signal line extend in a first direction.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority and all benefits arising therefrom to Korean Patent Application No. 10-2019-0134476, filed on October 28, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to an organic light emitting diode display, and more particularly, to an organic light emitting diode display and a method of manufacturing the same, in which a data voltage is transmitted to a pixel through an input capacitor. Background Art

[0004] As a display device for displaying an image, an organic light emitting diode display has received attention.

[0005] An organic light emitting diode display has a self-emitting property, and, unlike a liquid crystal display device, the organic light emitting diode display does not require a separate light source, thereby reducing its thickness and weight. In addition, the organic light emitting diode display exhibits high-quality characteristics such as low power consumption, high brightness, and fast response speed. Summary of the Invention

[0006] An organic light emitting diode display has a more complex pixel structure than that of a liquid crystal display, and as the resolution becomes higher, it is difficult to provide a space for forming a pixel.

[0007] Embodiments provide an organic light emitting display that can receive a data voltage with high efficiency when the data voltage is transmitted to a pixel using an input capacitor. In addition, embodiments provide an organic light emitting display having improved display quality because the voltage of the anode electrode of the organic light emitting diode hardly changes even when the data voltage flowing through the data line changes.

[0008] An embodiment of an organic light emitting diode display includes: a substrate; a semiconductor pattern disposed on the substrate; a first conductive layer disposed on the semiconductor pattern and including a first gate electrode having an island structure, a second gate electrode having an island structure, and a third gate electrode having an island structure; and a second conductive layer disposed on the first conductive layer and including a first initialization voltage line overlapping with the first gate electrode, a scan line overlapping with the second gate electrode, and a control signal line overlapping with the third gate electrode, wherein the control signal line is electrically connected to the third gate electrode, the scan line is electrically connected to the second gate electrode, and the first initialization voltage line, the scan line, and the control signal line extend in a first direction.

[0009] In another embodiment, the organic light emitting diode display may further include: a third conductive layer disposed on the second conductive layer and including data lines extending in a second direction intersecting the first direction; and a fourth conductive layer disposed on the third conductive layer and including a first driving voltage line and a second initialization voltage line extending in the second direction.

[0010] In another embodiment, the second conductive layer may further include a connection member, the semiconductor pattern may include a storage capacitor connection semiconductor, and the connection member may electrically connect the storage capacitor connection semiconductor of the semiconductor pattern to the first gate electrode.

[0011] In another embodiment, the semiconductor pattern may further include a lightly doped region, a heavily doped region, and an undoped region, and the connection member may contact the lightly doped region and the heavily doped region of the semiconductor pattern.

[0012] In another embodiment, the fourth conductive layer may further include a first electrode for the input capacitor, the data line may include an extended portion, and the first electrode for the input capacitor may overlap the extended portion of the data line to form the input capacitor.

[0013] In another embodiment, the semiconductor pattern may further include a data voltage input semiconductor, and the first electrode for the input capacitor may be connected to the data voltage input semiconductor of the semiconductor pattern.

[0014] In another embodiment, the fourth conductive layer may further include an anode connection member, the semiconductor pattern may include an anode connection semiconductor, and the anode connection member may be connected to the anode connection semiconductor and the anode of the semiconductor pattern.

[0015] In another embodiment, the first initialization voltage line and the second initialization voltage line may be electrically connected to each other.

[0016] In another embodiment, the first gate electrode and the first initialization voltage line may overlap to form a storage capacitor.

[0017] In another embodiment, the semiconductor pattern may include a heavily doped region that does not overlap the first conductive layer and an undoped region that overlaps the first conductive layer.

[0018] In another embodiment, a lightly doped region may be disposed between the heavily doped region and the undoped region, and the lightly doped region and the heavily doped region have an n-type material.

[0019] In another embodiment, the semiconductor pattern may have a symmetric structure with respect to the second direction, and the unit semiconductor pattern may correspond to two pixels.

[0020] In another embodiment, the unit semiconductor pattern may have a first driving voltage input semiconductor, the first driving voltage input semiconductor may be connected to the first driving voltage line, and the first driving voltage line may have a structure that shares two adjacent pixel columns.

[0021] An embodiment of an organic light emitting diode display includes: an organic light emitting element; a first transistor that supplies current to the organic light emitting element; a storage capacitor connected to the gate electrode of the first transistor; a second transistor and a third transistor that connect the organic light emitting element and the gate electrode of the first transistor; a data line including an extended portion; an input capacitor that transfers a data voltage from the data line between the second transistor and the third transistor; and a first electrode for the input capacitor, wherein the input capacitor is provided by the extended portion of the data line as a first input capacitor electrode and the first electrode for the input capacitor as a second input capacitor electrode, and the first electrode is disposed on and overlaps with the extended portion of the data line.

[0022] In another embodiment, the organic light emitting diode display may further include a storage capacitor provided by the gate electrode of the first transistor as a first storage capacitor electrode, and a first initialization voltage line as a second storage capacitor electrode to which an initialization voltage is applied.

[0023] In another embodiment, the gate electrode of the second transistor may receive a scan signal, the gate electrode of the third transistor may receive a control signal, the first electrode of the first transistor may receive a first driving voltage, and the cathode of the organic light emitting element may receive a second driving voltage.

[0024] In another embodiment, an initialization period, a threshold voltage compensation period, a programming period, and a light emission period may be included, and the second transistor and the third transistor may be turned on during the initialization period and the threshold voltage compensation period.

[0025] In another embodiment, the first driving voltage may include a high voltage having a high voltage value, a first low voltage having a first low voltage value, and a second low voltage having a second low voltage value lower than the first low voltage value. The first low voltage may be applied as the first driving voltage during the initialization period, the second low voltage may be applied as the first driving voltage during the threshold voltage compensation period, and the high voltage may be applied as the first driving voltage during the programming period and the light emission period.

[0026] In another embodiment, the initialization voltage may include a low voltage and a high voltage, and the initialization voltage may change from the low voltage to the high voltage and start during the light emission period.

[0027] In another embodiment, the low voltage may be applied as the initialization voltage during the threshold voltage compensation period.

[0028] By way of example, the size of the input capacitor electrode disposed above the data line may be large enough to receive the data voltage into the pixel with high efficiency. Additionally, as the data voltage flowing through the data line changes, the anode electrode voltage does not fluctuate or fluctuates little, thereby improving the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other embodiments, advantages, and features of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is an equivalent circuit diagram of an embodiment of a pixel of an organic light emitting diode display.

[0031] Figure 2 is applied to Figure 1 the pixel of the signal timing diagram.

[0032] Figure 3 , Figure 4 , Figure 7 , Figure 10 , Figure 13 and Figure 17 is a plan view divided according to the manufacturing process of the organic light emitting diode display in the embodiment.

[0033] Figure 5 , Figure 6 , Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 , Figure 15 , Figure 16 and Figure 18 is related to Figure 3 ,Figure 4 , Figure 7 , Figure 10 , Figure 13 and Figure 17 The sectional views corresponding to the sectional lines in.

[0034] Figure 19 and Figure 20 are sectional views showing embodiments of a method of forming a lightly doped region in an organic light emitting diode display.

[0035] Figure 21 is according to Figure 19 and Figure 20 An enlarged plan view of an embodiment of a contact portion in a pixel of an organic light emitting diode display.

[0036] Figure 22 is along Figure 21 The sectional view taken along the line XXII - XXII'.

[0037] Figure 23 is a plan view of an embodiment of a partial conductive layer of a portion provided with an input capacitor in a pixel of an organic light emitting diode display.

[0038] Figure 24 is along Figure 23 The sectional view taken along the line XXIV - XXIV'.

[0039] Figure 25 is a plan view of an embodiment of a partial conductive layer of a portion provided with a storage capacitor in a pixel of an organic light emitting diode display.

[0040] Figure 26 is along Figure 25 The sectional view taken along the line XXVI - XXVI'.

[0041] Figure 27 is an enlarged plan view of an embodiment of a contact portion in a pixel of an organic light emitting diode display.

[0042] Figure 28 is a plan view of an embodiment of a pixel of an organic light emitting diode display.

[0043] Figure 29 is an equivalent circuit diagram of another embodiment of a pixel of an organic light emitting diode display.

[0044] Figure 30 is applied to Figure 29 The timing diagram of the signal of the pixel. Detailed Description

[0045] The present invention will now be described more fully with reference to the accompanying drawings, in which embodiments of the present invention are shown. As those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention.

[0046] To clearly explain the present invention, parts not directly related to the present invention are omitted, and throughout the specification, the same reference numerals are attached to the same or similar components.

[0047] In addition, for better understanding and ease of description, the dimensions and thicknesses of each configuration shown in the drawings are arbitrarily shown, but the present invention is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0048] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, the element can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements. Further, in the specification, the words “on... ” or “above... ” mean being located on or below the object part, and do not necessarily mean being on the upper side of the object part based on the direction of gravity.

[0049] In addition, unless explicitly described to the contrary, the terms “comprise” and variations such as “comprises” and “comprising” will be understood to mean including the stated elements, but not excluding any other elements.

[0050] It will be understood that although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings herein, the “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below can be named the second element, second component, second region, second layer, or second part.

[0051] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, including “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0052] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the drawings. It will be understood that the relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device is flipped in one of the drawings, an element described as on the "lower" side of another element will then be oriented on the "upper" side of the other element. Thus, depending on the specific orientation of the drawings, the exemplary term "lower" can cover both the "lower" and "upper" orientations. Similarly, if the device is flipped in one of the drawings, an element described as "beneath" or "under" another element will then be oriented "above" the other element. Thus, the exemplary terms "beneath" or "under" can cover both the upper and lower orientations.

[0053] In addition, throughout the specification, the phrase "in a plan view" refers to observing the target portion from the top, and the phrase "in a cross section" refers to observing a cross section provided by vertically cutting the target portion from the side.

[0054] Now, referring to Figure 1 and Figure 2 , a pixel of the organic light emitting diode display in the embodiment will be described.

[0055] Figure 1 is an equivalent circuit diagram of an embodiment of a pixel of the organic light emitting diode display, and Figure 2 is a timing diagram of the signals applied to the Figure 1 pixel.

[0056] The pixel of the organic light emitting diode display in the embodiment includes three transistors T1, T2, and T3, two capacitors Cst and Cpr, and an organic light emitting element (e.g., an organic light emitting diode OLED). Figure 1 The transistors T1, T2, and T3 in the embodiment of can be n-type transistors that are turned on when the voltage applied to the gate electrode is a high voltage. However, the present invention is not limited thereto, and in another embodiment, at least some of the transistors T1, T2, and T3 can be p-type transistors.

[0057] The driving transistor T1 is a transistor in which the voltage applied to the gate electrode changes according to the data voltage Vdata, and thus, the output current is transmitted to the organic light emitting diode OLED. The gate electrode of the driving transistor T1 is connected to the storage capacitor Cst, the driving voltage ELVDD (hereinafter also referred to as the first driving voltage) is applied to the first electrode, and the anode electrode of the organic light emitting diode OLED is connected to the second electrode of the driving transistor T1.

[0058] The anode electrode of the organic light-emitting diode OLED is connected to the second electrode of the driving transistor T1, and the second driving voltage ELVSS is applied to the cathode of the organic light-emitting diode OLED.

[0059] In addition, the second transistor T2 and the third transistor T3 are connected between the gate electrode of the driving transistor T1 and the second electrode of the driving transistor T1. The input capacitor Cpr is connected to an intermediate terminal to which the second transistor T2 and the third transistor T3 are connected. Hereinafter, the intermediate terminal of the second transistor T2 and the third transistor T3 to which the input capacitor Cpr is connected is also referred to as the data voltage input terminal.

[0060] First, the second transistor T2 is described.

[0061] The second transistor T2 is disposed between the gate electrode of the driving transistor T1 and the data voltage input terminal. The first electrode of the second transistor T2 is connected to the data voltage input terminal to receive a data voltage, and is connected to the third transistor T3, and the second electrode is connected to the gate electrode of the driving transistor T1 and the storage capacitor Cst. The gate electrode of the second transistor T2 is connected to the scan line 142 such that a conduction voltage is sequentially applied according to the scan signal GW during the programming period, and a conduction voltage is applied during the initialization period and the threshold voltage compensation period.

[0062] The third transistor T3 is disposed between the second electrode of the driving transistor T1 and the data voltage input terminal. The first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1 and the anode electrode of the organic light-emitting diode OLED, and the second electrode of the third transistor T3 is connected to the data voltage input terminal which is to be connected to the first electrode of the second transistor T2. The gate electrode of the third transistor T3 is connected to the control signal line 143. During the initialization period and the threshold voltage compensation period, a conduction voltage is applied along with the control signal GC applied to the control signal line 143.

[0063] During the programming period, the second transistor T2 transfers the data voltage input through the input capacitor Cpr to the gate electrode of the driving transistor T1, and during the initialization period and the threshold voltage compensation period, the second transistor T2 and the third transistor T3 cooperate to initialize the voltage of the anode electrode of the organic light-emitting diode OLED and the voltage of the gate electrode of the driving transistor T1, and store the threshold voltage in the storage capacitor Cst.

[0064] The storage capacitor Cst stores and maintains the data voltage transmitted to the gate electrode of the driving transistor T1 through the second transistor T2. The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor T1 and the second electrode of the second transistor T2, and the initialization voltage Vint is applied to the second electrode of the storage capacitor Cst.

[0065] The data line 171 is connected to the data voltage input terminal through the input capacitor Cpr. That is, the first electrode of the input capacitor Cpr is connected to the data voltage input terminal, and the second electrode of the input capacitor Cpr is connected to the data line 171. Thus, as the voltage of the data line 171 changes, the voltage of the data voltage input terminal changes, and the second transistor T2 is turned on so that the data voltage of the corresponding pixel is transmitted to the gate electrode of the driving transistor T1. At this time, since the amount of change in the voltage generated at the data voltage input terminal is transmitted through the input capacitor Cpr, the amount of change in the voltage generated at the data voltage input terminal can be reduced and transmitted, rather than having the amount of change in the voltage generated at the data line 171. That is, although a voltage value lower than the data voltage Vdata applied to the data line 171 can be transmitted to the data voltage input terminal, for convenience, the expression "data voltage" is also used for the voltage transmitted to the data voltage input terminal. Thus, for convenience, the voltage transmitted to the data voltage input terminal and the voltage applied to the data line 171 can be referred to as the data voltage Vdata. However, for clarity, the data voltage Vdata of the data line 171 and the data voltage of the data voltage input terminal can be distinguished from each other. In addition, the data voltage of the data voltage input terminal can also be referred to as the data voltage transmitted through the input capacitor Cpr. For convenience, even when the data voltage transmitted to the data voltage input terminal is transmitted to the gate electrode of the driving transistor T1 and the storage capacitor Cst through the second transistor T2, the expression "data voltage" is used. For clarity, the data voltage of the gate electrode of the driving transistor T1 or the data voltage stored in the storage capacitor Cst can refer to the voltage of the data voltage input terminal transmitted to the gate electrode of the driving transistor T1 and the storage capacitor Cst through the second transistor T2.

[0066] Next, based on Figure 2 Describe the operation according to the applied signal with respect to the Figure 1 pixels in the image.

[0067] The pixels of the organic light emitting diode display in the embodiment operate in cycles classified as an initialization period Initial, a threshold voltage compensation period Vth Comp., a programming period Programming, and an emission period Emission.

[0068] While the first driving voltage ELVDD applied to the first electrode of the driving transistor T1 changes from a high voltage to a first low voltage, the organic light-emitting diode OLED that emits light during the light emission period Emission ends the light emission period Emission. At this time, the first low voltage is applied to the cathode of the organic light-emitting diode OLED and has a voltage value less than or equal to the second driving voltage ELVSS, so that current does not flow in the forward direction in the organic light-emitting diode OLED. Thereby, the light emission period Emission ends. In an embodiment, the first low voltage of the first driving voltage ELVDD may have a voltage value slightly greater than the voltage value of the second driving voltage ELVSS, but the voltage of the anode electrode of the organic light-emitting diode OLED has a voltage value not greater than the voltage of the cathode electrode to end the light emission period Emission.

[0069] Thereafter, the organic light-emitting diode OLED enters the initialization period Initial. The initialization period Initial starts while the scan signal GW applied to the scan line 142 and the control signal GC applied to the control signal line 143 respectively become high voltages (on voltages). The second transistor T2 and the third transistor T3 are turned on by the scan signal GW and the control signal GC to which the on voltage is applied, and the anode electrode of the organic light-emitting diode OLED (including the second electrode of the driving transistor T1), the first electrode of the input capacitor Cpr, and the first electrode of the storage capacitor Cst (including the gate electrode of the driving transistor T1) are connected to each other, so that the voltage of the anode electrode of the organic light-emitting diode OLED, the voltage of the first electrode of the input capacitor Cpr, and the voltage of the first electrode of the storage capacitor Cst become the same voltage while sharing the charging charge. The same voltage at this time is called the first connection voltage. In the illustrated embodiment, the scan signal GW[1] may be applied to the first scan line, the scan signal GW[2] may be applied to the second scan line, and the scan signal GW[n] may be applied to the nth scan line, where n is a natural number greater than 2.

[0070] Thereafter, during the Initial initialization period, the initialization voltage Vint becomes a low voltage. As a result, the voltage value of the first electrode of the storage capacitor Cst (including the gate electrode of the driving transistor T1) decreases. Therefore, the voltage of the anode electrode of the organic light-emitting diode OLED (including the second electrode of the driving transistor T1) and the first electrode of the input capacitor Cpr also decreases. That is, when the initialization voltage Vint becomes a low voltage during the Initial initialization period, the first connection voltage becomes the second connection voltage, and the second connection voltage has a voltage value lower than that of the first connection voltage. At this time, both the first connection voltage and the second connection voltage have voltage values less than or equal to the second driving voltage ELVSS, so that current does not flow into the organic light-emitting diode OLED in the forward direction, and the organic light-emitting diode OLED does not emit light.

[0071] Thereafter, the first driving voltage ELVDD changes from a first low voltage to a second low voltage having a voltage value less than the first low voltage value, and enters the threshold voltage compensation period Vth Comp. When the first driving voltage ELVDD changes to the second low voltage, the voltage of the gate electrode connected to the first electrode of the driving transistor T1 through the parasitic capacitance, that is, the voltage of the first electrode of the storage capacitor Cst can also decrease. However, the second low voltage value of the first driving voltage ELVDD is low enough so that the voltage of the gate electrode of the driving transistor T1 turns on the driving transistor T1. In the threshold voltage compensation period VthComp., similar to the initialization period Initial, the conduction voltage is also applied to the scan signal GW and the control signal GC, so that the second transistor T2 and the third transistor T3 are maintained in the on state. Therefore, since the voltage of the gate electrode of the driving transistor T1 has the conduction voltage value, the driving transistor T1 is in the diode-connected state where the gate electrode of the driving transistor T1 is connected to the second electrode of the driving transistor T1, and the current flows from the second electrode of the driving transistor T1 to the first electrode of the driving transistor T1. Since the second electrode of the driving transistor T1 is connected to the gate electrode of the driving transistor T1, as the charge flows out from the gate electrode of the driving transistor T1 to the first electrode of the driving transistor T1, the voltage of the gate electrode of the driving transistor T1 decreases. After the voltage of the gate electrode of the driving transistor T1 decreases, when the difference between the voltage of the gate electrode of the driving transistor T1 and the voltage of the first electrode of the driving transistor T1 (i.e., the second low voltage) becomes the threshold voltage value of the driving transistor T1, the driving transistor T1 turns off. At this time, the voltage value of the gate electrode of the driving transistor T1 is larger than the voltage value of the second low voltage by the threshold voltage value of the driving transistor T1, and the voltage value is stored in the first electrode of the storage capacitor Cst. When the voltage value of the second low voltage is called "ELVDD_L2" and the threshold voltage value is called "Vth", the value stored in the first electrode of the storage capacitor Cst is ELVDD_L2 + Vth. As described above, since the value corresponding to the threshold voltage value of the driving transistor T1 is stored in the storage capacitor Cst, this period is called the threshold voltage compensation period Vth Comp. Here, since both the second transistor T2 and the third transistor T3 are on, the voltage of the first electrode of the storage capacitor Cst and the voltage of the first electrode of the input capacitor Cpr have the same value, and the voltage of the anode also has the same value.

[0072] During the threshold voltage compensation period Vth Comp., since the voltage values of the gate electrode and the second electrode of the driving transistor T1 become values lower than the first connection voltage and the second connection voltage during the initialization period Initial, the voltage values of both the gate electrode and the second electrode of the driving transistor T1 can be less than the voltage value of the second driving voltage ELVSS. As a result, in the organic light-emitting diode OLED, no current flows in the forward direction, and the organic light-emitting diode OLED does not emit light.

[0073] Next, the scan signal GW applied to the scan line 142 and the control signal GC applied to the control signal line 143 become low voltages of the cut-off voltage, and the first driving voltage ELVDD changes from the second low voltage to the high voltage. When the first driving voltage ELVDD becomes the high voltage, the voltage of the gate electrode of the driving transistor T1 can increase. That is, the value pre-stored in the first electrode of the storage capacitor Cst is ELVDD_L2 + Vth, and when the high voltage value of the first driving voltage ELVDD is ELVDD_H, the value stored in the first electrode of the storage capacitor Cst is ELVDD_H + Vth - a. Here, the voltage change value of the first electrode of the driving transistor T1 is less than the voltage change value of the gate electrode, and the value a represents the degree of its smallness. As a result, the voltage difference between the first electrode and the gate electrode of the driving transistor T1 is less than the voltage value of the threshold voltage Vth, so the driving transistor T1 does not generate an output. In addition, since the second transistor T2 and the third transistor T3 are in the cut-off state, the increase in the voltage of the gate electrode of the driving transistor T1 does not affect the anode electrode of the organic light-emitting diode OLED. Therefore, the organic light-emitting diode OLED still does not emit light.

[0074] Thereafter, the programming cycle of applying the conduction voltage to each scan line 142 in sequence starts. In the programming cycle, when the second transistor T2 is turned on by the scan signal GW (the high voltage (conduction voltage) of which is applied to the scan line 142 in sequence), the data voltage of the data voltage input terminal is transmitted to and stored in the first electrode of the storage capacitor Cst. At this time, the data voltage of the data voltage input terminal can have a voltage value lower than the voltage value of the data voltage Vdata applied from the data line 171 as the voltage transmitted through the input capacitor Cpr from the data line 171. The voltage of the first electrode of the storage capacitor Cst before entering the programming cycle is (ELVDD_H + Vth - a), and when the data voltage of the data voltage input terminal is referred to as (Vdata - b) (here, b represents the resulting voltage value lower than the voltage value applied to the data line 171), the voltage of the first electrode of the storage capacitor Cst after entering the programming cycle is (ELVDD_H + Vth - a + Vdata - b). At this time, due to the values a and b, the voltage difference between the first electrode and the gate electrode of the driving transistor T1 is set to a voltage value less than the threshold voltage Vth. Therefore, the driving transistor T1 does not generate an output current. In the illustrated embodiment, the reference character DATA<1> may refer to the data voltage applied to the first pixel row, and the reference character DATA <n>It may refer to the data voltage applied to the nth pixel row.

[0075] In Figure 2 it, a hold period Hold is included within a programming cycle Programming, and the hold period Hold, as the period before or after the conduction voltage is applied to the scan signal GW, has a different hold period Hold for each scan line 142. The hold period Hold is a period for maintaining the voltage of the storage capacitor Cst and other terminals.

[0076] When the data voltage of the data voltage input terminal is stored in the first electrode of the storage capacitor Cst of all pixels, while the initialization voltage Vint changes from a low voltage to a high voltage, the organic light-emitting diode OLED emits light. This is called the emission period Emission.

[0077] When the initialization voltage Vint becomes a high voltage, the voltage of the first electrode of the storage capacitor Cst also increases, and the voltage difference between the first electrode and the gate electrode of the driving transistor T1 is greater than the threshold voltage Vth, such that the driving transistor T1 emits an output current. The current output from the driving transistor T1 is transmitted to the anode electrode of the organic light-emitting diode OLED, and the degree of light emission of the organic light-emitting diode OLED changes according to the magnitude of the current.

[0078] At this time, the voltage of the gate electrode of the driving transistor T1 is (ELVDD_H + Vth - a + Vdata – b + c), where c represents the voltage value that increases while the initialization voltage Vint becomes a high voltage. When the value c is set to a value that cancels the value a and the value b, the voltage of the gate electrode of the driving transistor T1 becomes (ELVDD_H + Vth + Vdata). In this case, since the first electrode of the driving transistor T1 has a voltage value of ELVDD_H, the voltage difference between the first electrode and the gate electrode is (Vth + Vdata). When the driving transistor T1 is turned on, the threshold voltage Vth is used, and only the remaining data voltage Vdata is used to actually determine the output current of the driving transistor T1. Thus, in the pixels in the illustrated embodiment, the output current of the driving transistor T1 is determined based on the data voltage Vdata applied to the data line 171.

[0079] In addition, even if the threshold voltage Vth is different for each driving transistor T1, the corresponding value has been included in and compensated for in the gate electrode of the driving transistor T1, and the output current is determined by the remaining data voltage Vdata, such that it is not necessary to consider the threshold voltage of each driving transistor T1. In addition, even when the threshold voltage of each of the driving transistors T1 is different, the same brightness is emitted for the same data voltage, such that the display quality does not deteriorate.

[0080] Here, when designing the pixels, values a, b, and c are determined based on the overlapping regions or intervals of the pixels such that the pixels can be designed to cancel out these values. Additionally, even when some values remain, all pixels are provided in a constant shape such that a constant value is maintained. Thus, when a voltage is applied to the data line considering the constant value for all pixels, the final desired data voltage value can determine the output current of the driving transistor T1. Therefore, the threshold voltage can be compensated and the output voltage of the driving transistor T1 can be determined as an appropriate data voltage value.

[0081] During the light emission period Emission, all pixels emit light simultaneously for the same duration. However, in an embodiment, the light emission can be performed by some pixels.

[0082] When the pixels of the organic light emitting diode display operated as described above are provided on an actual substrate, the structure can be the same as that in the following Figures 3 to 18 figure.

[0083] Figure 3 , Figure 4 , Figure 7 , Figure 10 , Figure 13 and Figure 17 are plan views divided according to the manufacturing process of the organic light emitting diode display in the embodiment, and Figure 5 , Figure 6 , Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 , Figure 15 , Figure 16 and Figure 18 are cross-sectional views corresponding to the cross-section lines in Figure 3 , Figure 4 , Figure 7 , Figure 10 , Figure 13 and Figure 17 .

[0084] First, Figure 3 is described.

[0085] Figure 3 is a plan view showing the semiconductor pattern 150 provided on the substrate.

[0086] Figure 3 The semiconductor pattern 150 shown in

[0087] In the semiconductor pattern 150, a unit semiconductor pattern having a symmetric structure is repeatedly provided, and one unit semiconductor pattern 150 corresponds to two pixels. The use of the symmetric structure is intended to form a high-resolution display device such as a 4K resolution display device or an 8K resolution display device by sharing wirings and reducing the area to be occupied. When the wirings are reduced, the openings defined as connecting the wirings and other parts are also reduced, thereby reducing the occupied area.

[0088] The semiconductor pattern 150 extends upward from the first driving voltage input semiconductor 150e, then extends in the horizontal direction, that is, extends in the left and / or right direction, and then bends downward and extends. The semiconductor 151 for driving the transistor T1 is located at the horizontal portion and the vertical portion with respect to the bent portion.

[0089] The anode electrode connecting semiconductor 150a is located at the portion extending downward from the semiconductor 151 for driving the transistor T1 and bends outward, and the semiconductor 153 for the third transistor T3 is provided at the portion extending outward and downward from the anode electrode connecting semiconductor 150a.

[0090] Subsequently, the data voltage input semiconductor 150i connected to the first electrode of the input capacitor Cpr is provided at the portion extending further downward and bending inward.

[0091] The semiconductor pattern 150 extends inward from the data voltage input semiconductor 150i and extends to bend upward, and the semiconductor 152 for the second transistor T2 is provided at the portion extending to bend upward.

[0092] The semiconductor pattern 150 extends upward from the semiconductor 152 of the second transistor T2, then extends in the inclined direction (the direction between the upper side and the outside), and then expands. The expanded portion is the storage capacitor connecting semiconductor 150c connected to the first electrode of the storage capacitor Cst.

[0093] Next, referring to Figures 4 to 6 , it is described that Figure 3 the structure provided on the semiconductor pattern 150.

[0094] Figure 4 is a plan view of the semiconductor pattern 150 and the first gate conductive layer provided thereon, and Figure 5 and Figure 6 are cross-sectional views taken along the Figure 4 lines V-V' and VI-VI' of

[0095] Referring to Figure 5 and Figure 6 , a first gate insulating layer 130 (hereinafter also referred to as the first insulating layer) is formed over a semiconductor pattern 150 disposed on a substrate 110. In Figure 5 and Figure 6 , semiconductors 152, 153, 152' and 153' are shown, and the prime symbol (') of 152' and 153' indicates that those semiconductors are not in the same pixel as semiconductors 152 and 153 without the prime symbol ('), but are disposed in adjacent pixels. This meaning of the prime symbol (') is used in the same way in the description herein. In an embodiment, the first gate insulating layer 130 includes an inorganic film, and for example, may include a film containing silicon oxide (SiO x ) or a film containing silicon nitride (SiN x ), or may include a bilayer including the above layers.

[0096] A first gate conductive layer (hereinafter also referred to as the first conductive layer) is disposed over the first gate insulating layer 130. In another embodiment, the first gate conductive layer includes island-shaped gate electrodes 124, 125, and 126, provided by etching the conductive layer with a mask after deposition, and may include two or more conductive layers.

[0097] The first gate electrode 124 (hereinafter also referred to as the driving gate electrode) may be the gate electrode of the driving transistor T1 and also serves as the first electrode of the storage capacitor Cst. That is, the lower surface of the first gate electrode 124 faces the semiconductor 151 for the driving transistor T1 and serves as the gate electrode of the driving transistor T1, and the upper surface of the first gate electrode 124 faces the horizontal initialization voltage line 141 (refer to Figure 7 ) to be described later and serves as the first electrode of the storage capacitor Cst. The first gate electrode 124 corresponds to only the driving transistor T1 of one pixel.

[0098] The second gate electrode 125 overlaps with the semiconductors 152 of the two facing second transistors T2 in one unit semiconductor pattern 150 to constitute the gate electrode of the second transistor T2. Thus, the gate electrodes of the second transistors T2 of two pixels include one second gate electrode 125.

[0099] The third gate electrode 126 overlaps with the semiconductors 153 of the two facing third transistors T3 in two adjacent unit semiconductor patterns 150 to constitute the gate electrode of the third transistor T3. Thus, the gate electrodes of the third transistors T3 of two pixels are composed of one third gate electrode 126.

[0100] In the illustrated embodiment, the first gate conductive layer does not have a linear structure extending in the horizontal direction, but has an island structure. Moreover, a gate electrode may have a maximum width corresponding to two adjacent pixels in the horizontal direction and does not exceed two adjacent pixels.

[0101] To apply a signal to each of the gate electrodes 124, 125, and 126, a linear structure extending from right to left is desired, and the first gate conductive layer does not have such a structure as shown in Figure 4 this structure shown in

[0102] After providing the first gate conductive layer as shown in Figures 4 to 6 this structure shown in Figures 19 to 22 a doping process is performed. In the doping process, the semiconductor pattern 150 not covered by the first gate conductive layer is doped at a high concentration through the first gate conductive layer used as a mask to have conductor characteristics. A part of the undoped semiconductor pattern 150 constitutes the channel of the transistor. At this time, when the doping material used is an n-type material, the transistor becomes an n-type transistor, and when a p-type material is used, the transistor becomes a p-type transistor. In the case of an n-type transistor, a lightly doped region may be provided between the conductive semiconductor part and the channel of the transistor, and the lightly doped region will be described in further detail with reference to

[0103] In contrast, the second gate conductive layer in the embodiment described below includes a linear pattern.

[0104] Hereinafter, with reference to Figures 7 to 9 the second gate conductive layer and the opening position will be described.

[0105] Figure 7 is a plan view of the second gate conductive layer and the opening provided on the semiconductor pattern 150 and the first gate conductive layer, and Figure 8 and Figure 9 are cross-sectional views taken along line VIII-VIII' and line IX-IX' according to Figure 7 this structure shown in

[0106] With reference to Figure 8 and Figure 9 a second gate insulating layer 131 (hereinafter also referred to as the second insulating layer) is covered on the first gate conductive layer, and a second gate conductive layer (hereinafter also referred to as the second conductive layer) is provided on the second gate insulating layer 131.

[0107] In the embodiment, the second gate insulating layer 131 may include an inorganic layer and may include a film containing silicon oxide (SiO x ) or a film containing silicon nitride (SiN x ), or may include a bilayer including them.

[0108] The second gate conductive layer includes a horizontal initialization voltage line 141, a scan line 142, a control signal line 143, and a connection member 144, and can be provided by etching the conductive layer with a mask after deposition.

[0109] In addition, in an embodiment, the second gate conductive layer may include two or more conductive layers.

[0110] Unlike the first gate conductive layer, the second gate conductive layer has a structure including wirings extending in the horizontal direction and a wiring form in which all elements except the connection member 144 extend in the horizontal direction.

[0111] The horizontal initialization voltage line 141 has a wiring extending in the horizontal direction and is disposed at a position overlapping the first gate electrode 124 to form a storage capacitor Cst. That is, the first gate electrode 124 also serves as the first electrode of the storage capacitor Cst, and the lower surface of the horizontal initialization voltage line 141 serves as the second electrode of the storage capacitor Cst. Referring to Figure 7 , the horizontal initialization voltage line 141 has a vertical width substantially equal to the vertical width of the first gate electrode 124 to form a sufficiently large storage capacitor Cst.

[0112] The scan line 142 and the control signal line 143 also have a wiring shape extending in the horizontal direction.

[0113] The scan line 142 extends while overlapping the second gate electrode 125 and is electrically connected to the second gate electrode 125 through an opening 162.

[0114] In addition, the control signal line 143 extends while overlapping the third gate electrode 126 and is electrically connected to the third gate electrode 126 through an opening 163.

[0115] The connection member 144 has a unique island structure in the second gate conductive layer, and one connection member 144 is provided for each pixel. The connection member 144 electrically connects the storage capacitor connection semiconductor 150c and the first gate electrode 124 through an opening 161. In particular, since the connection member 144 and the opening 161 can have a side contact structure, a part of the upper surface of the first gate electrode 124 and a part of the upper surface of the storage capacitor connection semiconductor 150c are exposed through the opening 161, and the connection member 144 electrically connects the two.

[0116] This side contact structure has the following advantages: the occupied horizontal area is narrow, which is suitable for high-resolution pixels, and the area overlapping the data line 171 to be provided in a subsequent process is reduced, so that the structure is less affected by the voltage change of the data line 171.

[0117] The general features of the structures of the first gate conductive layer and the second gate conductive layer are characterized in that only an island structure is provided in the first gate conductive layer, and a linear structure is provided in the second gate conductive layer. This feature has the advantage that the spatial arrangement can be efficient, and thus has the advantage of forming a large-area input capacitor Cpr. This is because the horizontal initialization voltage line 141, the scan line 142, and the control signal line 143 are provided in the second gate conductive layer and are uniformly provided in the pixel region, so that the first data conductive layer and the second data conductive layer to be provided thereon can have a relatively flat structure, thereby allowing the input capacitor Cpr to have a sufficiently large capacitance.

[0118] Hereinafter, with reference to Figures 10 to 12 , the first data conductive layer will be described.

[0119] Figure 10 is a plan view of the first data conductive layer provided on the semiconductor pattern 150, the first gate conductive layer, and the second gate conductive layer, and Figure 11 and Figure 12 are cross-sectional views taken along the lines XI-XI' and XII-XII' of Figure 10 .

[0120] With reference to Figure 11 and Figure 12 , a first interlayer insulating layer 132 (hereinafter also referred to as a third insulating layer) is provided on the second gate conductive layer, and a first data conductive layer (hereinafter also referred to as a third conductive layer) is provided on the first interlayer insulating layer 132.

[0121] The first interlayer insulating layer 132 includes an inorganic film and is provided with a thick thickness to reduce the steps generated when the conductive layer and the inorganic film are repeatedly provided. In an embodiment, the first interlayer insulating layer 132 may include a film containing silicon oxide (SiO x ) or a film containing silicon nitride (SiN x ), and may include a bilayer including each of them in order to increase the thickness.

[0122] The first data conductive layer includes data lines 171 and is provided by depositing a conductive layer and then etching the conductive layer through a mask. In an embodiment, the first data conductive layer may include two or more layers of conductive layers. Different from the second gate conductive layer, the first data conductive layer includes data lines 171 extending in the vertical direction.

[0123] Two data lines 171 are provided with respect to a semiconductor pattern 150, and one data line 171 is provided with respect to a pixel column. The two data lines 171 corresponding to a semiconductor pattern 150 have a symmetrical structure with respect to the center line in the vertical direction of the semiconductor pattern 150. In addition, the data line 171 includes an extended portion wider than the extended portion of the data line 171, and the extended portion of the data line 171 serves as the second electrode of the input capacitor Cpr. Due to the extended portion of the data line 171, the input capacitor Cpr can have a maximum capacitance.

[0124] Hereinafter, with reference to Figures 13 to 16 , the second data conductive layer and the opening position will be described.

[0125] Figure 13 is a plan view of the second data conductive layer, the first gate conductive layer, the second gate conductive layer, and the first data conductive layer provided on the semiconductor pattern 150, and Figures 14 to 16 is a cross-sectional view taken along the Figure 13 lines XIV-XIV', XV-XV', and XVI-XVI'.

[0126] With reference to Figures 14 to 16 , a second interlayer insulating layer 133 (hereinafter also referred to as the fourth insulating layer) is covered on the first data conductive layer, and a second data conductive layer (hereinafter also referred to as the fourth conductive layer) is provided on the second interlayer insulating layer 133.

[0127] The second interlayer insulating layer 133 includes an inorganic film and may include a film containing silicon oxide (SiO x ) or a film containing silicon nitride (SiN x ), or may include a double layer including both of them.

[0128] The second data conductive layer includes a first driving voltage line 172, a vertical initialization voltage line 173, an anode connection member 174, and a first electrode 175 for the input capacitor Cpr.

[0129] In an embodiment, the second data conductive layer is provided by depositing a conductive layer and then etching it through a mask, or the second data conductive layer may include two or more layers of conductive layers.

[0130] The first driving voltage line 172 extends in the vertical direction and is a wiring for transmitting the first driving voltage ELVDD. In addition, with reference to Figure 14 , the first driving voltage line 172 is electrically connected to the first driving voltage input semiconductor 150e through the opening 164. Thus, the first driving voltage ELVDD is transmitted to the first driving voltage input semiconductor 150e of the semiconductor pattern 150. Since the first driving voltage lines 172 are provided one by one for one semiconductor pattern 150, two pixel columns have a structure in which a single first driving voltage line 172 is shared. Thus, the area occupied by the pixels is reduced.

[0131] The vertical initialization voltage line 173 also extends in the vertical direction and is a wiring for transmitting the initialization voltage Vint. Refer to Figure 14 , the vertical initialization voltage line 173 is electrically connected to the horizontal initialization voltage line 141 through the opening 166. Thus, the initialization voltage Vint is connected horizontally and vertically so that the voltage is applied in a mesh form, and a constant initialization voltage Vint can be applied to the pixels provided at different positions.

[0132] The first driving voltage line 172 and the vertical initialization voltage line 173 extend in a direction parallel to the data line 171 provided in the first data conductive layer.

[0133] However, the first driving voltage line 172 and the vertical initialization voltage line 173 are provided in the second data conductive layer to be provided on a layer different from the layer of the data line 171, so that the data line 171 has a sufficient width regardless of other wirings. Thus, the input capacitor Cpr can have a sufficiently large capacitance so that the data voltage can enter the pixel with high efficiency.

[0134] The anode electrode connection member 174 has an island-like structure, and one anode electrode connection member 174 is provided for each pixel. Refer to Figure 14 , the anode electrode connection member 174 is connected to the anode electrode connection semiconductor 150a through the opening 165. The output current of the driving transistor T1 is transmitted to the anode electrode 191 through the anode electrode connection semiconductor 150a and the anode electrode connection member 174 (refer to Figure 17 and Figure 18 ). That is, the anode electrode connection member 174 is connected to the lower anode electrode connection semiconductor 150a and the upper anode electrode 191.

[0135] The first electrode 175 for the input capacitor Cpr also has an island-like structure, and one first electrode 175 for the input capacitor Cpr is provided for each pixel. As Figure 13 shown, the first electrode 175 has as large an area as possible, and refer to Figure 15 , the first electrode 175 provides the input capacitor Cpr by overlapping with the extended portion of the data line 171. In addition, refer to Figure 16 , the first electrode 175 for the input capacitor Cpr is connected to the data voltage input semiconductor 150i through the opening 167. Thus, the data voltage transmitted through the input capacitor Cpr is transmitted to the data voltage input semiconductor 150i between the second transistor T2 and the third transistor T3. The data voltage Vdata is applied along the data line 171 and then capacitively coupled to and transmitted to the first electrode 175 for the input capacitor Cpr, and the transmitted data voltage is transmitted to the data voltage input semiconductor 150i through the opening 167.

[0136] For the data voltage to be capacitively coupled to and transmitted to the first electrode 175 for the input capacitor Cpr, it is advantageous to have a larger overlapping area between the extended portion of the data line 171 and the first electrode 175 for the input capacitor Cpr, such that only the data line 171 is provided in the first data conductive layer in order to ensure the maximum area.

[0137] The pixel of the organic light emitting diode display can be mainly divided into an organic light emitting element portion and a pixel circuit portion, and the pixel circuit is Figures 3 to 16 the portion shown in, and the layer above the anode electrode 191 corresponds to the organic light emitting element portion. Hereinafter, with reference to Figure 17 and Figure 18 , the arrangement and structure of the organic light emitting element portion will be described.

[0138] Figure 17 is a plan view showing a part of the anode electrode 191 and the organic light emitting layer 192, and Figure 18 is a cross-sectional view taken along the line XVIII-XVIII' of Figure 17 .

[0139] In Figure 17 , in order to prevent the drawing from being complicated, the wirings provided under the anode electrode 191 are not shown, and a pixel circuit unit is simply shown in a rectangular shape for distinction. Figures 3 to 16 The wiring structure of is provided within a rectangular shape.

[0140] With reference to Figure 18 , the anode electrode 191 is connected to the anode connection member 174 through the opening 181 provided in the organic layer 190 to receive the output current of the driving transistor T1. A partition wall 194 is provided on the anode electrode 191, and an opening 182 is defined in the partition wall 194 to expose a part of the anode electrode 191.

[0141] The organic light emitting layer 192 is provided on the exposed anode electrode 191 and within the opening 182 of the partition wall 194. The cathode electrode 193 is entirely provided on the upper surface of the partition wall 194 and the organic light emitting layer 192.

[0142] An encapsulation layer 195 is provided thereon to prevent moisture and oxygen from entering the organic light-emitting layer 192 from the outside. In Figure 18 , the encapsulation layer 195 is shown as a single layer, but the encapsulation layer 195 includes at least one organic layer and at least one inorganic layer, which are alternately provided to block moisture and oxygen from the outside. In an embodiment, the encapsulation layer 195 may have a three-layer structure including a first inorganic film, an organic film, and a second inorganic film.

[0143] A touch electrode may be provided on the encapsulation layer 195, or a polarizer or a window may be provided.

[0144] Referring to Figure 17 , it can be confirmed that the positions of the openings 181 defined in the organic layer 190 are the same positions in all pixels. However, the positions of the openings 182 defined in the partition wall 194 are repeatedly positioned up and down with respect to the opening 181 of the organic layer 190. This is a structure capable of forming the large-sized openings 182 defined in the partition wall 194. That is to say, the openings 182 of the partition wall 194 can be defined in the upper part of adjacent pixel circuit portions, so that the area occupied by the organic light-emitting layer 192 can be enlarged. Accordingly, the light-emitting area can also be enlarged.

[0145] Each organic light-emitting layer 192 displays one color of primary colors such as red, green, and blue. In an embodiment, the number ratio of the red organic light-emitting elements to the green organic light-emitting elements and the blue organic light-emitting elements may be 1:1:1. Alternatively, the organic light-emitting elements of one color may be provided in a larger number than the organic light-emitting elements of other colors. That is to say, in an embodiment, the number ratio of the red organic light-emitting elements to the green organic light-emitting elements and the blue organic light-emitting elements may be 1:2:1, and the organic light-emitting elements may be arranged in the order of red, green, blue, and green.

[0146] As Figures 3 to 18 shown in, using a semiconductor pattern 150 or the like having a left-right symmetric structure is because two adjacent pixels have one wiring by sharing the first driving voltage line 172 and the vertical initialization voltage line 173, so that a high-resolution display device such as a 4K resolution display device or an 8K resolution display device is formed by reducing the occupied area. In this way, when the wiring is reduced, the openings provided for connecting the wiring and other parts are also reduced, thereby further reducing the occupied area.

[0147] The reduced occupied area portion can be used to increase the overlapping area between the extended portion of the data line 171 and the first electrode 175 for the input capacitor Cpr. As the overlapping area increases, the capacitance of the input capacitor Cpr increases, so that the efficiency of capacitively coupling the data voltage to and transmitting it from the data line 171 to the first electrode 175 for the input capacitor Cpr is improved.

[0148] In the following, a method of forming a lightly doped region when forming an n-type transistor will be described in detail by Figures 19 to 22 .

[0149] First, with reference to Figure 19 and Figure 20 , a method of forming a lightly doped region will be outlined.

[0150] Figure 19 and Figure 20 are cross-sectional views showing embodiments of a method of forming a lightly doped region in an organic light emitting diode display.

[0151] A semiconductor layer and a first gate insulating layer 130 are provided on a substrate 110. Next, a material for forming a first gate conductive layer is deposited, a photoresist is provided, and then the photoresist is exposed to form a photoresist pattern PR. Then, the material for forming the first gate conductive layer is etched along the photoresist pattern PR to form a first gate electrode 124. In this state, as shown in Figure 19 , doping is performed at a high concentration. The semiconductor layer covered by the photoresist pattern PR and the first gate electrode 124 is not doped to become a channel region 151-c, and the semiconductor layer doped at a high concentration is conductive to become a source region 151-s and a drain region 151-d.

[0152] Thereafter, as shown in Figure 20 , the size of the photoresist pattern PR is reduced by ashing, and the first gate electrode 124 is further etched along the reduced photoresist pattern PR'. As a result, the area where the semiconductor layer and the first gate electrode 124 overlap is reduced. Subsequently, when photo-doping is performed, the semiconductor layer in the portion that was previously the channel region 151-c and does not overlap with the first gate electrode 124 becomes a lightly doped region 151-l.

[0153] Here, both the material doped at a high concentration and the material doped at a low concentration are applied to the n-type transistor by an n-type dopant.

[0154] When the lightly doped region is provided in the above-described manner, an additional mask may not be required, thereby reducing the manufacturing cost and processing time.

[0155] This process can be applied to the embodiments of Figures 3 to 18 . By Figure 21 and Figure 22 , the periphery of the opening 161 for side contact is shown.

[0156] Figure 21 is according to Figure 19 and Figure 20 An enlarged plan view of an embodiment of a contact portion in a pixel of an organic light emitting diode display, and Figure 22 is a cross-sectional view taken along line Figure 21 XXII-XXII'.

[0157] In Figure 21 and Figure 22 , the opening 161 is mainly divided into three parts. The first opening 161a is an opening corresponding to the heavily doped region, the second opening 161b is an opening corresponding to the lightly doped region, and the third opening 161c is an opening corresponding to the undoped region.

[0158] In addition, the first gate electrode 124 is reduced in size while being additionally etched, which is indicated by a dashed line. The dashed line portion 124m is used as a mask during high-concentration doping and is then removed. Thereafter, light doping is performed through the first gate electrode 124 in its final form as a mask.

[0159] The connection member 144 of the second gate conductive layer with side contact has a structure that contacts not only the heavily doped semiconductor but also the lightly doped semiconductor. Since the conductive property is improved by doping, there is an advantage that the side contact property is also improved.

[0160] Even when a p-type transistor is provided, a lightly doped region can be provided, but since there are no operational problems, a lightly doped region is generally not provided.

[0161] Hereinafter, with reference to Figure 23 and Figure 24 , the portion where the input capacitor Cpr is provided is described more clearly.

[0162] Figure 23 is a plan view of an embodiment of a partial conductive layer in a portion of a pixel of an organic light emitting diode display where an input capacitor is provided, and Figure 24 is a cross-sectional view taken along line Figure 23 XXIV-XXIV'.

[0163] In Figure 23 , the data line 171 and the first electrode 175 for the input capacitor Cpr are mainly shown as the center, and the overlapping portion of the data line 171 and the first electrode 175 is indicated by a thick line to show the space occupied by the input capacitor Cpr.

[0164] Both the extended portions of the first electrode 175 and the data line 171 for the input capacitor Cpr are designed to be provided within the maximum width so that the efficiency of transmitting the data voltage through coupling is high. For this purpose, only the data line 171 is provided as a separate first data conductive layer to be large enough.

[0165] With reference to Figure 24 Since the first electrode 175 of the input capacitor Cpr is desirably connected to the semiconductor pattern 150 connected through the opening 165, a predetermined gap gap-1 needs to be formed between the extended portion of the data line 171 and the opening 165. In the case where the gap gap-1 is provided narrowly, the first electrode 175 of the input capacitor Cpr and the data line 171 can be short-circuited, so a predetermined gap needs to be formed to be ensured.

[0166] Referring to Figure 25 and Figure 26 more clearly describes the portion where the storage capacitor Cst is provided.

[0167] Figure 25 is a plan view of an embodiment of a partial conductive layer of a portion where a storage capacitor is provided in one pixel of an organic light emitting diode display, and Figure 26 is a cross-sectional view taken along the line Figure 25 XXVI-XXVI'.

[0168] The storage capacitor Cst is provided at a position where the horizontal initialization voltage line 141 overlaps with the first gate electrode 124. In Figure 25 what is shown, the portion where the two portions overlap each other is thick. The horizontal initialization voltage line 141 is connected to the vertical initialization voltage line 173 through the opening 166. Thus, the initialization voltage Vint can have a constant voltage value in each pixel.

[0169] Hereinafter, referring to Figure 27 and Figure 28 describes a deformable embodiment.

[0170] First, referring to Figure 27 describes a structure electrically connected through a contact assisting member.

[0171] Figure 27 is an enlarged cross-sectional view of a contact portion in one pixel of an organic light emitting diode display according to another embodiment.

[0172] Figure 27 shows such a structure: in the structure where the anode electrode connection member 174 is connected to the anode electrode connection semiconductor 150a through the opening 165, the anode electrode connection member 174 and the anode electrode connection semiconductor 150a are connected by providing a contact assisting member 174-1 therebetween.

[0173] The positive electrode connection member 174 is disposed in the second data conductive layer, and the positive electrode connection semiconductor 150a is directly disposed on the substrate 110, resulting in a large vertical distance. Since it may be difficult for the positive electrode connection member 174 to contact the positive electrode connection semiconductor 150a, the positive electrode connection member 174 and the positive electrode connection semiconductor 150a can be connected through one of the first gate conductive layer, the second gate conductive layer, and the first data conductive layer. Figure 27 The structure connected through the contact assist member 174-1 disposed in the first data conductive layer is shown. However, in an embodiment, a contact assist member disposed on the first gate conductive layer or the second gate conductive layer may be used.

[0174] Moreover, in addition to the case where the positive electrode connection member 174 is connected to the positive electrode connection semiconductor 150a through the opening 165, the contact assist member can also be used in the portion connected through another opening.

[0175] Refer to Figure 28 , and describe an embodiment in which the positions of the scan line 142 and the control signal line 143 are changed.

[0176] Figure 28 is a plan view of an embodiment of a pixel of an organic light emitting diode display.

[0177] Figure 28 is corresponding to Figure 7 However, in Figure 28 , the difference is that the scan line 142 is located above and the control signal line 143 is located below. Additionally, in Figure 28 , the second gate electrode 125 is disposed above compared to the third gate electrode 126.

[0178] Even when the vertical positions are changed as described above, the same is that the scan line 142 is electrically connected to the second gate electrode 125 through the opening 162, and the control signal line 143 is electrically connected to the third gate electrode 126 through the opening 163.

[0179] Additionally, from the perspective of the circuit, the circuit diagrams are the same.

[0180] Figure 28 shows that due to the dense provision of wirings, while the node voltages of other pixels are changed due to the signals applied to the scan line 142 and the control signal line 143, the characteristics can be changed such that Figure 7 of the embodiment and Figure 8 of the embodiment can be used according to appropriate circumstances. However, the present invention is not limited thereto, and both embodiments can be used when there is no significant difference.

[0181] The foregoing focuses on the case where all transistors are n-type transistors. However, according to an embodiment, p-type transistors may be used. The difference is that an n-type transistor operates only when the voltage value of the voltage of the gate electrode is greater than or equal to the voltage value of the threshold voltage of the voltage of the first electrode, while a p-type transistor operates only when the voltage value of the voltage of the gate electrode is smaller than the voltage value of the voltage of the first electrode by a threshold voltage value or more. In addition, although a lightly doped region is provided in the n-type transistor, a lightly doped region may not be provided in the p-type transistor. Due to this difference, when a p-type transistor is used, the waveform to be applied changes, which will be described in detail below.

[0182] Hereinafter, with reference to Figure 29 and Figure 30 , a pixel of an organic light emitting diode display using a p-type transistor will be described.

[0183] Figure 29 is an equivalent circuit diagram of a pixel of an organic light emitting diode display according to another embodiment, and Figure 30 is a timing diagram of signals applied to the Figure 29 pixel.

[0184] Comparing Figure 29 with Figure 1 , there is no difference except that all transistors T1, T2, and T3 are p-type transistors. However, comparing Figure 30 with Figure 2 , there are many differences in the signals to be applied. Therefore, hereinafter, with reference to Figure 30 , the operation of the pixel in the case of using a p-type transistor will be described in detail.

[0185] The pixel of the organic light emitting diode display in the embodiment is divided into an initialization period Initial to be operated, a threshold voltage compensation period Vth Comp., a programming period Programming, and an emission period Emission, and an on bias period may also be included between the emission period Emission and the initialization period Initial.

[0186] In the organic light emitting diode OLED that emits light during the emission period Emission, since current does not flow from the anode electrode of the organic light emitting diode OLED to the cathode side while the voltage of the second driving voltage ELVSS applied to the other electrode of the organic light emitting diode OLED becomes a high voltage, the emission period Emission ends.

[0187] Thereafter, the initialization voltage Vint changes from a high voltage to a low voltage and enters the on-bias period. When the voltage of the second electrode of the storage capacitor Cst to which the initialization voltage Vint is applied becomes a low voltage, the voltage of the first electrode of the storage capacitor Cst, i.e., the gate electrode voltage of the driving transistor T1, also decreases. As a result, the output of the driving transistor T1 can temporarily increase. However, since the second driving voltage ELVSS has a high voltage and a forward current does not flow through the organic light-emitting diode OLED, the organic light-emitting diode OLED does not emit light. This on-bias period is a period having the characteristics of the preparation initialization period Initial.

[0188] Thereafter, the initialization period Initial is entered, and the initialization period Initial changes the scan signal GW applied to the scan line 142 and the control signal GC applied to the control signal line 143 to a low voltage and starts while also changing the first driving voltage ELVDD to a low voltage. At this time, the initialization voltage Vint maintains a low voltage in the same manner as in the on-bias period.

[0189] Since the second transistor T2 and the third transistor T3 are p-type transistors, a low voltage applied to the scan line 142 and the control signal line 143 operates as a turn-on voltage, causing the second transistor T2 and the third transistor T3 to turn on. Additionally, as the first driving voltage ELVDD applied to the first electrode of the driving transistor T1 also drops to a low voltage, the voltage of the gate electrode of the driving transistor T1 also decreases. During the on-bias period, as the initialization voltage Vint decreases, the voltage of the gate electrode of the driving transistor T1 has decreased once and additionally has a lower value. In this case, when the voltage of the gate electrode of the driving transistor T1 is the voltage for turning on the driving transistor T1, the charge accumulated in the first electrode of the storage capacitor Cst leaves the first electrode of the driving transistor T1 after passing through the second transistor T2 and the third transistor T3, and finally has a voltage value corresponding to the low voltage value of the first driving voltage ELVDD, while initializing the voltage of the gate electrode of the driving transistor T1, and the driving transistor T1 turns off. In this case, the second electrode (anode) of the driving transistor T1, the first electrode of the storage capacitor Cst, and the first electrode of the input capacitor Cpr are connected to each other and initialized to the same voltage. When the voltage value of the voltage of the gate electrode of the driving transistor T1 is not lower than the voltage value of the low voltage of the first driving voltage ELVDD, the second transistor T2 and the third transistor T3 turn on, causing the second electrode (anode) of the driving transistor T1, the first electrode of the storage capacitor Cst, and the first electrode of the input capacitor Cpr to be connected to each other and initialized to the same voltage. As described above, the same voltage of the second electrode (anode) of the initialized driving transistor T1, the first electrode of the storage capacitor Cst, and the first electrode of the input capacitor Cpr is also referred to as the connection voltage hereinafter.

[0190] At this time, since the low voltage of the first driving voltage ELVDD has a voltage value lower than the voltage value of the high voltage of the second driving voltage ELVSS, a forward current does not flow through the organic light-emitting diode OLED, and the organic light-emitting diode OLED does not emit light.

[0191] Thereafter, the initialization voltage Vint becomes a high voltage, and the initialization period Initial ends. At this time, the voltage of the first electrode of the storage capacitor Cst has a value higher than the connection voltage value, which is the initialization voltage, and the voltage value of the voltage of the gate electrode of the driving transistor T1 is higher than the voltage value of the first electrode, so that the driving transistor T1 maintains the off state.

[0192] Thereafter, while the first driving voltage ELVDD becomes a high voltage, the threshold voltage compensation period VthComp. is executed.

[0193] When the voltage applied to the first electrode of the driving transistor T1 becomes a high voltage, the voltage of the gate electrode of the driving transistor T1 increases, but has a value smaller than the voltage value of the first electrode by the threshold voltage of the driving transistor T1 or more, causing the driving transistor T1 to turn on. At this time, since the third transistor T3 and the second transistor T2 are in the on state, the driving transistor T1 has a diode-connected structure. Due to this connection, the output of the driving transistor T1 is transmitted to the gate electrode of the driving transistor T1, and the voltage of the gate electrode increases. When the gradually increasing voltage of the gate electrode increases to a value smaller than the voltage of the first electrode of the driving transistor T1 (i.e., a value smaller than the high voltage value of the first driving voltage ELVDD by the threshold voltage of the driving transistor T1), the driving transistor T1 turns off. The voltage at this time is stored in the first electrode of the storage capacitor Cst, and when the high voltage value of the first driving voltage ELVDD is referred to as ELVDD_H and the threshold voltage value is referred to as Vth, this voltage has the value ELVDD_H - Vth. Since the second transistor T2 and the third transistor T3 are on, the voltage stored in the first electrode of the storage capacitor Cst is the same as the voltage of the anode and the voltage of the first electrode of the input capacitor Cpr.

[0194] Thereafter, both the scan signal GW applied to the scan line 142 and the control signal GC applied to the control signal line 143 become high voltages, and the second transistor T2 and the third transistor T3 turn off. As a result, the first electrode of the storage capacitor Cst, the anode, and the first electrode of the input capacitor Cpr are electrically separated from each other.

[0195] Thereafter, while the first driving voltage ELVDD is changed to a low voltage, the threshold voltage compensation period Vth Comp. ends. When the first driving voltage ELVDD becomes a low voltage, the voltage of the first electrode of the storage capacitor Cst decreases, but is not low enough to turn on the driving transistor T1.

[0196] In this case, since the second driving voltage ELVSS of the organic light-emitting diode OLED has a high voltage, no current flows to the organic light-emitting diode OLED.

[0197] Thereafter, the programming period Programming starts, and in the programming period Programming, the scan signal GW having a turn-on voltage (low voltage) value is sequentially applied to the scan line 142.

[0198] During the programming cycle, when the second transistor T2 is turned on, the data voltage of the data voltage input terminal is transferred to the first electrode of the storage capacitor Cst and stored therein. In this case, the data voltage of the data voltage input terminal, which is the voltage transferred through the input capacitor Cpr from the data line 171, can have a voltage value lower than the voltage value of the data voltage Vdata applied from the data line 171. This voltage is transferred to the first electrode of the storage capacitor Cst and stored therein. However, since the first driving voltage ELVDD has a low voltage, the driving transistor T1 does not operate.

[0199] Although not shown in Figure 30 the programming cycle of Figure 30 also includes a hold cycle as shown in Figure 2 . For each scan line 142, the hold cycle, which is the cycle before and after the conduction voltage is applied as the scan signal GW, is a different hold cycle. The hold cycle refers to the cycle during which the voltages of the storage capacitor Cst and other terminals are maintained.

[0200] When the data voltage of the data voltage input terminal is stored in the storage capacitor Cst through the first electrode of all pixels while the first driving voltage ELVDD becomes high again and the second driving voltage ELVSS becomes low again, the emission cycle begins.

[0201] In Figure 30 In the embodiment, it also includes the operation of reducing the initialization voltage Vint to a low voltage when entering the light emission cycle Emission and then changing the initialization voltage Vint to a high voltage. This is to eliminate the problem that the organic light-emitting diode OLED can emit light while the driving transistor T1 outputs an output current during the fluctuations of the first driving voltage ELVDD and the second driving voltage ELVSS. That is, after the voltages of the first driving voltage ELVDD and the second driving voltage ELVSS become high voltage and low voltage respectively, the initialization voltage Vint rises to a high voltage, so that the driving transistor T1 outputs a current and determines the timing when the organic light-emitting diode OLED emits light. Thus, unnecessary brightness is not displayed. In addition, the change of the initialization voltage Vint can be used to set the black voltage of the organic light-emitting diode OLED. That is, during the period when the first driving voltage ELVDD and the second driving voltage ELVSS fluctuate, the driving transistor T1 can generate an output current, but the current value of the output current is basically very small, so that the anode voltage increases accordingly, and therefore, there may be a problem of affecting the anode voltage during the actual light emission cycle. To eliminate this problem and prevent the anode voltage from being affected, the initialization voltage Vint can also be changed when entering the light emission cycle Emission.

[0202] In the embodiment, when entering the light emission cycle Emission, the change of the initialization voltage Vint may not be included.

[0203] In the light emission cycle Emission, all pixels emit light simultaneously for the same duration. However, in the embodiment, some pixels can emit light.

[0204] Different from Figure 2 , in Figure 30 the detailed description of the voltage is omitted, but Figure 30 the description of Figure 2 has the same characteristics as the analysis of

[0205] That is, in the threshold voltage compensation cycle Vth Comp., even when each driving transistor T1 has a different threshold voltage, by compensating the threshold voltage value of the driving transistor T1 stored in the first electrode of the storage capacitor Cst, the output current value is determined only according to the data voltage Vdata. Thus, the same brightness is emitted for the same data voltage, so that the display quality does not deteriorate.

[0206] In addition, the values a, b, and c used in the formula of Figure 2 can also be applied to Figure 30 , but when designing the pixels, since the value is determined based on the overlapping regions or intervals, the value can be made to cancel out and be ignored by designing the pixels.

[0207] Although the present disclosure has been described in connection with what are presently considered to be practical embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements.< / n>

Claims

1. An organic light emitting diode display, wherein, The organic light emitting diode display includes: a substrate; a semiconductor pattern disposed on the substrate; a first conductive layer disposed on the semiconductor pattern and including a first gate electrode having an island structure, a second gate electrode having an island structure, and a third gate electrode having an island structure; and a second conductive layer disposed on the first conductive layer and including a first initialization voltage line overlapping with the first gate electrode, a scan line overlapping with the second gate electrode, and a control signal line overlapping with the third gate electrode, wherein the control signal line is electrically connected to the third gate electrode, the scan line is electrically connected to the second gate electrode, and the first initialization voltage line, the scan line, and the control signal line extend in a first direction.

2. The organic light emitting diode display according to claim 1, wherein, The organic light emitting diode display further includes: a third conductive layer disposed on the second conductive layer and including a data line extending in a second direction intersecting the first direction; and a fourth conductive layer disposed on the third conductive layer and including a first driving voltage line and a second initialization voltage line extending in the second direction.

3. The organic light emitting diode display according to claim 2, wherein, the second conductive layer further includes a connection member, the semiconductor pattern includes a storage capacitor connection semiconductor, the connection member electrically connects the storage capacitor connection semiconductor of the semiconductor pattern to the first gate electrode, the semiconductor pattern further includes a lightly doped region, a heavily doped region, and an undoped region, and the connection member contacts the lightly doped region and the heavily doped region of the semiconductor pattern.

4. The organic light emitting diode display according to claim 2, wherein, the fourth conductive layer further includes a first electrode for an input capacitor, the data line includes an extended portion, the first electrode for the input capacitor overlaps with the extended portion of the data line to form the input capacitor, the semiconductor pattern further includes a data voltage input semiconductor, and the first electrode for the input capacitor is connected to the data voltage input semiconductor of the semiconductor pattern.

5. The organic light emitting diode display according to claim 2, wherein, the fourth conductive layer further includes an anode connection member, the semiconductor pattern includes an anode connection semiconductor; and the anode connection member is electrically connected to the anode connection semiconductor and the anode of the semiconductor pattern.

6. The organic light emitting diode display according to claim 2, wherein, the first initialization voltage line and the second initialization voltage line are electrically connected to each other, and the first gate electrode and the first initialization voltage line overlap to form a storage capacitor.

7. The organic light emitting diode display according to claim 1, wherein, the semiconductor pattern includes a heavily doped region not overlapping with the first conductive layer and an undoped region overlapping with the first conductive layer.

8. The organic light emitting diode display according to claim 2, wherein, the semiconductor pattern has a symmetric structure with respect to the second direction, and a unit semiconductor pattern corresponds to two pixels, The unit semiconductor pattern has a first driving voltage input semiconductor, The first driving voltage input semiconductor is connected to the first driving voltage line, and The first driving voltage line has a structure that shares two adjacent pixel columns.

9. An organic light emitting diode display, wherein, The organic light-emitting diode display includes: An organic light-emitting element; A first transistor that supplies current to the organic light-emitting element; A storage capacitor connected to the gate electrode of the first transistor; A second transistor and a third transistor that connect the organic light-emitting element and the gate electrode of the first transistor, the gate electrode of the second transistor receives a scan signal, and the gate electrode of the third transistor receives a control signal; A data line including an extended portion; An input capacitor that transfers a data voltage from the data line between the second transistor and the third transistor; and A first electrode for the input capacitor, wherein the input capacitor is provided by the extended portion of the data line as the first input capacitor electrode and the first electrode for the input capacitor as the second input capacitor electrode, and the first electrode is provided on the extended portion of the data line and overlaps with the extended portion of the data line.

10. The organic light emitting diode display according to claim 9, wherein, The organic light-emitting diode display further includes: A storage capacitor provided by the gate electrode of the first transistor as a first storage capacitor electrode, and a first initialization voltage line to which an initialization voltage is applied as a second storage capacitor electrode.

11. The organic light-emitting diode display according to claim 10, wherein, A first electrode of the first transistor receives a first driving voltage, and A cathode of the organic light-emitting element receives a second driving voltage.

12. The organic light-emitting diode display according to claim 11, wherein, An initialization period, a threshold voltage compensation period, a programming period, and a light emission period are included, and The second transistor and the third transistor are turned on during the initialization period and the threshold voltage compensation period.

13. The organic light-emitting diode display according to claim 12, wherein, The first driving voltage includes a high voltage having a high voltage value, a first low voltage having a first low voltage value, and a second low voltage having a second low voltage value lower than the first low voltage value, During the initialization period, the first low voltage is applied as the first driving voltage, During the threshold voltage compensation period, the second low voltage is applied as the first driving voltage, and During the programming period and the light emission period, the high voltage is applied as the first driving voltage.

14. The organic light-emitting diode display according to claim 13, wherein, The initialization voltage includes a low voltage and a high voltage, and The initialization voltage changes from the low voltage to the high voltage and starts during the light emission period.

15. The organic light-emitting diode display according to claim 14, wherein, During the threshold voltage compensation period, the low voltage is applied as the initialization voltage.

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