Semiconductor device and method for manufacturing semiconductor device

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method of a semiconductor device. A first gate insulating film is an insulating film made of silicon oxide and to which hafnium (Hf) is added without aluminum (Al). Also, a second gate insulating film is an insulating film made of silicon oxide and to which aluminum is added without hafnium. A third gate insulating film is an insulating film made of silicon oxide and to which aluminum is added. Further, a fourth gate insulating film is an insulating film made of silicon oxide and to which hafnium is added. Thus, power consumption of the semiconductor device can be reduced.

Description

[0001] Cross-reference to related applications

[0002] The disclosure of Japanese Patent Application No. 2019-186897, filed on October 10, 2019, includes a specification, drawings and an abstract, the entire contents of which are incorporated herein by reference. Background Technology

[0003] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and the invention can be suitably used in semiconductor devices and, for example, in methods for manufacturing semiconductor devices using SOI substrates.

[0004] The disclosed technologies are listed below:

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2013-219181

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2016-18936

[0007] [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2019-62170

[0008] As a semiconductor device using an SOI substrate, the SOI substrate has a semiconductor substrate (semiconductor base material), a BOX film (insulating layer) formed on the semiconductor substrate, and a silicon layer (SOI layer, semiconductor layer) formed on the BOX film. For example, as shown in Patent Document 1, there is a semiconductor device with a so-called hybrid structure, which includes an n-channel (or p-channel) field-effect transistor formed in the SOI region of the SOI substrate (which is the region with the BOX film and the silicon layer), and an n-channel (or p-channel) field-effect transistor formed in the bulk silicon region of the SOI substrate (which is the region without the BOX film and the silicon layer).

[0009] As shown in Patent Document 2, as a semiconductor device using an SOI substrate, there exists a semiconductor device comprising an n-channel field-effect transistor having a gate insulating film and a p-channel field-effect transistor having a gate insulating film. Furthermore, hafnium (Hf) is added to each gate insulating film, with a hafnium concentration of 1 × 10⁻⁶ per unit area on the surface of the gate insulating film. 13 cm 2 Or even higher. In this case, the work function of the gate electrode of each of the n-channel and p-channel field-effect transistors can be made smaller. That is, the threshold voltage of the n-channel field-effect transistor can be reduced, while the threshold voltage of the p-channel field-effect transistor can be increased.

[0010] Furthermore, as shown in the first embodiment of Patent Document 3, as a measure to address the NBTI (negative temperature instability) in a p-channel field-effect transistor due to BTI (biased temperature instability) where the threshold voltage of the field-effect transistor is altered, there exists a semiconductor device using an SOI substrate, wherein the ratio of the number of hafnium atoms in the gate insulating film of each of the n-channel and p-channel field-effect transistors to the total number of aluminum and hafnium atoms is 75% or greater and less than 100%. Moreover, as shown in the second embodiment of Patent Document 3, as a semiconductor device using an SOI substrate, there exists a semiconductor device comprising: an n-channel field-effect transistor having a gate insulating film with added aluminum (Al) but not hafnium (Hf); and a p-channel field-effect transistor having a gate insulating film with added hafnium (Hf) but not aluminum (Al). In this case, the reduction in the threshold voltage of the p-channel field-effect transistor due to aluminum (Al) can be suppressed. Summary of the Invention

[0011] As shown in Patent Document 2 or Patent Document 3, it is preferable to add a metal such as aluminum (Al) or hafnium (Hf) to the gate insulating film constituting the field-effect transistor in order to adjust the threshold voltage of the field-effect transistor. Furthermore, the occurrence of gate leakage current can be suppressed by employing a so-called high-dielectric-constant insulating film, which is a gate insulating film to which a metal such as aluminum (Al) or hafnium (Hf) has been added. That is, by employing a high-dielectric-constant insulating film, the capacitance of the gate insulating film can be increased without reducing its physical thickness.

[0012] On the other hand, in recent years there has been a need to further reduce the power consumption of semiconductor devices and / or improve their operating speed. In order to operate field-effect transistors at high speed, that is, to increase the ON current flowing through the channel region of the field-effect transistor, although the voltage applied to the field-effect transistor (drive voltage) is reduced, it is conceivable that the threshold voltage of the field-effect transistor is lower.

[0013] Therefore, the inventors have studied how to adjust the type and number (ratio, concentration) of the metals constituting the aforementioned high-dielectric-constant insulating film to achieve a lower threshold voltage in the field-effect transistor. Consequently, it has been found that it is difficult to produce semiconductor devices with desired characteristics based solely on the type or number of metals.

[0014] Other objects and novel features will become clear from the description in this specification and the accompanying drawings.

[0015] Typical embodiments disclosed in this application will be briefly described below.

[0016] A semiconductor device according to one embodiment includes: a first gate electrode of an n-type first field-effect transistor; a second gate electrode of a p-type second field-effect transistor; a third gate electrode of an n-type third field-effect transistor; and a fourth gate electrode of a p-type fourth field-effect transistor. Here, the first gate electrode is formed on a semiconductor layer located in a first region via a first gate insulating film. Furthermore, a second gate electrode is formed on a semiconductor layer located in a second region via a second gate insulating film. Furthermore, a third gate electrode is formed on a semiconductor substrate material located in a third region via a third gate insulating film. Further, a fourth gate insulating film is formed on a semiconductor substrate material located in a fourth region via a fourth gate insulating film. Here, the first gate insulating film is an insulating film made of silicon oxide with hafnium added but no aluminum added. Furthermore, the second gate insulating film is an insulating film made of silicon oxide with aluminum added but no hafnium added. Furthermore, the third gate insulating film is an insulating film made of silicon oxide with aluminum added. Further, the fourth gate insulating film is an insulating film made of silicon oxide with hafnium added.

[0017] Furthermore, a method for manufacturing a semiconductor device according to one embodiment includes: forming a first insulating film made of silicon oxide on a semiconductor layer in each of a first region and a second region, and forming a second insulating film made of silicon oxide on a semiconductor substrate material in each of a third region and a fourth region. The method further includes: adding aluminum to each of the first insulating film in the second region and the second insulating film in the third region while the semiconductor layer in the first region is covered by a first mask. The method also includes: adding hafnium to each of the first insulating film in the first region and the second insulating film in the fourth region while the semiconductor layer in the second region is covered by a second mask. Further, the method includes: forming a first gate electrode of an n-type first field-effect transistor on a semiconductor layer located in a first region via a first gate insulating film; forming a second gate electrode of a p-type second field-effect transistor on a semiconductor layer located in a second region via a second gate insulating film; forming a third gate electrode of an n-type third field-effect transistor on a semiconductor substrate material located in a third region via a third gate insulating film; and forming a fourth gate electrode of a p-type fourth field-effect transistor on a semiconductor substrate material located in a fourth region via a fourth gate insulating film. Here, the first gate insulating film is a first insulating film located in the first region with hafnium added but no aluminum added. Furthermore, the second gate insulating film is a first insulating film located in the second region with aluminum added but no hafnium added. Furthermore, the third gate insulating film is a second insulating film located in the third region with aluminum added. Further, the fourth gate insulating film is a second insulating film located in the fourth region with hafnium added.

[0018] Furthermore, a method for manufacturing a semiconductor device according to another embodiment includes: forming a first insulating film made of silicon oxide on a semiconductor layer in each of a first region and a second region, and forming a second insulating film made of silicon oxide on a semiconductor substrate material in each of a third region and a fourth region. The method further includes: adding aluminum and hafnium to each of the first insulating film in each of the first and second regions, and the second insulating film in each of the third and fourth regions. The method also includes: forming a first semiconductor material on each of the semiconductor layer in each of the first and second regions, and the semiconductor substrate material in each of the third and fourth regions, such that the first insulating film in each of the first and second regions, and the second insulating film in each of the third and fourth regions, are covered by the first semiconductor material. The method further includes: removing the first semiconductor material in the second region and the first insulating film in the second region to which aluminum and hafnium have been added, such that the first semiconductor material in each of the first, third, and fourth regions is retained. Finally, the method includes: forming a third insulating film made of aluminum oxide on the semiconductor layer in the second region. Furthermore, the method includes: adding aluminum to a third insulating film located in the second region. Furthermore, the method includes: forming a second semiconductor material on the third insulating film located in the second region to which aluminum has been added. Furthermore, the method includes: removing the first semiconductor material located in the first region and the first insulating film located in the first region to which both aluminum and hafnium have been added, such that the second semiconductor material located in the second region and the first semiconductor material located in each of the third and fourth regions are retained. Furthermore, the method includes: forming a fourth insulating film made of aluminum oxide on the semiconductor layer located in the first region. Furthermore, the method includes: adding hafnium to the fourth insulating film located in the first region. Furthermore, the method includes: forming a third semiconductor material on the fourth insulating film located in the first region to which hafnium has been added. Further, the method includes: patterning each of the first, second, and third semiconductor materials; forming a first gate electrode of an n-type first field-effect transistor on a semiconductor layer in the first region via a fourth insulating film located in the first region and to which hafnium is added; forming a second gate electrode of a p-type second field-effect transistor on a semiconductor layer in the second region via a third insulating film located in the first region and to which aluminum is added; forming a third gate electrode of an n-type third field-effect transistor on a semiconductor substrate material in the third region via a second insulating film located in the third region and to which both aluminum and hafnium are added; and forming a fourth gate electrode of a p-type fourth field-effect transistor on a semiconductor substrate material in the fourth region via a second insulating film located in the fourth region and to which both aluminum and hafnium are added.

[0019] According to the semiconductor device in one embodiment, the power consumption of the semiconductor device can be reduced.

[0020] Moreover, the method for manufacturing a semiconductor device according to one embodiment can increase the manufacturing yield of semiconductor devices.

[0021] Furthermore, the method for manufacturing a semiconductor device according to another embodiment can improve the reliability of the semiconductor device. Attached Figure Description

[0022] Figure 1 This is a cross-sectional view of a semiconductor device according to one embodiment.

[0023] Figure 2 This is a circuit diagram showing the memory cells that make up an SRAM circuit.

[0024] Figure 3 This is a graph showing the relationship between the amount of aluminum added and the threshold voltage of an n-type field-effect transistor.

[0025] Figure 4 This is a graph showing the relationship between the amount of hafnium added and the threshold voltage of a p-type field-effect transistor.

[0026] Figure 5 This is a process flow diagram illustrating the manufacturing process of a semiconductor device according to one embodiment.

[0027] Figure 6 This is a cross-sectional view of a semiconductor device during the manufacturing process according to one embodiment.

[0028] Figure 7 yes Figure 6 A cross-sectional view of the semiconductor device during the manufacturing process.

[0029] Figure 8 yes Figure 7 A cross-sectional view of the semiconductor device during the manufacturing process.

[0030] Figure 9 yes Figure 8 A cross-sectional view of the semiconductor device during the manufacturing process.

[0031] Figure 10 yes Figure 9 A cross-sectional view of the semiconductor device during the manufacturing process.

[0032] Figure 11 yes Figure 10 A cross-sectional view of the semiconductor device during the manufacturing process.

[0033] Figure 12 yes Figure 11A cross-sectional view of the semiconductor device during the manufacturing process.

[0034] Figure 13 yes Figure 12 A cross-sectional view of the semiconductor device during the manufacturing process.

[0035] Figure 14 yes Figure 13 A cross-sectional view of the semiconductor device during the manufacturing process.

[0036] Figure 15 yes Figure 14 A cross-sectional view of the semiconductor device during the manufacturing process.

[0037] Figure 16 It is a cross-sectional view of a semiconductor device based on the first modified example.

[0038] Figure 17 It is a process flow diagram of the manufacturing process of a semiconductor device according to the second modified example.

[0039] Figure 18 It is a cross-sectional view of a semiconductor device during the manufacturing process according to the second modified example.

[0040] Figure 19 yes Figure 18 A cross-sectional view of the semiconductor device during the manufacturing process.

[0041] Figure 20 yes Figure 19 A cross-sectional view of the semiconductor device during the manufacturing process.

[0042] Figure 21 yes Figure 20 A cross-sectional view of the semiconductor device during the manufacturing process.

[0043] Figure 22 yes Figure 21 A cross-sectional view of the semiconductor device during the manufacturing process.

[0044] Figure 23 yes Figure 22 A cross-sectional view of the semiconductor device during the manufacturing process.

[0045] Figure 24 yes Figure 23 A cross-sectional view of the semiconductor device during the manufacturing process.

[0046] Figure 25 yes Figure 24 A cross-sectional view of the semiconductor device during the manufacturing process.

[0047] Figure 26 yes Figure 25A cross-sectional view of the semiconductor device during the manufacturing process.

[0048] Figure 27 yes Figure 26 A cross-sectional view of the semiconductor device during the manufacturing process.

[0049] Figure 28 yes Figure 27 A cross-sectional view of the semiconductor device during the manufacturing process.

[0050] Figure 29 It is a cross-sectional view of a semiconductor device based on a further modified example of the second modified example.

[0051] Figure 30 It is a cross-sectional view of a semiconductor device based on the third modified example. Detailed Implementation

[0052] In the following embodiments, for convenience, the embodiments are described by dividing them into multiple parts or embodiments when necessary. However, except where explicitly stated, they are not independent of each other, and one may involve examples, details, supplementary descriptions, etc., of modifications to part or all of the other. In the following embodiments, the number of elements (number of elements, numerical values, quantities, ranges, etc.) is not limited to specific numbers, but may be not less than or equal to specific numbers, except where numbers are explicitly indicated and are explicitly limited to specific numbers in principle. Furthermore, it goes without saying that in the following embodiments, elements that are components (including element steps, etc.) are not necessarily necessary unless they are explicitly specified or are considered obviously necessary in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, it is assumed that the shape, etc., is substantially close to or similar to the shape, unless they are explicitly specified or are considered obvious in principle. The same applies to the numerical values ​​and ranges above.

[0053] The following embodiments will be described in detail based on the accompanying drawings. In all the drawings used to illustrate the embodiments, components with the same function are indicated by the same reference numerals and fill lines, and repetitive descriptions of them are omitted. In the following embodiments, descriptions of identical or similar parts will not be repeated in principle unless specifically necessary.

[0054] In the accompanying drawings used in the embodiments, even in the case of cross-sectional views, fill lines may be omitted to make the drawings easier to read. Furthermore, even in the case of plan views, fill lines may be used to make the drawings easier to read.

[0055] <Example>

[0056] The semiconductor device SMD1 and its manufacturing method in this embodiment will be described. Figure 1 This is a cross-sectional view of the semiconductor device SMD1 in this embodiment. Figure 2 This is a circuit diagram showing the memory cells that make up an SRAM (Static Random Access Memory) circuit. Further, Figure 3 This is a graph showing the relationship between the amount of aluminum (Al) added to the gate insulating film and the threshold voltage of the n-type field-effect transistor. Further, Figure 4 This is a diagram showing the relationship between the amount of hafnium (Hf) to be added to the gate insulating film and the threshold voltage of the p-type field-effect transistor.

[0057] <Semiconductor device SMD1 in this embodiment>

[0058] like Figure 1 As shown, the semiconductor device SMD1 in this embodiment includes a so-called hybrid structure: an SOI region 1SR and a bulk region 2BR. As... Figure 1 As shown, SOI region 1SR has region 1An, region 1SRn, region 1Ap, and region 1SRp. An n-channel (hereinafter referred to as n-type) field-effect transistor Q1n is formed in region 1An; region 1TAn is provided in region 1SRn for providing a back gate voltage to the n-type field-effect transistor Q1n (i.e., the n-type field-effect transistor); a p-channel (hereinafter referred to as p-type) field-effect transistor Q1p is formed in region 1Ap; and region 1TAp is provided in region 1SRp for providing a back gate voltage to the p-type field-effect transistor Q1p (i.e., the p-type field-effect transistor). On the other hand, as... Figure 1 As shown, the block region 2BR has region 2BRn and region 2BRp. An n-type field-effect transistor Q2n is formed in region 2BRn, and a p-type field-effect transistor Q2p is formed in region 2BRp. Figure 1 As shown, an isolation portion STI, for example made of silicon oxide, is formed between region 1An, which forms the n-type field-effect transistor Q1n, and region 1TAn, which provides the back gate voltage to the n-type field-effect transistor Q1n. That is, these two regions 1An and 1Tan are separated from each other by the element isolation portion STI. Figure 1 As shown, a device isolation section (STI) is also formed between region 1Ap, which forms the p-type field-effect transistor Q1p, and region 1TAp, which provides the back gate voltage to the p-type field-effect transistor Q1p. That is, regions 1An, 1TAn, 1Ap, 1TAp, 2BRn (2An), and 2BPp (2Ap) are divided and formed by the device isolation section (STI).

[0059] Each field-effect transistor Q1n and Q1p formed in the SOI region 1SR of the semiconductor device SMD1 is a memory cell MC that makes up the SRAM circuit (see Figure 2 ) field effect transistors, for example, the driving voltage of the SRAM circuit is 0.5V to 1.8V. On the other hand, each of the field effect transistors Q2n and Q2p formed in the bulk region 2BR is a field effect transistor constituting a peripheral circuit (not shown), such as an input / output circuit, and the driving voltage of the input / output circuit is, for example, 2.5V to 3.3V. In the present embodiment, each of the field effect transistors Q1n and Q1p is applied to the corresponding transistors constituting the memory cell MC of the SRAM circuit, but each of the field effect transistors Q1n and Q1p can be applied to the transistors constituting another circuit, for example, such as a word line driver circuit, which is connected to the word line of a DRAM (Dynamic Random Access Memory) circuit.

[0060] <SRAM circuit>

[0061] Here, reference will be made to Figure 2 to describe the memory cell MC of the SRAM circuit. As Figure 2 shown, the memory cell M constituting the SRAM circuit is provided at the intersection of the bit line pair BL, / BL and the word line WL. Further, as Figure 2 shown, the memory cell MC has a load transistor pair (load MISFET) Lo1, Lo2, an access transistor pair (transfer MISFET) Acc1, Acc2, and a driver transistor pair (drive MISFET) Dr1, Dr2. Here, each of the load transistors Lo1, Lo2 is a p-type field effect transistor, and each of the access transistors Acc1, Acc2 and the driver transistors Dr1, Dr2 is an n-type field effect transistor. In the present embodiment, the n-type field effect transistor Q1n formed in the region 1SRn is, for example, Figure 2 the driver transistors Dr1, Dr2 of the memory cell MC shown, and the p-type field effect transistor Q1p formed in the region 1SRp is, for example, Figure 2 the load transistors Lo1, Lo2 (or the access transistors Acc1, Acc2) of the memory cell MC shown.

[0062] In addition, among the six transistors constituting the memory cell MC, the load transistor Lo1 and the driver transistor Dr1 constitute one of the CMOS inverter pairs shown as Figure 2 shown. In addition, among the six transistors constituting the memory cell MC, the load transistor Lo2 and the driver transistor Dr2 constitute the other of the CMOS inverter pairs shown as Figure 2 shown. The nodes N1 and N2 that alternately serve as the input and output terminals of the CMOS inverter pair are cross-coupled. That is, as Figure 2As shown, the gate electrode of each of the load transistor Lo1 connected between the supply voltage Vdd and node N1, and the driver transistor Dr1 connected between node N1 and the reference voltage Vss, is electrically connected to node N2. Further, as... Figure 2 As shown, the gate electrode of each of the load transistor Lo2 connected between the supply voltage Vdd and node N2, and the driver transistor Dr2 connected between node N2 and the reference voltage Vss, is electrically connected to node N1. In other words, the cross-coupled CMOS inverter pair described above constitutes a trigger circuit as an information storage cell storing 1 bit of information. Furthermore, as... Figure 2 As shown, access transistor Acc1 is connected between bit line BL and node N1, and access transistor Acc2 is connected between bit line / BL and node N2. Therefore, as Figure 2 As shown, the gate electrode of each of the access transistors Acc1 and Acc2 is connected to the word line WL.

[0063] Next, the field-effect transistors formed in regions 1An, 1TAn, 1Ap, 1TAp, 2BRn (2An), and 2BPp (2Ap) will be described in detail. First, the n-type field-effect transistor Q1n formed in region 1SRn of SOI region 1SR will be described. Furthermore, in the field-effect transistor configurations described subsequently, the descriptions of configurations identical to those described above will be omitted.

[0064] <Field-effect transistor Q1n in this embodiment>

[0065] like Figure 1 As shown, the n-type field-effect transistor Q1n formed in the SOI region 1SR has a semiconductor substrate material BM located in region 1An, an insulating layer BX formed on the semiconductor substrate material BM located in region 1An, a semiconductor layer SL formed on the insulating layer BX located in region 1An, and a gate electrode GE1 formed on the semiconductor layer SL located in region 1An via a gate insulating film GI1. Here, the semiconductor substrate material BM is made of, for example, p-type single-crystal silicon having a resistivity of 1 Ωcm to 15 Ωcm. Further, the semiconductor layer SL is made of, for example, single-crystal silicon. Moreover, the gate electrode GE1 is made of, for example, polycrystalline silicon (especially doped polycrystalline silicon in which impurities or atoms are introduced). The thickness of the semiconductor layer SL located in region 1An is 10 nm to 20 nm. In addition, the thickness of the insulating layer BX located in region 1An is 10 nm to 20 nm. On the other hand, the details of the gate insulating film GI1 will be described later.

[0066] Furthermore, such as Figure 1As shown, the semiconductor substrate material BM is located in region 1SRn to contact the lower surface BXS2 of the insulating layer material BX located in region 1SRn, thereby forming a p-type well region PW. Next, the p-type well region PW contacts the lower surface BXS2 of the insulating layer material BX located in region 1SRn, thereby forming a p-type ground plane region GP1. The p-type ground plane region GP1 serves as the back gate BGE1 of the n-type field-effect transistor Q1n formed in region 1An. Furthermore, the impurity concentration constituting the ground plane region GP1 is higher than the impurity concentration constituting the well region PW.

[0067] like Figure 1 As shown, a sidewall spacer layer SW is formed on the sidewall of the gate electrode GE1 of the n-type field-effect transistor Q1n formed in region 1An. Figure 1 As shown, the sidewall spacer layer SW consists of an offset spacer layer IF3 formed on the sidewall of the gate electrode GE1, and an insulating film IF4 formed on the sidewall of the gate electrode GE1 through the offset spacer layer IF3. Here, the offset spacer layer IF3 is, for example, an insulating film made of silicon oxide. The insulating film IF4 is, for example, an insulating film made of silicon nitride. Further, as... Figure 1 As shown, an epitaxial growth layer EP is formed on the surface of the semiconductor layer SL located in region 1An, exposed from the gate electrode GE1 and the offset spacer layer IF3. This epitaxial growth layer EP is obtained by performing an epitaxial growth process on the surface of the semiconductor layer SL exposed from the gate electrode GE1 and the offset spacer layer IF3. Next, as... Figure 1 A portion of the epitaxial growth layer EP shown is covered by the insulating film IF4 that makes up the sidewall spacer layer SW.

[0068] Furthermore, such as Figure 1 As shown, an extended region EX1 is formed in the region overlapping with the offset spacer layer IF3 of the semiconductor layer SL formed in region 1An. Specifically, as Figure 1 As shown, the extended region EX1 is self-aligned with respect to the gate electrode GE1. Incidentally, the extended region EX1 is made of impurities of a certain concentration and conductivity type. Since the field-effect transistor Q1n formed in region 1An is an n-type field-effect transistor, the impurities constituting the extended region EX1 are n-type. The extended region EX1 is formed under the following implantation conditions: the implantation energy of the aforementioned impurities is, for example, 5 keV to 25 keV, and the dose of the aforementioned impurities is, for example, approximately 1 × 10⁻⁶. 14 cm -2 .

[0069] Furthermore, such as Figure 1As shown, an epitaxial growth layer EP and a diffusion layer SD1 are formed in the region overlapping with the epitaxial growth layer EP formed in the semiconductor layer SL in region 1An (i.e., the region not overlapping with the offset spacer layer IF3). Note that the polarity of the impurities constituting the diffusion layer SD1 is the same as the polarity of the impurities constituting the extension region EX1. That is, the impurities constituting the diffusion layer SD1 are n-type. Compared with the concentration of impurities constituting the extension region EX1, the diffusion layer SD1 is made of impurities with a higher concentration of conductivity type. Specifically, the diffusion region SD1 is formed under the following implantation conditions: the implantation energy of the aforementioned impurities is, for example, 5keV to 25keV, and the dose of the aforementioned impurities is, for example, approximately 1×10⁻⁶. 15 cm -2 The semiconductor region SDR1 that forms the source / drain of the n-type field-effect transistor Q1n includes the extended region EX1 and the diffusion region SD1 described above, and the n-type field-effect transistor Q1n is formed in region 1An.

[0070] like Figure 1 As shown, a p-type well region PW is also formed in region 1TAn to provide the back gate voltage Vbg2 to the n-type field-effect transistor Q1n formed in region 1An. That is, the p-type well region PW is formed in region 1SRn, which includes two regions, 1An and 1TAn. Figure 1 As shown, the p-type ground plane region GP1 is also formed in the p-type well region PW located in region 1TAn. Incidentally, as... Figure 1 As shown, the unformed region 1TAn, semiconductor layer SL, and insulating layer BX are present. On the other hand, as... Figure 1 As shown, the epitaxial growth layer EP is also formed on the surface of the semiconductor substrate material BM located in region 1TAn and exposed from the device isolation portion STI. Next, the epitaxial growth layer EP is formed on region 1TAn, thereby forming the diffusion layer SD2. The polarity of the impurities constituting this diffusion layer SD2 is different from the polarity of the impurities constituting the diffusion layer SD1 described above. That is, the impurities constituting this diffusion layer SD2 are p-type. The diffusion layer SD2 is a region formed under the following implantation conditions: the implantation energy of the impurities mentioned above is, for example, 2keV to 25keV, and the dose of the impurities mentioned above is, for example, approximately 1 × 10⁻⁶. 15 cm -2 .

[0071] <Field-effect transistor Q1p in this embodiment>

[0072] Next, the p-type field-effect transistor Q1p formed in region 1SRp of SOI region 1SR will be described.

[0073] like Figure 1As shown, similar to the n-type field-effect transistor Q1n formed in region 1An, the p-type field-effect transistor Q1p formed in region 1SR of SOI has a semiconductor substrate material in region 1Ap, an insulating layer BX formed on the semiconductor substrate material BM in region 1Ap, a semiconductor layer SL formed on the insulating layer BX in region 1Ap, and a gate electrode GE2 formed on the semiconductor layer SL in region 1Ap via a gate insulating film GI2. The semiconductor substrate material BM, insulating layer BX, semiconductor layer SL, and gate electrode GE2 constituting the p-type field-effect transistor Q1p formed in region 1Ap are made of the same material as the semiconductor substrate material BM, insulating layer BX, semiconductor layer SL, and gate electrode GE1 constituting the n-type field-effect transistor Q1n formed in region 1An. The insulating layer BX and semiconductor layer SL constituting the p-type field-effect transistor Q1p formed in region 1Ap have the same thickness as the insulating layer BX and semiconductor layer SL constituting the n-type field-effect transistor Q1n formed in region 1An. On the other hand, the gate insulating film GI2 will be described in detail later.

[0074] Furthermore, such as Figure 1 As shown, the semiconductor substrate material BM is located in region 1SRp to contact the lower surface BXS2 of the insulating layer material BX located in region 1SRp, thereby forming an n-type well region NW. Next, the n-type well region NW contacts the lower surface BXS2 of the insulating layer material BX located in region 1SRp, thereby forming an n-type ground plane region GP2. The n-type ground plane region GP2 serves as the back gate BGE2 of the p-type field-effect transistor Q1p formed in region 1Ap. Furthermore, the impurity concentration constituting the ground plane region GP2 is higher than the impurity concentration constituting the well region NW.

[0075] like Figure 1 As shown, similar to the n-type field-effect transistor Q1n formed in region 1An, a sidewall spacer layer SW is formed on the sidewall of the gate electrode GE2 of the p-type field-effect transistor Q1p formed in region 1Ap. Figure 1 As shown, the sidewall spacer layer SW consists of an offset spacer layer IF3 formed on the sidewall of the gate electrode GE2, and an insulating film IF4 formed on the sidewall of the gate electrode GE2 through the offset spacer layer IF3. Note that the offset spacer layer IF3 and the insulating film IF4, which respectively constitute the p-type field-effect transistor Q1p formed in region 1Ap, are made of the same material as the offset spacer layer IF3 and the insulating film IF4, which respectively constitute the n-type field-effect transistor Q1n formed in region 1An. Further, as Figure 1As shown, an epitaxial growth layer EP is formed on the surface of the semiconductor layer SL located in region 1Ap that exposes the gate electrode GE2 and the offset spacer layer IF3. The epitaxial growth layer EP is obtained by performing an epitaxial growth process on the surface of the semiconductor layer SL that exposes the gate electrode GE2 and the offset spacer layer IF3. Next, as... Figure 1 A portion of the epitaxial growth layer EP shown is covered by the insulating film IF4 that makes up the sidewall spacer layer SW.

[0076] Furthermore, such as Figure 1 As shown, an extended region EX2 is formed in the region overlapping with the offset spacing layer IF3 of the semiconductor layer SL formed in region 1Ap. Specifically, as Figure 1 As shown, the extended region EX2 is self-aligned with respect to the gate electrode GE2. Incidentally, the extended region EX2 is made of impurities with a certain concentration of conductivity type. Since the field-effect transistor Q1p formed in region 1Ap is a p-type field-effect transistor, the impurities constituting the extended region EX2 are p-type. The extended region EX2 is formed under the following implantation conditions: the implantation energy of the aforementioned impurities is, for example, 5keV to 25keV, and the dose of the aforementioned impurities is, for example, approximately 1 × 10⁻⁶. 14 cm -2 .

[0077] Furthermore, such as Figure 1 As shown, in the region overlapping with the epitaxial growth layer EP formed in region 1Ap (i.e., the region not overlapping with the offset spacer layer IF3), the epitaxial growth layer EP and the diffusion layer SD2 are formed. Note that the polarity of the impurities constituting the diffusion layer SD2 is the same as that of the impurities constituting the extension region EX2. That is, the impurities constituting the diffusion layer SD2 are p-type. Compared with the concentration of impurities constituting the extension region EX2, the diffusion layer SD2 is made of impurities with a higher concentration of conductivity type. Specifically, the diffusion region SD2 is formed under the following implantation conditions: the implantation energy of the impurities mentioned above is, for example, 5keV to 25keV, and the dose of the impurities mentioned above is, for example, approximately 1×10⁻⁶. 15 cm -2 The semiconductor region SDR2, which serves as the source / drain of the p-type field-effect transistor Q1p formed in region 1Ap, includes the extended region EX2 and the diffusion region SD2 described above.

[0078] like Figure 1 As shown, the n-type well region NW is also formed in region 1TAp to provide the back gate voltage Vbg1 to the p-type field-effect transistor Q1n formed in region 1Ap. That is, the n-type well region NW is formed in region 1SRp, which includes two regions, 1Ap and 1TAp. Figure 1As shown, the n-type ground plane region GP2 is also formed in the n-type well region NW located in region 1TAp. Incidentally, as... Figure 1 As shown, the semiconductor layer SL and the insulating layer BX are not formed in region 1TAp. On the other hand, as... Figure 1 As shown, the epitaxial growth layer EP is also formed on the surface of the semiconductor substrate material BM located in region 1TAp and exposed from the device isolation portion STI. Then, the epitaxial growth layer EP is formed on region 1TAp, thereby forming the diffusion layer SD1. The polarity of the impurities constituting this diffusion layer SD1 is different from the polarity of the impurities constituting the diffusion layer SD2 described above. That is, the impurities constituting this diffusion layer SD1 are n-type. The diffusion layer SD1 is a region formed under the following implantation conditions: the implantation energy of the impurities mentioned above is, for example, 2keV to 25keV, and the dose of the impurities mentioned above is, for example, approximately 1 × 10⁻⁶. 15 cm -2 .

[0079] <The field-effect transistor Q2n in this embodiment>

[0080] Next, the n-type field-effect transistor Q2n formed in region 2BRn of the bulk region 2BR will be described.

[0081] like Figure 1 As shown, the n-type field-effect transistor Q2n formed in the bulk region 2BR has a semiconductor substrate material BM formed in region 2An, and a gate electrode GE3 formed on the semiconductor substrate material BM located in region 2An via a gate insulating film GI3. The semiconductor substrate material BM and the gate electrode GE3 that constitute the n-type field-effect transistor Q2n formed in region 2An are made of the same material as the semiconductor substrate material BM and the gate electrode GE1 that constitute the n-type field-effect transistor Q1n formed in region 1An. On the other hand, the gate insulating film GI3 will be described in detail below.

[0082] Furthermore, such as Figure 1 As shown, the semiconductor substrate material BM is located in region 2BRn (i.e. region 2An) and is in contact with the lower surface GIS of the gate insulating film GI3 located in region 2BRn, thereby forming a p-type well region PW.

[0083] like Figure 1 As shown, similar to the n-type field-effect transistor Q1n formed in region 1An, a sidewall spacer layer SW is formed on the sidewall of the gate electrode GE3 of the n-type field-effect transistor Q2n formed in region 2An. Figure 1As shown, the sidewall spacer layer SW consists of an offset spacer layer IF3 formed on the sidewall of the gate electrode GE3, and an insulating film IF4 formed on the sidewall of the gate electrode GE3 through the offset spacer layer IF3. Note that the offset spacer layer IF3 and the insulating film IF4, which respectively constitute the n-type field-effect transistor Q2m formed in region 2An, are made of the same material as the offset spacer layer IF3 and the insulating film IF4, which respectively constitute the n-type field-effect transistor Q1n formed in region 1An. In this embodiment, as... Figure 1 As shown, although no epitaxial growth layer EP is formed on the surface of the semiconductor substrate material BM located in region 2An that is exposed from the gate electrode GE1 and the sidewall spacer layer SW, similar to the field-effect transistors Q1n and Q1p formed in region 1SR of SOI, this epitaxial growth layer can be formed on the surface of the semiconductor substrate material BM that is exposed from the gate electrode GE3 and the sidewall spacer layer SW.

[0084] Furthermore, such as Figure 1 As shown, an extended region EX3 is formed in the region overlapping with the sidewall spacer layer SW of the semiconductor substrate material BM formed in region 2An (i.e., the well region PW formed in region 2An). Specifically, as Figure 1 As shown, the extended region EX3 is self-aligned with respect to the gate electrode GE3. Incidentally, the extended region EX3 is made of impurities of a certain concentration and conductivity type. Since the field-effect transistor Q2n formed in region 2An is an n-type field-effect transistor, the impurities constituting the extended region EX3 are n-type. The extended region EX3 is formed under the following implantation conditions: the implantation energy of the aforementioned impurities is, for example, 5 keV to 25 keV, and the dose of the aforementioned impurities is, for example, approximately 1 × 10⁻⁶. 14 cm -2 .

[0085] Furthermore, such as Figure 1 As shown, a diffusion layer SD3 is formed in the region that does not overlap with the sidewall spacer layer SW of the semiconductor substrate material BM formed in region 2An. Specifically, as Figure 1 As shown, the diffusion layer SD3 is self-aligned with respect to the sidewall spacer layer SW formed on the sidewall of the gate electrode GE3. Note that the polarity of the impurities constituting the diffusion layer SD3 is the same as that of the impurities constituting the extension region EX3. That is, the impurities constituting the diffusion layer SD3 are n-type. Compared with the concentration of impurities constituting the extension region EX3, the diffusion layer SD3 is made of impurities with a higher concentration of conductivity type. Specifically, the diffusion region SD3 is formed under the following implantation conditions: the implantation energy of the impurities mentioned above is, for example, 5 keV to 25 keV, and the dose of the impurities mentioned above is, for example, approximately 1 × 10⁻⁶. 15 cm -2The semiconductor region SDR3 of the source / drain of the n-type field-effect transistor Q2n formed in region 2An includes the extended region EX3 and the diffusion region SD3 described above.

[0086] <The field-effect transistor Q2p in this embodiment>

[0087] Next, the p-type field-effect transistor Q2p formed in region 2BRp of the block region 2BR will be described.

[0088] like Figure 1 As shown, the p-type field-effect transistor Q2p formed in the bulk region 2BR has a semiconductor substrate material BM formed in region 2Ap, and a gate electrode GE4 formed on the semiconductor substrate material BM in region 2Ap via a gate insulating film GI4. The semiconductor substrate material BM and the gate electrode GE4 constituting the p-type field-effect transistor Q2p formed in region 2Ap are made of the same material as the semiconductor substrate material BM and the gate electrode GE3 constituting the n-type field-effect transistor Q2n formed in region 2An. The gate insulating film GI4 will be described in detail later.

[0089] Furthermore, such as Figure 1 As shown, the semiconductor substrate material BM is located in region 2BRp (i.e. region 2Ap) so as to contact the lower surface GIS of the gate insulating film GI3 located in region 2BRp, thereby forming an N-type well region NW.

[0090] like Figure 1 As shown, similar to the n-type field-effect transistor Q2n formed in region 2An, a sidewall spacer layer SW is formed on the sidewall of the gate electrode GE4 of the p-type field-effect transistor Q2p formed in region 2Ap. Figure 1 As shown, the sidewall spacer layer SW consists of an offset spacer layer IF3 formed on the sidewall of the gate electrode GE4, and an insulating film IF4 formed on the sidewall of the gate electrode GE4 through the offset spacer layer IF3. Note that the offset spacer layer IF3 and the insulating film IF4 constituting the p-type field-effect transistor Q2p formed in region 2Ap are made of the same material as the offset spacer layer IF3 and the insulating film IF4 constituting the n-type field-effect transistor Q2n formed in region 2An. In this embodiment, as... Figure 1 As shown, although no epitaxial growth layer EP is formed on the surface of the semiconductor substrate material BM located in region 2Ap that is exposed from the gate electrode GE4 and the off-sidewall spacer layer SW, similar to the field-effect transistors Q1n and Q1p formed in region 1SR of SOI, an epitaxial growth layer can be formed on the surface of the semiconductor substrate material BM that is exposed from the gate electrode GE4 and the off-sidewall spacer layer SW.

[0091] Furthermore, such as Figure 1 As shown, an extended region EX4 is formed in the region overlapping with the sidewall spacer layer SW of the semiconductor substrate material BM formed in region 2Ap (i.e., the well region NW formed in region 2Ap). Specifically, as Figure 1 As shown, the extended region EX4 is self-aligned with respect to the gate electrode GE4. Incidentally, the extended region EX4 is made of impurities with a certain concentration of conductivity type. Since the field-effect transistor Q2p formed in region 2Ap is a p-type field-effect transistor, the impurities constituting the extended region EX4 are p-type. The extended region EX4 is formed under the following implantation conditions: the implantation energy of the aforementioned impurities is, for example, 5 keV to 25 keV, and the dose of the aforementioned impurities is, for example, approximately 1 × 10⁻⁶. 14 cm -2 .

[0092] Furthermore, such as Figure 1 As shown, a diffusion layer SD4 is formed in a region that does not overlap with the sidewall spacer layer SW of the semiconductor substrate material BM formed in region 2Ap. Specifically, as Figure 1 As shown, the diffusion layer SD4 is self-aligned and formed about the sidewall spacer layer SW formed on the sidewall of the gate electrode GE4. Note that the polarity of the impurities constituting the diffusion layer SD4 is the same as that of the impurities constituting the extension region EX4. That is, the impurities constituting the diffusion layer SD4 are p-type. Compared with the concentration of impurities constituting the extension region EX4, the diffusion layer SD4 is made of impurities with a higher concentration of conductivity type. Specifically, the diffusion region SD4 is formed under the following implantation conditions: the implantation energy of the impurities mentioned above is, for example, 5 keV to 25 keV, and the dose of the impurities mentioned above is, for example, approximately 1 × 10⁻⁶. 15 cm -2 The semiconductor region SDR4, which forms the source / drain of the p-type field-effect transistor Q2p in region 2Ap, includes the extended region EX4 and the diffusion region SD4 described above.

[0093] Next, as Figure 1As shown, each gate electrode GE1, GE2, GE3, GE4 of each field-effect transistor Q1n, Q1p, Q2n, Q2p formed in each region 1An, 1Ap, 2Ap, 2An, a sidewall spacer layer SW formed on each gate electrode GE1, GE2, GE3, GE4, an epitaxial growth layer EP (i.e., diffusion layers SD1, SD2) formed in each region 1An, 1Ap, 1TAn, 1TAp, and the surface of the semiconductor substrate material BM located in the bulk region 2BR and exposed from each gate electrode GE3, GE4 formed in the bulk region 2BR are covered by an interlayer insulating film IL1. The interlayer insulating film IL1 is made of silicon oxide, for example. Further, the interlayer insulating film IL1 is formed by a CVD method.

[0094] Furthermore, such as Figure 1 As shown, a contact hole CH is formed in the interlayer insulating film IL1, extending from the surface of the interlayer insulating film IL1 to the corresponding epitaxial growth layer EP and the corresponding diffusion layers SD3 and SD4. Then, as... Figure 1 As shown, a contact plug PG is formed within each contact hole CH. Incidentally, the contact plug PG is made of a conductive material such as tungsten (W). Furthermore, a silicide layer can be formed in the portion where each epitaxial growth layer EP contacts each contact plug PG, and the contact plug PG can be electrically connected to the epitaxial growth layer EP through this silicide layer. Further, although not shown, contact holes CH and contact plugs PG are also formed on the corresponding gate electrodes GE1, GE2, GE3, and GE4.

[0095] Next, as Figure 1 As shown, an interlayer insulating film IL2 is formed on the surface of the interlayer insulating film IL1, covering a plurality of interconnects WL1 formed in the interconnect layer M1. The plurality of interconnects WL1 are electrically connected via a plurality of contact plugs PG and a plurality of epitaxial growth layers EP, respectively. Although not shown, the interconnect layer M1 and the interlayer insulating film IL2 described above are alternately stacked on the interlayer insulating film IL1. That is, the interconnect layer M1 and the interlayer insulating film IL2 are formed on the interlayer insulating film IL1, which serves as a contact interlayer insulating layer, and are components constituting a multilayer interconnect layer.

[0096] <Each gate insulating film GI1, GI2, GI3, GI4 in this embodiment>

[0097] Next, each gate insulating film GI1, GI2, GI3, and GI4 that makes up each field-effect transistor Q1n, Q1p, Q2n, and Q2p will be described in detail.

[0098] First, the gate insulating film of the n-type field-effect transistor Q1n formed in region 1An, which is the SOI region 1SR, is an insulating film in which hafnium (Hf) is added to an insulating film IF1 made of silicon oxide. Aluminum (Al) is not added to the insulating film IF1 that forms the gate insulating film GI1. The gate insulating film GI2 of the p-type field-effect transistor Q1p formed in region 1Ap, which is the SOI region 1SR, is an insulating film in which aluminum (Al) is added to an insulating film IF1 made of silicon oxide. Note that hafnium (Hf) is not added to the insulating film IF1 that forms the gate insulating film GI2. The gate insulating film of the n-type field-effect transistor Q2n formed in region 2An, which is the block region 2BR, is an insulating film in which aluminum (Al) is added to an insulating film IF2 made of silicon oxide. In this embodiment, hafnium (Hf) is not added to the insulating film IF2 that forms the gate insulating film GI3. Furthermore, the gate insulating film GI4 constituting the p-type field-effect transistor Q2p formed in region 2Ap, which is a block region 2BR, is an insulating film in which hafnium (Hf) is added to an insulating film IF2 made of silicon oxide. In this embodiment, aluminum (Al) is not added to the insulating film IF2 constituting the gate insulating film GI4.

[0099] Furthermore, such as Figure 1 As shown, the thickness of each gate insulating film GI3, GI4 formed in the bulk region 2BR is greater than the thickness of each gate insulating film GI1, GI2 formed on the SOI region 1SR. In this embodiment, the thickness of the gate insulating films GI1, GI2 formed on the SOI region 1SR is, for example, 1.5 nm to 3.0 nm. On the other hand, the thickness of the gate insulating films GI3, GI4 formed in the bulk region 2BR is, for example, 6.0 nm to 10.0 nm.

[0100] Although specific manufacturing methods for gate insulating films GI1, GI2, GI3, and GI4 will be described subsequently, the gate insulating films GI1, GI2, GI3, and GI4, with hafnium (Hf) or aluminum (Al), are formed by deposition on substantially the entire surface (upper surface) of the corresponding insulating films IF1 and IF2. Therefore, in Figure 1 In the diagram, each gate insulating film GI1, GI2, GI3, GI4 is illustrated as a sheet structure for convenience, wherein a metal film HK1 made of hafnium (Hf) or a metal film HK2 made of aluminum (Al) is formed (deposited) on the corresponding insulating films IF1 and IF2.

[0101] <Inventor's Inspection Results>

[0102] Next, through the inventor's study, it has become clear and will be referenced Figure 3 and 4The following descriptions are provided: the threshold voltage of an n-type field-effect transistor; the relationship between the corresponding amounts of aluminum (Al) and hafnium (Hf) added to the gate insulating film constituting an n-type field-effect transistor; the threshold voltage of a p-type field-effect transistor; and the relationship between the corresponding amounts of hafnium (Hf) and aluminum (Al) added to the gate insulating film constituting a p-type field-effect transistor. Incidentally, Figure 3 This is a graph showing the relationship between the ratio of the number of aluminum (Al) atoms to the total number of aluminum (Al) and hafnium (Hf) atoms in the gate insulating film and the threshold voltage of the n-type field-effect transistor in each case of adding aluminum (Al) and hafnium (Hf). Figure 4 This is a graph showing the relationship between the ratio of the number of hafnium (Hf) atoms to the total number of aluminum (Al) and hafnium (Hf) atoms and the threshold voltage of a p-type field-effect transistor when aluminum (Al) and hafnium (Hf) are added to the gate insulating film.

[0103] First, such as Figure 3 As shown, in an n-type field-effect transistor (FET), when both aluminum (Al) and hafnium (Hf) are added to the gate insulating film, the threshold voltage of the FET becomes lower. This is because the ratio of the number of hafnium (Hf) atoms to the total number of aluminum (Al) and hafnium (Hf) atoms (i.e., the hafnium concentration) is greater than the ratio of the number of aluminum (Al) atoms (i.e., the aluminum concentration). That is, in an n-type FET, as... Figure 3 As shown, the smaller the amount of aluminum (Al) added to the gate insulating film, the lower the threshold voltage in the n-type field-effect transistor.

[0104] On the other hand, such as Figure 4 As shown, in an n-type field-effect transistor, when aluminum (Al) and hafnium (Hf) are added, the ratio of the number of aluminum (Al) atoms to the total number of aluminum (Al) and hafnium (Hf) atoms (i.e., the aluminum concentration) is as large as the ratio of the number of hafnium (Hf) atoms (i.e., the hafnium concentration), resulting in a low threshold voltage in the n-type field-effect transistor. That is, in a p-type field-effect transistor, as... Figure 4 As shown, the smaller the number of hafnium (Hf) added to the gate insulating film, the lower the threshold voltage in the n-type field-effect transistor.

[0105] <Due to the effect of the semiconductor device SMD1 in this embodiment>

[0106] As described above, in this embodiment, the gate insulating film GI1 constituting the n-type field-effect transistor Q1n formed in region 1An (SOI region 1SR) uses the following insulating film (a so-called high dielectric constant insulating film): an insulating film IF1 made of silicon oxide, and in which hafnium (Hf) is added (deposited) but aluminum (Al) is not added (deposited). Therefore, as Figure 1As shown, the gate electrode GE1 of the n-type field-effect transistor Q1n is formed on the semiconductor layer SL located in region 1An (SOI region 1SR) via the gate insulating film GI1, which is a high-dielectric-constant insulating film as described above. Therefore, as Figure 3 As shown, the threshold voltage of the n-type field-effect transistor Q1n formed in region 1An can be reduced. Therefore, the drive voltage of the n-type field-effect transistor Q1n formed in region 1An can be reduced, that is, the power consumption can be reduced. In other words, the operating speed of the n-type field-effect transistor Q1n formed in region 1An can be improved.

[0107] In this embodiment, the gate insulating film GI2 constituting the p-type field-effect transistor Q1p formed in region 1Ap (SOI region 1SR) is made of silicon oxide and is made by adding (depositing) aluminum (Al) but not adding (depositing) hafnium (Hf). Therefore, as Figure 1 As shown, the gate electrode GE2 of the p-type field-effect transistor Q1p is formed on the semiconductor layer SL located in region 1Ap (SOI region 1SR) via the gate insulating film GI2, which serves as a high-dielectric-constant insulating film as described above. Therefore, as Figure 4 As shown, the threshold voltage of the p-type field-effect transistor Q1p formed in region 1Ap can be reduced. Therefore, the driving voltage of the p-type field-effect transistor Q1p formed in region 1Ap can be reduced, that is, the power consumption can be reduced. In other words, the operating speed of the p-type field-effect transistor Q1p formed in region 1Ap can be improved. Incidentally, regarding the above NBTI, when pressure such as voltage or temperature is applied to the p-type field-effect transistor, the threshold voltage of the field-effect transistor changes over time. Then, if the voltage value applied to the p-type field-effect transistor is higher, the NBTI becomes considerable. On the other hand, as described above, there has been a need to further reduce the power consumption of semiconductor devices in recent years. For this reason, in semiconductor devices where low power consumption measures are particularly needed, it is preferable, as in this embodiment, to use the following insulating film as the gate insulating film GI2 of the p-type field-effect transistor Q1p formed in region 1Ap (SOI region 1SR): aluminum (Al) is added (deposited) to the insulating film IF1 made of silicon oxide, but hafnium (Hf) is not added (deposited).

[0108] Furthermore, as described above, in this embodiment, the insulating film IF1, which is made of silicon oxide and has hafnium (Hf) added (deposited) but no aluminum (Al) added, is used as the gate insulating film GI1 constituting the n-type field-effect transistor Q1n formed in region 1An (SOI region 1SR); while the insulating film IF1, which is made of silicon oxide and has aluminum (Al) added (deposited) but no hafnium (Hf) added, is used as the gate insulating film GI2 constituting the p-type field-effect transistor Q1p formed in region 1Ap (SOI region 1SR). Therefore, the driving voltage of the SRAM circuit including the n-type field-effect transistor Q1n and the p-type field-effect transistor Q1p can be reduced. In other words, the operating speed of the SRAM circuit can be improved.

[0109] In this embodiment, the gate insulating film GI3, which forms the n-type field-effect transistor Q2n formed in region 2An (which is a block region 2BR), is an insulating film on which at least aluminum (Al) is deposited (on) an insulating film IF2 made of silicon oxide. In this embodiment, an insulating film on which at least hafnium (Hf) is deposited (on) a insulating film IF2 made of silicon oxide is used as the gate insulating film GI4, which constitutes the p-type field-effect transistor Q2p formed in region 2Ap (which is a block region 2BR). Therefore, the threshold voltage of the n-type field-effect transistor Q2n formed in region 2An is higher than the threshold voltage of the n-type field-effect transistor Q1n formed in region 1An. Similarly, the threshold voltage of the p-type field-effect transistor Q2p formed in region 2Ap is higher than the threshold voltage of the p-type field-effect transistor Q1p formed in region 1Ap. That is, in this embodiment, the threshold voltage of each of the field-effect transistors Q2n and Q2p formed in the block region 2BR is set to be higher than the threshold voltage of each of the field-effect transistors Q1n and Q1p formed in the SOI region 1SR.

[0110] Here, as described above, each of the n-type field-effect transistors Q2n and Q2p formed in the block region 2BR is a field-effect transistor constituting a peripheral circuit whose drive voltage is higher than that of the SRAM circuit, which is composed of each of the n-type field-effect transistors Q1n and Q1p formed in the SOI region 1SR. Like the field-effect transistors Q1n and Q1p formed in the SOI region 1SR, the SOI region does not have ground plane regions GP1 and GP2 that act as back gates BGE1 and BGE2. Therefore, if the threshold voltage of the n-type field-effect transistors Q2n and Q2p formed in the block region 2BR decreases, leakage current (subthreshold leakage current) may occur between the source and drain of the field-effect transistors Q2n and Q2p formed in the block region 2BR. Furthermore, in this embodiment, the insulating layer BX constituting the field-effect transistors Q1n and Q1p formed on the SOI region 1SR is as thin as 10 nm to 20 nm. Therefore, if the field-effect transistors Q1n and Q1p are driven with the same driving voltage as the peripheral circuit, the insulating layer BS formed in the SOI region 1SR may be damaged (so-called time-varying dielectric breakdown: TDDB).

[0111] However, in this embodiment, as Figure 1 As shown, each of the field-effect transistors Q1n and Q1p formed in the SOI region 1SR has ground plane regions GP1 and GP2, which serve as the back gates BGE1 and BGE2 of each of the field-effect transistors Q1n and Q1p on the lower surface of the insulating layer BX. Therefore, even if the threshold voltage of each of the field-effect transistors Q1n and Q1p decreases, the occurrence of leakage current between the source and drain of each of the field-effect transistors Q1n and Q1p can be suppressed. Furthermore, since the drive voltage of the SRAM circuit composed of the n-type field-effect transistor Q1n and the p-type field-effect transistor Q1p formed in the SOI region 1SR can be reduced, the occurrence of the aforementioned TDDB can be suppressed in the field-effect transistors Q1n and Q1p. In this embodiment, as described above, the threshold voltage of each of the field-effect transistors Q2n and Q2p formed in the block region 2BR is higher than the threshold voltage of each of the field-effect transistors Q1n and Q1p formed in the SOI region 1SR. Therefore, leakage current between the source and drain of field-effect transistors Q2n and Q2p formed in the block region 2BR can be suppressed.

[0112] In this embodiment, the thickness of each gate insulating film GI1, GI2 formed in the SOI region 1SR is, for example, 1.5 nm to 3.0 nm, while the thickness of each gate insulating film GI3, GI4 formed in the bulk region 2BR is, for example, 6.0 nm to 10.0 nm. In this embodiment, as... Figure 1 As shown, the thicknesses of the gate insulating films GI3 and GI4 of each of the field-effect transistors Q2n and Q2p formed in the block region 2BR are greater than the thicknesses of the gate insulating films GI1 and GI2 of each of the field-effect transistors Q1n and Q1p formed in the SOI region 1SR. Therefore, the breakdown voltage of the field-effect transistors Q2n and Q2p formed in the block region 2BR can be ensured. That is, even if a higher driving voltage is used in the peripheral circuit composed of the n-type field-effect transistor Q1n and the p-type field-effect transistor Q1p formed in the SOI region 1SR, the breakdown of the gate insulating films GI3 and GI4 of the field-effect transistors Q2n and Q2p formed in the block region 2BR can be suppressed compared to the driving voltage of the SRAM circuit composed of the n-type field-effect transistor Q1n and the p-type field-effect transistor Q1p formed in the SOI region 1SR.

[0113] <Method for manufacturing the semiconductor device SMD1 of this embodiment>

[0114] Next, we will refer to Figures 5 to 15 This embodiment describes a method for manufacturing a semiconductor device SMD1. Figure 5 This is a process flow diagram illustrating the manufacturing process of the semiconductor device in this embodiment. Figures 6 to 15 This is a cross-sectional view of the semiconductor device of this embodiment during the manufacturing process.

[0115] 1. Substrate preparation ( Figure 5 Step S1)

[0116] First, the substrate SB is fabricated. Specifically, in this embodiment, as follows: Figure 6 As shown, a substrate SB with at least four regions 1SRn, 1SRp, 2BRn, and 2BRp is fabricated. Figure 6 As shown, region 1SRn, which is SOI region 1SR, has a region that will be formed therein later. Figure 1 The diagram shows region 1An of the n-type field-effect transistor Q1n, and region 1TAn for providing the back gate voltage Vbg2 to the n-type field-effect transistor Q1n to be formed in region 1An. Figure 6 As shown, region 1SRp, which is SOI region 1SR, has a structure that will be formed therein later. Figure 1The diagram shows region 1Ap of the p-type field-effect transistor Q1p, and region 1TAp for providing the back gate voltage Vbg1 to the p-type field-effect transistor Q1p to be formed in region 1Ap. Region 2BRn, as a block region 2BR, is to be formed therein later. Figure 1 The n-type field-effect transistor Q2n is shown with region 2An. Region 2BRp, which is a block region 2BR, will be formed therein later. Figure 1 The p-type field-effect transistor Q2p shown is in region 2Ap.

[0117] Furthermore, such as Figure 6 As shown, the substrate SB includes a semiconductor substrate material BM, an insulating layer BX formed on the semiconductor substrate material BM, and a semiconductor layer SL formed on the insulating layer BX. This is a so-called SOI (silicon-on-insulator) substrate. Figure 6 As shown, the semiconductor substrate material BM has an upper surface (front surface) BMS1 and a lower surface (rear surface) BMS2 opposite to the upper surface BMS1, and an insulating layer BX is formed on the upper surface BMS1 of the semiconductor substrate material BM. Figure 6 As shown, the insulating layer BX has a lower surface BXS2 opposite to the upper surface BXS1 and an upper surface BXS1, and the semiconductor layer SL is formed on the upper surface BXS1 of the insulating layer BX.

[0118] Furthermore, such as Figure 6 As shown, a device isolation portion STI is formed in the substrate SB, penetrating through each of the semiconductor layer SL and the insulating layer BX and reaching the semiconductor substrate material BM. Furthermore, the corresponding regions 1An, 1TAn, 1Ap, 1TAp, 2An, and 2Ap are separated from each other by the device isolation portion STI. In this embodiment, a method for manufacturing a semiconductor device will be described based on the substrate SB in which the device isolation portion is formed.

[0119] 2. Formation of blocky regions ( Figure 5 Step S2)

[0120] Next, the semiconductor layer SL located in region 1TAn, the semiconductor layer SL located in region 1TAp, the semiconductor layer SL located in region 2An, and the semiconductor layer SL located in region 2Ap are removed. Therefore, the insulating layer BX located in each region 1TAn, 1Tap, 2An, and 2Ap is exposed.

[0121] Subsequently, a p-type well region PW is formed in the semiconductor substrate material BM located in each of regions 1SRn and 2BRn where an n-type field-effect transistor is formed. Conversely, an n-type well region NW is formed in the semiconductor substrate material BM located in each of regions 1SRp and 2BRp where a p-type field-effect transistor is formed. The p-type well region PW is formed by implanting p-type impurity atoms, such as boron (B), into the semiconductor substrate material BM. The n-type well region NW is formed by implanting n-type impurity atoms, such as arsenic (As) or phosphorus (P), into the semiconductor substrate material BM.

[0122] Subsequently, a p-type ground plane region GP1 is formed in the p-type well region PW formed in each of regions 1An and 1TAn. At this time, as... Figure 7 As shown, a p-type ground plane region GP1 is formed in region 1An to contact the lower surface BXS2 of the insulating layer BX located in region 1An, thereby forming a p-type well region PW therein. On the other hand, an n-type ground plane region GP2 is formed in each of regions 1Ap and 1Tap. At this time, as... Figure 7 As shown, an n-type ground plane region GP2 is formed in region 1Ap to contact the lower surface BXS2 of the insulating layer BX located in region 1An, thereby forming an n-type well region NW therein. A p-type ground plane region GP1 is formed by implanting p-type impurity atoms, such as boron (B), into the p-type well region PW. On the other hand, an n-type ground plane region GP2 is formed by implanting n-type impurity atoms, such as arsenic (As) or phosphorus (P), into the n-type well region NW. Furthermore, the concentration of impurities constituting the p-type ground plane region GP1 is higher than the concentration of impurities constituting the p-type well region PW. Furthermore, the concentration of impurities constituting the n-type ground plane region GP2 is higher than the concentration of impurities constituting the n-type well region NW.

[0123] Subsequently, the insulating layer BX located in regions 1TAn, 1TAp, 2An, and 2Ap is removed. Therefore, the semiconductor substrate material located in region 1TAn, region 1TAp, region 2An, and region 2Ap is exposed. Specifically, as... Figure 7 As shown, the p-type grounding plane region GP1 formed in region 1TAn, the n-type grounding plane region GP2 formed in region 1TAp, the p-type well region PW formed in region 2An, and the n-type well region NW formed in region 2Ap are exposed.

[0124] 3. Formation of the insulating film ( Figure 5 Step S3)

[0125] Next, as Figure 8 As shown, an insulating film IF1 made of silicon oxide is formed on the semiconductor layer SL located in each of regions 1An and 1Ap. On the other hand, as... Figure 8 As shown, an insulating film IF2 made of silicon oxide is formed on the semiconductor substrate material BM located in each of regions 2An and 2Ap. Incidentally, in this embodiment, as... Figure 8 As shown, the thickness of the insulating film IF2 formed in each of regions 1An and 1Ap, which are SOI regions 1SR, is greater than the thickness of the insulating film IF1 formed in each of regions 2An and 2Ap, which are block regions 2BR.

[0126] 4. Addition of aluminum ( Figure 5 Step S4)

[0127] Next, in SOI region 1SR, and within it, Figure 1 The insulating film IF1 formed in region 1Ap of the p-type field-effect transistor Q1p shown, the bulk region 2BR, and the region formed therein Figure 1 Aluminum (Al) is added to the insulating film IF2 formed in region 2An of the n-type field-effect transistor Q2n shown.

[0128] Regarding the details, firstly, such as Figure 9 As shown, since insulating film IF2 in insulating film IF1 and 2An in region 1Ap are exposed, and insulating film IF2 in insulating film IF1 and region 2Ap in region 1An are covered, a mask MSK1 is formed on the semiconductor layer SL in region 1An, on the semiconductor substrate material BM in region 1TAn, and on the semiconductor materials BM in regions 1TAp and 2Ap. The mask MSK1 is made of amorphous silicon, for example.

[0129] Next, as Figure 10 As shown, in the following state: the semiconductor layer SL in region 1An, the semiconductor substrate material BM in region 1TAn, the semiconductor substrate material BM in region 1TAp, and the semiconductor substrate material BM in region 2Ap are covered by mask MSK1. From the upper surface BMS1 side of the semiconductor substrate material BM, aluminum (Al)HK200 is deposited on each of the mask MKS1 in region 1An, the insulating film IF1 in region 1Ap, the insulating film IF2 in region 2An, and the mask MSK1 in region 2Ap. That is, aluminum (Al)HK200 is added to each insulating film IF1, IF2. In this embodiment, aluminum (Al)HK200 is added to the insulating films IF1, IF2, for example, by sputtering. Therefore, as Figure 10 As shown, an aluminum (Al) metal film HK2 is formed on each of the insulating films IF1 formed in the corresponding regions 1An, 1TAn, 1TAp, 2Ap, the insulating film IF1 located in region 1Ap, and the insulating film IF2 located in region 2An.

[0130] Subsequently, the mask MSK1 formed on the semiconductor layer SL in region 1An, the semiconductor substrate material BM in region 1TAn, the semiconductor substrate material BM in region 1TAp, and the semiconductor substrate material BM in region 2Ap is removed. Although not shown, during the removal of the mask MSK1, photoresist is formed, for example, on the insulating film IF1 formed in region 1Ap and the insulating film IF2 located in region 2An, and the mask MSK1 is removed by using this photoresist as a mask. The photoresist is then removed. Therefore, as... Figure 11 As shown, while the insulating film IF1 formed in region 1An and the insulating film IF2 formed in region 2Ap are exposed, a metal film HK2 made of aluminum (Al) is formed on the insulating film IF2 located on the insulating film IF1 and on region 2An located in region 1Ap.

[0131] 5. Addition of hafnium ( Figure 5 Step S5)

[0132] Next, hafnium (Hf) is added to the insulating film IF1 formed in region 1An (SOI region 1SR) and the insulating film IF2 formed in region 2Ap (bulk region 2BR), which is to be formed in region 1An. Figure 1 The n-type field-effect transistor Q1n shown is to be formed in region 2AP. Figure 1 The p-type field-effect transistor Q2p is shown.

[0133] Regarding the details, firstly, such as Figure 12 As shown, since insulating film IF2 in insulating film IF1 and 2Ap in region 1An are exposed, and insulating film IF2 in insulating film IF1 and region 2An in region 1Ap are covered, mask MSK2 is formed on the semiconductor substrate material BM in region 1TAn, on the semiconductor layer SL in region 1Ap, and on the semiconductor material BM in regions 1TAp and 2An. Note that, like mask MSK1 described above, mask MSK2 is made of, for example, amorphous silicon.

[0134] Next, as Figure 13As shown, in this state: the semiconductor substrate material BM located in region 1TAn, the semiconductor layer SL located in region 1Ap, the semiconductor substrate material BM located in region 1TAp, and the semiconductor substrate material BM located in region 2An are covered by mask MSK1. From the upper surface BMS1 side of the semiconductor substrate material BM, hafnium (Hf)HK100 is deposited on each of the insulating film IF1 located in region 1An, the mask MSK2 located in region 1Ap, the mask MSK2 located in region 2An, and the insulating film IF2 located in region 2Ap. That is, hafnium (Hf)HK100 is added to each insulating film IF1, IF2. In this embodiment, hafnium (Hf)HK100 is added to the insulating films IF1, IF2, for example, by sputtering. Therefore, as Figure 13 As shown, a metal film HK1 made of hafnium (Hf) is formed on each of the mask MSK2 formed in the corresponding regions 1TAn, 1Ap, 1TAp, 2An, the insulating film IF1 located in region 2Ap, and the insulating film IF2 located in region 2Ap.

[0135] Subsequently, the mask MSK2 formed on each of the semiconductor substrate material BM in region 1TAn, the semiconductor layer SL in region 1Ap, the semiconductor substrate material BM in region 1TAp, and the semiconductor substrate material BM in region 2An is removed. Although not shown, during the removal of the mask MSK2, photoresist is formed, for example, on the insulating film IF1 formed in region 1An and the insulating film IF2 located in region 2Ap, and the mask MSK2 is removed by using this photoresist as a mask. The photoresist is then removed. Therefore, as Figure 14 As shown, a metal film HK1 made of hafnium (Hf) is formed on the insulating film IF1 and on the insulating film IF2 located in regions 1An and 2Ap. At the same time, region 1Ap is formed, and the insulating film IF1 with aluminum (Al) added therein is formed in region 2An, and the insulating film IF2 with aluminum (Al) added therein is exposed.

[0136] 6. Formation of the gate electrode ( Figure 5 Step S6)

[0137] Next, gate electrodes GE1, GE2, GE3, and GE4 are formed in regions 1An, 1Ap, 2An, and 2Ap, respectively. Specifically, first, a semiconductor material is deposited on the substrate SB, for example, by a CVD method, such that the semiconductor material covers the corresponding regions 1An, 1Ap, 2An, and 2Ap. The semiconductor material deposited on the substrate SB is, for example, a polycrystalline silicon film.

[0138] Next, impurities are introduced into the deposited semiconductor material. Specifically, n-type impurity atoms, such as arsenic (As) or phosphorus (P), are implanted into the semiconductor material in regions 1An and 2An, where an n-type field-effect transistor is to be formed. On the other hand, p-type impurity atoms, such as boron (B), are implanted into the semiconductor material in regions 1Ap and 2Ap, where a p-type field-effect transistor is to be formed.

[0139] Next, the semiconductor material in which impurities are introduced is patterned into the desired shape. Furthermore, the corresponding portions of each insulating film IF1, IF2 exposed from the respective gate electrodes GE1, GE2, GE3, GE4 are removed as masks by the patterned gate electrodes GE1, GE2, GE3, GE4. Incidentally, the patterning of the semiconductor material or the removal of the insulating films IF1, IF2 is performed, for example, using photolithography and dry etching. Therefore, as... Figure 15 As shown, the gate electrode GE1 is formed on the semiconductor layer SL located in region 1An via a gate insulating film GI1 (i.e., a film made of an insulating film IF1 and a metal film HK1 formed on the insulating film IF1). This gate insulating film GI1 is formed by adding hafnium (Hf) to the insulating film IF1 located in region 1An without adding aluminum (Al). Moreover, as Figure 15 As shown, the gate electrode GE2 is formed on the semiconductor layer SL located in region 1Ap via a gate insulating film GI2 (i.e., a film made of an insulating film IF1 and a metal film HK2 formed on the insulating film IF1). This gate insulating film GI2 is formed by adding aluminum (Al) to the insulating film IF1 located in region 1Ap without adding hafnium (Hf). Furthermore, as... Figure 15 As shown, the gate electrode GE3 is formed on the semiconductor substrate material BM located in region 2An via a gate insulating film GI3 (i.e., a film made of an insulating film IF2 and a metal film HK2 formed on the insulating film IF2). This gate insulating film GI3 is formed by adding aluminum (Al) to the insulating film IF2 located in region 2An. Furthermore, as... Figure 15 As shown, the gate electrode GE4 is formed on the semiconductor substrate material BM located in region 2Ap via a gate insulating film GI4 (i.e., a film made of insulating film IF2 and metal film HK1 formed on insulating film IF2). The gate insulating film GI4 is formed by adding hafnium (Hf) to the insulating film IF2 located in region 2Ap.

[0140] Subsequently, a sidewall spacer layer SW as described above is formed on the sidewall of each gate electrode GE1, GE2, GE3, GE4. Further, in SOI region 1SR, the surfaces exposed relative to the surface (exposed surface) of the semiconductor substrate material BM in region 1TAp, namely the gate electrode GE1 and offset spacer layer IF3 (forming the sidewall spacer layer SW) of semiconductor layer SL in region 1An, the gate electrode GE2 and offset spacer layer IF3 (forming the insulating film of the sidewall spacer layer SW) of semiconductor layer SL in region 1Ap, and the surface (exposed surface) of the semiconductor substrate material BM in region 1TAn, undergo epitaxial growth processing. Therefore, an epitaxial growth layer EP is formed in the corresponding regions 1An, 1TAn, 1Ap, and 1TAp (see...). Figure 1 Next, as... Figure 1 As shown, after forming an interlayer insulating film IL1 on the substrate SB to cover the epitaxial growth layer EP, a contact hole CH is formed in the interlayer insulating film IL1. Furthermore, the contact hole CH is closed by a conductive component. Therefore, corresponding semiconductor regions SDR1, SDR2, SDR3, and SDR4, serving as the source or drain of field-effect transistors Q1n, Q2n, Q2n, and Q2p, are formed, along with contact plugs PG connected to each diffusion layer SD1 and SD2 formed in each region 1TAn and 1TAp. Incidentally, as an example, the contact plug PG is made of a conductive component such as tungsten (W). Further, after forming the contact plug PG, as... Figure 1 As shown, the multilayer interconnect layer described above is formed on the surface of the interlayer insulating film IL1.

[0141] <Effects of the method for manufacturing semiconductor devices in this embodiment>

[0142] As described above, in this embodiment, when an n-type field-effect transistor Q1n is formed in region 1An, which serves as SOI region 1SR, hafnium (Hf) is added to the silicon oxide insulating film IF1 (the film constituting the gate insulating film GI1 of the n-type field-effect transistor Q1n) formed in region 1An, but aluminum (Al) is not added. Therefore, the threshold voltage of the n-type field-effect transistor Q1n formed in region 1An can be reduced, while the generation of gate leakage current in the field-effect transistor Q1n is suppressed. Similarly, in this embodiment, when a p-type field-effect transistor Q1p is formed in region 1Ap, which serves as SOI region 1SR, aluminum (Al) is added to the silicon oxide insulating film IF1 (the film constituting the gate insulating film GI2 of the p-type field-effect transistor Q1p) formed in region 1Ap, but hafnium (Hf) is not added. Therefore, the threshold voltage of the p-type field-effect transistor Q1p formed in region 1Ap can be reduced, while the generation of gate leakage current in the field-effect transistor Q1p can be suppressed.

[0143] In this embodiment, when hafnium (Hf) is added to the insulating film IF1 formed in region 1An, the insulating film IF1 formed in region 1Ap is covered by the mask MKS2, as shown. Figure 13 As shown. On the other hand, when aluminum (Al) is added to the insulating film IF1 formed in region 1Ap, as Figure 10 As shown, an insulating film IF1 formed in region 1An is covered using mask MKS1. Here, the inventors have investigated the addition of hafnium (Hf) and aluminum (Al) to each region 1An and 1Ap. However, in region 1An, the ratio of the number of aluminum (Al) atoms to the total number of aluminum (Al) and hafnium (Hf) atoms in the gate insulating film decreases, while in region 1Ap, the ratio of the number of hafnium (Hf) atoms to the total number of aluminum (Al) and hafnium (Hf) atoms in the gate insulating film decreases. In this case, shortening the sputtering time of the metal is sufficient to reduce the ratio of the number of atoms. However, the shorter the sputtering time, the more likely a change in the number of metals to be deposited occurs. In other words, it has been found that it becomes difficult to set the number (concentration) of added metal to the desired value. This makes it difficult to produce semiconductor devices with the desired properties. On the other hand, in this embodiment, by using corresponding masks MSK1 and MSK2, metal is not added unnecessarily in the corresponding regions 1An and 1Ap. Therefore, the manufacturing yield of semiconductor devices can be improved.

[0144] Furthermore, in this embodiment, when hafnium (Hf) is added to the insulating film IF1 formed in region 1An, as... Figure 13 As shown, the insulating film IF1 formed in region 1Ap is covered by mask MKS2, but the insulating film IF2 formed in region 2Ap is not covered by mask MSK2. That is, as Figure 13 As shown, when hafnium (Hf) is added to the insulating film IF1 formed in region 1An, hafnium (Hf) is also added to the insulating film IF2 formed in region 2Ap. Similarly, when aluminum (Al) is added to the insulating film IF1 formed in region 1Ap, as... Figure 10 As shown, the insulating film IF1 formed in region 1An is covered by the mask MKS1, while the insulating film IF2 formed in region 2An is not covered by the mask MSK1. That is, as Figure 10As shown, when aluminum (Al) is added to the insulating film IF1 formed in region 1Ap, aluminum (Al) is also added to the insulating film IF2 formed in region 2An. Therefore, the number of manufacturing steps in the semiconductor device can be reduced. Furthermore, the number (ratio, concentration) of the metal (here, hafnium) to be added to the insulating film IF2 formed in region 2Ap can be made substantially the same as the number (ratio, concentration) of the metal (here, aluminum) to be added to the insulating film IF1 formed in region 1An. Similarly, the number (ratio, concentration) of the metal (here, aluminum) to be added to the insulating film IF2 formed in region 2An can be made substantially the same as the number (ratio, concentration) of the metal (here, hafnium) to be added to the insulating film IF1 formed in region 1Ap.

[0145] <Modification Example of This Embodiment>

[0146] Next, a description of a modified example of the above embodiments will be given.

[0147] (First Modification Example)

[0148] First, in the above embodiments, the semiconductor device SMD1 has been described, wherein an insulating film to which aluminum (Al) is deposited (without adding hafnium (Hf) to an insulating film IF2 made of silicon oxide is used as the gate insulating film GI3 constituting the n-type field-effect transistor Q2n formed in region 2An, which is a bulk region 2BR, and an insulating film to which hafnium (Hf) is deposited (without adding aluminum (Al) to an insulating silicon IF2 made of silicon oxide is used as the gate insulating film GI4 constituting the p-type field-effect transistor Q2p formed in region 2Ap, which is a bulk region 2BR. However, as Figure 16 As shown, the insulating film IF2, made of silicon oxide and to which hafnium (Hf) and aluminum (Al) are added (deposited), can be used as the gate insulating film GI5 constituting each field-effect transistor Q2nm1 and Q2pm1. As described above, the n-type field-effect transistor Q2n and p-type field-effect transistor Q2p formed in the bulk region 2BR are field-effect transistors constituting the peripheral circuit, whose drive voltage is higher than the drive voltage of the SRAM circuit composed of each of the n-type field-effect transistor Q1n and p-type field-effect transistor Q1p formed in the SOI region 1SR. That is, the drive voltage of each field-effect transistor formed in the bulk region 2BR is higher than the drive voltage of each field-effect transistor formed in the SOI region 1SR. Therefore, when it is desired to produce a semiconductor device SMD2 that also considers the above-mentioned NBTI, as... Figure 16As shown, a gate insulating film GI5 is preferably used, wherein the ratio of the number of hafnium atoms constituting the gate insulating film GI5 to the total number of atoms constituting the metal film HK3 is 75% or higher and less than 100%. The gate insulating film GI5 is an insulating film IF2 on which a metal film made of hafnium (Hf) and aluminum (Al) is formed (deposited). Furthermore, the NBTI described above specifically occurs in p-type field-effect transistors. Therefore, the bulk region 2BR and the region 2An in which an n-type field-effect transistor is formed can use the gate insulating film GI3 described above, or the gate insulating film GI5; and the bulk region 2BR and the region 2Ap in which a p-type field-effect transistor is formed can use the gate insulating film GI6.

[0149] (Second Modification Example)

[0150] In the embodiments and the first modified example mentioned above, the insulating film to which the added metal ("aluminum" in the embodiments mentioned above, "insulating film IF1" located in region 1Ap) is covered by a mask, and the insulating film to which another metal ("hafnium" in the embodiments mentioned above) is added ("insulating film IF1" located in region 1An in the embodiments mentioned above) is not covered by the mask, and therefore the insulating film exposed by removing the mask is used as the gate insulating film. However, the gate insulating film can be... Figures 17 to 28 The manufacturing method shown is used to form it.

[0151] Regarding the details, firstly, execution. Figure 17 Steps S11 to S13 are shown in the diagram. Here, because... Figure 17 Steps S11 to S13 shown are the same as those in the above embodiments. Figure 5 Steps S1 to S3 shown are the same, so the descriptions of steps S11 to S13 are omitted. Furthermore, Figure 17 The process flowchart shown is based on the process flowchart of the semiconductor device SMD2, which is the first modified example above.

[0152] Next, as Figure 17 In step S14 shown, aluminum and hafnium are both added to the insulating film IF1 located in each of regions 1An and 1Ap, which are SOI regions 1SR, and are added to the insulating film IF2 located in each of regions 2An and 2Ap, which are block regions 2BR. Therefore, as Figure 18 As shown, a metal film HK3 made of aluminum and hafnium was formed on insulating films IF1 and IF2.

[0153] Next, as Figure 17 Step S15 as shown, as Figure 19As shown, each region 1An is an SOI region 1SR, with an insulating film 1F located in 1Ap. Each region 2An is a bulk region 2BR, thereby covering the insulating film IF2 located in 2Ap. Each region 1An is an SOI region 1SR, and a semiconductor layer SL is located in 1Ap. Each region 2An is a bulk region 2BR, forming a semiconductor material PS1 on the semiconductor substrate material BM located in 2Ap. Incidentally, the semiconductor material PS1 is made of polycrystalline silicon, for example (specifically, doped polycrystalline silicon impurities or atomic implantation are introduced).

[0154] Next, as Figure 17 Step S16 as shown, as Figure 20 As shown, the semiconductor material PS1 located in region 1Ap, which forms the p-type field-effect transistor Q1p, and the insulating film IF1 located in region 1Ap and to which aluminum and hafnium are added, are removed, thereby retaining the semiconductor material PS1 located in regions 1An, 2An, and 2Ap. Therefore, the semiconductor layer SL located in region 1Ap is exposed.

[0155] Next, as Figure 17 Step S17 as shown, as Figure 21 As shown, using the semiconductor layer SL located in region 1An and the semiconductor substrate material BM located in regions 2An and 2Ap (bulk region 2BR) covered by semiconductor material PS1, an insulating film IF1 made of silicon oxide is formed again on the semiconductor layer located in region 1Ap where the p-type field-effect transistor Q1p is formed.

[0156] Next, as Figure 17 In step S18 shown, aluminum is added to the insulating film IF1 in region 1Ap, which forms the p-type field-effect transistor Q1p, using the semiconductor layer SL located in region 1An and the semiconductor substrate material BM located in regions 2An and 2Ap (bulk region 2BR) covered by semiconductor material PS1. Therefore, as Figure 22 As shown, a metal film HK2 made of aluminum is formed (deposited) on an insulating film IF1 located in region 1Ap. Figure 22 As shown, a metal film HK2 is also formed (deposited) on the semiconductor material PS1 located in the corresponding regions 1An, 2An and 2Ap.

[0157] Next, as Figure 17 Step S19 as shown, Figure 23 As shown, the semiconductor layer SL is located in region 1An, and each region 2An is a block region 2BR. While the semiconductor substrate material BM located in region 2Ap is covered with semiconductor material PS1, semiconductor material SP1 is formed again on the insulating film IF1 located in region 1Ap and to which aluminum is added. Incidentally, as Figure 22As shown, semiconductor material PS1 is formed (deposited) on semiconductor material PS1 located in the corresponding regions 1An, 2An, and 2Ap.

[0158] Next, as Figure 17 Step S20 as shown, Figure 24 As shown, the semiconductor material PS1 located in region 1An, where the n-type field-effect transistor Q1n is formed, and the insulating film IF1 located in region 1An and to which aluminum and hafnium are added, are removed, thereby leaving the semiconductor material PS1 in regions 1Ap, 2An, and 2Ap. Therefore, the semiconductor layer SL in region 1An is exposed.

[0159] Next, as Figure 17 Step S21 shown is as follows Figure 25 As shown, using the semiconductor layer SL located in region 1Ap and the insulating layer IF1 made of silicon oxide located in regions 2Ap and 2Ap, the semiconductor substrate material BM is formed again on the semiconductor layer SL located in region 1An where the n-type field-effect transistor Q1n is formed, and regions 2Ap and 2Ap are block regions 2BR covered by semiconductor material PS1.

[0160] Next, as Figure 17 In step S22 shown, hafnium is added to the insulating film IF1 in region 1An, which forms the n-type field-effect transistor Q1n, using the semiconductor layer SL located in region 1Ap and the semiconductor substrate material BM located in regions 2Ap and 2Ap. Regions 2Ap and 2Ap are blocky regions 2BR covered by semiconductor material PS1. Therefore, as Figure 26 As shown, a metal film HK1 is also formed (deposited) on the semiconductor material PS1 located in the corresponding regions 1Ap, 2An and 2Ap.

[0161] Next, as Figure 17 Step S23 shown, as Figure 27 As shown, the semiconductor layer SL is located in region 1Ap, and each region 2An is a block region 2BR. While the semiconductor substrate material BM in region 2Ap is covered with semiconductor material PS1, semiconductor material SP1 is formed again on the insulating film IF1 in region 1An, which is covered with hafnium. Incidentally, as Figure 27 As shown, semiconductor material PS1 is formed (deposited) on semiconductor material PS1 located in the corresponding regions 1Ap, 2An, and 2Ap.

[0162] Next, as Figure 17In step S24 shown, corresponding regions 1An, 1Ap, and 2An are used to form gate electrodes GE1, GE2, GE3, and GE4 in 2Ap. Incidentally, as a pretreatment for forming gate electrodes GE1, GE2, GE3, and GE4, such as... Figure 28 As shown, unwanted semiconductor material PS1 is removed, for example, by a CMP or etching process. The remaining semiconductor material PS1 is then patterned into the desired geometry. Subsequently, gate electrodes GE1, GE2, GE3, and GE4 are formed by patterning insulating films IF1 and IF2, which serve as masks, to remove portions exposed from the corresponding gate electrodes GE1, GE2, GE3, and GE4. Therefore, as Figure 16 As shown, the gate electrode GE1 is formed on the semiconductor layer SL located in region 1An via a gate insulating film GI1 (i.e., a film composed of an insulating film IF1 and a metal film HK1 formed on the insulating film IF1). The gate insulating film GI1 is formed by adding hafnium (Hf) to the insulating film IF1 located in region 1An without adding aluminum (Al). Moreover, as Figure 16 As shown, the gate electrode GE2 is formed on the semiconductor layer SL located in region 1Ap via a gate insulating film GI2 (i.e., a film composed of an insulating film IF1 and a metal film HK2 formed on the insulating film IF1). The gate insulating film GI2 is formed by adding aluminum (Al) to the insulating film IF1 located in region 1Ap without adding hafnium (Hf). Moreover, as Figure 16 As shown, the gate electrode GE3 is formed on the semiconductor substrate material BM located in region 2An via a gate insulating film GI5 (i.e., a film composed of an insulating film IF2 and a metal film HK3 formed on the insulating film IF2). The gate insulating film GI5 is formed by adding aluminum (Al) and hafnium (Hf) to the insulating film located in region 2An. Furthermore, as... Figure 16 As shown, the gate electrode GE4 is formed on the semiconductor substrate material BM located in region 2Ap via the gate insulating film GI5 (i.e., a film composed of insulating film IF2 and metal film HK3 formed on insulating film IF2). The gate insulating film GI5 is formed by adding aluminum (Al) and hafnium (Hf) to the insulating film located in region 2Ap.

[0163] According to the manufacturing method of this second modified example, after forming the gate insulating film GI5 in each region 2An, 2Ap, which is a block region 2BR (i.e., in Figure 17After step S14 shown, until each gate electrode GE3, GE4 is formed in the corresponding regions 2An, 2Ap, the gate protection film GI5 is protected by the semiconductor material PS1. As described in the above embodiments, the mask MKS1, mask MSK2 and photoresist are not affected by the removal process. Further, after the gate insulating film GI2 is formed in region 1Ap, which is the SOI region 1SR (i.e., in Figure 17 After step S18 shown, until the gate electrode GE2 is formed in region 1Ap, the gate protection film GI2 is protected by the semiconductor material PS1. This is because, as described in the above embodiments, the mask MKS1 is not affected by the process of removing the mask MSK2 and photoresist. Furthermore, after the gate insulating film GI1 is formed in region 1An, which is SOI region 1SR (i.e., in…), Figure 17 Following step S22 (as shown), until the gate electrode GE1 is formed in region 1An, the gate protection film GI1 is protected by the semiconductor material PS1. As described in the above embodiments, the mask MKS1, mask MSK2, and photoresist are not affected by the removal process. Therefore, the reliability of the semiconductor device SMD2 can be improved.

[0164] In this second modified example, during execution Figure 17 In step S21, an insulating film IF1 made of silicon oxide is also formed on the sidewall of the semiconductor material PS1 retained in region 1Ap where the p-type field-effect transistor Q1p is formed. Therefore, when the gate electrode GE1 of the field-effect transistor Q1n and the gate electrode GE2 of the field-effect transistor Q1p are formed, as shown... Figure 29 As shown, the two gate electrodes GE1 and GE2 can be interconnected via an insulating film IF1 formed on the sidewall of the semiconductor material PS1. Therefore, the contact plug PG used to provide gate voltage to each gate electrode GE1 and GE2 is connected to only one gate electrode (e.g., gate electrode GE1), and can also provide gate voltage to the other gate electrodes (e.g., gate electrode GE2) through this single gate electrode. Incidentally, Figure 29 It is a cross-sectional view along the gate width direction of gate electrodes GE1 and GE2. Furthermore, Figure 1 and 16 It is a cross-sectional view along the gate length of each gate electrode GE1, GE2.

[0165] (Third Modification Example)

[0166] In the above embodiments, semiconductor device SMD1 has been described, including region 1An for forming an n-type field-effect transistor Q1n, region 1SRn having region 1TAn for providing a back gate voltage to the n-type field-effect transistor Q1n, region 1Ap for forming a p-type field-effect transistor Q1p, and region 1SRp having region 1TAp for providing a back gate voltage to the p-type field-effect transistor Q1p. However, in addition to the two field-effect transistors Q1n and Q1p described above, another field-effect transistor Q3n has a breakdown voltage higher than the two field-effect transistors Q1n and Q1p. Q3p is formed in SOI region 1SR, which can be semiconductor device SMD3.

[0167] Regarding details, such as Figure 30 As shown, in addition to the two regions 1SRn and 1SRp described above, the SOI region 1SR of the semiconductor device SMD3 includes region 3An in which another n-type field-effect transistor Q3n is formed, region 2SRn having region 2TAn for providing a back gate voltage to the n-type field-effect transistor Q3n, region 3Ap in which another p-type field-effect transistor Q3p is formed, and region 2SRp having region 2TAp for providing a back gate voltage to the p-type field-effect transistor Q3p.

[0168] like Figure 30 As shown, the n-type field-effect transistor Q3n formed in region 3An has essentially the same configuration as the n-type field-effect transistor Q1n formed in region 1An, except that a gate insulating film GI7 with a gate electrode GE5 is formed thereon. Similarly, the p-type field-effect transistor Q3p formed in region 3Ap has essentially the same configuration as the p-type field-effect transistor Q1p formed in region 1Ap, except that a gate insulating film GI7 with a gate electrode GE6 is formed thereon.

[0169] The driving voltage of the n-type field-effect transistor Q3n formed in region 3An and the p-type field-effect transistor Q3p formed in region 3Ap is, for example, 1.5V to 2.4V. That is, the driving voltage of each of the n-type field-effect transistor Q3n formed in region 3An and the p-type field-effect transistor Q3p formed in region 3Ap is higher than the driving voltage of each of the n-type field-effect transistor Q1n formed in region 1An and the p-type field-effect transistor Q1p formed in region 1Ap. The thickness of each gate insulating film GI7 constituting the n-type field-effect transistor Q3n formed in region 3An and the p-type field-effect transistor Q3p formed in region 3Ap is greater than the thickness of each gate insulating film GI2 constituting the n-type field-effect transistor Q1n formed in region 1An and the p-type field-effect transistor Q1p formed in region 1Ap.

[0170] The driving voltage of each of the n-type field-effect transistor Q3n formed in region 3An and the p-type field-effect transistor Q3p formed in region 3Ap is lower than the driving voltage of each of the n-type field-effect transistor Q2n formed in region 2An and the p-type field-effect transistor Q2p formed in region 2Ap. The thickness of each gate insulating film GI7 constituting the n-type field-effect transistor Q3n formed in region 3An and the p-type field-effect transistor Q3p formed in region 3Ap is less than the thickness of each gate insulating film GI4 constituting the n-type field-effect transistor Q2n formed in region 2An and the p-type field-effect transistor Q2p formed in region 2Ap.

[0171] As described above, the drive voltage of each field-effect transistor Q3n and Q3p formed in each region 2SRn, 2SRp is higher than the drive voltage of each field-effect transistor Q1n and Q1p formed in each region 1SRn, 1SRp. Therefore, if the drive voltage of each of the field-effect transistors Q3n and Q3p is too low, leakage current (subthreshold leakage current) may occur between the source and drain of each of the field-effect transistors Q3n and Q3p. Therefore, in the semiconductor device SMD3 of this third modified example, firstly, the insulating film IF1 of the gate insulating film GI1 constituting the n-type field-effect transistor Q1n is not filled with aluminum (Al), but with hafnium (Hf). When aluminum (Al) is added to the insulating film IF1 of the gate insulating film GI2 constituting the p-type field-effect transistor Q1p, hafnium (Hf) is not added. Furthermore, aluminum (Al) and hafnium (Hf) are added to the insulating film IF5 of the gate insulating film GI7 that makes up the field-effect transistors Q3n and Q3p. That is, in the case of... Figure 30 In the third modified example shown, a metal film HK3 made of hafnium (Hf) and aluminum (Al) is formed (deposited) on the insulating film IF5.

[0172] As described above, the driving voltage of each of the field-effect transistors Q3n and Q3p formed in each of the regions 2SRn and 2SRp, which are SOI regions 1SR, is lower than the driving voltage of each of the field-effect transistors Q2n and Q2p formed in each of the regions 2BRn and 2BRp, which are block regions 2BR. Therefore, if the driving voltage of each of the field-effect transistors Q3n and Q3p formed in each of the regions 2SRn and 2SRp, which are SOI regions 1SR, is set too high, it is difficult to increase the turn-on current flowing in the channel region of each of the field-effect transistors Q3n and Q3p. In other words, it is difficult to operate the field-effect transistors Q3n and Q3p at a high speed. Therefore, in the semiconductor device SMD3 of this third modified example, firstly, the insulating film IF1 of the gate insulating film GI1 constituting the n-type field-effect transistor Q1n is not filled with aluminum (Al), but with hafnium (Hf). Aluminum (Al) is added to the insulating film IF1 of the gate insulating film GI2 constituting the p-type field-effect transistor Q1p, while hafnium (Hf) is not added. Hafnium (Hf) is added to the insulating film IF2 of the gate insulating film GI4 constituting the p-type field-effect transistor Q2p, while aluminum (Al) is not added. Furthermore, for the insulating film IF5 of the gate insulating film GI7 constituting the field-effect transistors Q3n and Q3p, both aluminum (Al) and hafnium (Hf) are added. That is, in the case of... Figure 30 In the third modified example shown, a metal film HK3 made of hafnium (Hf) and aluminum (Al) is formed (deposited) on the insulating film IF5.

[0173] (Fourth Modification Example)

[0174] In the above embodiments, the first modified example, the second modified example, and the third modified example, aluminum (Al) was not added to the insulating film IF1 formed in region 1An of the n-type field-effect transistor Q1n, and hafnium (Hf) was not added to the insulating film IF1 formed in region 1Ap of the p-type field-effect transistor Q1p. However, not only hafnium (Hf), but aluminum (Al) can also be added to the insulating film IF1 formed in region 1An of the n-type field-effect transistor Q1n. In order to reduce the threshold voltage of the n-type field-effect transistor Q1n formed in region 1An, which is the SOI region 1SR, it is preferable to minimize the ratio of the number of aluminum atoms (Al) to the total number of aluminum atoms (Al) and hafnium atoms (Hf), such as... Figure 3 As shown. Furthermore, not only aluminum (Al), hafnium (Hf) can also be added to the insulating film IF1 formed in region 1Ap, which forms the p-type field-effect transistor Q1p. To reduce the threshold voltage of the p-type field-effect transistor Q1p formed in region 1Ap, which serves as the SOI region 1SR, as... Figure 4As shown, the ratio of the number of hafnium (Hf) atoms to the total number of aluminum (Al) and hafnium (Hf) atoms is preferably as small as possible. However, as described above, the number of metals added tends to vary when each metal is deposited, for example, by sputtering. Therefore, in addition to reducing the threshold voltage of the field-effect transistor, n-type and p-type field-effect transistors are formed in the SOI region of the substrate. If it is desired to improve the manufacturing yield of semiconductor devices, as in the above embodiment, aluminum (Al) is not added to the insulating film IF1 formed in region 1An of the n-type field-effect transistor Q1n, and preferably hafnium (Hf) is not added to the insulating film IF1 formed in region 1Ap of the p-type field-effect transistor Q1p.

[0175] (Fifth revision example)

[0176] In the above embodiments, in the first and second modified examples above, it has been described that after adding aluminum (Al) to the insulating film IF1 formed in region 1Ap of the p-type field-effect transistor Q1p, the process of forming the n-type field-effect transistor Q1n (see above) is performed. Figure 1 Hafnium (Hf) is added to the insulating film IF1 formed in region 1An of the n-type field-effect transistor Q1n. However, after the step of adding hafnium (Hf) to the insulating film IF1 formed in region 1An of the n-type field-effect transistor Q1n, the step of adding hafnium (Hf) to the insulating film IF1 formed in region 1An of the n-type field-effect transistor Q1n can be performed to form the p-type field-effect transistor Q1p (see [link to article]). Figure 1 The step of adding aluminum (Al) to the insulating film IF1 formed in region 1Ap.

[0177] (Sixth Modification Example)

[0178] Furthermore, in the embodiments described above, each gate electrode GE1, GE2, GE3, GE4 has been described as being made of, for example, polysilicon (particularly doped polysilicon in which impurities are introduced or atomically implanted). However, each gate electrode GE1, GE2, GE3, GE4 can be a gate electrode made of metal, such as aluminum (Al). Further, the gate electrodes GE1, GE2 of the field-effect transistors Q1n and Q1p formed in the SOI region 1SR, or the gate electrodes GE1, GE2 of the field-effect transistors Q2n and Q2p formed in the bulk region 2BR, can be gate electrodes made of the aforementioned metal. Therefore, the work function of this metal can further adjust the threshold voltage of the field-effect transistor.

[0179] The invention made by the inventors has been described in detail above based on the embodiments. However, the invention is not limited to the embodiments described above, and various modifications can be made without departing from its spirit.

[0180] For example, although various modification examples have been described above, some or all of the modification examples described above can be applied in combination with each other within the scope of the main points described above for each modification example.

Claims

1. A semiconductor device, comprising: Semiconductor substrate material having a first region, a second region, a third region, and a fourth region; An insulating layer is formed on the semiconductor substrate material located in each of the first and second regions; A semiconductor layer is formed on the insulating layer located in each of the first and second regions; The first gate electrode of the n-type first field-effect transistor is formed on the semiconductor layer located in the first region via a first gate insulating film; The second gate electrode of the p-type second field-effect transistor is formed on the semiconductor layer located in the second region via a second gate insulating film; The third gate electrode of the n-type third field-effect transistor is formed on the semiconductor substrate material located in the third region via a third gate insulating film; and The fourth gate electrode of the p-type fourth field-effect transistor, the fourth gate electrode being formed on the semiconductor substrate material located in the fourth region via a fourth gate insulating film. The first gate insulating film is made of silicon oxide and is an insulating film with hafnium added but no aluminum added. The second gate insulating film is made of silicon oxide and is an insulating film with added aluminum but no hafnium. The third gate insulating film is made of silicon oxide and has aluminum added to it. The fourth gate insulating film is made of silicon oxide and is an insulating film with added hafnium.

2. The semiconductor device according to claim 1, The thickness of each of the third gate insulating film and the fourth gate insulating film is greater than the thickness of each of the first gate insulating film and the second gate insulating film.

3. The semiconductor device according to claim 1, The thickness of the semiconductor layer in each of the first and second regions is 10 nm to 20 nm. The thickness of the insulating layer in each of the first and second regions is 10 nm to 20 nm. The first p-type well region is formed in the semiconductor substrate material located in the first region, such that the first well region is in contact with the insulating layer located in the first region. The second well region of type n is formed in the semiconductor substrate material located in the second region, such that the second well region is in contact with the insulating layer located in the second region. The first ground plane region of type p is formed in the first well region, such that the first ground plane region is in contact with the insulating layer located in the first region. The second ground plane region of type n is formed in the second well region, such that the second ground plane region is in contact with the insulating layer located in the second region. The concentration of impurities constituting the first ground plane region is higher than the concentration of impurities constituting the first well region, and The concentration of impurities constituting the second ground plane region is higher than the concentration of impurities constituting the second well region.

4. The semiconductor device according to claim 3, The first offset spacer layer is formed on the sidewall of the first gate electrode. The second offset spacer layer is formed on the sidewall of the second gate electrode. The epitaxial growth layer is formed on each of the following front surfaces: the front surface of the semiconductor layer located in the first region exposed from the first gate electrode and the first offset spacer layer, and the front surface of the semiconductor layer located in the second region exposed from the second gate electrode and the second offset spacer layer. The first gate electrode to the fourth gate electrode, the first offset spacer layer to the second offset spacer layer, and the epitaxial growth layer are covered by an interlayer insulating film. The contact holes are formed in the interlayer insulating film, and The contact hole is filled with a conductive material.

5. The semiconductor device according to claim 1, Each of the third gate insulating film and the fourth gate insulating film is made of silicon oxide and is an insulating film with both aluminum and hafnium added.

6. The semiconductor device according to claim 5, The ratio of the number of hafnium atoms constituting the fourth gate insulating film to the total number of aluminum atoms and hafnium atoms constituting the fourth gate insulating film is 75% or greater and less than 100%.

7. The semiconductor device according to claim 6, The ratio of the number of hafnium atoms constituting the third gate insulating film to the total number of aluminum atoms and hafnium atoms constituting the third gate insulating film is 75% or greater and less than 100%.

8. The semiconductor device according to claim 5, The semiconductor substrate material further comprises a fifth region and a sixth region. The fifth gate electrode of the n-type fifth field-effect transistor is formed on the semiconductor layer located in the fifth region via a fifth gate insulating film. The sixth gate electrode of the p-type sixth field-effect transistor is formed on the semiconductor layer located in the sixth region via a sixth gate insulating film. The thickness of each of the fifth and sixth gate insulating films is greater than the thickness of each of the first and second gate insulating films, and Each of the fifth gate insulating film and the sixth gate insulating film is made of silicon oxide and is an insulating film with both aluminum and hafnium added.

9. The semiconductor device according to claim 1, The semiconductor substrate material further comprises a fifth region and a sixth region. The fifth gate electrode of the n-type fifth field-effect transistor is formed on the semiconductor layer located in the fifth region via a fifth gate insulating film. The sixth gate electrode of the p-type sixth field-effect transistor is formed on the semiconductor layer located in the sixth region via a sixth gate insulating film. The thickness of each of the fifth and sixth gate insulating films is greater than the thickness of each of the first and second gate insulating films, and Each of the fifth gate insulating film and the sixth gate insulating film is made of silicon oxide and is an insulating film with both aluminum and hafnium added.

10. A method for manufacturing a semiconductor device, comprising: (a) Providing an SOI substrate, the SOI substrate having: In the first region, the first n-type field-effect transistor will be formed. In the second region, a p-type second field-effect transistor will be formed. In the third region, an n-type third field-effect transistor will be formed, and In the fourth region, a p-type fourth field-effect transistor will be formed, and the SOI substrate consists of the following: Semiconductor substrate materials, An insulating layer is formed on the semiconductor substrate material, and A semiconductor layer is formed on the insulating layer; (b) After (a), the semiconductor layer and the insulating layer located in each of the third and fourth regions are removed, thereby exposing the semiconductor substrate material located in each of the third and fourth regions; (c) After (b), a first insulating film made of silicon oxide is formed on the semiconductor layer in each of the first and second regions, and a second insulating film made of silicon oxide is formed on the semiconductor substrate material in each of the third and fourth regions; (d) After (c), a first mask is formed on the semiconductor layer located in the first region, such that the first insulating film located in the second region and the second insulating film located in the third region are exposed from the first mask, and such that the first insulating film located in the first region is covered by the first mask. (e) After (d), while the semiconductor layer in the first region is covered by the first mask, aluminum is added to each of the first insulating film in the second region and the second insulating film in the third region; (f) After (e), remove the first mask; (g) After (f), a second mask is formed on the semiconductor layer located in the second region, such that the first insulating film located in the first region and the second insulating film located in the fourth region are exposed from the second mask, and such that the first insulating film located in the second region is covered by the second mask. (h) After (g), while the semiconductor layer located in the second region is covered by the second mask, hafnium is added to each of the first insulating film located in the first region and the second insulating film located in the fourth region. (i) After (h), remove the second mask; and (j) Following (i), the first gate electrode of the n-type first field-effect transistor is formed on the semiconductor layer located in the first region via a first gate insulating film; the second gate electrode of the p-type second field-effect transistor is formed on the semiconductor layer located in the second region via a second gate insulating film; the third gate electrode of the n-type third field-effect transistor is formed on the semiconductor substrate material located in the third region via a third gate insulating film; and the fourth gate electrode of the p-type fourth field-effect transistor is formed on the semiconductor substrate material located in the fourth region via a fourth gate insulating film. The first gate insulating film is located in the first region and is a first insulating film with hafnium added but no aluminum added. The second gate insulating film is the first insulating film located in the second region and having aluminum added but no hafnium added. The third gate insulating film is the second insulating film located in the third region and to which aluminum has been added, and The fourth gate insulating film is the second insulating film located in the fourth region and to which hafnium has been added.

11. The method according to claim 10, The thickness of each of the third gate insulating film and the fourth gate insulating film is greater than the thickness of each of the first gate insulating film and the second gate insulating film.

12. The method of claim 10, further comprising: After (b) and before (c), A p-type first well region is formed in the semiconductor substrate material located in the first region, such that the first well region is in contact with the insulating layer located in the first region; and an n-type second well region is formed in the semiconductor substrate material located in the second region, such that the second well region is in contact with the insulating layer located in the second region. After forming the first well and the second well in the first region and the second region respectively, and before step (c), a p-type first ground plane region is formed in the first well region such that the first ground plane region contacts the insulating layer located in the first region, and an n-type second ground plane region is formed in the second well region such that the second ground plane region contacts the insulating layer located in the second region. The thickness of the semiconductor layer constituting the SOI substrate provided in (a) and located in each of the first and second regions is 10 nm to 20 nm. The thickness of the insulating layer, which constitutes the SOI substrate provided in (a) and is located in each of the first and second regions, is 10 nm to 20 nm. The concentration of impurities constituting the first ground plane region is higher than the concentration of impurities constituting the first well region, and The concentration of impurities constituting the second ground plane region is higher than the concentration of impurities constituting the second well region.

13. The method of claim 12, further comprising: After step (j), a first offset spacing layer is formed on the sidewall of the first gate electrode, and a second offset spacing layer is formed on the sidewall of the second gate electrode. After the first offset spacer layer and the second offset spacer layer are formed, an epitaxial growth process is performed on each of the following front surfaces: a first front surface of the semiconductor layer located in the first region exposed from the first gate electrode and the first offset spacer layer, and a second front surface of the semiconductor layer located in the second region exposed from the second gate electrode and the second offset spacer layer, thereby forming an epitaxial growth layer on each of the first front surface and the second front surface. After the epitaxial growth layer is formed, the epitaxial growth layer is covered with an interlayer insulating film; After covering the epitaxial growth layer with the interlayer insulating film, contact holes are formed in the interlayer insulating film; and After the contact hole is formed, it is filled with a conductive material, thereby forming a contact plug connected to the epitaxial growth layer.

14. The method according to claim 10, in, In (j), the third gate electrode is formed on the semiconductor substrate material located in the third region via the third gate insulating film formed by adding both aluminum and hafnium to the second insulating film located in the third region, and the fourth gate electrode is formed on the semiconductor substrate material located in the fourth region via the fourth gate insulating film formed by adding both aluminum and hafnium to the second insulating film located in the fourth region.

15. The method according to claim 14, The ratio of the number of hafnium atoms constituting the fourth gate insulating film to the total number of aluminum atoms and hafnium atoms constituting the fourth gate insulating film is 75% or greater and less than 100%.

16. The method according to claim 15, The ratio of the number of hafnium atoms constituting the third gate insulating film to the total number of aluminum atoms and hafnium atoms constituting the third gate insulating film is 75% or greater and less than 100%.

17. A method for manufacturing a semiconductor device, comprising: (a) Providing an SOI substrate having: In the first region, the first n-type field-effect transistor will be formed. In the second region, a p-type second field-effect transistor will be formed. In the third region, an n-type third field-effect transistor will be formed, and In the fourth region, a p-type fourth field-effect transistor will be formed, and the SOI substrate consists of the following: Semiconductor substrate materials, An insulating layer is formed on the semiconductor substrate material, and A semiconductor layer is formed on the insulating layer; (b) After (a), the semiconductor layer and the insulating layer located in each of the third and fourth regions are removed, thereby exposing the semiconductor substrate material located in each of the third and fourth regions; (c) After (b), a first insulating film made of silicon oxide is formed on the semiconductor layer in each of the first and second regions, and a second insulating film made of silicon oxide is formed on the semiconductor substrate material in each of the third and fourth regions; (d) After (c), aluminum and hafnium are added to each of the first insulating film located in each of the first and second regions and the second insulating film located in each of the third and fourth regions; (e) After (d), a first semiconductor material is formed on each of the semiconductor layers in each of the first and second regions and the semiconductor substrate material in each of the third and fourth regions, such that the first insulating film in each of the first and second regions and the second insulating film in each of the third and fourth regions are covered by the first semiconductor material; (f) After (e), the semiconductor layer in the second region is exposed by removing the first semiconductor material in the second region and the first insulating film in the second region to which both aluminum and hafnium are added, such that the first semiconductor material in each of the first, third and fourth regions is retained; (g) After (f), while the semiconductor layer in the first region and the semiconductor substrate material in each of the third and fourth regions are covered by the first semiconductor material, a third insulating film made of silicon oxide is formed on the semiconductor layer in the second region. (h) After (g), while the semiconductor layer in the first region and the semiconductor substrate material in each of the third and fourth regions are covered by the first semiconductor material, aluminum is added to the third insulating film in the second region; (i) After (h), while the semiconductor layer in the first region and the semiconductor substrate material in each of the third and fourth regions are covered by the first semiconductor material, a second semiconductor material is formed on the third insulating film in the second region, on which aluminum is added; (j) After (i), the semiconductor layer in the first region is exposed by removing the first semiconductor material in the first region and the first insulating film in the first region to which both aluminum and hafnium are added, such that the second semiconductor material in the second region and the first semiconductor material in each of the third and fourth regions are retained; (k) After (j), while the semiconductor layer located in the second region is covered by the second semiconductor material, and while the semiconductor substrate material located in each of the third and fourth regions is covered by the first semiconductor material, a fourth insulating film made of silicon oxide is formed on the semiconductor layer located in the first region. (l) After (k), while the semiconductor layer in the second region is covered by the second semiconductor material, and while the semiconductor substrate material in each of the third and fourth regions is covered by the first semiconductor material, hafnium is added to the fourth insulating film in the first region; (m) After (l), while the semiconductor layer in the second region is covered by the second semiconductor material, and while the semiconductor substrate material in each of the third and fourth regions is covered by the first semiconductor material, a third semiconductor material is formed on the fourth insulating film located in the first region and to which hafnium has been added; and (n) After (m), by patterning each of the first semiconductor material, the second semiconductor material, and the third semiconductor material, the first gate electrode of the n-type first field-effect transistor is formed on the semiconductor layer located in the first region via a fourth insulating film located in the first region and to which hafnium is added; the second gate electrode of the p-type second field-effect transistor is formed on the semiconductor layer located in the second region via the third insulating film located in the second region and to which aluminum is added; the third gate electrode of the n-type third field-effect transistor is formed on the semiconductor substrate material located in the third region via a second insulating film located in the third region and to which both aluminum and hafnium are added; and the fourth gate electrode of the p-type fourth field-effect transistor is formed on the semiconductor substrate material located in the fourth region via a second insulating film located in the fourth region and to which both aluminum and hafnium are added.

18. The method according to claim 17, in, In the (n) mentioned above, the thickness of each of the fourth insulating film located in the first region and the third insulating film located in the second region is less than the thickness of the second insulating film located in each of the third and fourth regions.

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