Display device and manufacturing method thereof

Abstract

Provided are a display device and a method for manufacturing the display device. The display device includes: a display area and a transmission area located on a substrate; and an intermediate area arranged between the display area and the transmission area and including a first sub-intermediate area and a second sub-intermediate area located between the first sub-intermediate area and the transmission area, wherein the number of layers of thin films stacked on the substrate in the first sub-intermediate area is different from the number of layers of thin films stacked on the substrate in the second sub-intermediate area.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0127161, filed on October 14, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of one or more embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0003] The use of display devices is becoming more diverse. In addition, the thickness and weight of display devices are decreasing, and the scope of their use is expanding.

[0004] As various functions connected to or incorporated into display devices have been added, the area occupied by the display region in such display devices has increased. As a method of increasing various functions while expanding the area, research has been conducted on display devices capable of arranging various components in the display region. Summary of the Invention

[0005] According to aspects of one or more embodiments, a display device having a transmissive region within a display region and a method for manufacturing the display device are provided. According to aspects of one or more embodiments, a display panel having a transmissive region within the display region, in which various components can be arranged, and a display device including the display panel are provided. However, these are provided merely as examples, and the scope of the disclosure is not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed presented embodiments.

[0007] According to one or more embodiments, a display device includes: a display area and a transmission area, which are located on a substrate; and an intermediate area, which is arranged between the display area and the transmission area and includes a first sub-intermediate area and a second sub-intermediate area located between the first sub-intermediate area and the transmission area, wherein the number of layers of thin films stacked on the substrate in the first sub-intermediate area is different from the number of layers of thin films stacked on the substrate in the second sub-intermediate area.

[0008] The number of layers of the thin films stacked on the substrate in the second sub-middle region may be less than the number of layers of the thin films stacked on the substrate in the first sub-middle region.

[0009] The display apparatus may further include an uneven pattern layer including a plurality of protrusions and grooves arranged on the substrate in the second sub-middle region.

[0010] The uneven pattern layer may include polysilicon.

[0011] The display area may include a thin film transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The uneven pattern layer may include the same material as that of the semiconductor layer and be arranged in the same layer as the semiconductor layer.

[0012] The display area may further include a display element including a pixel electrode connected to the thin film transistor, a counter electrode opposite to the pixel electrode, and an intermediate layer located between the pixel electrode and the counter electrode.

[0013] The uneven pattern layer may include SiON, SiO2 and SiN x any material in.

[0014] The uneven pattern layer may include a plurality of protrusions arranged in an island shape and spaced apart from each other.

[0015] The uneven pattern layer may have a plurality of linear protrusions arranged to cross in a grid shape.

[0016] The display device may also include components that communicate using optical and / or acoustic signals that pass through the transmissive region.

[0017] According to one or more embodiments, a method for manufacturing a display device includes: forming a display area on a substrate; forming a transmission area on the substrate; and forming an intermediate area between the display area and the transmission area, the intermediate area including a first sub-intermediate area and a second sub-intermediate area located between the first sub-intermediate area and the transmission area, wherein, in forming the intermediate area, the number of layers of thin films stacked on the substrate in the first sub-intermediate area is different from the number of layers of thin films stacked on the substrate in the second sub-intermediate area.

[0018] The number of layers of the thin films stacked on the substrate in the second sub-middle region may be less than the number of layers of the thin films stacked on the substrate in the first sub-middle region.

[0019] The manufacturing method of the display device may also include: forming a sacrificial layer on the substrate in the second sub-middle area; forming a thin film layer on the sacrificial layer above the second sub-middle area and the first sub-middle area; and irradiating a laser beam to the second sub-middle area to remove the sacrificial layer and the thin film layer stacked on the sacrificial layer.

[0020] The manufacturing method of the display device may further include forming an uneven pattern layer having a plurality of protrusions and grooves arranged therein in the second sub-middle area, wherein a sacrificial layer is formed on the uneven pattern layer so that the uneven pattern layer remains after removing the sacrificial layer and the thin film layer stacked on the sacrificial layer.

[0021] The uneven pattern layer may include polysilicon, SiON, SiO2 and SiN xany material in.

[0022] The forming of the display area may include forming a thin film transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode on a substrate, and the uneven pattern layer may include the same material as the semiconductor layer and be arranged in the same layer as the semiconductor layer.

[0023] The forming of the display area may include forming a display element including a pixel electrode connected to the thin film transistor, a counter electrode opposite to the pixel electrode, and an intermediate layer between the pixel electrode and the counter electrode.

[0024] The uneven pattern layer may be formed in a shape in which a plurality of protrusions are arranged apart from each other in an island shape.

[0025] The uneven pattern layer may be formed in a grid shape in which a plurality of linear protrusions cross each other.

[0026] The method of manufacturing a display device may further include arranging components that communicate using optical signals and / or acoustic signals that pass through the transmissive area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of the disclosed embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a perspective view of a display device according to an embodiment;

[0029] Figure 2A and Figure 2B is a cross-sectional view of a display device according to some embodiments;

[0030] Figures 3A to 3D is a cross-sectional view of a display panel according to some embodiments;

[0031] Figures 4A to 4D is a cross-sectional view of a display panel according to still other embodiments;

[0032] Figure 5A and Figure 5B is a plan view of a display panel according to some embodiments;

[0033] Figure 6 is an equivalent circuit diagram of a pixel of a display panel according to an embodiment;

[0034] Figure 7A and Figure 7B is a plan view of a portion of a display panel according to some embodiments;

[0035] Figure 8 It is along Figure 7A or Figure 7Ba cross-sectional view of the display panel taken along line VIII-VIII';

[0036] 9A to 9D It shows Figure 8 A cross-sectional view of a manufacturing process of a display panel;

[0037] Figure 10 is a cross-sectional view of a display panel according to another embodiment;

[0038] 11A to 11D It shows Figure 10 A cross-sectional view of a manufacturing process of a display panel;

[0039] Figure 11E and Figure 11F yes Figure 10 A plan view of an example of a deformable planar shape of an uneven pattern layer;

[0040] Figure 12 The input sensing layer is set in Figure 8 A cross-sectional view of a structure on a display panel; and

[0041] Figure 13 The input sensing layer is set in Figure 10 A cross-sectional view of the structure on the display panel. DETAILED DESCRIPTION

[0042] Reference will now be made in more detail to some embodiments, examples of which are shown in the accompanying drawings, wherein like reference numerals always represent like elements. In this respect, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments will be described below solely by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0043] Here, some example embodiments will be described in more detail with reference to the accompanying drawings. The same reference numerals are used to represent the same elements, and their repeated description will be omitted.

[0044] It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms.

[0045] An expression used in the singular includes the expression in the plural form unless it has an obviously different meaning in the context.

[0046] It will also be understood that the terms “comprises” and / or “comprising” as used herein indicate the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0047] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings may be arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0048] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order from the described order.

[0049] In the specification, the term "A and / or B" means the case of A or B or the case of A and B.

[0050] It will be understood that when a layer, region, or component is connected to another part, the layer, region, or component may be directly connected to the part or there may be one or more intermediate layers, intermediate regions, or intermediate components such that the layer, region, or component may be indirectly connected to the part. For example, when a layer, region, or component is electrically connected to another part, the layer, region, or component may be directly electrically connected to the part or may be indirectly connected to the part through another one or more layers, regions, or components.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments of the inventive concepts belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0052] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0053] Reference Figure 1 , the display device 1 according to the embodiment may include a first area OA as a transmissive area and a display area DA as a second area at least partially surrounding the first area OA. The display device 1 may provide a certain image using light emitted from a plurality of pixels arranged in the display area DA. As an example, Figure 1 It is shown that a first area OA can be arranged inside the display area DA, wherein the first area OA can be completely surrounded by the display area DA. The first area OA can be arranged with Figure 2A and Figure 2BThe area of ​​component 20 is described.

[0054] The middle area MA is arranged as a third area between the first area OA and the display area DA as the second area, and the display area DA may be surrounded by the peripheral area PA as the fourth area. The middle area MA and the peripheral area PA may be a type of non-display area in which no pixels are arranged. In an embodiment, the middle area MA may be surrounded by (e.g., completely surrounded by) the display area DA, and the display area DA may be surrounded by (e.g., completely surrounded by) the peripheral area PA.

[0055] Here, an organic light emitting display device is described as an example of the display device 1 according to the embodiment, but the disclosed display device is not limited thereto. As another embodiment, a display device such as a quantum dot light emitting display may be used.

[0056] Although Figure 1 It is shown that one first area OA is provided and the first area OA is substantially circular, but the disclosure is not limited thereto. The number of first areas OA may be two or more, and the shape of each of the first areas OA may vary and may have, for example, a circular, elliptical, polygonal, star-shaped, or diamond-shaped shape.

[0057] Figure 2A and Figure 2B is a cross-sectional view schematically showing a display device 1 according to some embodiments, and can be compared with Figure 1 It corresponds to the cross section of the display device 1 taken along line II-II'. Figure 2A and Figure 2B The cross-sectional view represents a view defined in the xz plane.

[0058] Reference Figure 2A In an embodiment, a display device 1 may include a display panel 10, an input sensing layer 40 located on the display panel 10, and an optical functional layer 50 that may be covered with a window 60. The display device 1 may be any of various electronic devices such as a mobile phone, a notebook computer, and a smart watch.

[0059] The display panel 10 can display an image. The display panel 10 includes pixels arranged in a display area DA. The pixels may include display elements and pixel circuits connected thereto. The display elements may include organic light emitting diodes, quantum dot organic light emitting diodes, etc.

[0060] The input sensing layer 40 obtains coordinate information based on external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be located on the display panel 10. The input sensing layer 40 may sense external inputs using a mutual capacitance method and / or a self-capacitance method.

[0061] The input sensing layer 40 may be formed directly on the display panel 10, or may be formed separately and then bonded to the display panel 10 via an adhesive layer (such as an optically clear adhesive). For example, the input sensing layer 40 may be formed continuously after the process of forming the display panel 10. In this case, the input sensing layer 40 may be part of the display panel 10, and the adhesive layer may not be located between the input sensing layer 40 and the display panel 10. Although Figure 2A The input sensing layer 40 is shown to be located between the display panel 10 and the optical functional layer 50 . However, in another embodiment, the input sensing layer 40 may be located on the optical functional layer 50 .

[0062] In an embodiment, the optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display panel 10 through the window 60. In an embodiment, the anti-reflection layer may include a retarder and a polarizer. The retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a certain arrangement. The retarder and the polarizer may also include a protective film. The protective film of the retarder and the polarizer may be defined as a base layer of the anti-reflection layer.

[0063] In another embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged taking into account the color of light emitted from each pixel of the display panel 10. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located on the corresponding layer. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere, thereby reducing the external light reflectivity.

[0064] In an embodiment, the optical function layer 50 may include a lens layer. The lens layer may improve the luminous efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave lens or a convex lens shape and / or may include multiple layers having different refractive indices. The optical function layer 50 may include all or any one of the above-mentioned anti-reflection layer and lens layer.

[0065] In an embodiment, the optical function layer 50 may be formed continuously after the process of forming the display panel 10 and / or the input sensing layer 40. In this case, the adhesive layer may not be located between the optical function layer 50 and the display panel 10 and / or the input sensing layer 40.

[0066] In an embodiment, the display panel 10, the input sensing layer 40 and / or the optical functional layer 50 may include an opening. Figure 2A The display panel 10, the input sensing layer 40, and the optical function layer 50 are shown to include a first opening 10H, a second opening 40H, and a third opening 50H, respectively, and the first opening 10H, the second opening 40H, and the third opening 50H overlap each other. The first opening 10H, the second opening 40H, and the third opening 50H are positioned corresponding to the first area OA. In another embodiment, one or more of the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. For example, any one or more selected from the display panel 10, the input sensing layer 40, and the optical function layer 50 may not include an opening. Figure 2B As shown in , in an embodiment, for example, the display panel 10 , the input sensing layer 40 , and the optical function layer 50 may not include openings.

[0067] As described above, the first area OA may be a component area (eg, a sensor area, a camera area, a speaker area, etc.) in which a component 20 for adding any of various functions to the display device 1 is located. Figure 2A As shown in FIG, in an embodiment, the component 20 can be located in the first opening 10H, the second opening 40H and the third opening 50H. Figure 2B As shown in , in another embodiment, the component 20 may be located below the display panel 10 .

[0068] The component 20 may include an electronic component. For example, the component 20 may include an electronic component that utilizes light or sound. For example, the electronic component may include a sensor that outputs and / or receives light (such as an infrared sensor), a camera that captures an image by receiving light, a sensor that outputs and detects light or sound to measure distance or recognize a fingerprint, a small lamp that outputs light, a speaker that outputs sound, and the like. In the case of an electronic component using light, light of various wavelengths such as visible light, infrared light, ultraviolet light, and the like can be used. In some embodiments, the first area OA may be a transmission area in which light and / or sound output from the component 20 to the outside or traveling from the outside toward the electronic component can be transmitted.

[0069] In another embodiment, when the display device 1 is used as a smartwatch or a vehicle instrument panel, the component 20 may be a member such as a watch hand or a pointer indicating certain information (e.g., vehicle speed, etc.). In an embodiment, when the display device 1 includes a watch hand or a pointer indicating certain information (e.g., vehicle speed, etc.), the component 20 may be exposed to the outside through the window 60, and the window 60 may include an opening corresponding to the first area OA.

[0070] The assembly 20 may include one or more components associated with the functions of the display panel 10 as described above, or may include one or more components such as accessories that increase the aesthetics of the display panel 10. Figure 2Aand Figure 2B Not shown, but in embodiments, an optically clear adhesive may be located between the window 60 and the optically functional layer 50 .

[0071] Figures 3A to 3D is a cross-sectional view of a display panel 10 according to some embodiments.

[0072] Reference Figure 3A The display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include a glass material or a polymer resin. In an embodiment, the substrate 100 may be multi-layered. For example, Figure 3A As shown in the enlarged region of FIG, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104.

[0073] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, the first base layer 101 and the second base layer 103 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc. The above polymer resin may be transparent.

[0074] Each of the first barrier layer 102 and the second barrier layer 104 includes a barrier layer for preventing or substantially preventing penetration of external foreign matter, and may include a material containing silicon nitride (SiN x , x>0) or silicon oxide (SiO x , x>0) of a single layer or multiple layers of inorganic materials.

[0075] The display layer 200 includes a plurality of pixels. The display layer 200 may include a display element layer 200A and a pixel circuit layer 200B. The display element layer 200A includes a display element arranged for each pixel, and the pixel circuit layer 200B includes a pixel circuit and an insulating layer arranged for each pixel. Each pixel circuit may include a thin film transistor and a storage capacitor, and each display element may include an organic light-emitting diode (OLED).

[0076] The display element of the display layer 200 may be covered by an encapsulation member such as a thin film encapsulation layer 300. In an embodiment, the thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display panel 10 includes the substrate 100 including a polymer resin and the thin film encapsulation layer 300 including the inorganic encapsulation layer and the organic encapsulation layer, the flexibility of the display panel 10 may be improved.

[0077] The display panel 10 may include a first opening 10H penetrating the display panel 10. The first opening 10H may be located in the first area OA, and in this case, the first area OA may be a type of opening area. Figure 3A The substrate 100 and the thin film encapsulation layer 300 are shown to include through holes 100H and 300H, respectively, corresponding to the first opening 10H of the display panel 10. The display layer 200 may also include a through hole 200H corresponding to the first area OA.

[0078] In another embodiment, Figure 3B As shown in , the substrate 100 may not include a through hole corresponding to the first area OA. The display layer 200 may include a through hole 200H corresponding to the first area OA. The thin film encapsulation layer 300 may not include a through hole corresponding to the first area OA. In another embodiment, as Figure 3C As shown in FIG, the display layer 200 may not include the through hole 200H corresponding to the first area OA, and the display element layer 200A is not located in the first area OA.

[0079] Figures 3A to 3C The display element layer 200A is shown as not being arranged in the first area OA, but the disclosed embodiments are not limited thereto. In another embodiment, as shown in FIG. Figure 3D As shown in FIG, the auxiliary display element layer 200C may be located in the first area OA. The auxiliary display element layer 200C may include display elements that have a different structure and / or operate in a different manner than the display elements of the display element layer 200A.

[0080] In an embodiment, each pixel of the display element layer 200A may include an active organic light-emitting diode, and the auxiliary display element layer 200C may include pixels each including a passive organic light-emitting diode. When the auxiliary display element layer 200C includes a passive organic light-emitting diode as a display element, the elements constituting the pixel circuit may not be located below the passive organic light-emitting diode. For example, the portion of the pixel circuit layer 200B located below the auxiliary display element layer 200C does not include a transistor and a storage capacitor.

[0081] In another embodiment, the auxiliary display element layer 200C may include a display element of the same type as the display element of the display element layer 200A (e.g., an active organic light emitting diode), but the pixel circuits thereunder may be different. For example, the pixel circuit below the auxiliary display element layer 200C (e.g., a pixel circuit having a light-shielding film between the substrate and the transistor) may include a structure different from the structure of the pixel circuit below the display element layer 200A. In an embodiment, the display element of the auxiliary display element layer 200C may be operated according to a control signal different from the control signal of the display element of the display element layer 200A. In an embodiment, components that do not require relatively high transmittance (e.g., infrared sensors, etc.) may be arranged in the first area OA in which the auxiliary display element layer 200C is arranged. In this case, the first area OA may be a component area and an auxiliary display area.

[0082] Figures 4A to 4D is a cross-sectional view of a display panel 10' according to some other embodiments. Figures 3A to 3D The display panel 10 described is different, Figures 4A to 4D The display panel 10 ′ may include an encapsulation substrate 300A and a sealant 340 .

[0083] like Figures 4A to 4C As shown in FIG, one or more of the substrate 100, the display layer 200, and the encapsulation substrate 300A may have through holes 100H, 200H, and 300AH corresponding to the first area OA, respectively. The display element layer 200A may not be arranged in the first area OA, or the auxiliary display element layer 200C may be arranged as shown in FIG. Figure 4D As shown in FIG, it is arranged in the first area OA. Figure 3D The auxiliary display element layer 200C is described.

[0084] Figure 5A and Figure 5B is a plan view of a display panel 10 according to some embodiments; Figure 6 is an equivalent circuit diagram of a pixel P of the display panel 10 according to an embodiment.

[0085] Reference Figure 5A , the display panel 10 may include a first area OA, a display area DA as a second area, a middle area MA as a third area, and a peripheral area PA as a fourth area. Figure 5A It can be understood as a view of the substrate 100 of the display panel 10. For example, the substrate 100 may have a first area OA, a display area DA, a middle area MA, and a peripheral area PA.

[0086] The display panel 10 includes a plurality of pixels P arranged in a display area DA. Figure 6As shown in FIG, each pixel P may include a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC as a display element. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, or blue light from the organic light emitting diode OLED. In another embodiment, each pixel P may emit, for example, red light, green light, blue light, or white light from the organic light emitting diode OLED.

[0087] The second thin film transistor T2 is a switching thin film transistor connected to the scan line SL and the data line DL, and can be configured to transmit a data voltage input from the data line DL to the first thin film transistor T1 based on a switching voltage input from the scan line SL. The storage capacitor Cst is connected to the second thin film transistor T2 and the driving voltage line PL, and can store a voltage corresponding to a difference between a voltage received from the second thin film transistor T2 and the first power supply voltage ELVDD supplied to the driving voltage line PL.

[0088] The first thin film transistor T1 is a driving thin film transistor connected to the driving voltage line PL and the storage capacitor Cst. It can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED emits light with a certain brightness according to the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can be supplied with a second power supply voltage ELVSS.

[0089] Figure 6 The pixel circuit PC is shown to include two thin film transistors and one storage capacitor, but the disclosure is not limited thereto. The number of thin film transistors and the number of storage capacitors can be varied depending on the design of the pixel circuit PC. For example, in addition to the two thin film transistors mentioned above, the pixel circuit PC can also include four or more thin film transistors.

[0090] Refer again Figure 5A In an embodiment, the middle area MA may surround the first area OA in a plane. The middle area MA is an area in which no display element emitting light (such as an organic light emitting diode OLED) is arranged, and signal lines that provide signals to pixels P located around the first area OA may pass through the middle area MA. The peripheral area PA may include a scan driver 1100 for providing a scan signal to each pixel P, a data driver 1200 for providing a data signal to each pixel P, and a main power line (not shown) for providing a first power supply voltage ELVDD and a second power supply voltage ELVSS. Figure 5AThe data driver 1200 is shown adjacent to one side of the substrate 100. However, according to another embodiment, the data driver 1200 may be located on a flexible printed circuit board (FPCB) electrically connected to a pad (also referred to as a "pad" or "solder pad") located on one side of the display panel 10. Figure 5A shows a structure in which the first area OA is arranged on the upper left side of the display area DA, but Figure 5B As shown in , for example, the first area OA may also be located at the top center of the display area DA.

[0091] Figure 7A and Figure 7B is a plan view of a portion of a display panel according to some embodiments.

[0092] Reference Figure 7A , the pixels P are arranged in the display area DA around the transmission area OA. Some pixels P may be separated from each other relative to the transmission area OA, and the transmission area OA may be defined between the pixels P. For example, the pixels P may be arranged above and below or on the left and right sides of the transmission area OA, respectively.

[0093] A signal line adjacent to the transmission area OA among signal lines for supplying signals to the pixels P may bypass the transmission area OA. Figure 7A At least one of the data lines DL crossing the display area DA on the plane of FIG. 1 extends in the y direction to provide data signals to the pixels P arranged above and below the transmission area OA, and may be detoured along the edge of the transmission area OA in the middle area MA. Figure 7A At least one of the scan lines SL crossing the display area DA on the plane of the display area DA extends in the x direction to provide scan signals to the pixels P on the left and right sides of the transmission area OA and may detour along the edge of the transmission area OA in the middle area MA.

[0094] In an embodiment, the bypass portion (or detour portion) SL-D of the scan line SL and the extension portion SL-L passing through the display area DA are located on the same layer and may be formed integrally. In an embodiment, the bypass portion DL-D1 of at least one of the data lines DL may be formed on a layer different from the layer of the extension portion DL-L1 passing through the display area DA. The bypass portion DL-D1 and the extension portion DL-L1 of the data line DL may be connected to each other through a contact hole CNT. In an embodiment, the bypass portion DL-D2 of at least one of the data lines DL is located on the same layer as the extension portion DL-L2 and may be formed integrally.

[0095] In an embodiment, Figure 7BAs shown in FIG, the scan line SL can be cut off near the left and right sides of the transmissive area OA without a bypass portion. That is, the scan drivers 1100 described above can be arranged one by one on the left and right sides of the display area DA, so that the pixels P located on the left side of the transmissive area OA can be connected to the scan driver 1100 located on the left side, and the pixels P located on the right side of the transmissive area OA can be connected to the scan driver 1100 located on the right side. In this case, the scan line SL does not need to be connected as one line while bypassing the transmissive area OA.

[0096] Figure 8 is a cross-sectional view of a display panel 10-1 according to an embodiment, and can be compared with Figure 7A or Figure 7B The cross section of the display panel taken along line VIII-VIII' corresponds to the cross section of the display panel; 9A to 9D It shows Figure 8 sectional views of a manufacturing process of the display panel 10 - 1 .

[0097] Reference Figure 8 For the display area DA, the substrate 100 may include a glass material or a polymer resin. Figure 3A As shown in the enlarged region of FIG, in an embodiment, the substrate 100 may include a plurality of sub-layers.

[0098] The buffer layer 201 may be formed on the substrate 100 to prevent or substantially prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 may include an inorganic insulating material such as any one of silicon nitride, silicon oxynitride, and silicon oxide, and may include a single layer or multiple layers including the inorganic insulating material described above.

[0099] The pixel circuit PC may be located on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 8 The thin film transistor TFT shown in FIG can be compared with the reference Figure 6 The driving thin film transistor described corresponds to Figure 8 Although not shown, the data line DL of the pixel circuit PC is electrically connected to the switching thin film transistor included in the pixel circuit PC. This embodiment shows a top-gate transistor, in which the gate electrode GE is located above the semiconductor layer Act, and a gate insulating layer 203 is provided between the gate electrode GE and the semiconductor layer Act. However, according to another embodiment, the thin film transistor TFT may also be a bottom-gate transistor.

[0100] In an embodiment, the semiconductor layer Act may include polycrystalline silicon. In another embodiment, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), etc. The gate electrode GE may include a single layer or multiple layers including the materials described above.

[0101] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The gate insulating layer 203 may include a single layer or multiple layers including the above-described materials.

[0102] The source electrode SE and the drain electrode DE may be located on the same layer as the data line DL and may include the same material as that of the data line DL. The source electrode SE, the drain electrode DE, and the data line DL may include a material having high conductivity. The source electrode SE and the drain electrode DE may include a conductive material including Mo, Al, Cu, Ti, etc., and may be formed as a single layer or multiple layers including the materials described above. In an embodiment, the source electrode SE, the drain electrode DE, and the data line DL may include a multilayer of Ti / Al / Ti.

[0103] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 stacked on each other with a first interlayer insulating layer 205 therebetween. The storage capacitor Cst may be stacked with the thin film transistor TFT. In this regard, Figure 8 The gate electrode GE of the thin film transistor TFT is shown as the lower electrode CE1 of the storage capacitor Cst. In another embodiment, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered with a second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may include a conductive material including Mo, Al, Cu, Ti, etc. The source electrode SE and the drain electrode DE may include a single layer or multiple layers including the above materials.

[0104] The first and second interlayer insulating layers 205 and 207 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first and second interlayer insulating layers 205 and 207 may include a single layer or multiple layers including the above materials.

[0105] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered with a first organic insulating layer 209. The first organic insulating layer 209 may include a substantially flat top surface.

[0106] The pixel circuit PC may be electrically connected to the pixel electrode 221. For example, Figure 8 As shown in , the contact metal layer CM may be located between the thin film transistor TFT and the pixel electrode 221. The contact metal layer CM may be connected to the thin film transistor TFT through a contact hole formed in the first organic insulating layer 209, and the pixel electrode 221 may be connected to the contact metal layer CM through a contact hole formed in the second organic insulating layer 211 on the contact metal layer CM. The contact metal layer CM may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The contact metal layer CM may include a single layer or multiple layers including the materials described above. In an embodiment, the contact metal layer CM may include a multilayer of Ti / Al / Ti.

[0107] The first organic insulating layer 209 and the second organic insulating layer 211 may include an organic insulating material such as a general commercial polymer (such as any polymer among polymethyl methacrylate (PMMA) and polystyrene (PS), a polymer derivative including a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine-based polymer, a paraxylene-based polymer, a vinyl alcohol polymer, and a blend thereof. In an embodiment, the first organic insulating layer 209 and the second organic insulating layer 211 may include polyimide.

[0108] The pixel electrode 221 may be formed on the second organic insulating layer 211. The pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) and / or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode 221 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a mixture thereof. In another embodiment, the pixel electrode 221 may further include a film formed of ITO, IZO, ZnO or In2O3 above / below the reflective layer described above.

[0109] The pixel defining layer 215 may be formed on the pixel electrode 221. The pixel defining layer 215 may include an opening that exposes a portion of the upper surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. The pixel defining layer 215 may include an organic insulating material. Alternatively, the pixel defining layer 215 may include an organic insulating material such as silicon nitride (SiN x ), silicon oxynitride (SiON) or silicon oxide (SiO x In an embodiment, the pixel defining layer 215 may include an organic insulating material and an inorganic insulating material.

[0110] The intermediate layer 222 includes a light emitting layer 222b. The intermediate layer 222 may include a first functional layer 222a below the light emitting layer 222b and / or a second functional layer 222c above the light emitting layer 222b. The light emitting layer 222b may include a polymer organic material or a low molecular weight organic material that emits light of a certain color.

[0111] The first functional layer 222a may include a single layer or multiple layers. For example, when the first functional layer 222a includes a polymer, the first functional layer 222a may include a hole transport layer (HTL) having a single layer structure, and may include 3,4-ethylenedihydroxythiophene (PEDOT) or polyaniline (PANI). In an embodiment, when the first functional layer 222a is formed of a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0112] In an embodiment, the second functional layer 222c may be omitted. For example, when the first functional layer 222a and the light emitting layer 222b include a polymer material, the second functional layer 222c may be formed. The second functional layer 222c may include a single layer or multiple layers. In an embodiment, the second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0113] The light emitting layer 222b in the intermediate layer 222 may be arranged for each pixel in the display area DA. In an embodiment, the light emitting layer 222b may be patterned to correspond to the pixel electrode 221. In an embodiment, unlike the light emitting layer 222b, the first functional layer 222a and / or the second functional layer 222c of the intermediate layer 222 may extend toward the middle area MA to be located not only in the display area DA but also in the middle area MA.

[0114] The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a (semi) transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca) or an alloy thereof. In an embodiment, the counter electrode 223 may further include a layer such as ITO, IZO, ZnO or In2O3 located on the (semi) transparent layer comprising the materials described above. The counter electrode 223 may be formed not only in the display area DA, but also in the intermediate area MA. In an embodiment, the first functional layer 222a, the second functional layer 222c and the counter electrode 223 may be formed by thermal evaporation.

[0115] In an embodiment, the capping layer 230 may be located on the counter electrode 223. For example, the capping layer 230 may include LiF and may be formed by thermal evaporation. In some embodiments, the capping layer 230 may be omitted.

[0116] The spacer 217 may be formed on the pixel defining layer 215. The spacer 217 may include an organic insulating material such as polyimide. In an embodiment, the spacer 217 may include an inorganic insulating material, or may include an organic insulating material and an inorganic insulating material.

[0117] The spacer 217 may include a material different from that of the pixel defining layer 215, or may include the same material as that of the pixel defining layer 215. In an embodiment, the pixel defining layer 215 and the spacer 217 may include polyimide. In an embodiment, the pixel defining layer 215 and the spacer 217 may be formed together in a mask process using a half-tone mask.

[0118] The organic light emitting diode OLED is covered with a thin film encapsulation layer 300. In an embodiment, the thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, Figure 8 The thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first and second inorganic encapsulation layers 310 and 330. In another embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and / or the stacking order may be changed.

[0119] In an embodiment, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include a single layer or multiple layers comprising the aforementioned materials. In an embodiment, the organic encapsulation layer 320 may include a polymer material, examples of which may include acrylic resin, epoxy resin, polyimide, and / or polyethylene. In an embodiment, the organic encapsulation layer 320 may include acrylate.

[0120] In an embodiment, the thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be different from each other. The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Alternatively, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the thickness of the first inorganic encapsulation layer 310 may be the same as the thickness of the second inorganic encapsulation layer 330.

[0121] Reference Figure 8 The middle area MA may include a first sub-middle area SMA1 relatively far from the transmission area OA and a second sub-middle area SMA2 relatively close to the transmission area OA. A line bypassing the transmission area OA may be arranged in the middle area MA.

[0122] like Figure 8 As shown in FIG, a line (eg, a data line DL) may be located in the first sub-middle area SMA1. Figure 8 The data lines DL of the first sub-middle area SMA1 shown in FIG. Figure 7A and Figure 7B The described bypass portions of the data lines DL (eg, DL- D1 and DL- D2 ) correspond to the first sub-middle area SMA1 which may be understood as a line area or a bypass area in which a line such as the data line DL bypasses the transmission area OA.

[0123] The data lines DL may be arranged alternately with each other via an insulating layer. In an embodiment, for example, one of the adjacent data lines DL is located below the insulating layer (e.g., the first organic insulating layer 209), and the other is located above the insulating layer (e.g., the first organic insulating layer 209). When the data lines DL are arranged alternately with an insulating layer therebetween, the distance Δd (pitch) between the data lines can be reduced. Figure 8 The data lines DL located in the first sub-middle area SMA1 are shown. Figure 7A The described scan line SL (eg, a bypass portion of the scan line SL) may also be located in the first sub-middle area SMA1.

[0124] In the second sub-middle area SMA2, a much smaller number of thin films than those in the first sub-middle area SMA1 are stacked on the substrate 100. That is, in the first sub-middle area SMA1, various thin films such as the gate insulating layer 203, the first and second interlayer insulating layers 205 and 207, the first and second organic insulating layers 209 and 211, the pixel defining layer 215 and the spacer 217, the first and second functional layers 222a and 222c, the counter electrode 223, the capping layer 230, and the buffer layer 201 are stacked between the substrate 100 and the thin film encapsulation layer 300. However, in an embodiment, only the buffer layer 201 is stacked between the substrate 100 and the thin film encapsulation layer 300 in the second sub-middle area SMA2.

[0125] The difference in the number of thin film layers located on the substrate 100 between the first sub-middle area SMA1 and the second sub-middle area SMA2 is because all layers containing organic substances that could potentially serve as a path for water to penetrate into the display area DA have been removed in the second sub-middle area SMA2, which is located near the transmissive area OA. That is, because the second sub-middle area SMA2 is in contact with the first opening 10H in the transmissive area OA, moisture may penetrate from the outside through the second sub-middle area SMA2. Here, layers containing organic substances (such as the first functional layer 222a or the second functional layer 222c among the layers located on the substrate 100) may be a path for moisture to flow. Therefore, in an embodiment, the layers between the substrate 100 and the thin film encapsulation layer 300 in the second sub-middle area SMA2 are removed, leaving only the buffer layer 201 as an inorganic film. In this case, since the path through which moisture could potentially enter the display area DA through the transmissive area OA is blocked, damage to the display area DA due to penetration can be prevented or substantially prevented.

[0126] In an embodiment, 9A to 9D As shown in FIG, by using a sacrificial layer 500 (see Figure 9A ) and laser beam irradiation to achieve the structure from which the thin film layer of the second sub-middle area SMA2 is removed as described above.

[0127] First, if Figure 9A As shown in FIG, a sacrificial layer 500 and a semiconductor layer Act are formed on the buffer layer 201 located on the substrate 100. That is, the semiconductor layer Act is formed in the display area DA, and the sacrificial layer 500 is formed in the second sub-middle area SMA2 of the middle area MA. Here, the sacrificial layer 500 may include a material that is easily sublimated when irradiated with an infrared laser beam, such as a silver (Ag) material.

[0128] Then, if Figure 9B As shown in FIG, a thin film transistor TFT, a storage capacitor Cst, and an organic light emitting diode OLED are formed in the display area DA, wherein the first and second functional layers 222a and 222c, the opposing electrode 223, the capping layer 230, and the like stacked in the display area DA extend to the middle area MA. That is, the first and second functional layers 222a and 222c, the opposing electrode 223, the capping layer 230, and the like extend to the first sub-middle area SMA1 and the second sub-middle area SMA2 on which the sacrificial layer 500 is formed.

[0129] In this state, if Figure 9C As shown in FIG, when an infrared laser beam is irradiated toward the sacrificial layer 500, the sacrificial layer 500 is sublimated together with the thin film layers stacked thereon and separated from the buffer layer 201 located on the substrate 100.

[0130] In this case, if Figure 9D As shown in FIG, only the buffer layer 201 remains in the second sub-middle area SMA2, and a thin film encapsulation layer 300 is formed on the buffer layer 201.

[0131] The thin film encapsulation layer 300 covers the organic light emitting diode OLED of the display area DA to prevent or substantially prevent the organic light emitting diode OLED from being damaged or degraded by external impurities.

[0132] The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Compared with the first functional layer 222a, the second functional layer 222c and / or the counter electrode 223 described above, the first inorganic encapsulation layer 310 formed by the chemical vapor deposition method may have better step coverage.

[0133] The organic encapsulating layer 320 may be formed by applying a monomer or polymer material and curing the monomer or polymer material.

[0134] The second inorganic encapsulating layer 330 may be located on the organic encapsulating layer 320 .

[0135] When the first opening 10H is formed along the cutting line CL after the thin film encapsulation layer 300 is formed, as shown in FIG. Figure 9D As shown in FIG, the number of thin film layers stacked in the second sub-middle area SMA2 is much smaller than the number of thin film layers stacked in the first sub-middle area SMA1. Therefore, in this embodiment, there is no organic layer connected to the organic light-emitting diode OLED or thin film transistor TFT in the display area DA from the end of the first opening 10H contacting the transmissive area OA. In other words, all layers that may serve as a path for water penetration can be eliminated.

[0136] Therefore, such a structure can suppress problems such as water penetration from the transmissive area OA into the display area DA, and can be achieved through a simple process of first laying down the sacrificial layer 500 and then sublimating the sacrificial layer 500 using a laser beam, thereby simplifying the production process. In addition, since the sacrificial layer 500 does not need to have a large size, but only needs to be made large enough to destroy the organic film connection between the transmissive area OA and the display area DA, the area occupied by the intermediate area MA, which becomes the dead space, can also be reduced in plane.

[0137] Although the reference Figures 8 to 9D The display panel 10-1 described includes the first opening 10H corresponding to the transmission area OA, but in the above reference Figures 3B to 3DIn another embodiment described, the display panel 10-1 may not include the first opening 10H corresponding to the transmissive area OA. In this case, the first opening 10H may not be formed along the cut line CL, and the area corresponding to the first opening 10H may serve as the transmissive area OA. For example, in an embodiment, when a transmittance-sensitive device such as a camera is used as the component 20, the first opening 10H may be formed in the transmissive area OA. However, when a device such as an infrared sensor is used as the component 20, even without the first opening 10H, it is not difficult to exchange signals with the display panel 10-1 through the transmissive area OA. This feature can be similarly applied to the display panel 10-2, which will be described later.

[0138] Figure 10 is a cross-sectional view of a display panel 10 - 2 according to another embodiment.

[0139] Figure 10 The display panel 10-2 is substantially the same as that of the reference Figure 8 That is, the display panel 10-2 has a structure in which thin films are stacked in the second sub-middle area SMA2 and have a much smaller number of layers than in the first sub-middle area SMA1. Figure 8 The organic film between the substrate 100 and the thin film encapsulation layer 300 of the second sub-middle area SMA2 is removed in the same manner as the described structure, so that there is no moisture permeation path from the transmission area OA to the display area DA.

[0140] However, the difference of this embodiment is that an uneven pattern layer 510 is further provided in the second sub-middle area SMA2. In an embodiment, the uneven pattern layer 510 may be formed of polysilicon, which is the same material as the semiconductor layer Act forming the display area DA, and may be arranged in the second sub-middle area SMA2 in a shape in which a plurality of protrusions and grooves are arranged. The uneven pattern layer 510 may have a shape such as Figure 11E In the structure shown in FIG, a plurality of protrusions are separated from each other in an island shape on a plane, or may have a structure as shown in FIG. Figure 11F A structure in which a plurality of linear protrusions cross in a grid shape is shown.

[0141] A sacrificial layer 500 is formed on the uneven pattern layer 510. Figure 8 The following processes are performed in the same manner as in the embodiment: first, an uneven pattern layer 510 is formed on the buffer layer 201; a sacrificial layer 500 is formed on the uneven pattern layer 510; and then the sacrificial layer 500 is sublimated later.

[0142] Because the sacrificial layer 500 is formed on the uneven pattern layer 510, the heat absorption rate of the sacrificial layer 500 is first increased by widening its surface area for the infrared laser beam. Specifically, since the sacrificial layer 500 is also formed in the same pattern as the uneven shape of the uneven pattern layer 510, its surface area is increased compared to a flat shape without the uneven pattern layer 510. Therefore, when irradiated with an infrared laser beam, the heat absorption rate of the sacrificial layer 500 is improved by its increased surface area. Furthermore, since the sacrificial layer 500 reflects less infrared laser beams when it is uneven than when it is flat, its heat absorption rate is improved. Therefore, the sacrificial layer 500 can be easily sublimated with less energy. Furthermore, since the sacrificial layer 500 has a wider contact area with the thin-film encapsulation layer 300, which will be formed later on the uneven pattern layer 510, a more satisfactory bonding between the sacrificial layer 500 and the thin-film encapsulation layer 300 is ensured. Furthermore, even if moisture penetrates from the end portion of the second sub-middle area SMA2 contacting the transmission area OA, the moisture penetration path is long due to the uneven pattern layer 510, making the penetration possibility less.

[0143] Therefore, when the uneven pattern layer 510 is formed, sublimation of the sacrificial layer 500 may be easily performed, and effects such as ensuring a tighter bonding with the thin film encapsulation layer 300 can be further obtained.

[0144] In an embodiment, the 11A to 11D Manufacturing process Figure 10 display panel 10-2.

[0145] First, in the embodiment, Figure 11A As shown in FIG, the uneven pattern layer 510 and the semiconductor layer Act on the buffer layer 201 on the substrate 100 both include the same material (e.g., polysilicon). That is, the semiconductor layer Act of polysilicon is formed in the display area DA, and the uneven pattern layer 510 of the same polysilicon material is also formed in the second sub-middle area SMA2 of the middle area MA. A sacrificial layer 500 is formed on the uneven pattern layer 510. Here, the sacrificial layer 500 is also formed to have a large surface area along the uneven shape of the uneven pattern layer 510. The uneven pattern layer 510 can be formed into a regular tapered shape (i.e., a trapezoidal shape that narrows from the bottom to the top) so that the sacrificial layer 500 is well formed without being cut off on the uneven pattern layer 510.

[0146] Then, if Figure 11BAs shown in FIG, a thin film transistor TFT, a storage capacitor Cst, and an organic light emitting diode OLED are formed in the display area DA, wherein the first and second functional layers 222a and 222c, the opposing electrode 223, the capping layer 230, and the like stacked in the display area DA extend to the middle area MA. That is, the first and second functional layers 222a and 222c, the opposing electrode 223, the capping layer 230, and the like extend to the first sub-middle area SMA1 and the second sub-middle area SMA2 on which the uneven pattern layer 510 and the sacrificial layer 500 are formed.

[0147] In this state, if Figure 11C As shown in FIG, when an infrared laser beam is irradiated toward the sacrificial layer 500, as the sacrificial layer 500 rapidly sublimates, the sacrificial layer 500 having a larger surface area is separated from the uneven pattern layer 510 together with the thin film layers stacked thereon.

[0148] In this case, if Figure 11D As shown in the figure, only the buffer layer 201 and the uneven pattern layer 510 remain in the second sub-middle area SMA2, and the thin film encapsulation layer 300 including the first inorganic encapsulation layer 310, the organic encapsulation layer 320 and the second inorganic encapsulation layer 330 is formed on the buffer layer 201 and the uneven pattern layer 510.

[0149] When the first opening 10H is formed along the cutting line CL after the thin film encapsulation layer 300 is formed, as shown in FIG. Figure 11D As shown in FIG, the number of thin film layers stacked in the second sub-middle area SMA2 is much smaller than the number of thin film layers stacked in the first sub-middle area SMA1. Therefore, no organic layer is connected from the end of the first opening 10H contacting the transmissive area OA to the organic light-emitting diode OLED or thin film transistor TFT in the display area DA. In other words, all layers that could serve as a path for water penetration are eliminated.

[0150] Therefore, such a structure can suppress problems such as water penetration from the transmissive area OA into the display area DA, and can be achieved through a simple process of forming the uneven pattern layer 510 and the sacrificial layer 500 and then sublimating the sacrificial layer 500 using a laser beam, thereby simplifying the production process. In addition, since the sacrificial layer 500 does not need to have a large size, but only needs to be made large enough to destroy the organic film connection between the transmissive area OA and the display area DA, the area occupied by the intermediate area MA, which becomes the dead space, can also be reduced in plane. In addition, the uneven pattern layer 510 widens the surface area of ​​the sacrificial layer 500 that absorbs heat, making the sublimation operation easier even with a small amount of energy. In addition, the bonding force between the thin film encapsulation layer 300 and the second sub-intermediate area SMA2 is increased, which ensures a tighter sealing function.

[0151] In an embodiment, the uneven pattern layer 510 is formed of the same polysilicon material as the polysilicon material of the semiconductor layer Act, but the embodiment is not limited thereto. For example, the uneven pattern layer 510 may be formed of a polysilicon material such as SiON, SiO2 or SiN x material formation.

[0152] Figure 8 and Figure 10 The embodiments respectively show display panel 10-1 and display panel 10-2 in which layers up to thin film encapsulation layer 300 are formed on substrate 100. Input sensing layer 40 may be formed on display panel 10-1 and display panel 10-2 through subsequent processes.

[0153] Figure 12 shows that the input sensing layer 40 is formed in Figure 8 The structure on the display panel 10-1; and Figure 13 shows that the input sensing layer 40 is formed in Figure 10 The structure of the display panel 10-2. Figure 12 and Figure 13 The structure of the input sensing layer 40 is the same as that of the input sensing layer 40, so the reference Figure 12 Provide a description.

[0154] First, a planarization layer 420 is disposed on the thin film encapsulation layer 300. The planarization layer 420 may be an organic insulating layer. The planarization layer 420 may include a polymer material. For example, the planarization layer 420 may include silicone, acrylic, epoxy, polyimide, polyethylene, etc. In an embodiment, the planarization layer 420 may include a material different from that of the organic encapsulation layer 320.

[0155] The planarization layer 420 increases the flatness of the display panel 10 - 1 around the transmissive area OA by covering the step between the first sub-middle area SMA1 and the second sub-middle area SMA2 .

[0156] The first insulating layer 410 and the second insulating layer 430 are respectively arranged on the lower portion and the upper portion of the planarization layer 420. In an embodiment, the first insulating layer 410 and the second insulating layer 430 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Each of the first insulating layer 410 and the second insulating layer 430 may include a single layer or multiple layers including the above materials.

[0157] In an embodiment, the cover layer 440 covers the step between the end of the planarization layer 420 and the upper surface of the first insulating layer 410 to prevent or substantially prevent the film from being lifted or separated. In an embodiment, the cover layer 440 may include a metal. The cover layer 440 has a certain width and covers the end of the planarization layer 420, while each of the first insulating layer 410, the second insulating layer 430, and the third insulating layer 450 to be described later below extends in the display area DA and the middle area MA.

[0158] The third insulating layer 450 may be located on the capping layer 440. The third insulating layer 450 may include an organic insulating material. For example, the organic insulating material of the third insulating layer 450 may include a photoresist (negative or positive) or a polymer-based organic material, and may extend toward the display area DA to cover the display area DA.

[0159] Here, the second insulating layer 430 and the layers above the second insulating layer 430 may correspond to the input sensing layer 40 described above. In the input sensing layer 40, electrodes (not shown) for detecting a user's touch are arranged between the second insulating layer 430 and the third insulating layer 450 to perform a touch screen function of transmitting a signal to the display panel 10-1.

[0160] As described above, according to the embodiment, problems such as moisture penetration from the transmission area OA into the display area DA can be suppressed by a simple process of first laying the sacrificial layer 500 and then sublimating the sacrificial layer 500 using a laser beam. In addition, since the sacrificial layer 500 does not need to have a large size, but only needs to be made large enough to destroy the organic film connection between the transmission area OA and the display area DA, the area occupied by the middle area MA, which becomes the dead space, on the plane can also be reduced.

[0161] According to the display device and manufacturing method thereof according to one or more embodiments, the middle area surrounding the transmissive area can be formed to be very narrow through a simple process, thereby effectively reducing the dead space around the transmissive area. However, the aspects and effects described above are illustrative, and the aspects and effects according to the embodiments are not limited thereto.

[0162] It should be understood that the embodiments described herein should be considered in a descriptive sense rather than for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A display device, comprising: The display area and the transmission area are located on the substrate; and a middle region disposed between the display region and the transmission region and comprising a first sub-middle region close to the display region and a second sub-middle region located between the first sub-middle region and the transmission region and close to the transmission region; a buffer layer, on the substrate and disposed in the display area and the middle area; a thin film transistor, located on the buffer layer and disposed in the display area; a display element located on the thin film transistor and disposed in the display region, the display element comprising a thin film layer extending into the first sub-middle region; as well as a thin film encapsulation layer, located on the buffer layer in the display area and the middle area and covering the display element, The number of thin film layers stacked on the substrate in the second middle sub-region is less than the number of thin film layers stacked on the substrate in the first middle sub-region, and The thin film encapsulation layer directly contacts the buffer layer in the second intermediate sub-region and directly contacts the thin film layer in the first intermediate sub-region. 2 . The display apparatus of claim 1 , further comprising an uneven pattern layer comprising a plurality of protrusions and grooves arranged on the substrate in the second sub-middle region.

3. The display device according to claim 2, wherein The uneven pattern layer includes polysilicon.

4. The display device according to claim 2, wherein The display area includes a thin film transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and The uneven pattern layer includes the same material as that of the semiconductor layer and is disposed in the same layer as the semiconductor layer.

5. The display device according to claim 4, wherein The display element further includes a pixel electrode connected to the thin film transistor, a counter electrode opposite to the pixel electrode, and an intermediate layer located between the pixel electrode and the counter electrode. The display device according to claim 2 , wherein: The uneven pattern layer includes SiON, SiO2 and SiN x any material in.

7. The display device according to claim 2, wherein The uneven pattern layer includes a plurality of protrusions arranged in an island shape and spaced apart from each other.

8. The display device according to claim 2, wherein The uneven pattern layer includes a plurality of linear protrusions arranged to cross in a grid shape. 9 . The display device according to claim 1 , further comprising a component that communicates using an optical signal and / or an acoustic signal that passes through the transmissive area.

10. A method for manufacturing a display device, the method comprising: forming a display area on a substrate; forming a transmissive region on the substrate; as well as A middle area is formed between the display area and the transmission area, the middle area including a first sub-middle area close to the display area and a second sub-middle area between the first sub-middle area and the transmission area and close to the transmission area. The forming of the display area and the forming of the middle area include: forming a buffer layer on the substrate; forming a sacrificial layer on the buffer layer in the second sub-middle area and forming a semiconductor layer of a thin film transistor on the buffer layer in the display area; forming a thin film layer on the sacrificial layer above the second sub-middle area and the buffer layer in the first sub-middle area; irradiating a laser beam to the second sub-middle area to remove the sacrificial layer above the second sub-middle area and the thin film layer stacked on the sacrificial layer; and directly forming a thin film encapsulation layer on the buffer layer in the second sub-middle area and the thin film layer in the first sub-middle area. In the formation of the middle region, the number of thin film layers stacked on the substrate in the second sub-middle region is less than the number of thin film layers stacked on the substrate in the first sub-middle region.

11. The manufacturing method according to claim 10, further comprising: forming an uneven pattern layer in which a plurality of protrusions and grooves are arranged in the second sub-middle region, The sacrificial layer is formed on the uneven pattern layer such that the uneven pattern layer remains after the sacrificial layer and the thin film layer stacked on the sacrificial layer are removed.

12. The manufacturing method according to claim 11, wherein: The uneven pattern layer includes polysilicon, SiON, SiO2 and SiN x any material in.

13. The manufacturing method according to claim 11, wherein: The thin film transistor includes the semiconductor layer, a gate electrode, a source electrode, and a drain electrode, and The uneven pattern layer includes the same material as that of the semiconductor layer and is disposed in the same layer as the semiconductor layer.

14. The manufacturing method according to claim 13, wherein: The forming of the display area further includes forming a display element, the display element including a pixel electrode connected to the thin film transistor, a counter electrode opposite to the pixel electrode, and an intermediate layer located between the pixel electrode and the counter electrode.

15. The manufacturing method according to claim 11, wherein: The uneven pattern layer is formed in a shape in which a plurality of protrusions are arranged apart from each other in an island shape.

16. The manufacturing method according to claim 11, wherein: The uneven pattern layer is formed in a grid shape in which a plurality of linear protrusions cross each other. 17 . The manufacturing method according to claim 10 , further comprising arranging components that communicate using optical signals and / or acoustic signals that pass through the transmission area.

Images