Fin field effect transistor device and method for forming the same

Abstract

The present disclosure relates to a fin field effect transistor device and a method for forming the same. A method for forming a semiconductor device includes: forming a fin protruding above a substrate; forming an isolation region on the opposite side of the fin; forming a dummy gate electrode above the fin; removing a lower portion of the dummy gate electrode near the isolation region, wherein after removing the lower portion, a gap exists between the isolation region and a lower surface of the dummy gate electrode facing the isolation region; filling the gap with a gate filling material; after filling the gap, forming a gate spacer along a sidewall of the dummy gate electrode and along a sidewall of the gate filling material; and replacing the dummy gate electrode and the gate filling material with a metal gate.

Description

Technical Field

[0001] The present disclosure generally relates to FinFieldEffectTransistor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, the increase in integration density comes from the continuous reduction in minimum feature size, which allows more components to be integrated into a given area.

[0003] Fin field effect transistor (FinFET) devices are becoming commonly used in integrated circuits. FinFET devices have a three-dimensional structure including a semiconductor fin protruding from a substrate. A gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device surrounds the semiconductor fin. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming a conductive channel on the three sides of the semiconductor fin. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a fin protruding above a substrate; forming an isolation region on the opposite side of the fin; forming a dummy gate electrode above the fin; removing a lower portion of the dummy gate electrode near the isolation region, wherein after removing the lower portion, a gap exists between the isolation region and a lower surface of the dummy gate electrode facing the isolation region; filling the gap with a gate filling material; after filling the gap, forming a gate spacer along the sidewall of the dummy gate electrode and along the sidewall of the gate filling material; and replacing the dummy gate electrode and the gate filling material with a metal gate.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a dummy gate electrode above a fin, wherein the fin protrudes above a substrate and is interposed between isolation regions; reducing the height of the dummy gate electrode by removing a lower portion of the dummy gate electrode, wherein after the height is reduced, a gap exists between the dummy gate electrode and the isolation region; forming a gate filling material in the gap below the dummy gate electrode; forming a gate spacer on an opposite side of the dummy gate electrode and on an opposite side of the gate filling material; after forming the gate spacer, removing the dummy gate electrode and at least a portion of the gate filling material to form an opening between the gate spacers; and forming a metal gate in the opening.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a fin protruding above a substrate; an isolation region located on an opposite side of the fin; a gate structure located above the fin; a gate spacer along a side wall of the gate structure; and a gate filling material located between the gate structure and the gate spacer, wherein a distance between opposite lower side walls of the gate filling material facing the gate structure decreases as the gate filling material extends toward the isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A perspective view of a fin field effect transistor (FinFET) device is shown in accordance with some embodiments.

[0009] Figure 2-Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A-7F , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B and Fig. 15C Various views of a FinFET device 100 at various stages of fabrication are shown in accordance with an embodiment.

[0010] Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B and Fig.19C Cross-sectional views of a FinFET device 100A at various fabrication stages in an embodiment are shown.

[0011] Fig. 20A , Fig. 20B , Fig.21A and Fig. 21B Cross-sectional views of a FinFET device 100B at various fabrication stages in an embodiment are shown.

[0012] Figure 22A-22C Various embodiment cross-sectional views of gate electrodes of FinFET devices in some embodiments are shown.

[0013] Fig.23A , Fig. 23B , Fig.24A and Fig. 24B Various views of a FinFET device 100C at various stages of fabrication in an embodiment are shown.

[0014] Figure 25-Figure 30 Cross-sectional views of a portion of a FinFET device 200 at various stages of fabrication in an embodiment are shown.

[0015] Fig.31 A cross-sectional view of a portion of a FinFET device 200A in an embodiment is shown.

[0016] Fig.32 A cross-sectional view of a portion of a FinFET device 200B in an embodiment is shown.

[0017] Fig.33 A flow chart of a method of forming a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0019] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0020] Embodiments of the present disclosure are discussed in the context of forming a FinFET device, and in particular, in the context of forming a replacement gate (eg, a metal gate) for a FinFET device.

[0021] In some embodiments, a dummy gate electrode is formed above a fin disposed between the isolation regions. A lower portion of the dummy gate electrode is then removed to form a gap between the dummy gate electrode and the isolation region. Next, a gate fill material is formed to fill the gap, and spacers are formed along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material. After forming the gate spacers, at least some portions of the gate fill material and the dummy gate electrode are removed to form an opening between the gate spacers, and a metal gate structure is formed in the opening.

[0022] Figure 1 An example of a FinFET 30 is shown in a perspective view. The FinFET 30 includes a substrate 50 and a fin 64 protruding above the substrate 50. An isolation region 62 is formed on the opposite side of the fin 64, and the fin 64 protrudes above the isolation region 62. A gate dielectric 66 is along the sidewalls of the fin 64 and above the top surface of the fin 64, and a gate electrode 68 is above the gate dielectric 66. Source / drain regions 80 are in the fin 64 and on the opposite side of the gate dielectric 66 and the gate electrode 68. Figure 1 Cross-sectional references used in subsequent figures are further illustrated. Cross-sectional view BB extends along the longitudinal axis of gate electrode 68 of FinFET 30. Cross-sectional view AA is perpendicular to cross-sectional view BB and along the longitudinal axis of fin 64 and in the direction of current flow, for example, between source / drain regions 80. Cross-sectional view CC is parallel to cross-sectional view BB and spans source / drain regions 80. Cross-sectional view DD is parallel to cross-sectional view AA and outside fin 64 (e.g., between two adjacent fins). For clarity, subsequent figures refer to these reference cross-sectional views.

[0023] Figure 2-Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7A-7F , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B and Fig. 15C Various views (eg, cross-sectional views, perspective views, or top views) of the FinFET device 100 are shown at various stages of fabrication according to an embodiment. The FinFET device 100 is similar to Figure 1 The FinFET 30 in FIG. 1 is similar to the FinFET 30 in FIG. 1 , but has multiple fins and multiple gate structures. Throughout the discussion herein, figures with the same number but different letters (e.g., Figure 5A and Figure 5B ) refers to different views of FinFET devices at the same process stage. Figure 2-Figure 4 and Figure 5A A cross-sectional view of the FinFET device 100 along cross section BB is shown. Figure 5B , Figure 6 and Fig. 7A A cross-sectional view of the FinFET device 100 along cross-section DD is shown. Figure 7B and Figure 7C A perspective view and a cross-sectional view along cross section BB are shown, respectively. Fig.7D , Fig. 7E and Figure 7F A cross-sectional view along cross-section AA, a cross-sectional view along cross-section CC, and a top view of the FinFET device 100 are respectively shown. Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A A cross-sectional view of the FinFET device 100 along the cross-section DD is shown, and Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B A cross-sectional view of the FinFET device 100 along cross-section AA is shown. Fig. 15C yes Fig.15A A magnified view of a portion of .

[0024] Figure 2A cross-sectional view of a substrate 50 is shown. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0025] refer to Figure 3 , using techniques such as photolithography and etching to Figure 2 The substrate 50 shown is patterned. For example, a mask layer, such as a pad oxide layer 52 and a covering pad nitride layer 56, is formed over the substrate 50. The pad oxide layer 52 may be a thin film including silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesion layer between the substrate 50 and the covering pad nitride layer 56. In some embodiments, for example, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof, and may be formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0026] The mask layer may be patterned using photolithography techniques. Typically, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material (e.g., the mask layer in this example) from subsequent process steps (e.g., etching). In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, as shown in FIG. Figure 3 shown.

[0027] The patterned mask 58 is then used to pattern the exposed portions of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (eg, 64A and 64B) between adjacent trenches 61, as shown in FIG. Figure 3As shown. In some embodiments, semiconductor fins 64 are formed by etching trenches in substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process may be anisotropic. In some embodiments, trenches 61 may be strips that are parallel to each other and closely spaced relative to each other (as viewed from the top). In some embodiments, trenches 61 may be continuous and surround semiconductor fins 64. Semiconductor fins 64 may also be referred to as fins 64 hereinafter. As a non-limiting example, in Figure 3 Two fins 64 are shown. Other numbers of fins are possible and are fully intended to be included within the scope of the present disclosure.

[0028] The fin 64 may be patterned by any suitable method. For example, the fin 64 may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, the double patterning process or the multi-patterning process combines a photolithography process and a self-alignment process, allowing the creation of a pattern having a smaller pitch than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0029] Figure 4 An insulating material is shown formed between adjacent semiconductor fins 64 to form isolation regions 62. The insulating material may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it to another material, e.g., an oxide), etc., or a combination thereof. Other insulating materials and / or other formation processes may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. A planarization process such as chemical mechanical polishing (CMP) may remove any excess insulating material and form a flush top surface of the isolation region 62 and a top surface of the semiconductor fin 64 (not shown). The patterned mask 58 (see Figure 3 ) can also be removed by planarization process.

[0030] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0031] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region 62. The isolation region 62 is recessed so that the upper portion of the semiconductor fin 64 protrudes from between adjacent STI regions 62. The top surface of the STI region 62 may have a flat surface (as shown), a convex surface, a concave surface (e.g., recessed), or a combination thereof. The top surface of the STI region 62 may be formed to be flat, convex, and / or concave by appropriate etching. An acceptable etching process may be used to recess the isolation region 62, for example, an etching process that is selective to the material of the isolation region 62. For example, a dry etch or a wet etch using dilute hydrofluoric acid (dHF) may be performed to recess the isolation region 62.

[0032] Figures 2 to 4 An embodiment of forming fin 64 is shown, but the fin may be formed in a variety of different processes. For example, the top of substrate 50 may be replaced with a suitable material, such as an epitaxial material suitable for the intended type (e.g., N-type or P-type) of semiconductor device to be formed. Substrate 50 having the epitaxial material on top is then patterned to form semiconductor fin 64 including the epitaxial material.

[0033] As another example, a dielectric layer may be formed over a top surface of a substrate; a trench may be etched through the dielectric layer; a homoepitaxial structure may be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin.

[0034] In yet another example, a dielectric layer can be formed above a top surface of a substrate; a trench can be etched through the dielectric layer; a heteroepitaxial structure can be epitaxially grown in the trench using a different material than the substrate; and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0035] In embodiments where epitaxial material(s) or epitaxial structures (e.g., heteroepitaxial structures or homoepitaxial structures) are grown, the grown material(s) or structures may be doped in situ during growth, which may avoid prior and subsequent implants, but in situ and implant doping may be used together. Further, it may be advantageous to epitaxially grow a different material in the NMOS region than in the PMOS region. In various embodiments, the fins 64 may include silicon germanium (SiGe). x Ge 1-x , where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to: InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0036] Figure 5A and Figure 5B A dummy gate structure 75 is shown formed over the semiconductor fin 64. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate electrode 68. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, etc., and may be deposited or thermally grown.

[0037] A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, for example, by CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed, for example, of polysilicon, but other materials may also be used. The mask layer may be formed, for example, of silicon nitride, etc.

[0038] After forming the layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer may be patterned using acceptable photolithography and etching techniques to form a mask 70. The pattern of the mask 70 may then be transferred to the gate layer and the dielectric layer by acceptable etching techniques to form a gate electrode 68 and a gate dielectric 66, respectively. The gate electrode 68 and the gate dielectric 66 cover the corresponding channel regions of the semiconductor fin 64. The length direction of the gate electrode 68 may also be substantially perpendicular to the length direction of the corresponding semiconductor fin 64.

[0039] exist Figure 5AIn the example of fin 64, gate dielectric 66 is shown as being formed (e.g., by thermal oxidation of the material of fin 64) over fin 64 (e.g., over the top surface and sidewalls of fin 64), but not over STI region 62. In other embodiments, gate dielectric 66 may be formed (e.g., deposited) over fin 64 and over STI region 62. For example, gate dielectric 66 may extend continuously from fin 64A to fin 64B. These and other variations are fully intended to be included within the scope of the present disclosure. Figure 5B A corresponding cross-sectional view along the cross section DD is shown. As a non-limiting example, Figure 5B Two dummy gate structures 75 are shown in FIG. Other numbers of dummy gate structures are possible and are fully intended to be included within the scope of the present disclosure.

[0040] Figure 6 and Figure 7A-7F The dummy gate structure 75 is shown as being suspended by removing the lower portion of the dummy gate structure 75 near the isolation region 62. Figure 6 , a protective layer 71 is formed over the mask 70 and over the upper portion of the gate electrode 68, and the lower portion of the gate electrode 68 is exposed by the protective layer 71. The protective layer 71 is formed of a material different from that of the gate electrode 68, so that in a subsequent etching process, the protective layer 71 prevents or reduces etching of the layer below it (e.g., the upper portion of the gate electrode 68). The protective layer 71 may be a dielectric layer, such as a silicon oxide layer or a silicon nitride layer, formed by a suitable deposition process such as PECVD or atomic layer deposition (ALD), but other suitable materials (e.g., a carbon-based coating) may also be used as the protective layer 71. With the understanding that any suitable material may be used to form the protective layer 71, the following discussion may refer to the protective layer 71 as the dielectric layer 71.

[0041] Figure 6 The fin 64 is further shown in dashed lines because the fin 64 is not in the Figure 6 In the cross section. Figure 6In the example of , a dielectric layer 71 is formed above the upper portion of the gate electrode 68, which is arranged above the upper surface 64U of the fin 64, and the lower portion of the gate electrode 68 is arranged below the upper surface 64U not covered by the dielectric layer 71. Therefore, the deposition process of the dielectric layer 71 can be called a depth selective deposition process. This depth selective deposition process can be the result of the smaller space between adjacent fins 64. With the continuous development of semiconductor manufacturing processes, feature sizes are constantly shrinking. The distance between two adjacent fins 64 can become very small, so that the deposition rate of the deposition process becomes low in such a small space. As a result, when the dielectric layer 71 is formed, the sidewall of the upper portion of the gate electrode 68 (above the fin 64) is covered by the deposited dielectric layer 71. In contrast, little or no dielectric layer 71 is formed along the sidewall of the lower portion of the gate electrode 68.

[0042] Figure 6 The position of the dielectric layer 71 in is only a non-limiting example. For example, the dielectric layer 71 may extend below the upper surface 64U of the fin 64, and may stop at a position between the upper surface 64U of the fin 64 and the upper surface of the isolation region 62. In some embodiments, the sidewall of the lower portion of the gate electrode 68 is also covered by the dielectric layer 71, but the thickness of the dielectric layer 71 above the lower portion of the gate electrode 68 is less than the thickness of the dielectric layer 71 above the upper portion of the gate electrode 68. For example, the thickness of the dielectric layer 71 may continue to decrease as the gate electrode 68 extends toward the isolation region 62. As a result, in a subsequent etching process, the lower portion of the gate electrode 68 is consumed (e.g., etched) more than the upper portion of the gate electrode 68.

[0043] Next, in Fig. 7A In the embodiment, an etching process is performed to remove the lower portion of the gate electrode 68. In some embodiments, the etching process uses an etchant that is selective to the material of the gate electrode 68 (e.g., polysilicon). A suitable etching process such as an anisotropic etching process (e.g., a plasma etching process) can be used to remove the lower portion of the gate electrode 68. In embodiments where plasma etching is used, the lateral etching rate of the plasma etching process is adjusted, for example, by adjusting the bias power of the plasma etching process, to control the sidewall profile of the gate electrode 68. In other embodiments, a wet etching process is performed to remove the lower portion of the gate electrode 68.

[0044] like Fig. 7A As shown, after the etching process, the portion of the gate electrode 68 close to the isolation region 62 is removed, and a gap G exists between the lower surface of each gate electrode 68 and the isolation region 62. Fig. 7AIn the example of FIG. 5 , the upper surface 68U of the gate electrode 68 remains the same before and after the etching process, and the lower surface of the gate electrode 68 moves upward (e.g., toward the upper surface 68U) by the etching process. Therefore, the height of the gate electrode 68 measured in a direction perpendicular to the upper surface of the substrate 50 is reduced.

[0045] In some embodiments, dielectric layer 71 is removed (e.g., completely removed) by an etching process to remove the lower portion of gate electrode 68. In other embodiments, after performing the etching process to remove the lower portion of gate electrode 68, dielectric layer 71 is removed by another suitable etching process, for example, using an etchant that is selective to the material of dielectric layer 71.

[0046] Figure 7B FIG. 1 shows a perspective view of the FinFET device 100 after the lower portion of the gate electrode 68 is removed. Figure 7B Not all features of the FinFET device 100 are shown. For example, the isolation region 62 and the substrate 50 are not shown. Figure 7B In addition, Figure 7B Only one dummy gate structure is shown. Figure 7B It further shows Figure 1 Cross sections AA, BB, CC and DD are shown in FIG.

[0047] Figure 7C FIG. 4 shows a cross-sectional view of the FinFET device 100 along the cross-section BB. Figure 7C As shown, since the lower portion of the gate electrode 68 is removed, the gate electrode 68 no longer contacts (eg, physically contacts) the isolation region 62 and is suspended above the isolation region 62. Therefore, Figure 7C The (shortened) dummy gate structure 75 in FIG. 7 is also referred to as a suspended dummy gate structure 75 .

[0048] Since the gate electrode 68 no longer contacts the isolation region 62, the suspended dummy gate structure 75 may be prone to collapse. To prevent the dummy gate structure 75 from collapsing, the dimensions of the dummy gate structure 75 and the fin 64 are controlled. In some embodiments, the distance W1 between two adjacent fins 64 is less than approximately 200 nm (e.g., 0 nm ≤ W1 ≤ 200 nm), and the distance W2 between the edge 68E of the gate electrode 68 and the nearest sidewall of the underlying fin 64 is less than approximately 100 nm (e.g., 0 nm ≤ W2 ≤ 100 nm). In addition, the depth D1 between the bottom surface of the gate electrode 68 and the upper surface of the fin 64 is between approximately 10 nm and approximately 100 nm, and the height H1 between the upper surface of the fin 64 and the upper surface of the mask 70 is less than approximately 500 nm (e.g., 0 nm ≤ H1 ≤ 500 nm). In some embodiments, the ratio between H1 and D1 is less than approximately 30 (e.g., H1 / D1 ≤ 30). The dimensions H1 and D1 are also Fig. 7A By controlling the dimensions (eg, H1, D1, W1, W2) of the FinFET device 100 within the above ranges, the risk of the suspended dummy gate structure 75 collapsing can be reduced or avoided.

[0049] Fig.7D and Fig. 7E 1 and 10 show cross-sectional views of the FinFET device 100 along cross-sections AA and CC, respectively. Note that the dummy gate structure 75 is not in the cross-section CC and is therefore not shown in FIG. Fig. 7E Shown in. Figure 7F The FinFET device 100 is shown along Figure 7C , wherein the cross section EE is along a plane parallel to the upper surface 50U of the substrate 50 and crosses the channel region of the fin 64 .

[0050] Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B and Figure 15A-Figure 15C Additional process steps of the Finfin device 100 according to an embodiment are shown. For simplicity, not all features are shown in these figures. For example, the substrate 50 is not shown in these figures. To facilitate comparison with subsequent figures, Fig. 8A and Figure 8B It is shown in Fig. 7A and Fig.7D 00. A (simplified) cross-sectional view of a FinFET device 100 in FIG.

[0051] Next, in Fig.9A and Fig. 9B in Fig. 8A and Figure 8B A gate fill material 73 is formed above the FinFET device 100. The gate fill material 73 fills the gap G between each dummy gate structure 75 and the isolation region 62. The gate fill material 73 may also be formed along the sidewalls of the dummy gate structure 75. The gate fill material 73 may be formed in a bottom-up manner using a suitable deposition process (e.g., CVD, PECVD, ALD, or plasma enhanced ALD (PEALD)). In a subsequent replacement gate process, the gate fill material 73 is removed. Therefore, the gate fill material 73 may also be referred to as a dummy gate fill material. In the illustrated embodiment, the gate fill material 73 is formed of a suitable material that provides an etch selectivity to the material of the gate electrode 68 (e.g., having an etch rate different from that of the material of the gate electrode 68), so that the gate electrode 68 and the gate fill material 73 are removed in two different etching processes. The details are discussed below. Example materials of the gate fill material 73 include silicon germanium (SiGe), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbide (SiC), silicon oxycarbide (SiOC), or silicon oxide (SiO), etc.

[0052] Next, in Fig. 10A and Fig. 10B In an embodiment, an anisotropic etching process, such as a plasma etching process, is performed to remove a portion of the gate filling material 73 (e.g., a portion disposed outside the boundary of the gate electrode 68). In an embodiment in which a plasma etching process is used to remove a portion of the gate filling material 73, a bias voltage of the plasma etching process is adjusted (e.g., tuned) to adjust a lateral etching rate of the plasma etching process. Fig. 10A and Fig. 10B In the example of FIG. 1 , a portion of the gate filling material 73 is removed, for example, a portion disposed along the sidewall of the dummy gate structure 75 and a portion disposed between the dummy gate structures 75, and a remaining portion of the gate filling material 73 is disposed directly below the dummy gate structure 75 and fills the gap G (see FIG. 1 ). Fig. 8A The sidewalls of the remaining portion of the gate filling material 73 are aligned with the corresponding sidewalls of the dummy gate structure 75, such as Fig. 10A In other embodiments, after the anisotropic etching process, the remaining portion of the gate filling material 73 fills the gap G and extends along (eg, covers) the sidewall of the dummy gate structure 75 (see, eg, 16A). Note that Fig. 10B In the cross-sectional view of , no gate fill material 73 remains over the gate dielectric 66 after the anisotropic etching process.

[0053] Next, in Fig.11A and Fig. 11B In the embodiment of the present invention, gate spacers 87 are formed along the sidewalls of the dummy gate structures (e.g., 68 and 70) and along the sidewalls of the gate filling material 73. In some embodiments, the gate spacers 87 are formed of nitrides, such as silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof, and can be formed using, for example, thermal oxidation, CVD, or other suitable deposition processes. In some embodiments, the gate spacers 87 are formed of a material different from that of the gate filling material 73 and the gate electrode 68.

[0054] In an embodiment, the gate spacer 87 is formed by first conformally depositing a gate spacer layer over the FinFET device 100. Next, an anisotropic etching process, such as a dry etching process, is performed to remove a first portion of the gate spacer layer disposed on an upper surface of the FinFET device 100 (e.g., an upper surface of the mask 70), while maintaining a second portion of the gate spacer layer disposed along the sidewalls of the dummy gate structure 75 and along the sidewalls of the gate fill material 73. The second portion of the gate spacer layer remaining after the anisotropic etching process forms the gate spacer 87. The anisotropic etching process also removes a horizontal portion of the gate spacer layer.

[0055] like Fig.11A and Fig. 11B The shapes and formation methods of the gate spacers 87 shown are non-limiting examples only, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

[0056] Next, in Fig. 12A and Fig. 12B In the process, source / drain regions 80 are formed in / on the fin 64 on the opposite side of the dummy gate structure 75. The source / drain regions 80 are formed by forming recesses in the fin 64 and then epitaxially growing a material in the recesses using an appropriate method (e.g., metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc., or a combination thereof). The gate dielectric 66 disposed outside the boundaries (e.g., sidewalls) of the gate spacers 87 is removed by this process to form recesses for the source / drain regions 80. As shown in FIG. Fig. 11BAs shown, the epitaxial source / drain regions 80 may have surfaces that protrude from respective surfaces of the fins 64 (e.g., protrude above non-recessed portions of the fins 64), and may have facets. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80. In some embodiments, the source / drain regions 80 of adjacent fins 64 are not merged together, and separate source / drain regions 80 are maintained. In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain regions 80 include silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon carbon (SiCP), etc. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain regions 80 include SiGe and p-type impurities, such as boron or indium.

[0057] The epitaxial source / drain regions 80 may be implanted with dopants to form the source / drain regions 80, followed by an annealing process. The implantation process may include forming and patterning a mask, such as a photoresist, to cover areas of the FinFET device 100 that are to be protected from the implantation process. The source / drain regions 80 may have a thickness from about 1E19 cm -3 to about 1E21cm -3 The impurity (e.g., dopant) concentration may be within a range of . P-type impurities such as boron or indium may be implanted into the source / drain regions 80 of a P-type transistor. N-type impurities such as phosphorus or arsenide may be implanted into the source / drain regions 80 of an N-type transistor. In some embodiments, the epitaxial source / drain regions may be doped in situ during growth.

[0058] Next, in Fig.11A and Fig. 11B A contact etch stop layer (CESL) 89 is formed over the structure shown. CESL 89 serves as an etch stop layer in a subsequent etching process and may include a suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, etc., and may be formed by a suitable formation method, such as CVD, PVD, a combination thereof, etc.

[0059] Next, a first interlayer dielectric (ILD) 90 is formed over the CESL 89 and over the dummy gate structure 75. In some embodiments, the first ILD 90 is formed of a dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. A planarization process such as a CMP process may be performed to remove the mask 70 and remove the portion of the CESL 89 disposed over the gate electrode 68. In some embodiments, after the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68.

[0060] Next, in Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A and Fig. 15B In the embodiment, a gate-last process (sometimes referred to as a replacement gate process) is performed to replace the gate electrode 68, the gate fill material 73, and the gate dielectric 66 with an active gate (also referred to as a replacement gate or a metal gate) and (one or more) active gate dielectric materials. Therefore, in the gate-last process, the gate electrode 68 and the gate dielectric 66 can be referred to as a dummy gate electrode and a dummy gate dielectric, respectively. In some embodiments, the active gate is a metal gate.

[0061] refer to Fig.13A and 13B , the dummy gate electrode 68 is removed by a first etching process, for example, using an etchant that is selective to the material of the gate electrode 68 (for example, having a higher etching rate). A suitable etching process such as a wet etching process or a dry etching process may be performed as the first etching process. After the first etching process, a groove 88 is formed between the corresponding gate spacers 87. Fig.13A In FIG. 8 (a cross-sectional view along cross section DD), at least some portion of the gate filling material 73 remains at the bottom of the groove 88, and the upper inner sidewall of the gate spacer 87 (eg, the upper portion of the sidewall facing the gate filling material 73) is exposed. Fig. 13B In FIG. 8A (a cross-sectional view along cross-section AA), no gate filling material 73 is left, and the dummy gate dielectric 66 is exposed by the recess 88 .

[0062] Next, in Fig.14A and Fig. 14BIn the embodiment of the present invention, for example, an etchant having selectivity to the gate filling material 73 is used, and a second etching process is performed after the first etching process is completed to remove the gate filling material 73. A suitable etching process such as a wet etching process (e.g., using etching chemicals) or a dry etching process can be performed as the second etching process. In an embodiment, a plasma etching process is performed as the second etching process, wherein the plasma process uses a gas source including a main etching gas and a dilution gas (also referred to as a carrier gas). The main etching gas may include Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6 or H2, and the carrier gas includes an inert gas, for example, Ar, He, Ne, etc., or a combination thereof. In addition, the gas source may optionally include a passivation gas, including N2, O2, CO2, SO2, CO or SiCl4. The passivation gas is used to adjust the etching selectivity of the second etching process so as to advantageously reduce or avoid damage to, for example, the gate spacer 87 and the first ILD 90 during the second etching process.

[0063] In some embodiments, the power of the plasma etching process (as the second etching process) is between about 10 W and about 3000 W, and the bias power of the plasma etching process is between about 10 W and about 3000 W. In some embodiments, the bias power is adjusted to adjust the lateral etching rate of the plasma etching process. The pressure of the plasma etching process is between about 1 mTorr and about 800 mTorr. The flow rate of the main etching gas, the dilution gas, or the passivation gas is between about 10 standard cubic centimeters per minute (sccm) and about 5000 sccm. Fig.14A and Fig. 14B In the example of FIG. 8 , after the plasma etching process, the gate fill material 73 is removed from the recess 88 , and the plasma etching process also removes a portion of the gate dielectric 66 that is located below (eg, directly below) the recess 88 . Fig. 14B As shown, the remaining portion of the gate dielectric 66 is disposed directly below the gate spacer 87. In some embodiments, the second etching process also removes an upper portion of the isolation region (eg, due to over-etching), and as a result, the isolation region 62 has a concave upper surface 62U exposed by the recess 88.

[0064] Next, in Fig.15A and Fig. 15B In the embodiment, a metal gate structure 97 (also referred to as a replacement gate structure) is formed in each groove 88. In some embodiments, the metal gate structure 97 has a multi-layer structure (in Fig.15A and Fig. 15B Not shown, but in Fig. 15C ). Fig. 15C Shows Fig.15A Magnified view of area 77 in FIG.

[0065] like Fig. 15C As shown, the metal gate structure 97 includes a gate dielectric layer 94, a barrier layer 96, a work function layer 98, and a gate electrode 99. According to some embodiments, to form the replacement gate structure 97, the gate dielectric layer 94 is conformally deposited in the recess 88, for example, on the top surface and sidewalls of the fin 64 and on the sidewalls of the gate spacer 87, and on the top surface of the first ILD 90 (not shown). In some embodiments, the gate dielectric layer 94 includes silicon oxide, silicon nitride, or multiple layers thereof. In other embodiments, the gate dielectric layer 94 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0066] Next, barrier layer 96 is conformally formed over gate dielectric layer 94. Barrier layer 96 may include a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc. may be used instead. Barrier layer 96 may be formed using a CVD process such as PECVD. However, other alternative processes such as sputtering, metal organic chemical vapor deposition (MOCVD), or ALD may be used instead.

[0067] Next, a work function layer 98, for example, a P-type work function layer or an N-type work function layer, is formed in the recess above the barrier layer 96. Exemplary P-type work function metals that may be included in the gate structure of a P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Exemplary N-type work function metals that may be included in the gate structure of an N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value so as to achieve a target threshold voltage Vt in the device to be formed. The (one or more) work function layers may be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes.

[0068] Next, a seed layer (not shown) is conformally formed over the work function layer 98. The seed layer may include copper, titanium, tantalum, titanium nitride, tantalum nitride, etc., or a combination thereof, and may be deposited by ALD, sputtering, PVD, etc. In some embodiments, the seed layer is a metal layer, which may be a single layer, or a composite layer including multiple sublayers formed of different materials. For example, the seed layer includes a titanium layer and a copper layer over the titanium layer.

[0069] Next, a gate electrode 99 is deposited on the seed layer and fills the remaining portion of the recess 88. The gate electrode 99 may be made of a metal-containing material, such as Cu, Al, W, etc., a combination thereof, or multiple layers thereof, and may be formed by, for example, electroplating, chemical plating, or other suitable methods. After the gate electrode 99 is formed, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 that are above the top surface of the first ILD 90. Thus, the resulting remaining portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 form a replacement gate structure 97 of the resulting FinFET device 100. Now, due to the concave upper surface 62U of the isolation region (see Fig.14A ), the bottom surface of the metal gate structure 97 is curved (eg, curved downward into the insulating region 62), as shown Fig.15A shown. Fig. 15B The portion of metal gate structure 97 disposed directly over fin 64 is shown.

[0070] Those skilled in the art will readily appreciate that Fig.15A and Fig. 15B Additional processes are performed after the process steps, for example, processes for forming gate contact plugs, source / drain contact plugs, and interconnect structures, to complete the fabrication of the FinFET device 100. These details are not discussed here.

[0071] Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A and Fig.19B Cross-sectional views of a FinFET device 100A at various fabrication stages in an embodiment are shown. Fig.16A and Fig. 16B The FinFET device 100A in Fig. 10A and Fig. 10B In other words, Fig.16A and Fig. 16B The process in Fig.9A and Fig. 9B Specifically, Fig. 10A and Fig. 10B In comparison, the lateral etching rate of the anisotropic etching process is adjusted (eg, reduced) so that the sidewalls of the dummy gate structure 75 and the sidewalls of the gate filling material 73 are Fig.16A and Fig. 16B In another embodiment, Fig.16A and Fig. 16B The shape and position of the gate filling material 73 shown can be formed directly after the bottom-up deposition process to form the gate filling material 73, and no additional etching process is performed to adjust the shape of the gate filling material 73 to form the gate filling material 73. Fig.16A and Fig. 16B The structure shown.

[0072] Next, in Fig.17A and Fig. 17B In, use Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B The gate spacer 87, the source / drain region 80, the CESL 89 and the first ILD 90 are formed by the same or similar process steps as shown in FIG. Next, a planarization process such as CMP may be performed to remove the mask 70 and achieve a coplanar upper surface between the gate electrode 68, the gate spacer 87, the CESL 89 and the first ILD 90.

[0073] Next, a first etching process is performed to remove the dummy gate electrode 68, similar to Fig.13A and Fig. 13B After the first etching process, a groove 88 is formed. Note that Fig.13A In contrast, a portion of the gate filling material 73 is retained, covering the entire inner sidewall of the gate spacer 87 (eg, the sidewall facing the gate filling material 73). Fig.17A In the cross-sectional view of FIG. 8 , the gate filling material 73 extends continuously from the upper surface of the gate spacer 87 to the upper surface of the isolation region 62, and Fig. 17B In the cross-sectional view of , the gate filling material 73 extends continuously from the upper surface of the gate spacer 87 to the upper surface of the gate dielectric 66.

[0074] Next, in Fig.18A and Fig.18B In some embodiments, a second etching process is performed to remove a portion of the gate fill material 73. Fig.14A and Fig. 14BThe same or similar plasma etching process. The bias power of the plasma etching process can be adjusted to achieve a target level of anisotropy (e.g., a target level of lateral etching rate). Fig.18A and Fig.18B As shown, after the second etching process, the remaining portion of the gate filling material 73 covers the entire inner sidewall of the gate spacer 87. The lower portion 73L of the remaining gate filling material 73 is thicker than the upper portion 73U of the remaining gate filling material 73. The inner sidewall of the lower portion 73L of the remaining gate filling material 73 (e.g., facing the groove 88) is inclined or curved toward the central axis 88C of the groove 88. The inner sidewall of the upper portion 73U can be straight (e.g., perpendicular to the upper surface of the substrate), or can be inclined toward the central axis 88C of the groove 88 as the gate filling material 73 extends toward the isolation region 62.

[0075] In some embodiments, after the second etching process, the gate fill material 73 includes a first portion located directly above the fin (see, e.g., Fig.18B 73), wherein the thickness of the first portion remains the same as the first portion extends from the upper surface of the gate spacer 87 to the upper surface of the fin 64. The gate fill material 73 also includes a second portion located on the first side of the fin (see, e.g. Fig.18A 73), wherein the second portion contacts the isolation region 62, and the thickness of the second portion increases as the second portion extends toward the isolation region 62.

[0076] Note that Fig.18A In the embodiment, the central area of ​​the upper surface of the isolation region 62 (exposed by the groove 88) has a curved (e.g., concave) upper surface 62U2 due to, for example, over-etching by the second etching process. The upper surface 62U1 of the isolation region (below (e.g., covered by) the lower portion 73L of the gate filling material 73) is substantially flat because it is protected from the second etching process.

[0077] Next, in Fig.19A and Fig.19B In, use Fig.15A and Fig. 15B The same or similar process as in the above is used to form a metal gate structure 97 to fill the groove 88. These details will not be repeated here.

[0078] Fig.19C Shows Fig.19A An enlarged view of region 79 in FIG. Fig.19C As shown, the bottom surface of metal gate structure 97 is curved and extends into isolation region 62 . Upper sidewall 97S1 of metal gate structure 97 may be straight, and lower sidewall 97S2 of metal gate structure 97 may be inclined toward central axis 97C of metal gate structure 97 . Fig.19C The angle θ between the lower side wall 97S2 and the horizontal line HL D The angle D3 of the lower portion of the metal gate structure 97 measured between the isolation region 62 and the location where the upper sidewall 97S1 and the lower sidewall 97S2 abut is between about 0 angstroms and about 1000 angstroms. In an embodiment, the thickness W3 of the lower portion of the gate fill material 73 measured at the interface between the gate fill material 73 and the isolation region 62 is between about 0 angstroms and about 500 angstroms.

[0079] Fig. 20A , Fig. 20B , Fig.21A and Fig. 21B Cross-sectional views of a FinFET device 100B at various fabrication stages in an embodiment are shown. Fig. 20A and Fig. 20B The FinFET device 100B in FIG. Fig.13A and Fig. 13B The FinFET device 100 in FIG. 1 is a FinFET device 100 in FIG. 1 , but the process conditions of the second etching process are adjusted so that after the second etching process, only the lower portion 73L of the gate filling material 73 is left. Fig. 20A In the embodiment, a region of the upper surface of the isolation region 62 (which is exposed by the recess 88) has a curved (e.g., concave) upper surface 62U2 due to, for example, over-etching by the second etching process. The upper surface 62U of the isolation region (below (e.g., covered by) the lower portion 73L of the gate filling material 73) is substantially flat because it is protected from the second etching process.

[0080] Next, in Fig.21A and Fig. 21B In, use Fig.15A and Fig. 15B The same or similar process is used to form a metal gate structure 97 in the groove 88. Fig.21A , the width W2 of the lower portion 73L of the gate fill material 73 is between about 0 angstroms and about 500 angstroms. The height D2 of the lower portion 73L (which is the same as the height of the lower portion 97L of the metal gate structure 97) is between about 0 angstroms and about 1000 angstroms. Note that the upper portion of the metal gate structure 97 has straight sidewalls, and the lower portion of the metal gate structure 97 has inclined or curved sidewalls. Fig.21A In FIG. 6 , the bottom surface of the metal gate structure 97 is curved and extends into the isolation region 62 .

[0081] Figure 22A-22CVarious example cross-sectional views along cross section DD of the bottom of metal gate structure 97 are shown. By adjusting the second etching process (e.g., by controlling the bias voltage to control the lateral etching rate, and / or by adjusting the selectivity of the second etching process), different shapes and / or sizes of the remaining portion of gate fill material 73 (see, e.g., 13A, 17A, 20A) can be achieved to control the shape / size of the bottom of metal gate structure 97. For example, in Fig.22A In the embodiment, the bottom of the metal gate structure 97 gradually tapers and has a curved bottom surface. Fig. 22B In FIG. 1 , the metal gate structure 97 has inclined sidewalls, and the bottom surface 97B of the metal gate structure 97 has a slight recess in the middle. Fig. 22C In the embodiment, the bottom of the metal gate structure 97 has an inclined sidewall and a flat bottom surface 97B. The angle between the bottom surface 97B of the metal gate structure 97 and the corresponding sidewall 97S (in Fig.22A , 22B and 22C are represented by θ g1 ,θ g2 and θ g3 ) is greater than about 90 degrees.

[0082] Fig.23A , Fig. 23B , Fig.24A , Fig. 24B Various views (e.g., cross-sectional views, top views) of a FinFET device 100C at various stages of fabrication in an embodiment are shown. The FinFET device 100C is similar to the FinFET device 100, 100A, or 100B, but a dummy fin 64D is formed to prevent or reduce the risk of collapse of the suspended dummy gate structure 75, or alternatively, to allow a greater distance between adjacent fins 64, or between the fin 64 and the edge 68S of the dummy gate structure 75. Specifically, Fig.23A Similar to Figure 7C ,and Fig. 23B Similar to Figure 7F , but dummy fins 64D are formed between some adjacent fins 64 and / or at edges 68S of dummy gate structures 75. In some embodiments, outer sidewalls 64DS of dummy fins 64D extend further from outer fins 64 than edges 68S.

[0083] The dummy fin 64D can be formed of any suitable material, for example, the same material as the fin 64 (e.g., a semiconductor material), or a different material from the fin 64 (e.g., a dielectric material, such as silicon oxide, silicon nitride). In some embodiments, the dummy fin 64D is formed of a single material. In other embodiments, the dummy fin 64D is formed of two or more materials (e.g., two or more layers of different materials). In some embodiments, the dummy fin 64D is formed of a silicon-based material. In other embodiments, the dummy fin 64D is formed using a dielectric material, for example, a metal oxide (e.g., HfO, TaN, etc., or a combination thereof). In the illustrated embodiment, the dummy fin 64D is electrically isolated, and no source / drain region is formed on / in the dummy fin 64D.

[0084] Due to the interposed dummy fin 64D, the distance WA between the two fins 64 disposed on the opposite sides of the dummy fin 64D may be increased beyond the maximum value of the distance W1 (eg, 200 nm) (see Figure 7C For example, the distance WA between the fins 64 can be increased to a value greater than 200 nm while still maintaining a distance Wa and a distance Wa' of less than about 200 nm to reduce the risk of fin collapse, where Wa and Wa' are the distances between the dummy fin 64D and the corresponding fin 64. Similarly, the distance WB between the outer fin 64 and the edge 68S can be increased to a value greater than the maximum value of the distance W2 (e.g., about 100 nm) (see FIG. Figure 7C ), while still maintaining a distance Wb of less than about 100 nm to reduce the risk of fin collapse, where Wb is the distance between the external fin 64 and the dummy fin 64D. Fig. 23B 1 shows a cross-sectional view of the FinFET device 100C across the cross section FF, which spans the channel region of the fin 64 along a plane parallel to the upper surface of the substrate 50. Fig. 23B As shown, dummy fin 64D may be shorter than fin 64 and may be formed in region R2 having dummy fins while region R1 not having dummy fin 64D formed therein. In other embodiments, dummy fin 64D may be formed in both regions R1 and R2 and may have the same length as fin 64.

[0085] Fig.24A and Fig. 24B A corresponding cross-sectional view of the FinFET device 100C is shown after the metal gate structure 97 is formed following the same or similar process steps as described above. Fig.24A A metal gate structure 97 is shown, and Fig. 24B Gate spacers 87 are further shown, as well as source / drain regions 80 .

[0086] Figure 25-Figure 30The cross-sectional view of the FinFET device 200 at various manufacturing stages in the embodiment is shown. The FinFET device 200 shown may be, for example, a portion of the FinFET device 100A or 100B. Fig.16A (also Fig. 8A Note that the cross section E2-E2 crosses the lower portion (eg, the tapered lower portion) of the gate electrode 68.

[0087] refer to Fig.25 , the FinFET device 200 is in the Fig. 8A and Figure 8B The gate electrode 68 is shown as a thin strip due to the location of the cross section E2-E2 (e.g., near the end of the tapered gate electrode 68). Note that for simplicity, Figure 25-Figure 30 Only the portion of gate electrode 68 between fins 64 is shown. Fig.25 Also shown is a corner region 68C of the gate electrode 68, which extends away from the longitudinal axis 68A of the gate electrode 68, so that Fig.25 The cross section of the gate electrode 68 in FIG. 68 has a convex shape. The shape of the corner region 68C is caused by the etching process used to form the suspended dummy gate structure 75 (see, for example, FIG. 7A ), because the etching process may have a slower etching rate in the corner region (eg, the region of 68C).

[0088] Next, in Fig.26 , a gate filling material 73 is formed. Due to similar reasons (e.g., a slower etching rate at the corner region), the gate filling material 73 may also have a corner region 73C similar to the corner region 68C. Therefore, Fig.26 Can correspond to Fig.16A and Fig. 16B process steps.

[0089] Next, in Fig. 27 In the embodiment, gate spacers 87 are formed along the sidewalls of the gate filling material 73, and source / drain regions 80 are formed over the fins 64. Due to the conformal deposition process and / or etching process used to form the gate spacers 87, the gate spacers 87 have similar corner areas.

[0090] Next, in Fig.28 In the embodiment, the gate electrode 68 is removed by a first etching process, and a groove 88 is formed. Fig.28 Can correspond to Fig.17A and Fig. 17B process steps.

[0091] Next, in Fig.29In the embodiment of the present invention, a second etching process is performed to remove a portion of the gate filling material 73, and the remaining portion of the gate filling material 73 is disposed along the inner sidewalls of the gate spacers 87. Note that due to the slower etching rate of the gate filling material 73 at the corner regions, after the second etching process, the inner sidewalls 73S of the gate filling material 73 at the corner regions are curved toward the corresponding central axis 88A of the grooves 88. Therefore, each groove 88 now has a convex cross-section. Fig.29 Can correspond to Fig.18A and Fig.18B process steps.

[0092] Next, in Fig.30 In the embodiment of the present invention, a metal gate structure 97 is formed to fill the groove 88. Note that since the groove 88 has a convex shape, the metal gate structure 97 also has a convex shape. As a result, the angle θ between two adjacent sides in the corner region of the metal gate structure 97 is A The metal gate structure 97 is greater than about 90 degrees and less than about 180 degrees. Due to the convex shape of the metal gate structure 97, the corner region of the metal gate structure 97 is bent inwardly toward the central axis 97A of the metal gate structure 97, thereby moving away from the source / drain region 80. This advantageously increases the distance between the metal gate structure 97 and the source / drain region 80 and reduces the leakage current of the formed FinFET device (e.g., the leakage current between the gate and the source / drain region). In contrast, without the currently disclosed formation method, the metal gate structure 97 may have a corner region extending outwardly toward the source / drain region 80, which may have an increased leakage current.

[0093] Fig.31 FIG. 2 is a cross-sectional view of a FinFET device 200A in an embodiment. The FinFET device 200A is similar to Fig.30 , but the gate fill material 73 is only in the corner area, which may be due to the higher lateral etch rate of the etching process.

[0094] Fig.32 FIG. 2 shows a cross-sectional view of a FinFET device 200B in an embodiment. The FinFET device 200B is similar to Fig.30 2 , but the gate fill material 73 is completely removed. Note that the corner regions of the gate spacers 87 are bent inwardly due to the over-etching and the gate fill material 73 is completely removed, which again makes the cross-section of the metal gate structure 97 have a convex shape.

[0095] Fig.33 1 is a flow chart of a method 1000 of forming a semiconductor device according to some embodiments. It should be understood that Fig.33The embodiment methods shown are only examples of many possible embodiment methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the following may be added, removed, replaced, rearranged, and repeated. Fig.33 The steps shown.

[0096] refer to Fig.33 At step 1010, a fin is formed protruding above the substrate. At step 1020, an isolation region is formed on the opposite side of the fin. At step 1030, a dummy gate electrode is formed above the fin. At step 1040, a lower portion of the dummy gate electrode near the isolation region is removed, wherein after the lower portion is removed, a gap exists between the isolation region and a lower surface of the dummy gate electrode facing the isolation region. At step 1050, the gap is filled with a gate filling material. At step 1060, after the gap is filled, a gate spacer is formed along the sidewalls of the dummy gate electrode and along the sidewalls of the gate filling material. At step 1070, the dummy gate electrode and the gate filling material are replaced with a metal gate.

[0097] Embodiments can achieve advantages. For example, as semiconductor manufacturing processes continue to develop, feature sizes continue to shrink. As the distance between fins becomes smaller and smaller, it becomes increasingly difficult to deposit materials between the fins. In the material deposited between the fins, especially near the bottom of the fins, gaps or vacuum areas may be formed. In the process of forming the gate electrode 68, if there is a gap in the gate electrode layer, the gate electrode 68 may have a gap after patterning, especially at the bottom of the gate electrode 68. In a subsequent process, a gate spacer 87 is formed along the sidewall of the gate electrode 68. If there are gaps at the sidewalls of the gate electrode 68, the material of the gate spacer 87 (e.g., silicon nitride) will fill these gaps. In a subsequent replacement gate process, the gate electrode 68 is removed and replaced with a gate material. However, the material of the gate spacer 87 that fills the gap (e.g., silicon nitride) will not be etched away with the gate electrode 68, and will remain in the final metal gate structure 97. This may cause defects or high resistance of the metal gate structure 97. In contrast, the presently disclosed method forms a suspended dummy gate structure and fills the gap G with a dummy gate fill material 73, which is less likely to form a void under the gate electrode 68 (due to bottom-up deposition), and any void at the sidewall of the gate electrode 68 is filled with the dummy gate fill material 73, which is also removed in a subsequent replacement gate process. Therefore, the problem of voids at the sidewall of the gate electrode 68, such as defects of the metal gate structure 97 or increased gate resistance, is avoided or reduced. In addition, as shown in FIG. Figure 25-Figure 30 As shown, the disclosed embodiment method increases the distance between the metal gate structure and the source / drain region 80 , thereby reducing the leakage current of the formed FinFET device.

[0098] In an embodiment, a method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming an isolation region on an opposite side of the fin; forming a dummy gate electrode above the fin; removing a lower portion of the dummy gate electrode near the isolation region, wherein after removing the lower portion, there is a gap between the isolation region and a lower surface of the dummy gate electrode facing the isolation region; filling the gap with a gate filling material; after filling the gap, forming a gate spacer along a sidewall of the dummy gate electrode and along a sidewall of the gate filling material; and replacing the dummy gate electrode and the gate filling material with a metal gate. In an embodiment, removing the lower portion of the dummy gate electrode includes: forming a dielectric layer above an upper portion of the dummy gate electrode, wherein the lower portion of the dummy gate electrode is exposed by the dielectric layer; and performing an etching process, wherein a first etching rate of the dielectric layer is slower than a second etching rate of the dummy gate electrode. In an embodiment, the etching process is a plasma etching process, wherein performing the etching process includes controlling a lateral etching rate of the plasma etching process by adjusting a bias voltage of the plasma etching process. In an embodiment, filling the gap includes: depositing a gate fill material on the isolation region, the gate fill material filling the gap and extending along the sidewall of the dummy gate electrode; and after depositing the gate fill material, performing an anisotropic etching process to remove a portion of the gate fill material. In an embodiment, after the anisotropic etching process, the remaining portion of the gate fill material extends from the lower surface of the dummy gate electrode to the isolation region, and the uppermost surface of the remaining portion of the gate fill material contacts the lower surface of the dummy gate electrode. In an embodiment, after the anisotropic etching process, the remaining portion of the gate fill material covers the sidewall of the dummy gate electrode and extends from the upper surface of the dummy gate electrode to the isolation region. In an embodiment, replacing the dummy gate electrode and the gate fill material includes: performing a first etching process to remove the dummy gate electrode, wherein the gate fill material is exposed after the first etching process; performing a second etching process to remove at least a portion of the gate fill material to form an opening between the gate spacers; and forming a metal gate in the opening. In an embodiment, forming the metal gate includes: lining the sidewalls and bottom of the opening with a gate dielectric layer; forming a barrier layer over the gate dielectric layer; forming a work function layer over the barrier layer; and filling the opening with a metal material after forming the work function layer. In an embodiment, performing the second etching process includes performing a plasma etching process using a gas source including an etching gas, a passivation gas, and a carrier gas, wherein the etching gas includes Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, or H2, the passivation gas includes N2, O2, CO2, SO2, CO, or SiCl4, and the carrier gas includes an inert gas.In an embodiment, after the second etching process, a remaining portion of the gate filling material extends from an upper surface of the gate spacer to the isolation region, wherein a distance measured between lower sidewalls of the remaining portion of the gate filling material facing the metal gate decreases as the remaining portion of the gate filling material extends toward the isolation region. In an embodiment, after the second etching process, the remaining portion of the gate filling material covers the lower sidewalls of the gate spacer while exposing the upper sidewalls of the gate spacer, wherein an upper portion of the metal gate contacts the gate spacer, and a lower portion of the metal gate contacts the remaining portion of the gate filling material.

[0099] In an embodiment, a method of forming a semiconductor device includes: forming a dummy gate electrode above a fin, wherein the fin protrudes above a substrate and is between isolation regions; reducing the height of the dummy gate electrode by removing a lower portion of the dummy gate electrode, wherein after the height is reduced, there is a gap between the dummy gate electrode and the isolation region; forming a gate filling material in the gap below the dummy gate electrode; forming a gate spacer on an opposite side of the dummy gate electrode and an opposite side of the gate filling material; after forming the gate spacer, removing the dummy gate electrode and at least a portion of the gate filling material to form an opening between the gate spacers; and forming a metal gate in the opening. In an embodiment, the distance measured between the upper surface of the isolation region and the upper surface of the dummy gate electrode away from the isolation region remains the same before and after reducing the height of the dummy gate electrode. In an embodiment, the gate filling material is formed to have the same width as the dummy gate electrode so that the sidewalls of the dummy gate electrode are aligned with the corresponding sidewalls of the gate filling material. In an embodiment, the gate filling material is formed to fill the gap and extend along the sidewalls of the dummy gate electrode. In an embodiment, after removing at least a portion of the gate filling material, a remaining portion of the gate filling material is interposed between the metal gate and the gate spacer, wherein a width of a lower portion of the metal gate proximate the isolation region decreases as the metal gate extends toward the isolation region.

[0100] In an embodiment, a semiconductor device includes: a fin protruding above a substrate; an isolation region located on an opposite side of the fin; a gate structure located above the fin; a gate spacer along a sidewall of the gate structure; and a gate filling material located between the gate structure and the gate spacer, wherein the distance between the opposite lower sidewalls of the gate filling material facing the gate structure decreases as the gate filling material extends toward the isolation region. In an embodiment, the gate filling material is disposed on and in contact with the isolation region, wherein the gate filling material covers the lower sidewall of the gate spacer and exposes the upper sidewall of the gate spacer. In an embodiment, the thickness of the gate filling material increases as the gate filling material extends toward the isolation region. In an embodiment, the gate filling material separates the gate structure from the gate spacer, wherein the gate filling material includes: a first portion located directly above the fin, wherein the thickness of the first portion remains the same as the first portion extends from the upper surface of the gate spacer to the upper surface of the fin; and a second portion located on a first side of the fin and in contact with the isolation region, wherein the thickness of the second portion increases as the second portion extends toward the isolation region.

[0101] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0102] Example 1 is a method for forming a semiconductor device, the method comprising: forming a fin protruding above a substrate; forming an isolation region on the opposite side of the fin; forming a dummy gate electrode above the fin; removing a lower portion of the dummy gate electrode near the isolation region, wherein, after removing the lower portion, a gap exists between the isolation region and a lower surface of the dummy gate electrode facing the isolation region; filling the gap with a gate filling material; after filling the gap, forming a gate spacer along the side wall of the dummy gate electrode and along the side wall of the gate filling material; and replacing the dummy gate electrode and the gate filling material with a metal gate.

[0103] Example 2 is the method described in Example 1, wherein removing the lower portion of the dummy gate electrode includes: forming a dielectric layer above the upper portion of the dummy gate electrode, wherein the lower portion of the dummy gate electrode is exposed by the dielectric layer; and performing an etching process, wherein a first etching rate of the dielectric layer is slower than a second etching rate of the dummy gate electrode.

[0104] Example 3 is the method of Example 2, wherein the etching process is a plasma etching process, and wherein performing the etching process includes controlling a lateral etching rate of the plasma etching process by adjusting a bias voltage of the plasma etching process.

[0105] Example 4 is the method described in Example 1, wherein filling the gap includes: depositing the gate filling material on the isolation region, the gate filling material filling the gap and extending along the sidewall of the dummy gate electrode; and after depositing the gate filling material, performing an anisotropic etching process to remove a portion of the gate filling material.

[0106] Example 5 is the method described in Example 4, wherein, after the anisotropic etching process, the remaining portion of the gate filling material extends from the lower surface of the dummy gate electrode to the isolation region, and the uppermost surface of the remaining portion of the gate filling material contacts the lower surface of the dummy gate electrode.

[0107] Example 6 is the method described in Example 4, wherein, after the anisotropic etching process, the remaining portion of the gate filling material covers the sidewalls of the dummy gate electrode and extends from the upper surface of the dummy gate electrode to the isolation region.

[0108] Example 7 is the method described in Example 1, wherein replacing the dummy gate electrode and the gate filling material includes: performing a first etching process to remove the dummy gate electrode, wherein the gate filling material is exposed after the first etching process; performing a second etching process to remove at least a portion of the gate filling material to form an opening between the gate spacers; and forming the metal gate in the opening.

[0109] Example 8 is the method described in Example 7, wherein forming the metal gate includes: lining the sidewalls and bottom of the opening with a gate dielectric layer; forming a barrier layer above the gate dielectric layer; forming a work function layer on the barrier layer; and filling the opening with a metal material after forming the work function layer.

[0110] Example 9 is the method described in Example 7, wherein performing the second etching process includes: performing a plasma etching process using a gas source including an etching gas, a passivation gas and a carrier gas, wherein the etching gas includes Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6 or H2, the passivation gas includes N2, O2, CO2, SO2, CO or SiCl4, and the carrier gas includes an inert gas.

[0111] Example 10 is the method described in Example 7, wherein, after the second etching process, the remaining portion of the gate filling material extends from the upper surface of the gate spacer to the isolation region, wherein the distance measured between the lower side walls of the remaining portion of the gate filling material facing the metal gate decreases as the remaining portion of the gate filling material extends toward the isolation region.

[0112] Example 11 is the method described in Example 7, wherein, after the second etching process, the remaining portion of the gate filling material covers the lower side wall of the gate spacer and exposes the upper side wall of the gate spacer, wherein the upper portion of the metal gate contacts the gate spacer and the lower portion of the metal gate contacts the remaining portion of the gate filling material.

[0113] Example 12 is a method for forming a semiconductor device, the method comprising: forming a dummy gate electrode above a fin, wherein the fin protrudes above a substrate and is between isolation regions; reducing the height of the dummy gate electrode by removing a lower portion of the dummy gate electrode, wherein after the height is reduced, a gap exists between the dummy gate electrode and the isolation region; forming a gate filling material in the gap below the dummy gate electrode; forming a gate spacer on an opposite side of the dummy gate electrode and on an opposite side of the gate filling material; after forming the gate spacer, removing the dummy gate electrode and at least a portion of the gate filling material to form an opening between the gate spacers; and forming a metal gate in the opening.

[0114] Example 13 is the method of Example 12, wherein a distance measured between an upper surface of the isolation region and an upper surface of the dummy gate electrode away from the isolation region remains the same before and after reducing the height of the dummy gate electrode.

[0115] Example 14 is the method of Example 12, wherein the gate filling material is formed to have the same width as the dummy gate electrode so that a sidewall of the dummy gate electrode is aligned with a corresponding sidewall of the gate filling material.

[0116] Example 15 is the method of Example 12, wherein the gate filling material is formed to fill the gap and extend along a sidewall of the dummy gate electrode.

[0117] Example 16 is the method described in Example 12, wherein, after removing at least a portion of the gate filling material, the remaining portion of the gate filling material is interposed between the metal gate and the gate spacer, wherein the width of the lower portion of the metal gate near the isolation region decreases as the metal gate extends toward the isolation region.

[0118] Example 17 is a semiconductor device comprising: a fin protruding above a substrate; an isolation region located on an opposite side of the fin; a gate structure located above the fin; a gate spacer along a side wall of the gate structure; and a gate filling material located between the gate structure and the gate spacer, wherein a distance between opposite lower side walls of the gate filling material facing the gate structure decreases as the gate filling material extends toward the isolation region.

[0119] Example 18 is the semiconductor device of Example 17, wherein the gate filling material is disposed on and in contact with the isolation region, wherein the gate filling material covers a lower sidewall of the gate spacer and exposes an upper sidewall of the gate spacer.

[0120] Example 19 is the semiconductor device of Example 18, wherein a thickness of the gate fill material increases as the gate fill material extends toward the isolation region.

[0121] Example 20 is a semiconductor device as described in Example 17, wherein the gate filling material separates the gate structure from the gate spacer, wherein the gate filling material includes: a first portion located directly above the fin, wherein the thickness of the first portion remains the same as the first portion extends from the upper surface of the gate spacer to the upper surface of the fin; and a second portion located on a first side of the fin and in contact with the isolation region, wherein the thickness of the second portion increases as the second portion extends toward the isolation region.

Claims

1. A method for forming a semiconductor device, the method comprising: forming a fin protruding above the substrate; forming an isolation region on opposite sides of the fin; forming a dummy gate electrode above the fin; Removing a lower portion of the dummy gate electrode close to the isolation region, wherein after the lower portion is removed, a gap exists between the isolation region and a lower surface of the dummy gate electrode facing the isolation region; filling the gap with a gate fill material; After filling the gap, forming a gate spacer along a sidewall of the dummy gate electrode and along a sidewall of the gate filling material; as well as The dummy gate electrode and the gate fill material are replaced with a metal gate.

2. The method according to claim 1, wherein: Removing the lower portion of the dummy gate electrode comprises: forming a dielectric layer over an upper portion of the dummy gate electrode, wherein the lower portion of the dummy gate electrode is exposed by the dielectric layer; and An etching process is performed, wherein a first etching rate of the dielectric layer is slower than a second etching rate of the dummy gate electrode.

3. The method according to claim 2, wherein: The etching process is a plasma etching process, wherein performing the etching process includes controlling a lateral etching rate of the plasma etching process by adjusting a bias voltage of the plasma etching process.

4. The method according to claim 1, wherein: Filling the gap includes: depositing the gate filling material on the isolation region, the gate filling material filling the gap and extending along the sidewall of the dummy gate electrode; and After depositing the gate filling material, an anisotropic etching process is performed to remove portions of the gate filling material.

5. The method according to claim 4, wherein: After the anisotropic etching process, a remaining portion of the gate filling material extends from the lower surface of the dummy gate electrode to the isolation region, and an uppermost surface of the remaining portion of the gate filling material contacts the lower surface of the dummy gate electrode.

6. The method according to claim 4, wherein: After the anisotropic etching process, a remaining portion of the gate filling material covers the sidewall of the dummy gate electrode and extends from an upper surface of the dummy gate electrode to the isolation region.

7. The method according to claim 1, wherein: Replacing the dummy gate electrode and the gate filling material includes: performing a first etching process to remove the dummy gate electrode, wherein the gate filling material is exposed after the first etching process; performing a second etching process to remove at least a portion of the gate fill material to form openings between the gate spacers; and The metal gate is formed in the opening.

8. The method according to claim 7, wherein: Forming the metal gate includes: lining the sidewalls and bottom of the opening with a gate dielectric layer; forming a barrier layer over the gate dielectric layer; a work function layer on the barrier layer; and After forming the work function layer, the opening is filled with a metal material.

9. The method according to claim 7, wherein: Performing the second etching process includes: performing a plasma etching process using a gas source including an etching gas, a passivation gas and a carrier gas, wherein the etching gas includes Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6 or H2, the passivation gas includes N2, O2, CO2, SO2, CO or SiCl4, and the carrier gas includes an inert gas.

10. The method according to claim 7, wherein: After the second etching process, the remaining portion of the gate filling material extends from the upper surface of the gate spacer to the isolation region, wherein a distance measured between lower side walls of the remaining portion of the gate filling material facing the metal gate decreases as the remaining portion of the gate filling material extends toward the isolation region.

11. The method according to claim 7, wherein: After the second etching process, the remaining portion of the gate filling material covers the lower sidewall of the gate spacer and exposes the upper sidewall of the gate spacer, wherein the upper portion of the metal gate contacts the gate spacer and the lower portion of the metal gate contacts the remaining portion of the gate filling material.

12. A method for forming a semiconductor device, the method comprising: forming a dummy gate electrode over a fin, wherein the fin protrudes over the substrate and is interposed between the isolation regions; reducing a height of the dummy gate electrode by removing a lower portion of the dummy gate electrode, wherein after reducing the height, a gap exists between the dummy gate electrode and the isolation region; forming a gate filling material in the gap below the dummy gate electrode; forming a gate spacer on an opposite side of the dummy gate electrode and an opposite side of the gate filling material; After forming the gate spacers, removing the dummy gate electrodes and removing at least a portion of the gate fill material to form openings between the gate spacers; and A metal gate is formed in the opening.

13. The method according to claim 12, wherein: A distance measured between an upper surface of the isolation region and an upper surface of the dummy gate electrode remote from the isolation region remains the same before and after reducing the height of the dummy gate electrode.

14. The method according to claim 12, wherein: The gate filling material is formed to have the same width as the dummy gate electrode such that sidewalls of the dummy gate electrode are aligned with corresponding sidewalls of the gate filling material.

15. The method according to claim 12, wherein: The gate filling material is formed to fill the gap and extend along a sidewall of the dummy gate electrode.

16. The method according to claim 12, wherein: After removing at least a portion of the gate filling material, a remaining portion of the gate filling material is interposed between the metal gate and the gate spacer, wherein a width of a lower portion of the metal gate proximate the isolation region decreases as the metal gate extends toward the isolation region.

Images