Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. A fully wrapped gate device and a method for manufacturing the same are described herein, the method comprising forming a multilayer structure above a substrate, and forming a plurality of source / drain regions in the multilayer structure. Then, the multilayer structure is patterned into a fin through adjacent source / drain regions. A line release process is performed to remove one or more layers of material in the multilayer structure. The remaining layers of the multilayer structure form a stack of nanostructures connected to adjacent source / drain regions of the fin.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and patterning the various material layers using lithography processes to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the size of the smallest feature, so that more components can be integrated into a given area. However, when the size of the smallest feature is reduced, additional problems that should be solved emerge. Summary of the invention

[0004] In some embodiments, a method for manufacturing a semiconductor device is provided, the method comprising forming a multilayer stack above a substrate, the multilayer stack comprising a first layer, a second layer above the first layer, a third layer above the second layer, and a fourth layer above the third layer, the first layer and the third layer comprising a first semiconductor material, and the second layer and the fourth layer comprising a second semiconductor material; etching a first opening in the multilayer stack, the first opening exposing the substrate; forming a first source / drain region in the first opening; after forming the first source / drain region, etching a fin from the multilayer stack; removing the first layer and the third layer from the fin; and forming a gate structure to surround the second layer and the fourth layer.

[0005] In some other embodiments, a method for manufacturing a semiconductor device is provided, which includes forming a first opening in a multilayer structure; forming a first source / drain region in the first opening; after forming the first source / drain region, etching the multilayer structure to form a fin; performing a line release process on the fin to form a plurality of nanostructures; and after performing the line release process, depositing a gate structure around each of the plurality of nanostructures.

[0006] In some other embodiments, a semiconductor device is provided, which includes a first source / drain region; a second source / drain region; a stack of nanostructures, each nanostructure in the stack of nanostructures extending between the first source / drain region and the second source / drain region; a gate dielectric layer surrounding each nanostructure in the stack of nanostructures, wherein the gate dielectric layer directly physically contacts the first source / drain region and the second source / drain region; and a gate contact surrounding the gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the present disclosure may be better understood with reference to the following detailed description and accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the drawings are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0008] Figure 1 The formation of a multi-layer structure is shown in an intermediate step of forming a semiconductor device according to some embodiments.

[0009] Figures 2A-2D The formation of source / drain regions in a multi-layer structure according to some embodiments is shown.

[0010] Figure 3A-3B The formation of fins and isolation regions in a multi-layer structure is shown in accordance with some embodiments.

[0011] Figures 4A-4C The formation of a dummy gate stack above the channel region of the multi-layer structure is shown in accordance with some embodiments.

[0012] Figure 5A and 5B The formation of spacers adjacent to the dummy gate stack and source / drain regions of the multi-layer structure is shown in accordance with some embodiments.

[0013] Figures 6A-6C The formation of a contact etch stop layer and a first interlayer dielectric over a multi-layer structure is shown in accordance with some embodiments.

[0014] Fig. 7A and 7B The removal of a dummy gate stack over a multi-layer structure is shown in accordance with some embodiments.

[0015] Fig. 8A and 8B A wire-release process is shown for a multi-layer structure according to some embodiments.

[0016] Fig.9A and 9B The formation of a gate dielectric and a gate contact over a channel region of a multi-layer structure is shown in accordance with some embodiments.

[0017] Figures 10A-12B The steps of forming source / drain contacts and conductive plugs of the semiconductor device 1200 according to some embodiments are shown.

[0018] Description of reference numerals:

[0019] 100: Multi-layer structure

[0020] 101: Base

[0021] 103: Multilayer stack

[0022] 105: First floor

[0023] 106: First device area

[0024] 107: Second floor

[0025] 108: Second device area

[0026] 201: Source / drain region

[0027] 301: Fin

[0028] 303: Quarantine

[0029] 305: Channel area

[0030] 401: Dummy Gate Stack

[0031] 403: Dummy Gate Dielectric

[0032] 405: Dummy gate electrode

[0033] 407: First Hard Mask

[0034] 409: Second hard mask

[0035] 501: The first spacer layer

[0036] 601: Contact Etch Stop Layer

[0037] 603: First interlayer dielectric

[0038] 801: Nanostructures

[0039] 901: Gate Dielectric

[0040] 903: Gate contact

[0041] 1001: Dielectric cap layer

[0042] 1003: Second interlayer dielectric

[0043] 1101: Source / Drain Contact

[0044] 1103: Protective layer

[0045] 1105: Silicide Contacts

[0046] 1200: Semiconductor devices

[0047] 1201: Conductive plug

[0048] 1203: Third interlayer dielectric

[0049] D1: First Depth

[0050] Dist1: First distance

[0051] Dist2: Second distance

[0052] Dist3: The third distance

[0053] Dist4: The fourth distance

[0054] H1: First height

[0055] H2: Second height

[0056] H4: The fourth height

[0057] H5: Fifth height

[0058] L1: first length

[0059] L2: Second length

[0060] P1: First spacing

[0061] P2: Second spacing

[0062] W1: First width

[0063] W3: Third width

[0064] TH1: First thickness DETAILED DESCRIPTION

[0065] It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the provided subject. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present disclosure. For example, the following disclosure describes forming a first component on or above a second component, which means that it includes an embodiment in which the formed first component and the second component are in direct contact, and also includes an embodiment in which an additional component can be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and / or the described appearance structures.

[0066] Furthermore, spatially relative terms, such as "under," "below," "lower," "above," "upper," and the like, may be used to facilitate description of the relationship of one element or component to another (plural) element or component in the drawings. Spatially relative terms also encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description of the spatially relative terms used would be interpreted accordingly.

[0067] Please refer to Figure 1 , which shows the formation of a multilayer structure 100 in an intermediate step of forming a semiconductor device according to some embodiments. In particular, Figure 1 A substrate 101 is shown, wherein dopants have been implanted into the substrate 101 to form a well region. In one embodiment, the substrate 101 is a semiconductor substrate, which may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, a III-V material substrate (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb and / or GaInAsP or a combination of the foregoing), or a substrate formed of other semiconductor materials having, for example, high-energy band-to-band tunneling (BTBT). The substrate 101 may be doped or undoped. In some embodiments, the substrate 101 may be a bulk semiconductor substrate, such as a bulk silicon substrate of a wafer, a semiconductor-on-insulator (SOI) substrate, a multi-layer or gradient substrate, or the like.

[0068] Figure 1 The substrate 101 further includes a first device region 106 for forming an n-type device (e.g., an n-type metal oxide semiconductor (NMOS) transistor (e.g., an n-type fully wrapped gate transistor)) and a second device region 108 for forming a p-type device (e.g., a p-type metal oxide semiconductor (PMOS) transistor (e.g., a p-type fully wrapped gate transistor). In order to separate the first device region 106 from the second device region 108, a well region (not shown separately) may be formed by n-type dopants and p-type dopants. Figure 1) is formed in the substrate 101. In order to form the desired well region, n-type dopants and p-type dopants are implanted into the substrate 101 according to the desired device to be formed. For example, n-type dopants (such as phosphorus or arsenic) can be implanted to form the n-type well region, and p-type dopants (such as boron) can be implanted to form the p-type well region. The n-type well region and the p-type well region can be formed by using one or more implantation techniques, such as diffusion implantation, ion implantation (such as plasma doping, beam-line implantation doping), selective implantation, deep well implantation, the like, or a combination of the foregoing. During the process of implanting the first well region (such as the n-type well region), a masking technique can also be used to mask some areas of the substrate 101 (such as the second device region 108) while exposing other areas of the substrate 101 (such as the first device region 106).

[0069] After the first well region implantation process is completed, the mask is removed to expose the previously masked area (e.g., the second device region 108), and during the second well region implantation process (e.g., the p-type well region), another mask may be placed over the previously exposed area (e.g., the first device region 106). In some embodiments, further doping implantation may be performed to form a deep well implantation region in the substrate 101.

[0070] Figure 1 Further shown is a deposition process according to some embodiments to form a multilayer structure 100 in an intermediate stage of manufacturing a gate all-around (GAA) device. In particular, Figure 1 Further shown is a series of depositions performed to form a multilayer stack 103 of alternating materials of first layer 105 and second layer 107 over substrate 101 .

[0071] According to some embodiments, the first layer 105 may be formed by using a first semiconductor material having a first lattice constant, such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like. In some embodiments, the first layer 105 is epitaxially grown on the substrate 101 using a deposition technique, such as epitaxial growth, vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), but other deposition processes may also be used, such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD), combinations thereof, or the like. In some embodiments, first layer 105 is formed to a thickness between about 4 nm and about 20 nm, such as about 15 nm. However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0072] After the first layer 105 has been formed on the substrate 101, the second layer 107 may be formed on the first layer 105. According to some embodiments, the second layer 107 may be formed by using a second semiconductor material having a second lattice constant different from the first lattice constant of the first layer 105, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like. In a specific embodiment where the first layer 105 is silicon germanium, the material of the second layer 107 is, for example, silicon. However, any suitable combination of materials may be used for the first layer 105 and the second layer 107.

[0073] In some embodiments, the second layer 107 is epitaxially grown on the first layer 105 using a deposition technique similar to that used to form the first layer 105. However, the second layer 107 may be formed using any suitable deposition technique described above for forming the first layer 105 or other suitable techniques. According to some embodiments, the second layer 107 is formed to a thickness similar to that of the first layer 105. However, the second layer 107 may also be formed to a thickness different from that of the first layer 105. According to some embodiments, the second layer may be formed to a thickness between about 4 nm and about 20 nm, such as about 10 nm. However, any suitable thickness may be used.

[0074] After the second layer 107 has been formed over the first layer 105, the deposition process is repeated to form the remaining material layers in a series of alternating first layers 105 and second layers 107 until the desired topmost layer of the multilayer stack 103 is formed. According to some embodiments, the first layers 105 may be formed to the same or similar first thickness, and the second layers 107 may be formed to the same or similar first thickness. However, the first layers 105 may have different thicknesses from one another, and / or the second layers 107 may have different thicknesses from one another, and any combination of thicknesses may be used for the first layers 105 and the second layers 107. According to the current embodiment, the topmost layer of the multilayer stack 103 is formed as the second layer 107, however, in other embodiments, the topmost layer of the multilayer stack 103 is formed as the first layer 105. Furthermore, while the embodiments disclosed herein include three first layers 105 and three second layers 107, the multilayer stack 103 may have any suitable number of layers (e.g., nanosheets). For example, the multilayer stack 103 may include a plurality of nanosheets ranging from 2 to 10 nanosheets. In some embodiments, the multilayer stack 103 may include the same number of first layers 105 and second layers 107. However, in other embodiments, the number of first layers 105 may be different from the number of second layers 107. According to some embodiments, the multilayer stack 103 may be formed to a first height H1 between about 24 nm and about 120 nm, such as about 60 nm. However, any suitable height may be used.

[0075] Please refer to Figure 2A , which shows a top view of a patterning process of a multilayer structure 100 in an intermediate step of manufacturing a gate-all-around (GAA) device according to some embodiments. In some embodiments, the multilayer stack 103 is formed of a semiconductor material that can cooperate with the substrate 101 to form a nanostructure (e.g., a nanosheet, a nanowire, or the like) for a gate-all-around (GAA) device. According to some embodiments, the patterning process includes applying one or more masks over the multilayer stack 103, and then developing and etching the photoresist to form a mask over the multilayer stack 103. After the mask is formed, the mask is then used during an etching process (e.g., an anisotropic etching process) to transfer the pattern of the mask to the underlying layer and form an opening in the multilayer structure 100.

[0076] After the openings have been formed in the multilayer structure 100, source / drain regions 201 may be formed in the openings. According to some embodiments, the source / drain regions 201 may be formed by using a growth process (e.g., a selective epitaxial process) of a semiconductor material suitable for forming the desired device. For example, in an embodiment in which the source / drain regions 201 are used to form an n-type metal oxide semiconductor device, the source / drain regions 201 may be a semiconductor material such as silicon, silicon phosphorus, silicon carbon phosphorus, a combination of the foregoing, or the like. According to a specific embodiment, the source / drain regions 201 are silicon. The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, and the like, and may last from about 5 minutes to about 120 minutes, such as about 30 minutes. The epitaxial growth process may continue until the semiconductor material of the source / drain regions 201 fills and / or overfills the openings. According to some embodiments, after the epitaxial growth process has been completed, a process such as chemical mechanical planarization (CMP) is used to remove the semiconductor material of the source / drain region 201 outside the opening. However, any other suitable process may be used.

[0077] After the material of the source / drain region 201 has been formed, dopants may be implanted into the source / drain region 201 by implanting appropriate dopants to supplement the dopants in the remaining portion of the first device region 106. For example, n-type dopants such as phosphorus (P), carbon (C), arsenic (As), silicon (Si), antimony (Sb), or the like and combinations thereof (SiP, SiC, SiPC, SiAs, Si, Sb, etc.) may be implanted to form an n-type metal oxide semiconductor field effect transistor (NMOSFET) device.

[0078] In another embodiment, dopants of the source / drain region 201 may be disposed during the epitaxial growth of the source / drain region 201. For example, phosphorus may be disposed in situ when the source / drain region 201 is formed. Dopants may be disposed in the source / drain region 201 using any suitable process, and all such processes are fully intended to be included within the scope of the embodiments. Furthermore, an annealing process may be performed to activate the dopants in the source / drain region 201. During the annealing process, dopants of the source / drain region 201 may diffuse laterally into the second layer 107. In this way, a lightly doped drain (LDD) region may be formed in the second layer 107 of the first device region 106.

[0079] According to some embodiments, the source / drain region 201 is formed with straight sidewalls from the top surface of the source / drain region 201 to the bottom surface of the source / drain region 201. As such, the source / drain region 201 will maintain a shape (e.g., rectangular, square, circular, etc.) as the source / drain region 201 extends from the bottom surface of the source / drain region 201 to the top surface of the source / drain region 201. As such, the source / drain region 201 may be formed with a consistent first length L1 between about 10 nm and about 200 nm, such as about 40 nm. However, any suitable length may be used. Furthermore, the source / drain region 201 may be spaced apart at a first spacing P1 between the lengths of adjacent source / drain regions 201. According to some embodiments, the first spacing P1 may be between about 20 nm and about 150 nm, such as about 40 nm, but any suitable spacing may be used. According to some embodiments, the source / drain regions 201 may be formed to a first width W1 between about 5 nm and about 100 nm, such as about 20 nm. However, any suitable width may be used. Furthermore, the source / drain regions 201 may be spaced apart at a second spacing P2 between the widths of adjacent source / drain regions 201. According to some embodiments, the second spacing P2 may be between about 40 nm and about 180 nm, such as about 50 nm, but any suitable spacing may be used.

[0080] According to some embodiments, Figure 2A A first cut line AA, a second cut line BB, and a third cut line CC that cut through the multilayer structure 100 are further shown, and these cut lines will be referenced in the subsequent discussion of the figures. In particular, the first cut line AA extends through three source / drain regions 201 in the length direction of the source / drain regions 201. The second cut line BB extends through two source / drain regions 201 in the width direction of the source / drain regions 201. The third cut line CC extends between two sets of adjacent source / drain regions 201 in the width direction of the source / drain regions 201.

[0081] Figure 2B A schematic cross-sectional view of the multilayer structure 100 taken along a first tangent line AA is shown. Figure 2B Three source / drain regions 201 are shown extending into substrate 101. According to some embodiments, source / drain regions 201 are formed to a second height H2 between about 40 nm and about 300 nm, such as about 100 nm, although any suitable height may be used. Figure 2BThe source / drain region 201 is further shown extending into the substrate 101 below the multilayer stack 103 by a first distance Dist1. According to some embodiments, the first distance Dist1 is between about 1 nm and about 100 nm, such as about 10 nm. However, any suitable distance may be used. Although the source / drain region 201 is formed to a second height H2 in this embodiment, the source / drain region 201 may also be formed to have different heights. For example, the source / drain region 201 of the second device region 108 may be formed to have a different height than the source / drain region 201 of the first device region 106.

[0082] Figure 2C A schematic cross-sectional view of the multilayer structure 100 taken along the second tangent line BB is shown. Both source / drain regions 201 are located in the first device region 106. According to some embodiments, the source / drain regions 201 are formed to a second height H2 and extend into the substrate 101 below the multilayer stack 103 by a first distance Dist1. However, any suitable height and distance may be used.

[0083] Figure 2D A schematic cross-sectional view of the multilayer structure 100 along a third cutting line CC is shown. Figure 2D The multi-layer stack 103 has Figure 2C The two source / drain regions 201 are indicated by dotted lines and are hidden in the figure.

[0084] Figure 3A A top view showing a patterning process of the multilayer structure 100 and the formation of the isolation region 303 at an intermediate stage of manufacturing a gate-all-around (GAA) device according to some embodiments. The patterning process is used to form the fins 301 in the multilayer structure 100. According to some embodiments, two fins 301 in the multilayer structure 100 are patterned using two adjacent columns of source / drain regions 201 to form the fins 301. According to some embodiments, the first thickness Th1 is between about 5 nm and about 150 nm, for example about 20 nm.

[0085] Although Figure 3A Each column of adjacent source / drain regions 201 is shown patterned as a single fin, but in other embodiments, each column of adjacent source / drain regions 201 may be patterned as two or more fins 301. Again, any suitable number of columns of adjacent source / drain regions 201 may be formed in the multilayer structure 100, and each column may be patterned as any suitable number of fins 301. The formation of the fins 301 will be discussed in more detail below with reference to subsequent figures.

[0086] After the fin 301 has been formed, the remaining portion of the multilayer stack 103 defines a channel region 305 in the fin 301, the channel region 305 being separated by the source / drain region 201. The channel region 305 is defined to have a second length L2 and a first thickness Th1. According to some embodiments, the second length L2 may be between about 5 nm and about 100 nm, such as about 10 nm. However, any suitable length and any suitable thickness may be used.

[0087] After the fins 301 have been formed, isolation regions 303 are formed over the substrate 101 and separate the fins 301 from each other. The isolation regions 303 may be formed to a third width W3 between about 15 nm and about 150 nm, such as about 30 nm, but any suitable width may be used. The formation of the isolation regions 303 will be discussed in more detail below with reference to subsequent figures.

[0088] Please refer to Figure 3B , this figure shows more details about the formation of the fin 301 and the isolation region 303 on the second tangent line BB. In one embodiment, the multilayer stack 103 is formed of a semiconductor material that can cooperate with the substrate 101 to help form nanostructures (such as nanosheets, nanowires, or the like) for a gate-all-around (GAA) device. According to some embodiments, a patterning process to form the fin 301 includes applying a photoresist over the multilayer stack 103, then patterning and developing the photoresist to form a mask over the multilayer stack 103. After the mask is formed, the mask is then used during an etching process (such as an anisotropic etching process) to transfer the pattern of the mask to the underlying layer to form trenches in the multilayer structure 100 and define the fins 301, wherein the fins 301 are separated by the trenches. The etching process is used to form trenches having a first depth D1 in the multilayer structure 100. According to some embodiments, the first depth D1 is between about 20 nm and about 600 nm, such as about 100 nm, but any suitable depth can be used. Although not Figure 3A and 3B However, a portion of the first layer 105, the second layer 107, and the substrate 101 are exposed along the sidewalls of the fin 301 because the thin strips are alternately stacked in the multilayer structure 100 along the first depth D1 of the trench.

[0089] Furthermore, while a single mask process has been described, this is illustrative only and is not intended to be limiting, as the all-around gate (GAA) device structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the all-around gate device structure may then be patterned using the remaining spacers.

[0090] In one embodiment, the isolation region 303 is formed as a shallow trench isolation region by depositing a dielectric material in the trench. According to some embodiments, the dielectric material used to form the isolation region 303 may be, for example, an oxide material (e.g., a flowable oxide), a high-density plasma (HDP) oxide, or the like. After selectively cleaning and lining the trench, the dielectric material may be formed by using a chemical vapor deposition (CVD) method (e.g., a high aspect ratio process (HARP)), a high-density plasma chemical vapor deposition method, or other suitable formation method to fill or overfill the area around the fin 301.

[0091] After densification, excess dielectric material may be removed by a suitable process, such as chemical mechanical polishing (CMP), etching, combinations thereof, or the like. In one embodiment, the removal process also removes any dielectric material above the fin 301, such that the removal of the dielectric material exposes the surface of the fin 301 to further processing steps.

[0092] After the dielectric material has been deposited to fill or overfill the area around the fin 301, the dielectric material may then be recessed from the surface of the fin 301 to form the isolation region 303. The recessing may be performed to expose at least a portion of the sidewall of the fin 301 adjacent to the top surface of the fin 301. The dielectric material may be recessed by using a dry etch, which may be performed by immersing the top surface of the fin 301 in an etchant that is selective to the material of the dielectric material, but other methods may be used, such as reactive ion etching, dry etching, chemical oxide removal, or dry chemical cleaning. In some embodiments, the isolation region 303 may be formed to a fourth height H4 between about 10 nm and about 300 nm, such as about 50 nm. However, any suitable height may be used for the fourth height H4.

[0093] Figure 3B It is further shown that the exposed area of ​​the fin 301 above the isolation region 303 may be a fifth height H5 above the isolation region 303. According to some embodiments, the fifth height H5 may be a height between about 10 nm and about 300 nm, such as about 50 nm. However, any suitable height may be used for the fifth height H5.

[0094] However, those skilled in the art will appreciate that the above steps may be only part of the overall process flow for filling and recessing the dielectric material. For example, a liner step, a cleaning step, an annealing step, a gap filling step, a combination of the foregoing, or the like may also be used to form the dielectric material. All potential process steps are fully intended to be included within the scope of the embodiments.

[0095] Figure 4A A top view showing the formation of a dummy gate stack 401 above a channel region 305 in a fin 301 at an intermediate stage of fabricating a gate-all-around (GAA) device according to some embodiments. In particular, Figure 4A Further shown is a first tangent line AA extending through three source / drain regions 201 and two dummy gate stacks 401 in the length direction of one of the fins 301. A second tangent line BB extends through two source / drain regions 201, each of which is located in a different one of the two fins 301, and is located between the dummy gate stacks 401. A third tangent line CC extends through one dummy gate stack 401 and two fins 301. Figure 4A A second hard mask 409 of the dummy gate stack 401 is further shown, and the second hard mask 409 will be discussed in more detail below with reference to subsequent figures.

[0096] Please refer to Figure 4B , this figure shows in more detail the formation of the dummy gate stack 401 with reference to the first tangent line AA. In particular, Figure 4B Two dummy gate stacks 401 are shown formed over the fin 301. Each dummy gate stack 401 is located on top of the channel region 305 in one of the first device region 106 and the second device region 108.

[0097] In accordance with some embodiments, the dummy gate stack 401 is formed by initially forming a dummy gate dielectric 403 above the fin 301. In one embodiment, the dummy gate dielectric 403 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known to and used by those skilled in the art for forming a gate dielectric. Depending on the technology of the gate dielectric, the thickness of the dummy gate dielectric 403 at the top may be different from the thickness of the dummy gate dielectric 403 on the sidewalls. In some embodiments, the dummy gate dielectric 403 may be formed by depositing a material (e.g., silicon) and then oxidizing or nitriding the silicon layer to form a dielectric (e.g., silicon dioxide or silicon oxynitride). In these embodiments, the dummy gate dielectric 403 may be formed to a thickness of about 100 Å to about 500 Å. About In the range between, for example, about In other embodiments, the dummy gate dielectric 403 may also be formed of a high-k material, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON) or zirconium oxide (ZrO 2 ) or a combination of the foregoing, and having an equivalent oxide thickness of about About Between, for example In addition, silicon dioxide, silicon oxynitride and / or a high dielectric constant material may also be used for the dummy gate dielectric 403 .

[0098] After the dummy gate dielectric 403 has been formed, the dummy gate electrode 405 may include a conductive material and may be selected from the group consisting of polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of the foregoing, or the like. The dummy gate electrode 405 may be deposited by chemical vapor deposition (CVD), sputtering, or other techniques known to those skilled in the art for depositing conductive materials. The thickness of the dummy gate electrode 405 may be about 1000 Å. About The top surface of the dummy gate electrode 405 may have a non-planar top surface and may be planarized before patterning or gate etching the dummy gate electrode 405. At this stage, ions may or may not be introduced into the dummy gate electrode 405. The ions may be introduced, for example, by ion implantation techniques.

[0099] After the dummy gate electrode 405 has been formed, the dummy gate dielectric 403 and the dummy gate electrode 405 may be patterned. In one embodiment, the patterning may be performed by first forming a first hard mask 407 over the dummy gate electrode 405 and forming a second hard mask 409 over the first hard mask 407.

[0100] According to some embodiments, the first hard mask 407 includes a dielectric material such as silicon oxide, silicon nitride, titanium nitride, silicon oxynitride, combinations thereof, or the like. The first hard mask 407 may be formed by a process using, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable material and formation method may be used. The first hard mask 407 may be formed to a thickness of about About Between, for example

[0101] According to some embodiments, the second hard mask 409 includes a respective dielectric material, such as silicon nitride, silicon oxide, titanium nitride, silicon oxynitride, combinations thereof, or the like. The second hard mask 409 may be formed by a process using, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or the like. However, any other suitable material and formation method may be used. The second hard mask 409 may be formed to a thickness of about About Between, for example

[0102] Figure 4C The formation of the dummy gate stack 401 is shown in more detail with reference to the third cut line CC. In particular, Figure 4C A dummy gate stack 401 is shown formed over two fins 301. A dummy gate dielectric 403 is formed along the sidewalls of the fins 301 and over the tops of the fins 301. A dummy gate electrode 405 is formed over the fins 301 and surrounds the dummy gate dielectric 403. A first hard mask 407 and a second hard mask 409 are disposed over the dummy gate electrode 405.

[0103] Please refer to Figure 5A and 5B , these figures show the formation of the first spacer layer 501 (of the top gate spacer) with reference to the first cut line AA and the second cut line BB, respectively. According to one embodiment, the first spacer layer 501 is formed by blanket deposition on the multilayer structure 100. As such, the first spacer layer 501 is deposited over the top surface and sidewalls of the dummy gate stack 401, the top surface and sidewalls of the source / drain region 201, and the top surface of the isolation region 303. According to some embodiments, the first spacer layer 501 may include a dielectric material, such as silicon oxide (SiO 2), silicon oxynitride (SiON), silicon nitride (Si 3 N 4 ), silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), but any suitable material may be used, such as a low dielectric constant material having a dielectric constant value of less than about 4.0, a combination of the foregoing, or the like. The first spacer layer 501 may be formed by using, for example, chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition, sputtering, thermal oxidation, or any other suitable method.

[0104] After the first spacer layer 501 has been formed, an optional second spacer layer (not shown separately) may be formed by blanket deposition over the first spacer layer 501. The optional second spacer layer may be formed by any material and method suitable for forming the first spacer layer 501.

[0105] After the first spacer layer 501 is formed, the first spacer layer 501 and the optional second spacer layer (if formed) may be etched to shape these spacers on the dummy gate stack 401 and the source / drain region 201. In one embodiment, the first spacer layer 501 and the optional second spacer layer may be recessed by using an anisotropic etching process (e.g., a dry etching process) (e.g., a reactive ion etching (RIE) process), an isotropic etching process (e.g., a wet etching process), a combination of the foregoing, or the like. During the etching process, an initial etching step may be performed to remove the material of the first spacer layer 501 and the optional second spacer layer (if formed) from all horizontal surfaces of the multilayer structure 100. In this way, the top of the dummy gate stack 401, the top of the source / drain region 201, and the top of the isolation region 303 are exposed.

[0106] If desired, in some embodiments, a further etching step may be performed to recess the remaining portions of the first spacer layer 501 and the optional second spacer layer. According to some embodiments, the remaining portions of the optional second spacer layer may be recessed along the vertical sidewalls of the dummy gate stack 401, so that only the first spacer layer 501 remains along the sidewalls of the dummy gate stack 401. According to some embodiments, the remaining portions of the first spacer layer 501 and the remaining portions of the optional second spacer layer may be recessed along the vertical sidewalls of the source / drain region 201, so that the tops of the vertical sidewalls of the source / drain region 201 are exposed, and the bottoms of the vertical sidewalls of the source / drain region 201 are still covered by the first spacer layer 501 and the optional second spacer layer.

[0107] However, although the described embodiments use one or two dielectric spacer layers, this is illustrative only and not limiting. Rather, any number of spacer layers and any combination of deposition and removal processes may be used and are fully intended to be included within the scope of the embodiments.

[0108] Please refer to Fig. 6A , this figure shows the formation of a contact etch stop layer (CESL) 601 and a first interlayer dielectric (ILD) 603 with reference to a first tangent line AA. In some embodiments, the contact etch stop layer 601 is formed by blanket deposition on the exposed surfaces of the second hard mask 409, the first spacer layer 501, and the source / drain region 201. The contact etch stop layer 601 includes a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etching rate from the first interlayer dielectric 603.

[0109] After the contact etch stop layer 601 has been formed, the first interlayer dielectric 603 may be formed as a bulk material layer above the contact etch stop layer 601. According to some embodiments, the first interlayer dielectric 603 includes a dielectric material and is deposited using a suitable method, such as chemical vapor deposition, plasma-enhanced CVD (PECVD), or flowable chemical vapor deposition (FCVD), although other processes such as low pressure chemical vapor deposition (LPCVD) may also be used. The first interlayer dielectric 603 can be formed by using, for example, silicon dioxide, a low dielectric constant material (e.g., a material having a dielectric constant lower than that of silicon dioxide, such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), SiO x C y ), spin-on glass, spin-on polymer, silicon carbon material, compounds of the foregoing, composites of the foregoing, the like, or combinations thereof, but any suitable dielectric may be used.

[0110] Figure 6BThe deposition of the contact etch stop layer 601 and the first interlayer dielectric 603 in the first device region 106 is shown with reference to the second tangent line BB. In particular, Figure 6B A contact etch stop layer 601 is shown deposited over the exposed surfaces of the source / drain regions 201 , the first spacer layer 501 , and the isolation regions 303 . A first interlayer dielectric 603 is deposited over the contoured surface of the contact etch stop layer 601 .

[0111] Figure 6C The deposition of the contact etch stop layer 601 and the first interlayer dielectric 603 is shown with reference to the third cut line CC. According to some embodiments, the contact etch stop layer 601 and the upper first interlayer dielectric 603 are disposed over the top of the second hard mask 409 .

[0112] Please refer to Fig. 7A , this figure shows a planarization process after the first interlayer dielectric 603 has been deposited. According to some embodiments, the first interlayer dielectric 603 can be planarized with the first spacer layer 501 by using a planarization process (e.g., a chemical mechanical polishing process), but any suitable process can be used. In addition, the planarization process can also remove the second hard mask 409 and stop on the first hard mask 407. After the planarization process has been completed, the first hard mask 407 and the dummy gate electrode 405 can be removed to expose the dummy gate dielectric 403. In one embodiment, the first hard mask 407 can be removed by using an etching process or a planarization process (e.g., continuing a previous chemical mechanical polishing process) to remove the material of the first hard mask 407. However, any method suitable for removing the first hard mask 407 to expose the material of the dummy gate electrode 405 can be used.

[0113] After the dummy gate electrode 405 has been exposed, the dummy gate electrode 405 may be removed to expose the dummy gate dielectric 403 in the first device region 106 and / or the second device region 108. In one embodiment, the dummy gate electrode 405 may be removed by using, for example, one or more wet etching processes or dry etching processes that use an etchant that is selective to the material of the dummy gate electrode 405. However, any suitable removal process may be used.

[0114] Figure 7B The planarization process and removal of the first hard mask 407 and the dummy gate electrode 405 above the channel region 305 with reference to the third cut line CC are shown. In particular, the first interlayer dielectric 603, the contact etch stop layer 601, the second hard mask 409, the first hard mask 407, and the dummy gate electrode 405 are removed during the planarization process or etching process described above. As a result, the dummy gate dielectric 403 is exposed in the channel region 305 of the first device region 106.

[0115] Fig. 8A and 8B The removal of the dummy gate dielectric 403 and the line release process in the channel region 305 are shown in accordance with some embodiments. In particular, Fig. 8A 1. The wire release process in the first device area 106 and the second device area 108 is shown with reference to the first tangent line AA, Figure 8B The wire-releasing process in the first device region 106 is shown with reference to the third tangent line CC. The wire-releasing process step may also be referred to as a sheet-releasing process step, a sheet-forming process step, a nanosheet-forming process step, or a wire-forming process step.

[0116] After the dummy gate dielectric 403 has been exposed, the dummy gate dielectric 403 in the first device region 106 and the second device region 108 may be removed. In one embodiment, the dummy gate dielectric 403 may be removed using, for example, a wet etching process, although any suitable etching process may be used.

[0117] Fig. 8A and 8B It is further shown that after the dummy gate dielectric 403 has been removed (this step also exposes the side of the first layer 105), the first layer 105 between the substrate 101 and the second layer 107 and between the second layer 107 in the first device area 106 and / or the second device area 108 can be removed. In one embodiment, the first layer 105 can be removed by using a wet etching process that selectively removes the material of the first layer 105 (e.g., silicon germanium (SiGe)) without significantly removing the material of the substrate 101 and the material of the second layer 107 (e.g., silicon (Si)). However, any suitable removal process can be used. In one embodiment, an etchant such as high temperature HCl can be used. In addition, the wet etching process can be performed at a temperature between about 400° C. and about 600° C., such as about 560° C., and for a duration between about 100 seconds and about 600 seconds, such as about 300 seconds. However, any suitable etchant, process parameters, and time can be used.

[0118] By removing the material of the first layer 105, the material of the second layer 107 (in Fig. 8A 8 (re-labeled as nanostructure 801 in FIG. 1 ) is formed as a stack of nanostructures 801 in the first device region 106 and / or the second device region 108, and the nanostructures 801 are separated from each other. The stack of nanostructures 801 includes a channel region 305 extending between the source / drain regions 201 on both sides in the first device region 106 and / or the second device region 108. In one embodiment, the nanostructure 801 is formed to have a thickness that is the same as or thinner than the original thickness of the second layer 107.

[0119] Fig. 8AThe nanostructure 801 is further shown to span a second distance Dist2 between adjacent source / drain regions 201 within the fin 310 along the first tangent line AA. The second distance Dist2 of the nanostructure 801 may represent the channel length in the channel region 305. According to some embodiments, the second distance Dist2 is between about 5nm and about 100nm, for example, about 10nm. However, any suitable distance may be used. In addition, the nanostructure 801 of the first device region 106 and the second device region 108 may span a third distance Dist3 between the outermost interfaces of the source / drain region 201 along the first tangent line AA of the fin 301. According to some embodiments, the third distance Dist3 is between about 10nm and about 300nm, for example, about 30nm. However, any suitable distance may be used. The source / drain region 201 also supports the nanostructure 801 and helps prevent the nanosheet from collapsing during the online release process step.

[0120] In addition, although Fig. 8A Three nanostructures 801 are shown formed in the stack, but any number of nanostructures 801 may be formed by the second layer 107 provided in the multilayer stack 103. For example, the multilayer stack 103 may be formed to include any number of first layers 105 and any number of second layers 107. As such, a multilayer stack 103 including fewer first layers 105 and fewer second layers 107 may form one or two nanostructures 801 in the stack after the first layer 105 is removed. Conversely, a multilayer stack 103 including many first layers 105 and many second layers 107 may form four or more nanostructures 801 in the stack after the first layer 105 is removed.

[0121] Figure 8B A schematic cross-sectional view of the first device region 106 along the third cut line CC is shown. As shown in the figure, with the removal of the dummy gate dielectric 403, the second layer 107 (at Figure 8B Thus, the first layer 105 (e.g. Fig. 7A ) may be exposed to an etchant and removed from between the substrate 101 and the second layer 107 and between the second layer 107 to form a nanostructure 801 in the first device region 106 and / or the second device region 108. Figure 8B A fourth distance Dist4 of the nanostructure 801 is further shown. The fourth distance Dist4 may represent a channel width in the channel region 305. According to some embodiments, the fourth distance Dist4 is between about 5 nm and about 100 nm, such as about 10 nm. However, any suitable distance may be used.

[0122] Fig.9A and 9BThe formation of gate dielectric 901 and gate contact 903 is shown according to some embodiments. In particular, Fig.9A The formation of the gate dielectric 901 and the gate contact 903 is shown with reference to a first tangent line AA through the channel region 305 of the first device region 106 and the second device region 108, and Fig. 9B The formation of the gate dielectric 901 and the gate contact 903 is shown with reference to a third cut line CC through the channel region 305 of the first device region 106 .

[0123] According to some embodiments, after the nanostructure 801 has been exposed, a gate dielectric 901 may be formed around the nanostructure 801. In some embodiments, before forming the gate dielectric 901, an optional first interfacial layer (not shown separately) may be formed around the nanostructure 801. In some embodiments, the first interfacial layer includes a buffer material, such as silicon oxide, but any suitable material may be used. The first interfacial layer may be formed around the nanostructure 801 to a thickness of about 1000 Å by using processes such as chemical vapor deposition, physical vapor deposition, or even oxidation. About Between, for example However, any suitable process or thickness may be used. Furthermore, according to some embodiments, the width of the gate dielectric 901 between the source / drain regions 201 may be equal to the second distance Dist2. According to some embodiments, the interface between the gate dielectric 901 and the nanostructure 801 may be equal to the channel length of the channel region 305.

[0124] In one embodiment, the gate dielectric 901 includes a high dielectric constant material (eg, dielectric constant value>=9), such as Ta. 2 O 5 、Al 2 O 3 , Hf oxide, Ta oxide, Ti oxide, Zr oxide, Al oxide, La oxide (such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, TiO), combinations of the foregoing, or the like, and deposited by processes such as atomic layer deposition, chemical vapor deposition, or the like. In some embodiments, gate dielectric 901 includes a nitrogen-doped oxide dielectric formed prior to forming a metal-containing high dielectric constant (e.g., dielectric constant value>13) dielectric material. Gate dielectric 901 may be deposited to a thickness between about 1 nm and about 3 nm, but any suitable material and thickness may be used. Fig.9A and 9B As shown, the gate dielectric 901 surrounds and separates the nanostructures 801 , thereby forming a stack of channels in the fins 301 in the first device region 106 and the second device region 108 .

[0125] Furthermore, in some embodiments, the first interface layer and / or the gate dielectric 901 physically contacts the source / drain region 201. In particular, the first interface layer and / or the gate dielectric 901 are formed without forming additional spacers between the nanostructures 801. Without these spacers, the overall process can be simplified and made more efficient. Fig.9A As shown, each nanostructure 801 in the stack extends between adjacent source / drain regions 201, and the gate dielectric 901 directly contacts the source / drain regions 201. Fig. 9B As shown, each gate dielectric 901 surrounds each nanostructure 801 in the stack.

[0126] Fig.9A and 9B The gate contact 903 is further shown formed to surround the nanostructures 801 in the first device region 106 and / or the second device region 108. In one embodiment, the gate contact 903 is formed by using multiple layers, each layer being sequentially deposited adjacent to each other using a highly compliant deposition process, such as atomic layer deposition, but any suitable deposition process may be used. According to some embodiments, the gate contact 903 may include a cap layer, a barrier layer, an n-type metal work function layer, a p-type metal work function layer, and a fill material. Furthermore, as Fig. 9B As shown, the gate contact 903 is above and surrounds the gate dielectric 901 , and the gate dielectric 901 surrounds each nanostructure 801 .

[0127] The cap layer may be formed adjacent to the gate dielectric 901 and may be formed of a metal material (e.g., TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN), other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations of the foregoing, or the like. The metal material may be deposited by a deposition process using, for example, atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.

[0128] The barrier layer may be formed adjacent to the cap layer and may be formed of a different material than the cap layer. For example, the barrier layer may be formed of one or more layers of material, such as one or more layers of a metal material, such as TiN, TaN, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations of the foregoing, or the like. The barrier layer may be deposited by a deposition process using, for example, atomic layer deposition, chemical vapor deposition, or the like, although any suitable deposition process may be used.

[0129] The n-type metal work function layer may be formed adjacent to the barrier layer. In one embodiment, the n-type metal work function layer is a material such as W, Cu, AlCu, TiAlC, TiAlN, TiAl, Pt, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the n-type metal work function layer may be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition process, or the like. However, any suitable material and process may be used to form the n-type metal work function layer.

[0130] The p-type metal work function layer may be formed adjacent to the n-type metal work function layer. In one embodiment, the p-type metal work function layer may be formed of a metal material, such as W, Al, Cu, TiN, Ti, TiAlN, TiAl, Pt, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi 2 、NiSi 2 、Mn、Zr、ZrSi 2 , TaN, Ru, AlCu, Mo, MoSi 2 , WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations of the foregoing, or the like. In addition, the p-type metal work function layer may be deposited by a deposition process using, for example, atomic layer deposition, chemical vapor deposition, or the like, but any suitable deposition process may be used.

[0131] After the p-type metal work function layer has been formed, a fill material is deposited to fill the remaining portion of the opening. In one embodiment, the fill material may be tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TiAl, Pt, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, a combination of the foregoing, or the like, and may be formed by a deposition process using, for example, plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination of the foregoing, or the like. However, any suitable material may be used.

[0132] According to some embodiments, one or more layers in the gate contact 903 in the first device region 106 and the second device region 108 can be formed in the same series of steps. For example, the cap layer and the barrier layer in the gate contact 903 can be formed at the same time, while other layers (e.g., the n-type metal work function layer and the p-type metal work function layer can be formed and / or patterned independently of each other). Any suitable deposition and removal can be used to form the gate contact 903 in the first device region 106 and the second device region 108.

[0133] After the openings left by removing the dummy gate electrodes 405 have been filled, the material of the gate contacts 903 in the first device region 106 and the second device region 108 may be planarized to remove any material outside of the openings left by the dummy gate electrodes 405. In a particular embodiment, this removal may be performed using a planarization process such as chemical mechanical polishing. However, any suitable planarization and removal process may be used.

[0134] Please refer to Figures 10A-10C , these figures show the recessing of the gate contact 903 and the deposition of the dielectric capping layer 1001 according to some embodiments. After the gate contact 903 has been formed, the material of the gate contact 903 and the gate dielectric 901 can be recessed below the planarized surface of the first interlayer dielectric 603. After the recessing, the dielectric capping layer 1001 can be formed in the recess, and then the dielectric capping layer 1001 can be planarized with the first interlayer dielectric 603. In one embodiment, the dielectric capping layer 1001 can be a dielectric material (such as a silicon nitride layer or a high-k dielectric layer) and is formed by a deposition process using, for example, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of the foregoing, or the like. After the dielectric capping layer 1001 has been formed, the dielectric capping layer 1001 can be planarized by using a planarization process (such as a chemical mechanical polishing process). According to some embodiments, the first spacer layer 501 and / or the contact etch stop layer 601 may be recessed along the gate dielectric 901 and the gate contact 903. In these embodiments, the dielectric cap layer 1001 is formed on top of the first spacer layer 501 and the contact etch stop layer 601 as well as the gate dielectric 901 and the gate contact 903.

[0135] Figures 10A-10C It is further shown that the second interlayer dielectric 1003 can be formed by depositing a dielectric material over the first device region 106 and the second device region 108. The second interlayer dielectric 1003 can be formed and planarized by any of the processes and materials described above as being suitable for forming the first interlayer dielectric 603.

[0136] Continue to Fig.11A and 11B , these figures show the formation of source / drain contacts 1101 according to some embodiments. In some embodiments, the steps for forming source / drain contacts 1101 in the first device region 106 and the steps for forming source / drain contacts 1101 in the second device region 108 are performed separately, but some or all of the steps may be performed together.

[0137] In an initial step of forming the source / drain contacts 1101, the second interlayer dielectric 1003, the first interlayer dielectric 603, and the contact etch stop layer 601 are etched to form openings above the source / drain regions 201 and to expose the surfaces of the source / drain regions 201. These openings may be formed using an anisotropic etching process, such as a reactive ion etching (RIE) process, a neutral beam etch (NBE), or the like. In some embodiments, a first etching process may be used to etch the openings through the second interlayer dielectric 1003 and the first interlayer dielectric 603, and then a second etching process may be used to etch the openings through the contact etch stop layer 601. A mask (e.g., a photoresist) may be formed over the second interlayer dielectric 1003 and patterned to shield portions of the second interlayer dielectric 1003 from the first etching process and the second etching process.

[0138] According to some embodiments, the protective layer 1103 may be formed along the sidewalls of the openings in the second interlayer dielectric 1003, the first interlayer dielectric 603, and the contact etch stop layer 601. In some embodiments, a dielectric material may be deposited as a compliant layer above the second interlayer dielectric 1003 and in the openings, so that the dielectric material conforms to the exposed surfaces of the source / drain regions 201 and along the sidewalls of the openings. This compliant layer of dielectric material may be deposited by thermal oxidation or by chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like, and may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. After the dielectric material is formed, the compliant layer of dielectric material may be etched using a suitable etching process (e.g., anisotropic etching (e.g., a dry etching process) or the like) to remove the dielectric material on the top surface of the second interlayer dielectric 1003 and re-expose the source / drain regions 201 in the openings. As Fig.11A and 11BAs shown, the remaining portion of the dielectric material forms a protective layer 1103 along the sidewalls of the opening.

[0139] According to some embodiments, the material of the source / drain region 201 is etched to extend the opening into the source / drain region 201. In some embodiments, the source / drain region 201 may be etched by an anisotropic etching process such as reactive ion etching (RIE), neutron beam etching (NBE), or the like. The source / drain region 201 may be etched by an iterative etching process different from the etching process used to etch the first interlayer dielectric 603, the second interlayer dielectric 1003, and the contact etch stop layer 601.

[0140] Fig.11A and 11B The formation of silicide contacts 1105 according to some embodiments is further shown to reduce the Schottky barrier height of the source / drain contacts 1101. In some embodiments, the silicide contacts 1105 are formed using materials such as titanium, nickel, cobalt, or erbium. However, other metals such as platinum, palladium, and the like may also be used. Silicidation may be performed by blanket deposition of a suitable metal layer followed by annealing to cause the metal to react with the exposed silicon below the source / drain region 201. Unreacted metal is then removed, for example, by a selective etching process. The thickness of the silicide contacts 1105 may be between about 5 nm and about 50 nm. However, any suitable thickness may be used.

[0141] In one embodiment, the source / drain contacts 1101 may be a conductive material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations of the foregoing, or the like, but any suitable material may be deposited into the opening using a deposition process to fill and / or overfill the opening, such as sputtering, chemical vapor deposition, electroplating, electroless plating, or the like. After filling or overfilling the opening, any deposited material outside the opening may be removed using a planarization process, such as chemical mechanical polishing (CMP). However, any suitable material and formation process may be used.

[0142] Furthermore, according to some embodiments, Fig.11A It is further shown that some source / drain regions 201 can be shared between the first device region 106 and the second device region 108. Furthermore, the shared source / drain regions 201 can be electrically connected via a source / drain contact 1101 and a silicide contact 1105 for external connection. According to some embodiments, Fig. 11BIt is further shown that the source / drain contact 1101 in the first device region 106 is sized to span between and electrically connect two source / drain regions 201 in the first device region 106. A silicide contact 1105 is formed at the interface of each source / drain region 201. However, in some other embodiments, a separate source / drain contact 1101 and a separate silicide contact 1105 may be formed to each source / drain region 201.

[0143] Please refer to Fig. 12A and 12B , these figures show that a conductive plug 1201 is formed to the source / drain contacts 1101 and the gate contact 903 of the semiconductor device 1200 according to some embodiments. According to some embodiments, the semiconductor device 1200 can be a gate all around (GAA) device. However, other suitable devices can also be used. A third interlayer dielectric 1203 can be formed by first forming the second interlayer dielectric 1003 and the source / drain contacts 1101 in the first device region 106 and the second device region 108. The third interlayer dielectric 1203 can be formed by using any of the materials and methods described above that are suitable for forming and planarizing the first interlayer dielectric 603.

[0144] In addition, after forming the third interlayer dielectric 1203, a conductive plug 1201 may be formed through the third interlayer dielectric 1203 and the dielectric cap layer 1001 to provide electrical connection. In one embodiment, a first opening through the third interlayer dielectric 1203 may be formed above the source / drain contact 1101, and a second opening through the second interlayer dielectric 1003 and through the dielectric cap layer 1001 may be formed above the gate contact 903 by using, for example, a masking and etching process. After the opening has been formed, a conductive material (e.g., copper) may be deposited using a deposition process (e.g., plating, chemical vapor deposition, sputtering, a combination of the foregoing, or the like) to fill and / or overfill the opening. Then, a planarization process (e.g., chemical mechanical polishing or the like) may be used to remove excess material.

[0145] A replacement polysilicon gate (RPG) loop process or a multi-patterning gate (MPG) loop process may be used to pattern the gate electrode of the fin field effect transistor. The polysilicon gate or the multi-patterning gate loop may damage the gate undesirably due to the undesirable reduction of the gate height. In the conventional nanosheet fin field effect transistor process, the source / drain epitaxial layer is formed before the nanosheet to prevent the nanosheet from collapsing, which may reduce the accuracy of the optical critical-dimension (OCD) measurement. The test pattern before the source / drain epitaxial layer can be used to replace the polysilicon gate loop and the multi-patterning gate loop to control the gate height and the bias voltage (Vt). The embodiments of the present disclosure provide one or more of the following advantages. According to some embodiments, the source / drain region 201 is formed as a homogeneous block of silicon. Furthermore, the source / drain region 201 is formed before the fin 301 is formed. The source / drain regions 201 provide support for the nanostructures 801 during the line release process and further processing of the nanostructures 801 in the channel region 305. In this way, undesirable destruction of the nanostructures 801 (e.g., due to nanosheet collapse during the line release process) can be prevented, even if the nanostructures 801 span a distance greater than 30 nm in embodiments. Furthermore, highly accurate measurements of the critical dimensions of the nanostructures 801 can be achieved during formation (e.g., using in-line optical critical dimension (OCD) monitoring) with little or no disturbance caused by subsequent changes during the source / drain epitaxial growth process. In this way, these highly accurate critical dimensions can be used to help control process parameters (e.g., bias voltage (Vt), etching parameters, etching time, and / or the like) to control the formation of the nanostructures 801 (e.g., during line release) and / or to control the gate height during the formation of the gate dielectric 901 and the gate contact 903. Furthermore, these critical dimensions can also be used as feedback to improve process recipes and maintain manufacturing consistency across a batch of subsequently formed wafers. Furthermore, the process described herein can be integrated into other manufacturing processes (e.g., etch and growth processes for p-type metal oxide semiconductors and other etch and growth processes) so that the overall manufacturing process does not require additional costs. Thus, the disclosed embodiments provide a robust optical critical dimension model in replacement polysilicon gate loops and multi-patterned gate loops without interference from source / drain epitaxy process variations.

[0146] According to one embodiment, a method includes: forming a multilayer stack above a substrate, the multilayer stack including a first layer, a second layer above the first layer, a third layer above the second layer, and a fourth layer above the third layer, the first layer and the third layer including a first semiconductor material, and the second layer and the fourth layer including a second semiconductor material; etching a first opening in the multilayer stack, the first opening exposing the substrate; forming a first source / drain region in the first opening; etching a fin from the multilayer stack after forming the first source / drain region; removing the first layer and the third layer from the fin; and forming a gate structure to surround the second layer and the fourth layer. In one embodiment, the step of forming the first source / drain region also includes depositing a second semiconductor material in the first opening. In one embodiment, the second semiconductor material is silicon. In one embodiment, in the step of forming the gate structure, the gate structure physically contacts the first source / drain region. In one embodiment, the shape of the first source / drain region in a top view is rectangular. In one embodiment, the step of forming the first source / drain region includes epitaxially growing the first source / drain region. In one embodiment, the first source / drain region has a first width, and the fin has a first width.

[0147] According to another embodiment, a method includes: forming a first opening in a multilayer structure; forming a first source / drain region in the first opening; after forming the first source / drain region, etching the multilayer structure to form a fin; performing a line release process on the fin to form a plurality of nanostructures; and after performing the line release process, depositing a gate structure around each of the plurality of nanostructures. In one embodiment, the step of forming the first source / drain region includes depositing a silicon material in the first opening. In one embodiment, the line release process includes using a selective etching process to remove a first semiconductor material from the fin, the first semiconductor material being different from the semiconductor material of each remaining layer of the multilayer structure. In one embodiment, the first source / drain region has a straight sidewall from the top of the first source / drain region to the bottom of the first source / drain region. In one embodiment, the fin has a first width, and the first source / drain region has a first width. In one embodiment, the first source / drain region includes a first material, and the plurality of nanostructures include the first material. In one embodiment, the method further includes, after etching the multilayer structure, forming an isolation region adjacent to the first source / drain region.

[0148] According to another embodiment, a semiconductor device includes: a first source / drain region; a second source / drain region; a stack of nanostructures, each nanostructure in the stack of nanostructures extending between the first source / drain region and the second source / drain region; a gate dielectric layer surrounding each nanostructure in the stack of nanostructures, wherein the gate dielectric layer directly physically contacts the first source / drain region and the second source / drain region; and a gate contact surrounding the gate dielectric layer. In one embodiment, the first source / drain region and the second source / drain region are silicon. In one embodiment, the distance between the first source / drain region and the second source / drain region is at least 30 nm. In one embodiment, the first source / drain region has a straight sidewall from the top of the first source / drain region to the bottom of the first source / drain region. In one embodiment, the shape of the first source / drain region in a top view is rectangular. In one embodiment, the stack of nanostructures has a first width, and the first source / drain region has a first width.

[0149] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present disclosure from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present disclosure, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the public concept and scope of the present disclosure. Various changes, substitutions or modifications may be made to the embodiments of the present disclosure without departing from the public concept and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a multilayer stack over a substrate, the multilayer stack comprising a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer, the first layer and the third layer comprising a first semiconductor material, and the second layer and the fourth layer comprising a second semiconductor material; etching a first opening in the multilayer stack, the first opening exposing the substrate; forming a first source / drain region in the first opening; After forming the first source / drain region, forming a dummy gate structure and etching a fin from the multi-layer stack; removing the first layer and the third layer from the fin; as well as A gate structure is formed to surround the second layer and the fourth layer. 2 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the step of forming the first source / drain region further comprises depositing the second semiconductor material in the first opening. 3 . The method for manufacturing a semiconductor device as claimed in claim 2 , wherein the second semiconductor material is silicon. 4 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein in the step of forming the gate structure, the gate structure physically contacts the first source / drain region. 5 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first source / drain region is rectangular in shape in a top view. 6 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the step of forming the first source / drain region comprises epitaxially growing the first source / drain region. 7 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first source / drain region has a first width, and the fin has the first width.

8. A method for manufacturing a semiconductor device, comprising: forming a first opening in a multi-layer structure; forming a first source / drain region in the first opening; After forming the first source / drain region, etching the multilayer structure to form a fin; After forming the first source / drain region, forming a dummy gate structure; performing a line releasing process on the fin to form a plurality of nanostructures; as well as After performing the line release process, a gate structure is deposited around each of the plurality of nanostructures. 9 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the step of forming the first source / drain region comprises depositing a silicon material in the first opening. 10 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the line release process comprises using a selective etching process to remove a first semiconductor material from the fin, the first semiconductor material being different from semiconductor materials of each remaining layer of the multi-layer structure. 11 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the first source / drain region has a straight sidewall from a top of the first source / drain region to a bottom of the first source / drain region. 12 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the fin has a first width, and the first source / drain region has the first width. 13 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the first source / drain region comprises a first material, and the plurality of nanostructures comprises the first material. 14 . The method for manufacturing a semiconductor device as claimed in claim 8 , further comprising forming an isolation region adjacent to the first source / drain region after etching the multi-layer structure.

15. A semiconductor device comprising: a first epitaxial source / drain region; a second epitaxial source / drain region; a stack of nanostructures, each nanostructure in the stack of nanostructures extending between the first epitaxial source / drain region and the second epitaxial source / drain region, wherein a first plane extends through the first epitaxial source / drain region, the second epitaxial source / drain region, and the stack of nanostructures, wherein the first epitaxial source / drain region has a uniform width in a second plane perpendicular to the first plane for the entire height of the first epitaxial source / drain region; a gate dielectric layer surrounding each nanostructure in the stack of nanostructures, wherein the gate dielectric layer is in direct physical contact with the first epitaxial source / drain region and the second epitaxial source / drain region; and A gate contact surrounds the gate dielectric layer. 16 . The semiconductor device of claim 15 , wherein the first epitaxial source / drain region and the second epitaxial source / drain region are silicon. 17 . The semiconductor device of claim 15 , wherein a distance between the first epitaxial source / drain region and the second epitaxial source / drain region is at least 30 nm. 18 . The semiconductor device of claim 15 , wherein the first epitaxial source / drain region has a straight sidewall from a top of the first epitaxial source / drain region to a bottom of the first epitaxial source / drain region.

19. The semiconductor device of claim 15, wherein the first epitaxial source / drain region is rectangular in shape in a top view. 20 . The semiconductor device of claim 15 , wherein the stack of nanostructures has a first width, and the first epitaxial source / drain region has the first width.

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