Semiconductor memory device and apparatus including the same

Abstract

Semiconductor memory devices and apparatuses including the same are provided. The semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines in a second direction that intersects the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application Nos. 10-2019-0135755 and 10-2020-0054106, filed with the Korean Intellectual Property Office on October 29, 2019 and May 6, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor memory devices including boron nitride layers and devices including the same. Background Technology

[0004] Due to their characteristics such as miniaturization, versatility, and / or low manufacturing cost, semiconductor memory devices have become a focal point of attention as a crucial element in the electronics industry. Semiconductor memory devices can be categorized into semiconductor memory devices that store logic data, semiconductor logic devices that operate and process logic data, and hybrid semiconductor memory devices that include both storage elements and logic elements.

[0005] Typically, semiconductor memory devices may include vertically stacked patterns and contact plugs for electrically connecting the vertically stacked patterns. As semiconductor memory devices become more highly integrated, the spacing between patterns and / or between patterns and contact plugs is gradually decreasing. Consequently, parasitic capacitances between patterns and / or between patterns and contact plugs can increase. Parasitic capacitances can lead to a decrease in the performance of semiconductor memory devices, such as a reduction in operating speed. Summary of the Invention

[0006] Provides a semiconductor memory device comprising a boron nitride layer having a low dielectric constant and / or an apparatus comprising thereto.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to an example embodiment, a semiconductor memory device includes: word lines extending in a first direction on a semiconductor substrate; bit line structures extending across the word lines, the bit line structures extending in a second direction intersecting the first direction; contact pad structures between the word lines and between the bit line structures; and spacers between the bit line structures and the contact pad structures. The spacers include a boron nitride layer.

[0009] In some embodiments, the spacer may extend along one sidewall of the bit line structure in the second direction.

[0010] In some embodiments, the spacer may surround at least a portion of the contact pad structure.

[0011] In some embodiments, the spacer may be in direct contact with at least a portion of the contact pad structure.

[0012] In some embodiments, the bit line structure may include a polysilicon pattern, a barrier / pad pattern, a metal pattern, and a hard mask pattern sequentially stacked on the semiconductor substrate. The spacers may overlap with the polysilicon pattern, the barrier / pad pattern, and the metal pattern with respect to the first direction.

[0013] In some embodiments, the spacer may be in direct contact with at least one of the polysilicon pattern, the barrier / pad pattern, and the metal pattern.

[0014] In some implementations, the spacer may overlap with at least a portion of the hard mask pattern in the first direction.

[0015] In some embodiments, the boron nitride layer may have a dielectric constant of 2.5 or less at an operating frequency of 100 kHz.

[0016] In some embodiments, the boron nitride layer may include at least one amorphous material and a nanocrystalline material.

[0017] In some embodiments, the boron nitride layer may be non-porous.

[0018] In some embodiments, the bit line structure may include polysilicon patterns, barrier / pad patterns, metal patterns, and hard mask patterns sequentially stacked on the semiconductor substrate, and the semiconductor memory device may further include a capping layer between the metal patterns and the hard mask patterns.

[0019] In some embodiments, the capping layer may include a boron nitride layer.

[0020] In some embodiments, the boron nitride layer included in the capping layer may have the same physical properties as the boron nitride layer included in the spacer.

[0021] In some embodiments, the end portion of the capping layer may contact the spacer.

[0022] In some embodiments, the semiconductor memory device may further include a gate hard mask pattern on the word line; an interlayer insulating layer on the gate hard mask pattern; and an insulating pattern on the interlayer insulating layer, wherein at least one of the interlayer insulating layer and the insulating pattern may include a boron nitride layer.

[0023] In some embodiments, the boron nitride layer included in at least one of the interlayer insulating layer and the insulating pattern may have the same physical properties as the boron nitride layer included in the spacer.

[0024] In some embodiments, the insulating pattern may include the boron nitride layer, and the insulating pattern and the spacer may be integrated with each other (as a single unit).

[0025] In some embodiments, the interlayer insulation layer may be in contact with the spacer.

[0026] According to an example embodiment, a semiconductor memory device includes: a semiconductor substrate including active portions spaced apart from each other, the active portions including a plurality of first impurity regions and a plurality of second impurity regions, such that each corresponding active portion includes a corresponding first impurity region spaced apart from a corresponding second impurity region; a word line extending in a first direction on the semiconductor substrate, the word line intersecting the plurality of first impurity regions and the plurality of second impurity regions above the active portions; a bit line structure extending across the word line, the bit line structure extending in a second direction intersecting the first direction, the lower portion of the bit line structure each including a bit line contact pattern contacting the first impurity region; and a spacer extending along at least a portion of the sidewall of the bit line structure, the spacer including a boron nitride layer.

[0027] In some embodiments, the boron nitride layer may include at least one amorphous material and a nanocrystalline material.

[0028] In some embodiments, the bit line structure may include polysilicon patterns, barrier / pad patterns, metal patterns, and hard mask patterns that may be sequentially stacked on the semiconductor substrate. The spacers may extend along the sidewalls of the polysilicon patterns, barrier / pad patterns, and metal patterns.

[0029] In some embodiments, the semiconductor memory device may further include an interlayer insulating layer on the semiconductor substrate. The bit line contact pattern may extend through the interlayer insulating layer. The interlayer insulating layer may include at least one of amorphous boron nitride or nanocrystalline boron nitride.

[0030] According to an example implementation, the device may include a memory and a controller. The memory may include any of the semiconductor memory devices described above. The controller may be configured to control the operation of the memory. For example, the memory may be configured to: store data in the memory or read data from the memory.

[0031] In some embodiments, the device may be at least one of a computer, a portable electronic device, a display, or a storage system. Attached Figure Description

[0032] The above and other aspects, features, and effects of some embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, wherein:

[0033] Figure 1 A diagram illustrating a system for manufacturing a boron nitride layer according to an embodiment;

[0034] Figures 2A to 2C Reference figures are provided to illustrate the method for manufacturing a boron nitride layer according to the embodiments;

[0035] Figures 3A to 3D A diagram showing the atomic structure of the boron nitride layer according to an embodiment;

[0036] Figure 4A The results are for the Raman spectra of the boron nitride layer according to the embodiment.

[0037] Figure 4B The Fourier transform infrared (FTIR) spectra of the boron nitride layer according to the embodiment are shown;

[0038] Figure 5 A diagram illustrating the X-ray photoelectron spectroscopy (XPS) profile of the amorphous boron nitride layer according to the embodiment;

[0039] Figure 6 The FTIR spectral results for the amorphous boron nitride layer according to the embodiment are shown;

[0040] Figure 7A The results show the high-resolution Rutherford backscattering energy dispersive spectroscopy (HR-RBS) distribution of the amorphous boron nitride layer according to the embodiment.

[0041] Figure 7B The results show the distribution of high-resolution elastic recoil detection analysis (HR-ERDA) of the amorphous boron nitride layer according to the embodiment.

[0042] Figure 7C Showing the composition ratio of the boron nitride layer calculated using HR-RBS and HR-ERDA spectra;

[0043] Figure 8A The Raman spectra of the boron nitride layer transferred to the substrate according to the embodiment are shown;

[0044] Figure 8B XPS image of the transferred boron nitride layer according to the embodiment;

[0045] Figure 9A The results of measuring the dielectric constant of the amorphous boron nitride layer according to the embodiment are displayed;

[0046] Figure 9B The results show the dielectric constant of the boron nitride layer obtained by using elliptic polarization spectroscopy (SE).

[0047] Figure 10A Simulation results regarding the mass density of the amorphous boron nitride layer according to the embodiment;

[0048] Figure 10B A graph showing the relationship between dielectric constant and mass density for various materials;

[0049] Figure 11 A graph showing the relationship between dielectric constant and breakdown field for various materials;

[0050] Figure 12 A table summarizing the properties of the amorphous boron nitride layer and the hexagonal boron nitride layer according to the embodiments;

[0051] Figure 13 The energy dispersive spectral distribution of the amorphous boron nitride layer after a thermal diffusion test according to the embodiment;

[0052] Figure 14(i) shows a cross-sectional transmission electron microscope (TEM) image after a thermal diffusion test of a TiN layer as a comparative example, and Figure 14(ii) shows the EDS spectral distribution after a thermal diffusion test of a TiN layer as a comparative example.

[0053] Figure 15 To show the results of the breakdown bias at the temperature of the amorphous boron nitride layer according to the embodiment;

[0054] Figure 16A This is a selected area electron diffraction image of a boron nitride layer grown at approximately 700°C according to an embodiment.

[0055] Figure 16B A high-magnification TEM image of a boron nitride layer grown at approximately 700°C according to an embodiment;

[0056] Figure 16C The results of the fast Fourier transform for the boron nitride layer grown at approximately 700°C according to the embodiment are shown.

[0057] Figure 17 The results are for the Raman spectra of the nanocrystalline boron nitride layer according to the embodiments;

[0058] Figure 18The FTIR spectra of the nanocrystalline boron nitride layer according to the embodiment are shown;

[0059] Figure 19 A graph illustrating the XPS distribution results of the nanocrystalline boron nitride layer according to the embodiment;

[0060] Figure 20 A figure illustrating an example of using a nanocrystalline boron nitride layer as a diffusion barrier layer according to an embodiment;

[0061] Figure 21 A graph showing the dielectric constant of the nanocrystalline boron nitride layer with respect to various frequencies according to the embodiment;

[0062] Figure 22A An atomic force microscope (AFM) image of a boron nitride layer grown at approximately 400°C;

[0063] Figure 22B AFM image of a boron nitride layer grown at approximately 700°C;

[0064] Figure 23 A plan view of a semiconductor memory device including a boron nitride layer according to an embodiment;

[0065] Figure 24A To illustrate along Figure 23 A diagram of the cross sections taken by lines A-A' and B-B';

[0066] Figure 24B This describes a boron nitride layer based on some example implementations;

[0067] Figures 25A to 25F A diagram illustrating a semiconductor memory device according to another embodiment;

[0068] Figure 26 A block diagram illustrating an electronic device including a semiconductor memory device according to an embodiment; and

[0069] Figure 27 A block diagram illustrating a storage system including a semiconductor storage device according to an embodiment. Detailed Implementation

[0070] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" modify the entire list of elements and not individual elements of the list when appearing before or after the list of elements.

[0071] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. Furthermore, for ease of explanation and clarity, the dimensions of the layers shown in the drawings may be enlarged. In this respect, the embodiments may take different forms and should not be construed as limited to the description set forth herein.

[0072] It will also be understood that when an element is referred to as being "on" or "above" another element, the element may be in direct contact with the other element or there may be other intermediate elements present. Singular expressions include plural expressions unless they have a distinctly different meaning in the context. It should be understood that when a component "contains" or "includes" an element in the specification, other elements are not excluded from the component unless otherwise defined, and the component may further include other elements. The use of the term "the" and similar indicative words in the context will be interpreted to cover both the singular and plural.

[0073] In the following embodiments, a boron nitride layer, a method for manufacturing the boron nitride layer using plasma, and an apparatus including the boron nitride layer will be described.

[0074] Figure 1 A diagram illustrating a system 10 for manufacturing a boron nitride layer according to an embodiment. (See reference...) Figure 1 The system 10 for fabricating a boron nitride layer may include: a chamber 11 containing a space in which a reaction gas for growing the boron nitride layer can move; a supply source 12 for supplying the reaction gas to the chamber 11; a flow rate controller 13 for controlling the mass flow rate of the reaction gas moving into the chamber 11; a plasma device 14 for generating plasma in the chamber 11; and a furnace 15 for regulating the temperature of the chamber 11, and for depositing the boron nitride layer in the chamber 11. Additionally, the device for regulating the temperature may be a hot-wall type in which radiant heat is transferred to the substrate, or a cold-wall type in which the substrate is directly heated.

[0075] Figures 2A to 2C The reference figure illustrates the method for manufacturing a boron nitride layer according to an embodiment.

[0076] First, a substrate S can be prepared in chamber 11 of system 10. The substrate S may include at least one of a group IV semiconductor material, a semiconductor compound, an insulating material, and a metal. As a specific example, the substrate S may include a group IV semiconductor material such as Si, Ge, or Sn. Alternatively, the substrate S may include at least one of Si, Ge, C, Zn, Cd, Al, Ga, In, B, N, P, S, Se, As, Sb, Te, Ta, Ru, Rh, Ir, Co, Ti, W, Pt, Au, Ni, and Fe. Furthermore, the substrate S, as a SiCOH-based composition, may further include, for example, N and F, and may also include pores to reduce permittivity (dielectric constant). Additionally, the substrate S may further include dopants. The materials of the substrate S mentioned above are merely examples.

[0077] Before placing the substrate S in chamber 11, the substrate S can be pretreated. For example, the substrate S can be immersed in an organic solvent such as acetone, ultrasonically treated, and then cleaned with isopropanol (IPA) and nitrogen. The surface of the cleaned substrate S can be plasma-treated with oxygen, hydrogen, NH3, etc., to remove residual carbon impurities on the surface. Alternatively, the substrate S can be immersed in an HF solution to remove natural oxides or anhydrous ethanol and N2 gas can be used to remove residual HF solution.

[0078] The process temperature for growing the boron nitride layer can be about 700°C or lower, which is lower than the temperature used for chemical vapor deposition processes. For example, the process temperature inside chamber 11 can be about 400°C. Before increasing the process temperature, the process pressure for growing the boron nitride layer can be set to about 2 Torr or lower. For example, the process pressure can be 10... -2 To or lower.

[0079] Next, a reaction gas for growing the boron nitride layer can be injected into chamber 11. Here, the reaction gas can be a source of boron nitride for growing the boron nitride layer, and can be a source including both nitrogen and boron, such as borazine (B3N3H6) or ammonia-borane (NH3-BH3). Alternatively, the reaction gas can include a nitrogen source including nitrogen and a boron source including boron. The nitrogen source can include at least one of ammonia (NH3) or nitrogen gas (N2), and the boron source can include at least one of BH3, BF3, BCl3, B2H6, (CH3)3B, and (CH3CH2)3B.

[0080] The reactant gas may further include an inert gas. The inert gas may include at least one of, for example, argon, neon, helium, krypton, and xenon. The reactant gas may further include hydrogen. Additionally, the mixing ratio of the reactant gas injected into chamber 11 may be varied depending on the growth conditions of the boron nitride layer.

[0081] The flow rate controller 13 controls the flow rate of the reactive gases flowing into the chamber 11. The flow rate of the boron nitride source can be lower than that of the other reactive gases. When the boron nitride layer is grown using plasma, the mixing ratio of the reactive gases injected into the chamber 11, i.e., the volume ratio of the boron nitride source to the inert gas, can be, for example, about 1:10 to 5000, and the volume ratio of the boron nitride source, the inert gas, and hydrogen can be, for example, about 1:10 to 5000:10 to 500.

[0082] Because the source of boron nitride is significantly smaller in proportion than the other reactant gases, the crystallinity of boron nitride can be weak. Therefore, the boron nitride layer according to the embodiment can be formed with an amorphous or nanoscale crystal structure.

[0083] When an excess of the boron nitride source is supplied, the boron nitride layer can grow irregularly, and precursors can be adsorbed, and therefore, the flow rate of the boron nitride source can be low.

[0084] For example, during the growth of the boron nitride layer, the flow rate controller 13 can control the flow rate of the boron nitride source to 0.05 sccm, the flow rate of the inert gas to 50 sccm, and the flow rate of the hydrogen gas to 20 sccm. The flow rate controller 13 controls the flow rates of the boron nitride source and the inert gas, but is not limited thereto. The flow rate controller 13 can also control only the flow rate of the boron nitride source.

[0085] Subsequently, when the boron nitride source is introduced into chamber 11, plasma device 14 can generate plasma inside chamber 11. Here, the power used for plasma generation can be from about 10W to about 4000W. For example, the power used for plasma generation is about 30W, but it is not limited to this.

[0086] Plasma device 14 can be a device for providing plasma, including, but not limited to, inductively coupled plasma, capacitively coupled plasma, microwave plasma, plasma enhancement methods, electron cyclotron resonance plasma, arc discharge plasma, spiral wave (spiral) plasma, etc. For example, an inductively coupled plasma device can provide a plasma in which energy is supplied by a current generated by electromagnetic induction (i.e., a magnetic field that changes over time). When power for generating plasma is applied from plasma device 14 to the interior of chamber 11, an electric field can be induced inside chamber 11. As described above, when an electric field is induced in a state in which reactive gases are injected, plasma for the growth of boron nitride (BN) layers can be formed.

[0087] refer to Figure 2BActivated nitrogen (N) and activated boron (B) can be generated by a plasma of a reactant gas consisting of a boron nitride source, an inert gas, and hydrogen, and can be adsorbed onto the surface of the substrate S. Furthermore, the plasma of the inert gas can continuously activate the substrate S, thus accelerating the adsorption of activated nitrogen (N) and activated boron (B) onto the surface of the substrate S. Activated nitrogen (N) and activated boron (B) can be adsorbed as amorphous substances. Even when activated nitrogen and boron combine with each other, due to their small amounts, they can also be adsorbed as nanoscale crystals.

[0088] refer to Figure 2C Since the adsorption of activated nitrogen (N) and activated boron (B) onto the surface of the substrate S is accelerated even at low temperatures, a boron nitride layer (BN) can be grown on the surface of the substrate S. According to this embodiment, since the boron nitride layer (BN) is grown directly on the surface of the substrate S at low temperatures, such as 700°C or lower, by means of a low ratio of activated nitrogen (N) and activated boron (B), the grown boron nitride layer (BN) can have weak crystallinity.

[0089] The boron nitride (BN) layer according to the embodiments can be grown amorphously or as nanoscale crystals. Although crystals are present in the boron nitride layer BN formed amorphously, crystals of 3 nm or smaller may be present, and the boron nitride layer BN formed as nanocrystals may include crystals having a size of about 100 nm or smaller. More specifically, the boron nitride layer BN may include crystals having a size of about 0.5 nm to about 100 nm.

[0090] The thickness of the boron nitride (BN) layer according to the embodiments can be about 100 nm or less. For example, the thickness of the boron nitride (BN) layer can be 50 nm or less. Furthermore, the boron nitride (BN) layer can be formed thin because it comprises amorphous or nanocrystalline materials. However, the boron nitride (BN) layer is not limited to this. Because the boron nitride (BN) layer comprises amorphous or nanocrystalline materials, it can also be formed thick. The thickness of the boron nitride (BN) layer can be selected according to the application.

[0091] After growth, the plasma can be shut off, and furnace 15 can be gradually cooled to room temperature. For example, furnace 15 can be cooled to room temperature by introducing 20 sccm of H2 gas into chamber 11.

[0092] The device can be manufactured by forming an additional layer on a boron nitride (BN) layer manufactured using the method described above. Alternatively, the manufactured boron nitride (BN) layer can be transferred to another layer. Hydrofluoric acid transfer technology can be applied during the transfer, but this disclosure is not limited thereto.

[0093] like Figures 2A to 2CThe boron nitride (BN) layer fabricated as shown may be amorphous. Although the boron nitride (BN) layer according to the embodiments comprises crystalline material, it may comprise nanoscale crystals. Due to the direct growth of low-density activated nitrogen and boron at low temperatures, crystallinity may be weak. The lower the growth temperature and process pressure, the higher the amorphous content.

[0094] In the boron nitride layer BN according to the embodiments, the ratio of nitrogen to boron can be substantially the same. The boron to nitrogen ratio can be from about 0.9 to about 1.1. Furthermore, the boron nitride layer BN may contain hydrogen, but the hydrogen content in the boron nitride layer BN can be small. For example, the hydrogen content can be about 10% by weight or less and greater than 0% by weight, based on the total weight of the boron nitride layer. Due to its low hydrogen content, the boron nitride layer BN can be chemically stable.

[0095] The boron nitride layer BN according to the embodiments may have a dielectric constant of 3 or less at an operating frequency of about 100 kHz (here, dielectric constant may refer to the relative dielectric constant with respect to vacuum or air). For example, the amorphous boron nitride layer a-BN may have a dielectric constant of 2.3 or less at an operating frequency of about 100 kHz, and the nanocrystalline boron nitride layer nc-BN may have a dielectric constant of 2.3 to 2.5 at an operating frequency of about 100 kHz.

[0096] Furthermore, the mass density of the boron nitride layer BN according to the embodiment can be varied according to the dielectric constant of the boron nitride layer BN. For example, the boron nitride layer BN according to the embodiment can have a mass density of 1 to 3 g / cm³. 3 . mass density.

[0097] Furthermore, the breakdown field of the boron nitride layer BN according to the embodiment can be 4 MVcm. -1 Or even greater. In particular, the breakdown field of the boron nitride layer (BN) according to the embodiment can be about 5 to about 10 MVcm. -1 .

[0098] The boron nitride layer BN according to the embodiment may have a smooth surface. For example, the surface of the boron nitride layer BN may have a root mean square (RMS) roughness of about 0.3 to about 0.6 nm. The surface roughness of the boron nitride layer BN may be determined by the flow rate of the boron nitride source.

[0099] To obtain the properties of the boron nitride (BN) layer, inductively coupled plasma-chemical vapor deposition (ICP-CVD) was used at approximately 10... -4 The boron nitride (BN) layer is grown on a Si substrate under process pressure and at a process temperature of approximately 400°C.

[0100] Figures 3A to 3DA diagram showing the atomic structure of a boron nitride layer grown at a process temperature of approximately 400°C according to an embodiment. Figure 3A This is a low-magnification transmission electron microscopy (TEM) image of the boron nitride layer, and Figure 3B The image is a selected area electron diffraction pattern of the boron nitride layer. Figure 3B The image shows a diffraction pattern without discernible crystal rings. Figure 3C This is a high-magnification TEM image of the boron nitride layer, showing that the atoms in the boron nitride layer are arranged randomly. Additionally, Figure 3D A graph showing the Fast Fourier Transform (FFT) results for the boron nitride layer is displayed, illustrating a typical diffusion diffraction pattern of an amorphous film. Therefore, it can be confirmed that the boron nitride layer manufactured by the manufacturing method according to the embodiment is amorphous.

[0101] Figure 4A The values ​​shown are Raman spectra of the boron nitride layer according to the embodiments. SiO2 / Si represents the Raman spectra measured for the substrate itself, for example, a substrate comprising SiO2 / Si. In Example 1, the Raman spectra were measured after forming the boron nitride layer a-BN according to the embodiments on a substrate comprising SiO2 / Si. Tri-hBN represents the Raman spectra measured after epitaxially growing three hexagonal boron nitride layers on a substrate comprising SiO2 / Si.

[0102] like Figure 4A As shown, the Raman spectrum of the substrate and the Raman spectrum of the boron nitride layer according to the embodiment are similar to each other. When comparing the amorphous boron nitride layer a-BN and the three-layer hexagonal boron nitride layer Tri-hBN according to the embodiment, it can be confirmed that at 1373 cm⁻¹... -1 The peak present in the three hexagonal boron nitride layers Tri-hBN is not present in the amorphous boron nitride layer a-BN. This may mean that the boron nitride layer a-BN according to the embodiment does not have the crystallinity included in the hexagonal boron nitride layer Tri-hBN.

[0103] Figure 4B The Fourier transform infrared (FTIR) spectra of the boron nitride layer according to the embodiment are shown. The FTIR spectrum of the boron nitride layer was measured using s-polarized radiation at an incident angle of 60°. Figure 4B As shown, this can be confirmed in the boron nitride layer according to the embodiment, at 1370 cm⁻¹ -1 There is an absorption peak nearby, which is attributed to the transverse optical mode, while at 1570 cm⁻¹... -1 Another absorption peak exists nearby. At 1570 cm⁻¹ -1 The presence of nearby peaks indicates that the boron nitride layer according to the embodiment has amorphous properties.

[0104] Based on the experimental results, it can be confirmed that the boron nitride layer formed at a process temperature of approximately 400°C is amorphous. Hereinafter, the boron nitride layer formed at a process temperature of approximately 400°C using the manufacturing method according to the embodiment is referred to as the amorphous boron nitride layer a-BN.

[0105] Figure 5 A graph illustrating the X-ray photoelectron spectroscopy (XPS) distribution results of the amorphous boron nitride layer a-BN according to the embodiment. Figure 5 As shown, it can be confirmed that the 1s peaks for boron and nitrogen are 190.4 eV and 397.9 eV, respectively. Figure 5 XPS distribution confirms that the atomic ratio of boron to nitrogen is approximately 1:1.08, based on the peak sizes of boron and nitrogen respectively, and including sp. 2 Combine.

[0106] Figure 6 The FTIR spectra of the amorphous boron nitride layer a-BN according to the embodiment are shown. Figure 6 As shown, no peaks were observed in the FTIR spectrum at the frequencies corresponding to BH and NH.

[0107] Figure 7A The results show the high-resolution Rutherford backscattering energy dispersive spectroscopy (HR-RBS) distribution of the amorphous boron nitride layer a-BN according to the embodiment, and Figure 7B This displays the distribution results of high-resolution elastic recoil detection analysis (HR-ERDA) for the amorphous boron nitride layer a-BN according to the embodiment. Figure 7A The results are shown in the energy range of 240-400 keV, and Figure 7B The results, measured in the energy range of 52-68 keV, show that Si and O atoms, which form the substrate, were measured, and B and N atoms, which form the boron nitride layer, were measured. Additionally, hydrogen was also measured.

[0108] Figure 7C The compositional ratios of the boron nitride layers are shown, calculated using HR-RBS and HR-ERDA spectra. For example... Figure 7C As shown, the ratio of boron to nitrogen is approximately 1.04:1. Additionally, it is confirmed that the hydrogen content in the boron nitride layer is approximately 5.5%.

[0109] The above confirms the properties of the boron nitride layer grown on the substrate. The boron nitride layer according to the embodiment can be grown on a substrate including a catalyst material and then transferred to another substrate.

[0110] Figure 8A and 8BA diagram illustrating the properties of the transferred boron nitride layer according to an embodiment. Figure 8A The Raman spectral results of a boron nitride layer transferred to a SiO2 substrate according to an embodiment are shown. A boron nitride layer was grown on a copper foil at a plasma power of approximately 30 W and a growth temperature of approximately 300 °C. The grown boron nitride layer was then transferred to a SiO2 substrate, and Raman spectra were obtained. It can be confirmed that SiO2 substrates without a boron nitride layer are... 2基 The Raman spectra of the substrate and the transferred boron nitride layer are similar. This confirms that, like the SiO2 substrate, the transferred boron nitride layer is also amorphous.

[0111] Figure 8B XPS image of the transferred boron nitride layer according to an embodiment. Figure 8B As shown, it can be confirmed that, in the same manner as boron nitride layers grown at a process temperature of approximately 400°C, the 1s peaks for boron and nitrogen are 190.4 eV and 397.9 eV, respectively. Figure 8B XPS distribution confirms that the atomic ratio of boron to nitrogen is approximately 1:1.08, based on the peak sizes of boron and nitrogen, and including sp. 2 Therefore, it can be confirmed that even when the growth substrate is a catalyst substrate, an amorphous boron nitride layer a-BN can be obtained by growing a boron nitride layer at low temperature.

[0112] The dielectric properties of the amorphous boron nitride layer a-BN are described below. The dielectric constant is a physical measure of how easily an electric dipole can be induced in a material by applying an electric field. The dielectric constant of air or vacuum is 1, but the polarization in solid materials is caused by the dipole, atomic, and electronic components (compositions, assemblies) most relevant to high-performance electronic devices. The contributions from these can be measured as a function of frequencies ranging from about 10 kHz to about 30 MHz. The dielectric constant can be measured using capacitance-frequency measurements for metal-insulator-metal (MIM) structures. For comparison, the relative dielectric constants of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer h-BN are measured at different frequencies.

[0113] Figure 9A The results show the dielectric constant of the amorphous boron nitride layer a-BN grown at a growth temperature of approximately 300°C according to the embodiment. Figure 9A The dielectric constant shown is the average of more than 50 measurements. Figure 9AAs shown, the dielectric constants of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer h-BN are inversely proportional to the operating frequency. It has been confirmed that at an operating frequency of approximately 10 kHz, the dielectric constants of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer h-BN are approximately 2 and 3.5, respectively. It has been confirmed that at an operating frequency of approximately 100 kHz, the dielectric constants of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer h-BN are approximately 1.78 and 3.28, respectively. It has been confirmed that the dielectric constant of the amorphous boron nitride layer a-BN decreases to approximately 1.16 at a frequency of 1 MHz, which is close to the dielectric constant of air or vacuum. This is because the low dielectric constant of the amorphous boron nitride layer a-BN is attributed to the lack of order in the nonpolar bonds between BN layers (which restricts and / or prevents dipole alignment even at high frequencies).

[0114] The refractive index *n* of the boron nitride layer can be measured using elliptic polarization spectroscopy (SE), and its dielectric constant *k* can be determined using the relationship between refractive index *n* and dielectric constant *k*. 2 =k is obtained.

[0115] Figure 9B The results show the dielectric constants of the boron nitride layers measured using the SE method. The refractive indices of the hexagonal boron nitride layer h-BN and the amorphous boron nitride layer a-BN at a wavelength of 633 nm, measured using the SE method, are 2.16 and 1.37, respectively. Therefore, it can be confirmed that the dielectric constants of the hexagonal boron nitride layer h-BN and the amorphous boron nitride layer a-BN are 4.67 and 1.88, respectively, and are approximately the same as the values ​​obtained by electrical measurements at 100 kHz.

[0116] Figure 10A To simulate the mass density of the amorphous boron nitride layer a-BN according to an embodiment, an amorphous boron nitride layer a-BN with a thickness of 40 nm was grown on a Si substrate, and then the mass density was simulated along the z-direction, which is the thickness direction of the amorphous boron nitride layer a-BN on the Si substrate. Figure 10A As shown, the mass density of the amorphous boron nitride layer a-BN is approximately 2 g / cm³. 3 It can be seen that the amorphous boron nitride layer a-BN has a low dielectric constant and a high density, which prevents the mechanical strength from deteriorating.

[0117] Figure 10B A graph showing the relationship between the dielectric constant and mass density of various materials. (e.g.) Figure 10BAs shown, the dielectric constant and mass density of a material are typically proportional. Therefore, a material with a low dielectric constant may have a low mass density and low mechanical strength. However, the amorphous boron nitride layer a-BN, having a dielectric constant of approximately 2, has a mass density of approximately 2, which is relatively higher than other materials. Therefore, the amorphous boron nitride layer a-BN can possess high mechanical strength.

[0118] Meanwhile, as another method to achieve low-dielectric materials, the material is made porous to take advantage of the low dielectric constant of air. However, this reduces the density of the material, which in turn leads to poor mechanical strength. However, the amorphous boron nitride layer a-BN has good mechanical strength because it is not porous, as described above. Figures 3A to 3D As shown in the diagram, at least one pore can be formed in the amorphous boron nitride layer a-BN. Multiple pores can be formed in the amorphous boron nitride layer a-BN, and thus the dielectric constant can be further reduced. In some cases, other materials can be filled into the pores of the amorphous boron nitride layer a-BN. Even if the pores of the amorphous boron nitride layer a-BN are filled with other materials, the utilization of the amorphous boron nitride layer a-BN can be increased without significantly increasing the dielectric constant.

[0119] Figure 11 This is a graph showing the relationship between the dielectric constant and breakdown field of various materials. (Example) Figure 11 As shown, it can be confirmed that the dielectric constant and the breakdown field are proportional (directly proportional). Figure 11 As shown, it can be confirmed that the breakdown field of the amorphous boron nitride layer a-BN is higher than that of other materials with a dielectric constant close to 2.

[0120] Figure 12 A table summarizing the properties of the amorphous boron nitride layer a-BN and the hexagonal boron nitride layer according to the embodiments is provided. Figure 12 As shown, it can be confirmed that the amorphous boron nitride layer a-BN has a dielectric constant of 2 or less at operating frequencies of 100 kHz or higher. Furthermore, the breakdown field of the amorphous boron nitride layer a-BN is 7.3 MV-cm. -1 It has a much larger breakdown field than the hexagonal boron nitride layer, and its refractive index for electromagnetic waves at 633 nm is 2 or less.

[0121] Due to its electrical and dielectric properties as described above, the amorphous boron nitride layer a-BN can be used as an interlayer insulating layer. In particular, when the amorphous boron nitride layer a-BN is used as an interlayer insulating layer between conductive materials, parasitic capacitance can be reduced.

[0122] In addition, since the amorphous boron nitride layer a-BN is chemically stable, it can be used as a diffusion barrier.

[0123] For example, a key step in back-end-of-line (BEOL) CMOS fabrication of logic and memory devices is depositing a diffusion barrier between a low-dielectric material and metal interconnects to limit and / or prevent the migration of metal atoms into the insulator. Ideally, if the low-dielectric material can also serve as a diffusion barrier, it is not necessary to deposit a separate diffusion barrier. Due to its low dielectric constant and large breakdown field, amorphous boron nitride (a-BN) layers according to embodiments can be used as diffusion barriers.

[0124] Figure 13 Energy dispersive spectroscopy (EDS) line distribution was obtained after a thermal diffusion test on the amorphous boron nitride layer a-BN according to the embodiment. An amorphous boron nitride layer a-BN with a thickness of 3 nm was formed on a Si substrate, and an 80 nm cobalt layer was deposited on the amorphous boron nitride layer a-BN according to the embodiment. The diffusion-blocking properties of the amorphous boron nitride layer a-BN were tested by annealing the Co / a-BN / Si device in vacuum at 600°C for 1 hour.

[0125] like Figure 13 As shown, it can be confirmed that the cobalt and silicon components are separated according to the thickness. This means that the cobalt component does not diffuse into the silicon region. It can be seen that the amorphous boron nitride layer a-BN acts as a diffusion barrier.

[0126] Figure 14(i) shows a cross-sectional TEM image after a thermal diffusion test of the TiN layer as a comparative example, and Figure 14(ii) shows the EDS spectral distribution after a thermal diffusion test of the TiN layer as a comparative example. A 3 nm thick TiN layer was formed on a silicon substrate, and an 80 nm thick cobalt layer was deposited on the TiN layer. The Co / TiN / Si device was then annealed in vacuum at 600 °C for about 1 hour. As shown in Figures 14(i) and 14(ii), it can be confirmed that the cobalt separated from the cobalt layer and diffused into the silicon substrate.

[0127] Depend on Figure 13 , 14(i) As can be seen from the results of 14(ii), the amorphous boron nitride layer a-BN has a greater effect in restricting and / or preventing the diffusion of metals than TiN layers, which are usually used as diffusion barriers.

[0128] Figure 15The results are shown to illustrate the breakdown bias at temperature according to the embodiment of the amorphous boron nitride layer a-BN. It can be seen that the breakdown bias of the amorphous boron nitride layer a-BN is inversely proportional to temperature. Although the breakdown voltage decreases with increasing temperature, it can be observed that the breakdown bias of the amorphous boron nitride layer a-BN is greater than that of the TiN layer. This means that the amorphous boron nitride layer a-BN is stable at various temperatures, and as a result, the amorphous boron nitride layer a-BN can be an excellent low-k material for high-performance CMOS electronic devices.

[0129] The boron nitride layer formed at 400°C or lower using inductively coupled plasma-chemical vapor deposition (ICP-CVD) is amorphous and functions as a diffusion barrier. Furthermore, the amorphous boron nitride layer a-BN has a low dielectric constant and a large breakdown field compared to materials with similar dielectric constants. The amorphous boron nitride layer a-BN is fabricated at 400°C or lower, and the process temperature can be adjusted depending on the substrate, pressure, etc. For example, when the substrate is used as a catalyst for forming the boron nitride layer, the boron nitride layer can be formed at a temperature below 400°C, such as 300°C.

[0130] The following describes boron nitride layers formed at temperatures above 400°C. For example, these layers are formed using an ICP-CVD method at approximately 10 °C. -4 Boron nitride layers are grown on silicon substrates under process pressure and at a process temperature of approximately 700°C.

[0131] Figures 16A to 16C A diagram showing the atomic structure of a boron nitride layer grown at approximately 700°C according to an embodiment. Figure 16A This is a selected area electron diffraction image of a boron nitride layer grown at approximately 700°C. Figure 16A The image shows a polycrystalline ring pattern. Figure 16B This is a high-magnification TEM image of a boron nitride layer grown at approximately 700°C, which confirms the arrangement of small, nanoscale crystallites. Additionally, Figure 16C A graph showing the Fast Fourier Transform (FFT) results for a boron nitride layer grown at approximately 700°C is provided, confirming that the boron nitride layer possesses a hexagonal superstructure. Therefore, it can be confirmed that boron nitride layers grown at temperatures above approximately 400°C, such as 700°C, comprise nanoscale microcrystals.

[0132] The nanocrystalline boron nitride layer nc-BN exhibits good mechanical strength because it is not porous, as described above. Figures 16A to 16CAs shown in the diagram. According to the apparatus for applying the nanocrystalline boron nitride layer nc-BN thereto, one or more pores can be formed in the nanocrystalline boron nitride layer nc-BN. Pores can be formed in the nanocrystalline boron nitride layer nc-BN, and therefore the dielectric constant can be further reduced. According to an embodiment, other materials can be filled into the pores of the nanocrystalline boron nitride layer nc-BN. Even if the pores of the nanocrystalline boron nitride layer nc-BN are filled with other materials, the utilization of the nanocrystalline boron nitride layer nc-BN can be increased without significantly increasing the dielectric constant.

[0133] Figure 17 The Raman spectra of the nanocrystalline boron nitride layer nc-BN according to the embodiment are shown. Figure 17 As shown, it can be confirmed that in a substrate comprising SiO2 / Si and the amorphous boron nitride layer a-BN, at approximately 1370 cm⁻¹... -1 There is no peak at the wavelength, while in Example 2, which is a boron nitride layer formed at 700°C, and the hexagonal boron nitride layer Tri-hBN, there is a peak at approximately 1370 cm⁻¹. -1 A peak is observed at the specified wavelength. This indicates that the boron nitride layer formed at 700℃ is crystalline. In the following text, the boron nitride layer with nanoscale crystals is referred to as nanocrystalline boron nitride layer nc-BN.

[0134] Figure 18 The FTIR spectra of the nanocrystalline boron nitride layer nc-BN according to the embodiment are shown. The FTIR spectra of the boron nitride layer were measured using s-polarized radiation at an incident angle of 60°. Figure 18 As shown, this can be confirmed in the nanocrystalline boron nitride layer nc-BN at 1370 cm⁻¹. -1 There is an absorption peak nearby, which is attributed to the transverse optical mode, while at 1570 cm⁻¹... -1 There are no absorption peaks nearby. This means that the nanocrystalline boron nitride layer nc-BN according to the embodiment does not have amorphous properties.

[0135] Figure 19 A graph illustrating the XPS distribution results of the nanocrystalline boron nitride layer nc-BN according to the embodiment. (See figure) Figure 19 As shown, it can be confirmed that the 1s peaks for boron and nitrogen are 190.3 eV and 397.9 eV, respectively. It can also be confirmed that the 1s peaks for boron and nitrogen in the nanocrystalline boron nitride layer nc-BN and the amorphous boron nitride layer a-BN are almost identical. Figure 19 The XPS distribution confirms that the atomic ratio of boron to nitrogen is approximately 1:1.08.

[0136] Figure 20This diagram illustrates an example of the nanocrystalline boron nitride layer nc-BN used as a diffusion barrier layer according to an embodiment. A boron nitride layer is grown on a silicon substrate at 700°C, and a cobalt layer with a thickness of 50 nm is deposited on the boron nitride layer. The boron nitride layer grown at 700°C can be a nanocrystalline boron nitride layer nc-BN. The above structure is then vacuum annealed at 600°C for 1 hour. Figure 20 As shown, very low-density needle-like cobalt silicide was observed on the silicon substrate. This confirms that the nanocrystalline boron nitride layer nc-BN functions as a diffusion barrier even under annealing conditions.

[0137] Figure 21 A graph showing the dielectric constant of the nanocrystalline boron nitride layer nc-BN according to an embodiment at various frequencies. Figure 21 As shown, it can be confirmed that the nanocrystalline boron nitride layer nc-BN has a dielectric constant of 2.5 or less in the operating frequency range of about 50 kHz to about 1 MHz. For example, it can be confirmed that the nanocrystalline boron nitride layer nc-BN has a dielectric constant of about 2.3 to about 2.5. It can be confirmed that crystalline hexagonal boron nitride typically has a dielectric constant of about 2.9 to about 3.8 in the operating frequency range of about 50 MHz to about 100 kHz, while the nanocrystalline boron nitride layer nc-BN has a low dielectric constant of 2.5 or less. As mentioned above, due to its low dielectric constant, the nanocrystalline boron nitride layer nc-BN can be used as an interlayer insulating layer. In particular, when the nanocrystalline boron nitride layer nc-BN is used as an interlayer insulating layer between conductive materials, parasitic capacitance can be reduced.

[0138] Even if the amorphous boron nitride layer a-BN itself is not porous, pores can be formed within the amorphous boron nitride layer a-BN, depending on the device in which the amorphous boron nitride layer a-BN is applied. Pores can be formed within the amorphous boron nitride layer a-BN, and therefore the dielectric constant can be further reduced.

[0139] The amorphous boron nitride layer a-BN can have a band gap of about 6.00 eV or less. Typically, it has been confirmed that a trigonal hexagonal boron nitride layer has a band gap of about 6.05 eV, while a boron nitride layer grown at 400 °C has a band gap of about 5.96 eV, and a boron nitride layer grown at 700 °C has a band gap of about 5.85 eV. That is, the amorphous boron nitride layer a-BN and / or the nanocrystalline boron nitride layer nc-BN have lower band gaps than the hexagonal boron nitride layer. Therefore, the amorphous boron nitride layer a-BN and / or the nanocrystalline boron nitride layer nc-BN are chemically stable.

[0140] Figure 22A This is an atomic force microscopy (AFM) image of a boron nitride (BN) layer grown at approximately 400 °C. Figure 22B AFM image of a boron nitride layer grown at approximately 700°C. Figure 22A As shown, the surface roughness of the boron nitride (BN) layer grown at approximately 400°C is confirmed to be approximately 0.45 nm, and as... Figure 22B As shown, the surface roughness of the boron nitride layer grown at approximately 700°C is approximately 0.39 nm. Because the surface of the boron nitride layer is smooth, it is easy to form additional layers on the boron nitride (BN) layer, thereby facilitating the manufacture of the device.

[0141] Figure 23 This is a plan view of a semiconductor memory device including a boron nitride layer according to an embodiment. Figure 24A To illustrate along Figure 23 A diagram of the cross sections taken by lines A-A' and B-B'. Figure 24B This describes a boron nitride layer based on some example implementations.

[0142] The device isolation layer 101 that defines the active portion ACT can be disposed in the semiconductor substrate 100. The semiconductor substrate 100 can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate.

[0143] According to an example, the active portion ACT has a rectangular shape (or a strip shape) and can be arranged two-dimensionally along a first direction D1 and a second direction D2 that intersects (e.g., is perpendicular to) the first direction D1. The active portion ACT can be arranged in a zigzag (sawtooth) shape in plan view and can have a major axis in a diagonal direction relative to the first direction D1 and the second direction D2. The active portions ACT can be spaced apart from each other.

[0144] The word line WL can be disposed in the semiconductor substrate 100 and can extend in the first direction D1 as seen in the plan view to intersect with the active portion ACT and the device isolation layer 101.

[0145] The gate insulating layer 103 may be located between the word line WL and the semiconductor substrate 100, and the upper surface of the word line WL may be disposed below the upper surface of the semiconductor substrate 100, and the gate hard mask pattern 105 may be disposed on the word line WL.

[0146] First and second impurity regions 1a and 1b may be formed in active portions ACT on both sides of word lines WL, respectively. The lower surfaces of the first and second impurity regions 1a and 1b may be located at a desired and / or alternatively predetermined depth from the upper surface of the active portions ACT. The first impurity region 1a may be disposed in each active portion ACT between word lines WL, and the second impurity region 1b may be spaced apart from the first impurity region 1a and disposed in the end portion of each active portion ACT. The first and second impurity regions 1a and 1b may be doped with a dopant having a conductivity type opposite to that of the semiconductor substrate 100.

[0147] According to an embodiment, the bit line structure BL may extend across the word line WL in a second direction D2 on the semiconductor substrate 100. The bit line structure BL may be provided on the first impurity region 1a. According to an exemplary embodiment, the bit line structure BL may include a polysilicon pattern 121, a barrier / pad pattern 122, a metal pattern 123, and a hard mask pattern 125 stacked sequentially. An interlayer insulating layer 110 may be disposed between the polysilicon pattern 121 and the semiconductor substrate 100. The interlayer insulating layer 110 may include an insulating material used in conventional semiconductor manufacturing processes. For example, the interlayer insulating layer 110 may include silicon oxide, nitride, silicon nitride, silicon carbide, silicate, etc. However, this is only an example, and many other insulating materials may be used as the interlayer insulating layer 110.

[0148] Furthermore, a portion of the polysilicon pattern 121 (hereinafter, bit line contact pattern DC) may contact the first impurity region 1a. The lower surface of the bit line contact pattern DC may be located below the upper surface of the semiconductor substrate 100 and above the upper surface of the word line WL. In an example, the bit line contact pattern DC may be partially disposed in a recessed region formed in the semiconductor substrate 100 that exposes the first impurity region 1a.

[0149] According to an embodiment, insulating patterns 143 may be spaced apart from each other between bit line structures BL in a second direction D2 and disposed on the interlayer insulating layer 110. The insulating patterns 143 may overlap with word lines WL in a plan view and may have an upper surface at the same level as the upper surface of the bit line structure BL.

[0150] According to an embodiment, contact pad structures CPS, respectively connected to the second impurity region 1b, can be disposed between bit line structures BL. From a plan view, each contact pad structure CPS can be disposed between word lines WL and between bit line structures BL. Each contact pad structure CPS can fill the space defined by the adjacent bit line structure BL in the first direction D1 and the adjacent insulating pattern 143 in the second direction D2.

[0151] The upper surface of the contact pad structure CPS can be located on the upper surface of the bit line structure BL, and from a plan view, a portion of the contact pad structure CPS can overlap with a portion of the bit line structure BL. In an embodiment, the upper width of the contact pad structure CPS can be greater than the distance between the bit line structures BL or the width of the bit line structure BL.

[0152] In an embodiment, each of the contact pad structures CPS may include a contact conductive pattern 153 and a landing pad 155 that contacts the second impurity region 1b.

[0153] The conductive contact pattern 153 may include, for example, a polysilicon layer doped with impurities, and may directly contact the second impurity region 1b via the interlayer insulating layer 110. In an example, the conductive contact pattern 153 may be located below the upper surface of the semiconductor substrate 100 and above the lower surface of the bit line contact pattern DC. Furthermore, the conductive contact pattern 153 may be insulated from the bit line contact pattern DC via the bit line contact spacer DCP. The upper surface of the conductive contact pattern 153 may be located below the upper surface of the metal pattern 123 of the bit line structure BL.

[0154] Although not shown in the figures, a contact silicide pattern (not shown) may cover the upper surface of the contact conductive pattern 153. The contact silicide pattern may include, for example, titanium silicide, cobalt silicide, nickel silicide, tungsten silicide, platinum silicide, or molybdenum silicide. In other embodiments, the contact silicide pattern may be omitted.

[0155] The upper surface of the landing pad 155 may be located above the upper surface of the bit line structure BL, and the lower surface of the landing pad 155 may be located below the bit line structure BL. For example, the lower surface of the landing pad 155 may be located below the upper surface of the metal pattern 123 of the bit line structure BL.

[0156] The landing pad 155 can be electrically connected to each of the second impurity regions 1b via contact conductive patterns 153. The landing pad 155 may include sequentially stacked metal barrier layer patterns and pad metal patterns.

[0157] According to one embodiment, the landing pad 155 may include a lower portion filled between the bit line structure BL and the insulating pattern 143, and an upper portion extending from the lower portion onto a portion of the bit line structure BL. That is, in plan view, the upper portion of the landing pad 155 may overlap with a portion of the bit line structure BL. In other words, the upper width of the landing pad 155 may be greater than the distance between the bit line structures BL or the width of the bit line structure BL. As described above, since the upper portion of the landing pad 155 extends onto the bit line structure BL, the area of ​​the upper surface of the landing pad 155 can be increased.

[0158] According to an embodiment, the upper portion of the landing pad 155, viewed in plan view, may have an elliptical shape having a major axis and a minor axis, and may have a longitudinal axis in an inclined direction relative to the first direction D1 and the second direction D2. According to an embodiment, the upper portion of the landing pad 155 may have a circular rhombus, a circular trapezoid, or a circular square shape.

[0159] According to an embodiment, spacer 131 may be located between bit line structure BL and contact pad structure CPS. Spacer 131 may extend along one sidewall of bit line structure BL in a second direction D2. Additionally, from a plan view, spacer 131 may surround portions of the contact pad structures CPS between bit line structures BL. Spacer 131 may have a ring shape. Spacer 131 may extend on interlayer insulating layer 110 along both sidewalls of bit line structure BL in the second direction D2, and may extend between bit line structure BL and contact pad structure CPS in the second direction D2 between bit line structure BL and insulating pattern 143.

[0160] Spacer 131 may include a boron nitride layer according to an embodiment. For example, spacer 131 may include at least one amorphous boron nitride layer and a nanocrystalline boron nitride layer. When the boron nitride layer according to an embodiment has a dielectric constant of about 2.5 or less, the boron nitride layer as spacer 131 can not only support the bit line structure BL, but also reduce the parasitic capacitance affecting the bit line structure BL. Spacer 131 may further include a dielectric material with a low dielectric constant other than the boron nitride layer according to an embodiment.

[0161] In some embodiments, spacer 131 may further include a boron nitride layer, such as Figure 24B The layers depicted may be a single layer BNL1 of amorphous boron nitride (a-BN) or nanocrystalline boron nitride (nc-BN), or a double layer BNL2 or multiple layers (e.g., a triple layer BNL3) of amorphous boron nitride (a-BN) or nanocrystalline boron nitride (nc-BN), but the exemplary embodiments are not limited thereto. In multilayer boron nitride layers, such as double layer BNL2 and triple layer BNL3, the layers may be of the same material, or some layers may be of a different material than the others. For example, double layer BNL2 or triple layer BNL3 may all be amorphous boron nitride (a-BN) layers, all be nanocrystalline boron nitride (nc-BN) layers, or any combination of amorphous boron nitride (a-BN) layers and nanocrystalline boron nitride (nc-BN) layers.

[0162] In related technologies, silicon nitride is formed on spacer 131 to reduce parasitic capacitance affecting the bit line structure BL. Silicon nitride can form a depletion region at the junction interface with the polysilicon pattern 121 to increase the resistance of the bit line structure BL. Since the boron nitride layer according to the embodiment has a low dielectric constant, its physical rigidity can be increased and its parasitic capacitance can be reduced when used as a material for spacer 131. Therefore, the response time of the semiconductor memory device can be shortened.

[0163] The spacer 131 may contact the sidewall of the bit line structure BL. In an example, the first spacer 131 may extend to the sidewall of the bit line contact pattern DC and may be disposed on the interlayer insulating layer 110.

[0164] Furthermore, the spacer 131 may surround the lower portion of the landing pad 155. That is, the spacer 131 may have a ring shape when viewed in plan view and may be located below the upper portion of the landing pad 155. In other words, when viewed in plan view, the spacer 131 may overlap with the lower portion of the landing pad 155.

[0165] According to one embodiment, the pad insulation pattern LPI can be filled between the upper portions of the landing pad LP. The pad insulation pattern LPI can have a rounded lower surface. The upper surface of the pad insulation pattern LPI can be coplanar with the upper surface of the landing pad LP.

[0166] The pad insulation pattern LPI may include a first capping insulation layer 161 and a second capping insulation layer 163 stacked sequentially. The first capping insulation layer 161 may have a substantially uniform thickness, and the second capping insulation layer 163 may fill the spaces between the landing pads LP. The first capping insulation layer 161 may directly contact the hard mask pattern 125 of the landing pads LP and the bit line structure BL. Additionally, the first capping insulation layer 161 may cover the upper surface of the insulation pattern 143 and may directly contact a portion of the spacer 131. The first and second capping insulation layers 161 and 163 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0167] According to the embodiment, the data storage pattern DSP can be respectively disposed on the contact pad structure CPS. The data storage pattern DSP can be electrically connected to the second impurity region 1b through the contact pad structure CPS. The data storage pattern DSP can be respectively disposed offset from the landing pad LP of the contact pad structure CPS, and can respectively contact a portion of the landing pad LP. In an example, from a plan view, the data storage pattern DSP can be arranged in a honeycomb or zigzag shape.

[0168] According to examples, the data storage pattern DSP can be a capacitor and may include lower and upper electrodes and a dielectric layer between the lower and upper electrodes. Alternatively, the data storage pattern DSP can be a variable resistance pattern that can be switched to two resistance states by an electrical pulse applied to the storage element. For example, the data storage pattern DSP may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material whose crystal state changes according to the amount of current.

[0169] Figures 25A to 25F A diagram illustrating a semiconductor memory device according to another embodiment. When compared... Figure 24A and 25A hour, Figure 25A Spacers 131a of the semiconductor memory device may be disposed on a portion of the sidewall of the bit line structure BL. For example, spacers 131a may overlap with the polysilicon pattern 121, the barrier / pad pattern 122, and the metal pattern 123 in a first direction, but may not overlap with the hard mask pattern 125. Since the hard mask pattern 125 itself has insulating properties, spacers 131 may not be disposed on the hard mask pattern 125.

[0170] like Figure 25B As shown, the interlayer insulating layer 110a of the semiconductor memory device may include a boron nitride layer according to an embodiment. For example, the interlayer insulating layer 110a may include at least one amorphous boron nitride layer and a nanocrystalline boron nitride layer. The boron nitride layer according to the embodiment is chemically stable, thereby limiting and / or preventing the diffusion of material between the polycrystalline silicon pattern 121 and the semiconductor substrate 100. The boron nitride layer according to the embodiment has been described above, and therefore its detailed description will be omitted.

[0171] When the interlayer insulating layer 110a includes a boron nitride layer according to an embodiment, the spacer 131b may or may not include a boron nitride layer according to an embodiment. For example, the spacer 131b may be formed of a dielectric material with a low dielectric constant, without including a boron nitride layer according to an embodiment.

[0172] Alternatively, such as Figure 25C As shown, in the semiconductor memory device, a capping layer 132 may be further disposed between the metal pattern 123 of the bit line structure BL and the hard mask pattern 125. The capping layer 132 may restrict and / or prevent the diffusion of metal material from the metal pattern 123 to the hard mask pattern 125. The capping layer 132 may include a boron nitride layer according to an embodiment. For example, the capping layer 132 may include at least one of an amorphous boron nitride layer and a nanocrystalline boron nitride layer. The amorphous boron nitride layer and the nanocrystalline boron nitride layer are chemically stable, thereby restricting and / or preventing the diffusion of metal material from the metal pattern 123 to the outside.

[0173] In addition to the boron nitride layer according to the embodiment, the capping layer 132 may further include other materials. For example, the capping layer 132 may include at least one of magnesium (Mg), aluminum (Al), scandium (Sc), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), and ruthenium (Ru), and may include nitrides or oxides comprising at least one of titanium (Ti), tantalum (Ta), tungsten (W), and cobalt (Co).

[0174] Alternatively, such as Figure 25D As shown, the semiconductor memory device may include spacers 131a comprising a boron nitride layer according to an embodiment and a capping layer 132 comprising a boron nitride layer according to an embodiment. The edge of the capping layer 132 may contact the spacers 131a. When the spacers 131a and the capping layer 132 are formed from boron nitride layers according to an embodiment, the spacers 131a and the capping layer 132 can be formed using a single-mask process, thereby simplifying the process.

[0175] like Figure 25E As shown, the insulating pattern 143a of the semiconductor memory device may include a boron nitride layer according to an embodiment. When the insulating pattern 143a includes a boron nitride layer according to an embodiment, the diffusion of material included in the bit line structure BL to the outside can be limited and / or prevented, and the parasitic capacitance between conductive materials can be reduced. In addition, no separate spacers are provided on the sidewalls of the bit line structure BL in contact with the insulating pattern 143a, and thus the process can be simplified.

[0176] Alternatively, such as Figure 25F As shown, the semiconductor memory device may include an insulating pattern 143a comprising a boron nitride layer according to an embodiment and a capping layer 132a comprising a boron nitride layer according to an embodiment. In addition to the boron nitride layer according to an embodiment, the insulating pattern 143a may further comprise an insulating material, and in addition to the boron nitride layer according to an embodiment, the capping layer 132a may further comprise a metallic material.

[0177] As described above, since the boron nitride layer according to the embodiment is stable, it can be used as a capping layer, i.e., a diffusion barrier layer, in a semiconductor memory device, and can also be used as an interlayer insulating material layer because it has a low dielectric constant. Additionally, the boron nitride layer according to the embodiment can be used as a spacer to reduce parasitic capacitance between conductive materials.

[0178] The semiconductor memory devices described above can be implemented in various types of semiconductor packages. For example, the semiconductor memory devices according to embodiments of this disclosure can be packaged as follows: PoP (Package-on-Package), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Chip Carrier with Leads (PLCC), Plastic Dual In-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip on Board (COB), Ceramic Dual In-line Package (CERDIP), Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System-in-Package (SIP), Multi-Chip Package (MCP), Wafer-Scale Fabrication Package (WFP), Wafer-Scale Process Stacked Package (WSP), etc. The package in which the semiconductor memory device according to embodiments of this disclosure is mounted may further include a controller and / or logic devices for controlling the semiconductor memory device.

[0179] Figure 26 A block diagram illustrating an electronic device 1100 including a semiconductor memory device according to an embodiment.

[0180] refer to Figure 26 The electronic device 1100 according to the embodiments may be one of a PDA, laptop computer, portable computer, display device, network tablet, cordless phone, mobile phone, digital music player, and wired or wireless electronic device, or a composite electronic device including at least two of these. The electronic device 1100 may include a controller 1110 connected (coupled) to each other via a bus 1150, input / output devices 1120 such as a keyboard, keyboard, and display, a memory 1130, and a wireless interface 1140. The controller 1110 may include, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. The memory 1130 may be used, for example, to store instructions executed by the controller 1110. The memory 1130 may be used to store user data. The memory 1130 may include at least one semiconductor memory device according to embodiments of this disclosure. The electronic device 1100 may use the wireless interface 1140 to transmit data to or receive data from a wireless communication network that communicates using RF signals. For example, the wireless interface 1140 may include an antenna, a wireless transceiver, etc. Electronic device 1100 can be used in communication interface protocols such as third-generation communication systems such as CDMA, GSM, NADC, E-TDMA, WCDAM, and CDMA2000.

[0181] Figure 27A block diagram illustrating a storage system 1200 including a semiconductor storage device according to an embodiment is provided.

[0182] refer to Figure 27 The semiconductor memory device according to the embodiments can be used to implement a memory system. The memory system 1200 may include a memory 1210 for storing large amounts of data and a memory controller 1220. The memory controller 1220 controls the memory 1210 to read or write data stored in the memory 1210 in response to a read / write request from the host 1230, thereby transforming the memory controller 1220 into a dedicated controller configured to control the memory 1210. The memory controller 1220 may be configured with an address mapping table to map addresses provided from the host 1230, such as a mobile device or computer system, to physical addresses of the memory 1210. The memory 1210 may include at least one semiconductor memory device according to embodiments of this disclosure.

[0183] Figure 26 Controller 1110 and Figure 27 The memory controller 1220 may include: processing lines, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing lines may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit (ASIC), etc.

[0184] Figure 26 The controller 1110 may operate as follows: in response to receiving commands via wireless interface 1140 and / or input / output device 1120, and / or instructions stored in memory 1130, thereby transforming the controller 1110 into a dedicated controller 1110 configured to control the operation of an electronic device including memory 1130, which may include at least one semiconductor memory device according to embodiments of the present disclosure.

[0185] While embodiments of low dielectric constant boron nitride layers have been described and illustrated above, this disclosure is not limited to the specific embodiments described above, nor does it depart from the spirit of this disclosure as claimed in the claims.

[0186] It should be understood that the embodiments described herein should be considered in the descriptive sense only and are not intended for limiting purposes. The descriptions of features or aspects in each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. Semiconductor memory devices, including: Semiconductor substrate; Word lines extending in a first direction on the semiconductor substrate; A bit line structure extending across the word line, the bit line structure extending in a second direction intersecting the first direction; Contact pad structure between the word lines and between the bit line structure; as well as The spacer between the bit line structure and the contact pad structure includes a boron nitride layer. The spacer contacts the sidewall of the bit line structure and extends the length of the sidewall of the bit line structure, and the spacer extends along the upper surface of the bit line structure between and in direct contact with at least a portion of the bit line structure and the contact pad structure.

2. The semiconductor memory device of claim 1, wherein the spacer surrounds at least a portion of the contact pad structure.

3. The semiconductor memory device of claim 1, wherein... The bit line structure includes polysilicon patterns, barrier / pad patterns, metal patterns, and hard mask patterns sequentially stacked on the semiconductor substrate. The spacer overlaps with the polysilicon pattern, the barrier / pad pattern, and the metal pattern in the first direction.

4. The semiconductor memory device of claim 3, wherein the spacer is in direct contact with at least one of the polysilicon pattern, the barrier / pad pattern, and the metal pattern.

5. The semiconductor memory device of claim 3, wherein the spacer is configured to overlap with at least a portion of the hard mask pattern in the first direction.

6. The semiconductor memory device of claim 1, wherein the boron nitride layer has a dielectric constant of 2.5 or less at an operating frequency of 100 kHz.

7. The semiconductor memory device of claim 1, wherein the boron nitride layer comprises at least one amorphous material and nanocrystalline material.

8. The semiconductor memory device of claim 1, wherein the boron nitride layer is non-porous.

9. The semiconductor memory device of claim 1, wherein... The bit line structure includes polysilicon patterns, barrier / pad patterns, metal patterns, and hard mask patterns sequentially stacked on the semiconductor substrate. The semiconductor memory device further includes a capping layer disposed between the metal pattern and the hard mask pattern.

10. The semiconductor memory device of claim 9, wherein the capping layer comprises a boron nitride layer.

11. The semiconductor memory device of claim 10, wherein the boron nitride layer in the capping layer has the same physical properties as the boron nitride layer included in the spacer.

12. The semiconductor memory device of claim 9, wherein the end portion of the capping layer contacts the spacer.

13. The semiconductor memory device of claim 1, further comprising: Gate hard mask pattern on the word line; Interlayer insulating layer on the gate hard mask pattern; and The insulating pattern on the interlayer insulating layer, wherein At least one of the interlayer insulation layer and the insulation pattern includes a boron nitride layer.

14. The semiconductor memory device of claim 13, wherein the boron nitride layer in at least one of the interlayer insulating layer and the insulating pattern has the same physical properties as the boron nitride layer included in the spacer.

15. The semiconductor memory device of claim 13, wherein... The insulating pattern includes the boron nitride layer, and The insulating pattern and the spacer are integrated with each other.

16. The semiconductor memory device of claim 13, wherein the interlayer insulating layer is in contact with the spacer.

17. Equipment, including: The memory includes the semiconductor memory device as described in any one of claims 1-16; and A controller configured to: store data in the memory or read data from the memory.

18. The device of claim 17, wherein the device is at least one of a computer, a portable electronic device, a display, or a storage system.

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