Vertical memory device

Abstract

A vertical memory device includes gate electrode structures, a channel, first to third split patterns, and a first support layer. The gate electrode structures include gate electrodes stacked in a first direction and extend in a second direction. The gate electrode structures are spaced apart from each other in a third direction. The first split pattern extends between the gate electrode structures in the second direction. The second split pattern and the third split pattern are alternately disposed between the gate electrode structures in the second direction. The first support layer is at substantially the same height as upper portions of the first split pattern and the second split pattern on the gate electrode structures and contacts the upper portions of the first split pattern and the second split pattern. In a plan view, the upper portions of the first split pattern and the second split pattern are arranged in a zigzag pattern in the second direction.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present inventive concept relate to a vertical memory device. BACKGROUND

[0002] In a VNAND flash memory device, as the number of stacked gate electrodes increases, a mold including a sacrificial layer for forming the gate electrodes can be bent or collapsed. SUMMARY

[0003] According to an example embodiment of the present inventive concept, a vertical memory device can include gate electrode structures, channels, a first split pattern, a second split pattern, and a third split pattern, and a first support layer. Each gate electrode structure can include gate electrodes spaced apart from each other in a first direction substantially perpendicular to an upper surface of a substrate and extending in a second direction substantially parallel to the upper surface of the substrate. The gate electrode structures can be spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. Each channel can extend in the first direction through one of the gate electrode structures. The first split pattern can extend in the second direction between first gate electrode structures adjacent in the third direction among the gate electrode structures. The second split pattern and the third split pattern can be alternately disposed in the second direction between second gate electrode structures adjacent in the third direction among the gate electrode structures. The first support layer can be formed on the gate electrode structures at substantially the same height as upper portions of the first split pattern and the second split pattern. The first support layer can contact the upper portions of the first split pattern and the upper portions of the second split pattern. In a plan view, the upper portions of the first split pattern and the upper portions of the second split pattern can be arranged in a zigzag pattern in the second direction.

[0004] According to an example embodiment of the present inventive concept, a vertical memory device can include gate electrode structures, channels, a first split pattern, a second split pattern, a third split pattern, and a support layer. Each gate electrode structure can include gate electrodes spaced apart from each other in a first direction substantially perpendicular to an upper surface of a substrate and extending in a second direction substantially parallel to the upper surface of the substrate on the substrate. The gate electrode structures can be spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. The channels can each extend in the first direction through one of the gate electrode structures. The first split pattern can include first lower portions and first upper portions. The first lower portions can extend in the second direction between first gate electrode structures adjacent in the third direction among the gate electrode structures to separate the first gate electrode structures from each other. The first upper portions can be spaced apart from each other in the second direction and contact upper surfaces of the first lower portions. The second split pattern can include second lower portions and second upper portions. The second lower portions can be spaced apart from each other in the second direction and disposed between second gate electrode structures among the gate electrode structures. The second upper portions can contact upper surfaces of the second lower portions. The third split pattern can be disposed between the second lower portions of the second split pattern. The support layer can be formed on the gate electrode structures and can face sidewalls of the first upper portions of the first split pattern and sidewalls of the second upper portions of the second split pattern, respectively.

[0005] According to an example embodiment of the present inventive concept, a vertical memory device can include gate electrode structures, channels, a first split pattern, a second split pattern, a support layer, and first and second insulating patterns. Each gate electrode structure can include gate electrodes spaced apart from each other in a first direction substantially perpendicular to an upper surface of a substrate and extending in a second direction substantially parallel to the upper surface of the substrate on the substrate. The gate electrode structures can be spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. The channels can each extend in the first direction through one of the gate electrode structures. Each first split pattern can extend in the second direction between first gate electrode structures adjacent in the third direction among the gate electrode structures to separate the first gate electrode structures from each other. The second split pattern can be spaced apart from each other in the second direction between second gate electrode structures adjacent in the third direction among the gate electrode structures. The support layer can be formed on the gate electrode structures and the first and second split patterns and can include first and second openings at least partially exposing upper surfaces of the first and second split patterns, respectively. The first and second insulating patterns can fill the first and second openings, respectively. The first and second insulating patterns can be arranged in a zigzag pattern in the third direction.

[0006] According to an example embodiment of the inventive concept, a vertical memory device can include a common source plate (CSP), a channel connection pattern, a first support layer, gate electrode structures, channels, a first division pattern, a second division pattern, and a third division pattern, and a second support layer. The CSP can be formed on a substrate. The channel connection pattern and the first support layer can be sequentially stacked on the CSP in a first direction substantially perpendicular to an upper surface of the substrate. The gate electrode structures can each include a gate electrode, the gate electrodes being spaced apart from each other in the first direction on the first support layer and extending in a second direction substantially parallel to the upper surface of the substrate. The gate electrode structures can be spaced apart from each other in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. The channels can each extend in the first direction on the CSP through one of the gate electrode structures, the first support layer, and the channel connection pattern, and the channels can be electrically connected to each other. The first division pattern can extend in the second direction between first ones of the gate electrode structures adjacent in the third direction to separate the first ones of the gate electrode structures from each other. The second division pattern and the third division pattern can be alternately disposed in the second direction between second ones of the gate electrode structures adjacent in the third direction to separate the second ones of the gate electrode structures from each other. The second support layer can be formed on the gate electrode structures at substantially the same height as upper portions of the first division pattern and the second division pattern. The upper portions of the first division pattern and the second division pattern can be arranged in a zigzag pattern in the second direction.

[0007] A method of manufacturing a vertical memory device can include forming a common source plate (CSP) on a substrate in a first direction; forming a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in the first direction to form a mold on the CSP; etching the mold to form first openings exposing the CSP and to divide the plurality of sacrificial layers into sacrificial patterns, wherein the first openings separate the sacrificial patterns in a third direction crossing the first direction; forming a first division pattern in the first openings; forming second openings and third openings extending in a second direction crossing the first and third directions, wherein the second openings are disposed between the first division pattern in the second direction; forming a first support layer on the mold and the first division pattern, wherein the first support layer includes fourth openings and fifth openings; removing the sacrificial patterns to form gaps between the plurality of insulating layers; forming gate electrodes in the gaps, wherein the gate electrodes are alternately stacked with the plurality of insulating layers; filling the second to fifth openings to form division layers; and planarizing the division layers until the first support layer is exposed to form a second division pattern and a third division pattern, wherein the second division pattern is disposed in the second and fourth openings and the third division pattern is disposed in the third and fifth openings. The first division pattern and the second division pattern are alternately disposed in the second direction. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 、 Figure 2A 、 Figure 2B and Figure 3 are plan and sectional views showing a vertical storage device according to an example embodiment of the present inventive concept.

[0009] Figures 4 to 25 are plan and sectional views showing a method of manufacturing a vertical storage device according to an example embodiment of the present inventive concept.

[0010] Figure 26 and Figure 27 are plan views showing a vertical storage device according to an example embodiment of the present inventive concept.

[0011] Figures 28 to 30 are plan views showing a vertical storage device according to an example embodiment of the present inventive concept. DETAILED DESCRIPTION

[0012] Example embodiments of the present inventive concept provide a vertical storage device having improved characteristics.

[0013] Example embodiments of the present inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can be used to refer to like elements throughout this application.

[0014] It will be understood that, although the terms "first", "second", "third", and so on can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. The terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Therefore, a first element, component, region, layer or section discussed below could be termed a second or third element, component, region, layer or section without departing from the teachings of the present inventive concept.

[0015] Hereinafter, in this specification (not necessarily in the claims), a direction substantially perpendicular to an upper surface of a substrate can be referred to as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other can be referred to as a second direction and a third direction, respectively. In example embodiments of the present inventive concept, the second direction and the third direction can be substantially perpendicular to each other.

[0016] Figure 1 、 Figure 2A 、 Figure 2B and Figure 3 are plan and sectional views showing a vertical storage device according to an example embodiment of the present inventive concept. Figure 1 is a plan view, Figure 2A andFigure 2B is a cross-sectional view taken along a line A-A' of Figure 1 , Figure 3 is a cross-sectional view taken along a line B-B' of Figure 1 . To avoid complexity of the drawings, Figure 1 the fourth and fifth insulating intermediate layers, the contact plug, and the wiring are not shown.

[0017] Referring to Figure 1 , Figure 2A and Figure 3 , the vertical memory device can include a common source plate (CSP) 100, a channel connection pattern 280, a first support layer 150, a second support layer 300, a gate electrode structure, a channel 200, a charge storage structure 190, and first to fourth division patterns 230, 235, 350, and 355 on a substrate 10. The vertical memory device can further include a lower circuit pattern, a fill pattern 210, a cap pattern 220, an insulating pattern 165, first to fourth insulating intermediate layers 20, 180, 240, and 360, a fifth insulating intermediate layer, a contact plug 370, and an upper wiring 380.

[0018] The substrate 10 can include silicon, germanium, silicon germanium, or a group III-V compound such as GaP, GaAs, GaSb, etc. In an exemplary embodiment of the inventive concept, the substrate 10 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0019] In an exemplary embodiment of the inventive concept, the vertical memory device can have a cell-on-periphery (COP) structure. In other words, a lower circuit pattern can be formed on the substrate 10, and a memory cell can be formed on the lower circuit pattern. The lower circuit pattern can include, for example, a transistor, a lower contact plug, a lower wiring, a lower via, etc. The lower circuit pattern can be covered by the first insulating intermediate layer 20 on the substrate 10.

[0020] The CSP 100 can be formed on the first insulating intermediate layer 20, and can include, for example, polysilicon doped with an n-type impurity.

[0021] The gate electrode structure can include gate electrodes 342, 344, and 346 spaced apart from each other in a first direction on the CSP 100. Each of the gate electrodes 342, 344, and 346 can extend in a second direction. The length of the gate electrodes 342, 344, and 346 extending in the second direction can decrease from a lower level to an upper level, and thus the gate electrode structure can have a stepped shape.

[0022] The gate electrodes 342, 344, and 346 can include a first gate electrode 342, a second gate electrode 344, and a third gate electrode 346 stacked in order in the first direction. The first gate electrode 342 can function as a ground select line (GSL), each of the second gate electrodes 344 can function as a word line, and the third gate electrode 346 can function as a string select line (SSL).

[0023] Each of the first to third gate electrodes 342, 344, and 346 can be formed in one or more tiers. In an exemplary embodiment of the inventive concept, the first gate electrode 342 can be formed in a lowermost tier, the third gate electrode 346 can be formed in an uppermost tier and one tier directly below the uppermost tier, and the second gate electrodes 344 can be formed at a plurality of tiers between the first gate electrode 342 and the third gate electrode 346. The uppermost tier is farthest from the substrate 10, and the lowermost tier is closest to the substrate 10. Or in other words, the uppermost tier (or upper tier) is closer to the first support layer 150 than to the substrate 10.

[0024] Each of the first to third gate electrodes 342, 344, and 346 can include a conductive pattern and a barrier pattern covering lower and upper surfaces and sidewalls of the conductive pattern. The conductive pattern can include a low-resistance metal such as tungsten, titanium, tantalum, platinum, etc., and the barrier pattern can include a metal nitride such as titanium nitride, tantalum nitride, etc.

[0025] Lower and upper surfaces and sidewalls of each of the gate electrodes 342, 344, and 346 facing the channel 200 can be covered by a second blocking pattern 335. The second blocking pattern 335 can include a metal oxide such as aluminum oxide, hafnium oxide, etc., and thus can be referred to as a metal oxide pattern. The second blocking pattern 335 can also cover sidewalls of the insulating pattern 165, sidewalls of the first and second support layers 150 and 300, sidewalls of the channel connection pattern 280, sidewalls of the second and third insulating intermediate layers 180 and 240, and an upper surface of the CSP 100.

[0026] The insulating pattern 165 can be formed between the gate electrodes 342, 344, and 346 adjacent to each other in the first direction, and the gate electrodes 342, 344, and 346 and the insulating pattern 165 can form a molding having a stepped shape. The insulating pattern 165 can include an oxide such as silicon oxide.

[0027] In an exemplary embodiment of the inventive concept, the gate electrode structure can extend in the second direction, and a plurality of gate electrode structures can be formed in the third direction. The second to fourth split patterns 235, 350, and 355 can be formed between the gate electrode structures separated from each other in the third direction.

[0028] The third split pattern 350 can include a first lower portion 350a extending between the gate electrode structures in the second direction, and first upper portions 350b each of which can contact upper surfaces of the first lower portion 350a, spaced apart from each other in the second direction. The gate electrode structures can be separated from each other in the third direction by the first lower portion 350a of the third split pattern 350.

[0029] In an exemplary embodiment of the inventive concept, a width of each of the first upper portions 350b in the third direction can be greater than a width of the first lower portion 350a in the third direction; however, the inventive concept can not be limited thereto. The second barrier pattern 335 can cover a portion of sidewalls of the first lower portion 350a of the third split pattern 350 and sidewalls of the first upper portions 350b of the third split pattern 350. A plurality of the third split patterns 350 can be spaced apart from each other in the third direction.

[0030] The fourth split pattern 355 can include second lower portions 355a spaced apart from each other in the second direction between the gate electrode structures, and second upper portions 355b each of which collectively contacts upper surfaces of the second lower portions 355a (e.g., adjacent second lower portions) adjacent to each other in the second direction. In an exemplary embodiment of the inventive concept, the fourth split pattern 355 can be formed between the third split patterns 350 (e.g., adjacent third split patterns) adjacent to each other in the third direction.

[0031] In an exemplary embodiment of the inventive concept, a width of each of the second upper portions 355b in the third direction can be greater than a width of each of the second lower portions 355a in the third direction; however, the inventive concept can not be limited thereto. The second barrier pattern 335 can cover a portion of sidewalls of the second lower portions 355a of the fourth split pattern 355 and sidewalls of the second upper portions 355b of the fourth split pattern 355. In other words, the second upper portions 355b and the second lower portions 355a of the fourth split pattern 355 can be similar to the first upper portions 350b and the first lower portions 350a of the third split pattern 350; however, the inventive concept can not be limited thereto.

[0032] In an exemplary embodiment of the inventive concept, the first upper portions 350b of the third split patterns 350 and the second upper portions 355b of the fourth split patterns 355 can be arranged in a zigzag pattern in the second direction or the third direction in a plan view. In an exemplary embodiment of the inventive concept, each of the first upper portions 350b of the third split patterns 350 can partially overlap at least one of the second upper portions 355b of the fourth split patterns 355 in the third direction. In an exemplary embodiment of the inventive concept, the first upper portions 350b of the third split patterns 350 and the second upper portions 355b of the fourth split patterns 355 can be disposed at substantially the same height.

[0033] The third split patterns 350 and the fourth split patterns 355 can include substantially the same material, e.g., an oxide such as silicon oxide. Accordingly, the third split patterns 350 and the fourth split patterns 355 can be referred to as first and second insulating patterns, respectively. Alternatively, the first and second upper portions 350b and 355b or the first and second lower portions 350a and 355a of the third and fourth split patterns 350 and 355 can be referred to as first and second insulating patterns, respectively. If the first and second upper portions 350b and 355b of the third and fourth split patterns 350 and 355 are referred to as first and second insulating patterns, respectively, the first and second insulating patterns can be arranged in a zigzag pattern in the second direction or the third direction, and each of the first insulating patterns can partially overlap at least one of the second insulating patterns in the third direction.

[0034] The second split patterns 235 can be formed between and connected with the second lower portions 355a of the fourth split patterns 355 adjacent to each other in the second direction. Accordingly, the gate electrode structures can be separated from each other in the third direction by the second split patterns 235 and the second lower portions 355a of the fourth split patterns 355. In an exemplary embodiment of the inventive concept, each of the second split patterns 235 can overlap the second upper portions 355b of the fourth split patterns 355 in the first direction.

[0035] In an exemplary embodiment of the inventive concept, an upper surface of the second division pattern 235 can be substantially coplanar with an upper surface of the second insulating intermediate layer 180 on an uppermost one of the insulating patterns 165 and an upper surface of the cap pattern 220, and thus, can be lower than upper surfaces of first lower portions 350a and second lower portions 355a of the third division pattern 350 and the fourth division pattern 355, the upper surfaces of the first lower portions 350a and the second lower portions 355a can be substantially coplanar with an upper surface of the third insulating intermediate layer 240 on the second insulating intermediate layer 180. In other words, the upper surfaces of the first lower portions 350a and the second lower portions 355a of the third division pattern 350 and the fourth division pattern 355 are farther from the substrate 10 than the upper surface of the second division pattern 235.

[0036] The second division pattern 235 can include an oxide, for example, a silicon oxide. Thus, the second to fourth division patterns 235, 350, and 355 can include substantially the same material.

[0037] The channel 200 can be formed in a channel hole extending through the mold and the second insulating intermediate layer 180 to expose an upper surface of the CSP 100, the mold can include the first to third gate electrodes 342, 344, and 346 and the insulating pattern 165 interposed therebetween, which are sequentially stacked in the first direction. Thus, the channel 200 can extend in the first direction.

[0038] For example, the channel 200 can extend in the first direction on the CSP 100 and can have a cup shape. The channel 200 can include undoped or doped polysilicon or single-crystal silicon.

[0039] In an exemplary embodiment of the inventive concept, the channel 200 can be formed in each of the second direction and the third direction. A plurality of channels 200 arranged in the second direction can form a channel column, a plurality of channel columns arranged in the third direction can form a channel group, and a plurality of channel groups arranged in the third direction can form a channel block. In the drawings, one channel block includes two channel groups, and each channel group includes nine channel columns; however, the inventive concept can not be limited thereto.

[0040] The charge storage structure 190 can include an upper portion extending in the first direction to cover most of the outer sidewall of the channel 200 and having a hollow cylindrical shape, and a lower portion covering the bottom surface and the lower sidewall of the channel 200 on the CSP 100 and having a cup shape. The lower portion of the charge storage structure 190 can be spaced apart from the upper portion of the charge storage structure 190. Each of the lower portion and the upper portion of the charge storage structure 190 can include a tunnel insulating pattern, a charge storage pattern, and a first blocking pattern, which are sequentially stacked from the outer sidewall and / or the bottom surface of the channel 200.

[0041] The tunnel insulating pattern and the first blocking pattern can include an oxide, such as silicon oxide, and the charge storage pattern can include a nitride, such as silicon nitride.

[0042] The fill pattern 210 can fill an inner space formed by inner sidewalls of the channel 200. The fill pattern 210 can include an oxide, such as silicon oxide.

[0043] The channel 200, the charge storage structure 190, and the fill pattern 210 can be formed in a channel hole on the CSP 100, and the cap pattern 220 can be formed in an upper portion of the channel hole, such as on the channel 200, the charge storage structure 190, and the fill pattern 210. The cap pattern 220 can include, for example, polysilicon doped with n-type impurities.

[0044] The first split pattern 230 can extend through upper portions of the channels 200 included in a channel column at a central portion of each channel group in the third direction, and can extend in the second direction. In other words, the first split pattern 230 can extend in the second direction between the third split pattern 350 and the fourth split pattern 355. In an exemplary embodiment of the inventive concept, the first split pattern 230 can extend not only through the upper portions of the channels 200, but also through upper portions of the charge storage structure 190 and the fill pattern 210, the cap pattern 220, the second insulating intermediate layer 180, the insulating patterns 165 at the upper two levels, and the third gate electrodes 346. Accordingly, the third gate electrodes 346 at the upper two levels in the gate electrode structure can be separated from each other in the third direction by the first split pattern 230.

[0045] The channel connection pattern 280 and the first support layer 150 can be sequentially stacked on the CSP 100 in the first direction. The channel connection pattern 280 can contact lower outer sidewalls of each channel 200, such as outer sidewalls of each channel 200 that can be formed between a lower portion and an upper portion of the charge storage structure 190 and thus are not covered by the charge storage structure 190, and thus the channels 200 included in each channel group can be connected to each other. The channel connection pattern 280 can include, for example, polysilicon doped with n-type impurities, and can have an air gap 285 therein.

[0046] The first support layer 150 can be formed between the channel connection pattern 280 and the first gate electrode 342. However, a portion of the first support layer 150 can extend through the channel connection pattern 280 to contact an upper surface of the CSP 100, which can be referred to as a support pattern. A plurality of support patterns can be formed, and can have various types of layouts. The first support layer 150 can include, for example, polysilicon doped with n-type impurities.

[0047] The second insulating intermediate layer 180 can cover the mold and can be formed on the uppermost one of the CSP 100 and the insulating pattern 165. The third insulating intermediate layer 240 can be formed on the second insulating intermediate layer 180, the cap pattern 220, and the first and second division patterns 230 and 235.

[0048] The second support layer 300 can be formed on the third insulating intermediate layer 240 and can include a fifth opening 310 and a sixth opening 315 (refer to Figure 18 ). Accordingly, the second support layer 300 can be formed at substantially the same height as the first upper portion 350b of the third division pattern 350 and the second upper portion 355b of the fourth division pattern 355 respectively located in the fifth and sixth openings 310 and 315, and can face the portions of the second barrier pattern 335 on the sidewalls of the fifth and sixth openings 310 and 315. The second support layer 300 can include an oxide such as silicon oxide.

[0049] The fourth insulating intermediate layer 360 can be formed on the second support layer 300 and the first and second upper portions 350b and 355b of the third and fourth division patterns 350 and 355, and the fifth insulating intermediate layer can be formed on the fourth insulating intermediate layer 360.

[0050] The contact plug 370 can extend through the third and fourth insulating intermediate layers 240 and 360 and the second support layer 300 to contact the upper surface of the cap pattern 220, and the upper wiring 380 can extend in the third direction to contact the contact plug 370. In the exemplary embodiment of the inventive concept, a plurality of upper wirings 380 can be formed in the second direction. The upper wiring 380 can function as a bit line of a vertical memory device.

[0051] The fourth division pattern 355 can include a protruding portion 355c. At least a portion of the protruding portion 355c can be formed at substantially the same height as the channel connection pattern 280 to protrude below the second division pattern 235 in the second direction. The surface of the protruding portion 355c of the fourth division pattern 355 can be covered by the second barrier pattern 335.

[0052] Alternatively, referring to Figure 2B , instead of the protruding portion 355c of the fourth division pattern 355, the channel connection pattern 280 can be formed below the second division pattern 235. In this case, the channels 200 included in each of the channel groups adjacent in the second direction can be electrically connected to each other by the channel connection pattern 280.

[0053] As described above, a vertical storage device may include second to fourth dividing patterns 235, 350, and 355 between the gate electrode structures and a second support layer 300 on the gate electrode structures. Therefore, even if the molded object has a high upper surface or a long extension length, the molded object including the gate electrode structure may not bend or collapse, as will be shown and described below.

[0054] Figures 4 to 25 These are plan and cross-sectional views illustrating a method for manufacturing a vertical storage device according to an exemplary embodiment of the concept of the present invention. Figure 4 , Figure 6 , Figure 8 , Figure 10 , Figure 16 , Figure 18 and Figure 20 It's a floor plan. Figure 5 , Figure 7 , Figure 9 , Figures 11-15 , Figure 17 , Figure 19 and Figures 21-25 It is a cross-sectional view.

[0055] Figure 5 , Figure 7 , Figure 9 , Figure 12 , Figure 14 , Figure 22 and Figure 24 It is a cross-sectional view taken along line A-A' of the corresponding plan view. Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 23 and Figure 25 It is a cross-sectional view taken along line B-B' of the corresponding plan view.

[0056] Reference Figure 4 and Figure 5 A lower circuit pattern can be formed on the substrate 10, and a first insulating intermediate layer 20 can be formed on the substrate 10 to cover the lower circuit pattern.

[0057] CSP 100, sacrificial layer structure 140 and first support layer 150 can be sequentially formed on the first insulating intermediate layer 20.

[0058] The sacrificial layer structure 140 may include first to third sacrificial layers 110, 120 and 130 stacked sequentially. Each of the first sacrificial layer 110 and the third sacrificial layer 130 may include an oxide, such as silicon oxide, and the second sacrificial layer 120 may include a nitride, such as silicon nitride.

[0059] The first support layer 150 may include a material having etch selectivity relative to the first through third sacrificial layers 110, 120, and 130, such as polycrystalline silicon doped with n-type impurities. In an exemplary embodiment of the inventive concept, the first support layer 150 may be formed to include polycrystalline silicon doped with n-type impurities by depositing amorphous silicon doped with n-type impurities and by performing a heat treatment or by crystallizing via heat generated during a deposition process for other structures.

[0060] The insulating layer 160 and the fourth sacrificial layer 170 can be formed alternately and repeatedly on the first support layer 150, thus forming a molded layer including the insulating layer 160 and the fourth sacrificial layer 170. The insulating layer 160 may include an oxide, such as silicon oxide, and the fourth sacrificial layer 170 may include a material that has etch selectivity relative to the insulating layer 160, such as a nitride such as a silicon nitride.

[0061] Reference Figure 6 and Figure 7 An etching process using a photoresist pattern as an etching mask and a trimming process for reducing the area of ​​the photoresist pattern can be performed alternately and repeatedly to form a molded object with multiple stepped layers, each stepped layer including a fourth sacrificial layer 170 and an insulating layer 160 stacked in sequence, and the multiple stepped layers having a stepped shape.

[0062] A second insulating intermediate layer 180 can be formed on the CSP 100 to cover the molded material, and channel holes can be formed through the second insulating intermediate layer 180, the molded material, the first support layer 150, and the sacrificial layer structure 140 to expose the upper surface of the CSP 100. Multiple channel holes can be formed in each of the second and third directions.

[0063] A charge storage structure layer and a channel layer can be formed on the sidewalls of each via, the exposed upper surface of the CSP 100, and the upper surface of the second insulating intermediate layer 180. A fill layer can be formed on the channel layer to fill the via. The fill layer, channel layer, and charge storage structure layer can be planarized until the upper surface of the second insulating intermediate layer 180 can be exposed to form a charge storage structure 190, a channel 200, and a fill pattern 210 in each via.

[0064] In an exemplary embodiment of the present invention, a plurality of channels 200 may be formed in each of the second direction and the third direction. The plurality of channels 200 arranged in the second direction may form a channel column, the plurality of channel columns arranged in the third direction may form a channel group, and the plurality of channel groups arranged in the third direction may form a channel block.

[0065] In an exemplary embodiment of the present invention, the charge storage structure 190 may include a tunnel insulating pattern, a charge storage pattern, and a first barrier pattern stacked sequentially from the outer sidewall of the channel 200 in a horizontal direction substantially parallel to the upper surface of the substrate 10.

[0066] The upper portion of the columnar structure, including the charge storage structure 190, the channel 200, and the filling pattern 210 stacked in each channel hole, can be removed to form a groove, and a cap pattern 220 can be formed to fill the groove.

[0067] Reference Figure 8 and Figure 9 Some of the second insulating intermediate layer 180, insulating layer 160 and some of the fourth sacrificial layer 170 can be etched to form a first opening extending in the second direction, and a first dividing pattern 230 can be formed to fill the first opening.

[0068] In an exemplary embodiment of the present invention, the first dividing pattern 230 may extend through the upper portion of the channel 200 included in the channel column at the central portion of each channel group in the third direction. In an exemplary embodiment of the present invention, the first dividing pattern 230 may extend not only through the upper portion of the channel 200, but also through the fourth sacrificial layer 170 at the upper two levels and the insulating layer 160 at the upper two levels, as well as a portion of the insulating layer 160 directly below it. The first dividing pattern 230 may extend in a second direction and may extend through the upper two stepped layers included in the molding. Therefore, the fourth sacrificial layers 170 at the upper two levels can be separated from each other in the third direction by the first dividing pattern 230.

[0069] Additionally, the second insulating intermediate layer 180, the molding, the first support layer 150, and the sacrificial layer structure 140 can be etched to form a second opening exposing the upper surface of the CSP 100, and a second segmentation pattern 235 can be formed in the second opening. In an exemplary embodiment of the inventive concept, a plurality of second segmentation patterns 235 may be spaced apart from each other in a second direction between adjacent first segmentation patterns 230 along a third direction (more specifically, between adjacent groups of channels along a third direction in each channel block).

[0070] The first segmentation pattern 230 and the second segmentation pattern 235 can be formed by the same etching and deposition processes or by separate etching and deposition processes.

[0071] Reference Figure 10 and Figure 11A third insulating intermediate layer 240 can be formed on the second insulating intermediate layer 180, the cover pattern 220, the first dividing pattern 230, and the second dividing pattern 235, and a third opening 260 and a fourth opening 265 can be formed through the second insulating intermediate layer 180, the third insulating intermediate layer 240, and the molded material by, for example, a dry etching process.

[0072] A dry etching process can be performed until each of the third opening 260 and the fourth opening 265 can expose the upper surface of the first support layer 150, and each of the third opening 260 and the fourth opening 265 can extend through the upper portion of the first support layer 150. The insulating layer 160 and the fourth sacrificial layer 170 included in the molded material can be exposed through the third opening 260 and the fourth opening 265.

[0073] In an exemplary embodiment of the present invention, a third opening 260 may extend in a second direction between adjacent channel blocks in a third direction, and a plurality of third openings 260 may be formed in the third direction. In an exemplary embodiment of the present invention, a fourth opening 265 may be formed between second dividing patterns 235 arranged in the second direction, and may be connected to the end of each second dividing pattern 235 in the second direction. In other words, a plurality of fourth openings 265 may be spaced apart from each other in the second direction, and each fourth opening 265 may be formed between adjacent groups of channels in the third direction within each channel block.

[0074] When the second dividing pattern 235 and the third opening 260 and the fourth opening 265 are formed, the insulating layer 160 can be divided into a plurality of first insulating patterns 165, each of which extends in the second direction, and the fourth sacrificial layer 170 can be divided into a plurality of fourth sacrificial patterns 175, each of which extends in the second direction.

[0075] A plurality of fourth openings 265 may be spaced apart from each other in a second direction between adjacent third openings 260 along a third direction, each fourth opening 265 may extend in the second direction, and a second dividing pattern 235 may be formed between adjacent fourth openings 265 along the second direction. Therefore, even if the upper surface of the molded article is high and the length of the molded article extending in the second direction is long, the fourth openings 265 do not extend to the ends of the molded article in the second direction. Since the plurality of fourth openings 265 are spaced apart from each other in the second direction, and the second dividing pattern 235 is formed therebetween, the molded article may not bend or collapse in the third direction.

[0076] The first spacer layer can be formed on the sidewalls of the third opening 260 and the fourth opening 265 and the sidewalls of the third insulating intermediate layer 240, and can be anisotropically etched to remove the portion of the first spacer layer at the bottom of the third opening 260 and the fourth opening 265, thereby forming the first spacer 250 and exposing the upper surface of the first support layer 150.

[0077] The exposed portion of the first support layer 150 and the portion of the sacrificial layer structure 140 below it can be removed to widen the third opening 260 and the fourth opening 265 downwards. Thus, the third opening 260 and the fourth opening 265 can expose the upper surface of the CSP 100 and extend further through the upper portion of the CSP 100.

[0078] In an exemplary embodiment of the inventive concept, the first spacer 250 may comprise undoped amorphous silicon or undoped polycrystalline silicon. However, if the first spacer 250 comprises undoped amorphous silicon, it may crystallize through heat generated during deposition processes for other layers, thereby comprising undoped polycrystalline silicon.

[0079] Reference Figure 12 and Figure 13 The sacrificial layer structure 140 exposed through the third opening 260 and the fourth opening 265 can be removed by, for example, a wet etching process to form the first gap 270.

[0080] Wet etching processes can be performed using, for example, hydrofluoric acid or phosphoric acid.

[0081] When the sacrificial layer structure 140 is partially removed, the sidewalls of the third opening 260 and the fourth opening 265 can be covered by the first spacer 250, so the insulating pattern 165 and the fourth sacrificial pattern 175 of the molded material can remain unremoved.

[0082] When the first gap 270 is formed, the lower surface of the first support layer 150 and the upper surface of the CSP 100 can be exposed. Additionally, a portion of the sidewall of the charge storage structure 190 can be exposed by the first gap 270, and the exposed portion of the sidewall of the charge storage structure 190 can also be removed during a wet etching process to expose the outer sidewall of the channel 200. Therefore, the charge storage structure 190 can be divided into an upper portion extending through the molding and covering most of the outer sidewall of the channel 200, and a lower portion covering the bottom surface of the channel 200 on the CSP 100.

[0083] When the first gap 270 is formed, the portion of the second segmentation pattern 235 at substantially the same height as the sacrificial layer structure 140 can also be removed to form the second gap 275.

[0084] ReferenceFigure 14 and Figure 15 The first spacer 250 can be removed, and a channel connection layer can be formed on the sidewalls of the third opening 260 and the fourth opening 265, as well as in the first gap 270 and the second gap 275. For example, a back etching process or a wet etching process can be performed to remove the portion of the channel connection layer in the third opening 260 and the fourth opening 265, so that a channel connection pattern 280 can be formed in the first gap 270.

[0085] During the etch-back process or wet etching process, a portion of the channel connection layer in the second gap 275 may also be removed; however, the inventive concept is not limited thereto. Therefore, in some cases, a portion of the channel connection layer in the second gap 275 may be retained therein as a channel connection pattern 280.

[0086] When the channel connection pattern 280 is formed, the channels 200 in each channel group can be connected to each other, and if the channel connection pattern 280 is retained in the second gap 275, the channels 200 in each channel block can be connected to each other via the channel connection pattern 280.

[0087] The channel connection pattern 280 may include, for example, amorphous silicon doped with n-type impurities, and may crystallize by heat generated during the deposition process for other layers, thereby including polycrystalline silicon doped with n-type impurities.

[0088] An air gap 285 can be formed in the channel connection pattern 280.

[0089] Reference Figure 16 and Figure 17 A second spacer 290 may be formed on the sidewalls of the third opening 260 and the fourth opening 265 and on the exposed upper surface of the CSP100, and a fifth sacrificial layer 295 may be formed on the second spacer 290 to fill the third opening 260 and the fourth opening 265.

[0090] If the channel connection pattern 280 is not retained in the second gap 275, the second spacer 290 may also be formed on the lower and upper surfaces and sidewalls of the second gap 275, and the remaining portion of the second gap 275 may be filled with the fifth sacrificial layer 295.

[0091] The second spacer 290 may include a nitride, such as silicon nitride, and the fifth sacrificial layer 295 may include, for example, polysilicon.

[0092] Reference Figure 18 and Figure 19The second support layer 300 may be formed on the third insulating intermediate layer 240, the second spacer 290 and the fifth sacrificial layer 295, and may be partially etched to form the fifth opening 310 and the sixth opening 315.

[0093] In an exemplary embodiment of the present invention, the fifth opening 310 may overlap with the third opening 260 in the first direction, wherein the second spacer 290 and the fifth sacrificial layer 295 are formed, and the plurality of fifth openings 310 may be spaced apart from each other in the second direction on each third opening 260. In an exemplary embodiment of the present invention, the fifth opening 310 may have a width in the third direction that is larger than the width of the third opening 260; however, the present invention is not limited thereto.

[0094] In an exemplary embodiment of the present invention, the sixth opening 315 may overlap with the second dividing pattern 235 and the fourth opening 265 therein forming the second spacer 290 and the fifth sacrificial layer 295 in a first direction, and a plurality of sixth openings 315 may be spaced apart from each other in a second direction on the second dividing pattern 235 and the fourth opening 265. In an exemplary embodiment of the present invention, the sixth opening 315 may have a width in a third direction that is larger than the width of the fourth opening 265 and the second dividing pattern 235; however, the present invention is not limited thereto.

[0095] In an exemplary embodiment of the present invention, the sixth opening 315 may overlap in a first direction with the opposite portion of the fourth opening 265 adjacent in a second direction and the second dividing pattern 235 therebetween.

[0096] In an exemplary embodiment of the present invention, the fifth opening 310 and the sixth opening 315 may be arranged in a zigzag pattern in the second direction. The fifth opening 310 and the sixth opening 315 may partially overlap each other in the third direction.

[0097] Reference Figure 20 and 21 The second spacer 290 and the fifth sacrificial layer 295 in the third opening 260 and the fourth opening 265 can be removed through the fifth opening 310 and the sixth opening 315, so that the third opening 260 and the fourth opening 265 can be formed again.

[0098] Even if the third opening 260 and the fourth opening 265 are formed again, the upper ends of the third opening 260 and the fourth opening 265 can be at least partially covered by the second support layer 300. Therefore, even if the molded object has a high upper surface and a long extension length in the second direction, the molded object can remain unbent or collapse in the third direction due to the second support layer 300 that at least partially covers the areas of the third opening 260 and the fourth opening 265.

[0099] In an exemplary embodiment of the present invention, the second spacer 290 and the fifth sacrificial layer 295 can be removed by a wet etching process. If the second spacer 290 and the fifth sacrificial layer 295 are formed in the second gap 275, they can also be removed to re-form the second gap 275.

[0100] The fourth sacrificial pattern 175 exposed by the third opening 260 and the fourth opening 265 can be removed to form a third gap 320 between the insulating patterns 165 at the corresponding level, and a portion of the outer wall of the charge storage structure 190 can be exposed by the third gap 320.

[0101] In an exemplary embodiment of the present invention, the fourth sacrificial pattern 175 can be removed by a wet etching process using phosphoric acid or sulfuric acid.

[0102] Reference Figure 22 and Figure 23 A second barrier layer 330 may be formed on the exposed portion of the outer wall of the charge storage structure 190, the inner wall of the third gap 320, the surface of the insulating pattern 165, the sidewall of the first support layer 150, the sidewall of the channel connection pattern 280, the upper surface of the CSP 100, a portion of the upper surface and sidewall of the third insulating intermediate layer 240, and the sidewall and upper surface of the second support layer 300. A gate electrode layer may be formed on the second barrier layer 330.

[0103] If a second gap 275 is formed again, a second barrier layer 330 and a gate electrode layer can be formed in the second gap 275.

[0104] The gate electrode layer may include a gate barrier layer and a gate conductive layer stacked sequentially. The gate barrier layer may include a metal nitride, and the gate conductive layer may include a metal.

[0105] The gate electrode layer can be partially removed to form a gate electrode in each third gap 320. In an exemplary embodiment of the inventive concept, the gate electrode layer can be partially removed by a wet etching process. If the second barrier layer 330 and the gate electrode layer are formed in the second gap 275, the gate electrode layer can be removed.

[0106] In an exemplary embodiment of the present invention, the gate electrode may extend in a second direction, and multiple gate electrodes may be formed in a first direction to form a gate electrode structure. The gate electrode structure may have a stepped shape including a stepped layer of gate electrodes.

[0107] Additionally, multiple gate electrode structures can be formed in a third direction and can be spaced apart from each other by a third opening 260 and a fourth opening 265 and a second dividing pattern 235. The gate electrode structures may include a first gate electrode 342, a second gate electrode 344, and a third gate electrode 346 stacked sequentially in a first direction. In an exemplary embodiment of the inventive concept, the first gate electrode 342 may be formed at the lowest layer and can be used as a ground select line (GSL). The third gate electrode 346 may be formed at the highest layer and the second layer from the top (e.g., below the highest layer) and can be used as a string select line (SSL). The second gate electrode 344 may be formed at multiple layers between the first gate electrode 342 and the third gate electrode 346 and can be used as a word line.

[0108] Reference Figure 1 , Figure 24 and Figure 25 A third segmentation layer can be formed on the second barrier layer 330 to fill the third to sixth openings 260, 265, 310 and 315, and the third segmentation layer and the second barrier layer 330 can be planarized until the upper surface of the second support layer 300 can be exposed to form a third segmentation pattern 350 and a fourth segmentation pattern 355 as well as a second barrier pattern 335.

[0109] The third dividing pattern 350 can fill the third opening 260 and the fifth opening 310, and can extend in the second direction. The first upper portion 350b filling the fifth opening 310 can have a width in the third direction that is greater than the width of the first lower portion 350a filling the third opening 260, and the plurality of first upper portions 350b can be spaced apart from each other in the second direction on the first lower portion 350a extending in the second direction.

[0110] The fourth dividing pattern 355 can fill the fourth opening 265 and the sixth opening 315. The second upper portion 355b filling the sixth opening 315 can have a width in the third direction that is greater than the width of the second lower portion 355a filling the fourth opening 265. The second lower portion 355a can extend in the second direction, but can be partially cut off by the second dividing pattern 235. The second upper portion 355b can be spaced apart from the second lower portion 355a and the second dividing pattern 235 in the second direction.

[0111] If the second barrier layer 330 is formed in the second gap 275 and the gate electrode layer is removed from the second gap 275, a protrusion 355c of the fourth segmentation pattern 355 can be formed in the remaining portion of the second gap 275.

[0112] Return to reference Figure 2A , Figure 2B andFigure 3 A fourth insulating intermediate layer 360 can be formed on the second support layer 300, the third dividing pattern 350 and the fourth dividing pattern 355 and the second blocking pattern 335, and the contact plug 370 can be formed through the third insulating intermediate layer 240 and the fourth insulating intermediate layer 360 and the second support layer 300 to contact the upper surface of the cover pattern 220.

[0113] A fifth insulating intermediate layer may be formed on the fourth insulating intermediate layer 360 and the contact plug 370, and an upper wiring 380 may be formed through the fifth insulating intermediate layer to contact the upper surface of the contact plug 370. The upper wiring 380 may serve as a bit line for a vertical storage device. In an exemplary embodiment of the inventive concept, the upper wiring 380 may extend upward in a third direction, and a plurality of upper wirings 380 may be spaced apart from each other in a second direction.

[0114] Vertical storage devices can be manufactured using the processes described above.

[0115] As described above, even if the molded object has a high upper surface and a long extension length in the second direction, the molded object may not bend or collapse in the third direction due to the second support layer 300 that at least partially covers the upper end of the third opening 260 extending through the molded object and in the second direction, and the second dividing pattern 235 between the fourth openings 265 spaced apart from each other in the second direction (each fourth opening 265 extending through the molded object).

[0116] Figure 26 and Figure 27 This is a plan view illustrating an exemplary embodiment of a vertical storage device according to a concept of the present invention. Except for some components, the vertical storage device can be coupled with... Figures 1 to 3 The vertical storage devices are essentially the same. Therefore, the same reference numerals refer to the same elements, and their detailed descriptions are omitted here.

[0117] Reference Figure 26 The fourth dividing pattern 355 may include a second lower portion 355a that is spaced apart from each other in the second direction and connected to the second dividing pattern 235, and a second upper portion 355b that respectively contacts the upper surface of the second lower portion 355a.

[0118] In this case, the first upper portion 350b and the second upper portion 355b of each of the third dividing pattern 350 and the fourth dividing pattern 355 can be arranged in a Z-shaped pattern in the second direction or in the third direction, and the first upper portion 350b of each third dividing pattern 350 can overlap with the second upper portion 355b of the fourth dividing pattern 355 in the third direction.

[0119] Reference Figure 27The fourth dividing pattern 355 may include a second lower portion 355a that is spaced apart from each other in the second direction and connected to the second dividing pattern 235, and a second upper portion 355b that is spaced apart from each other in the second direction and respectively contacts the second lower portion 355a.

[0120] In this case, the first upper portion 350b and the second upper portion 355b of each of the third dividing pattern 350 and the fourth dividing pattern 355 can be arranged in a Z-shaped pattern in the second direction or in the third direction, and the first upper portion 350b of each third dividing pattern 350 can overlap with the second upper portion 355b of the fourth dividing pattern 355 in the third direction.

[0121] Figures 28 to 30 This is a plan view illustrating an exemplary embodiment of a vertical storage device according to a concept of the present invention. Except for some components, the vertical storage device can be coupled with... Figure 1 , Figure 26 and Figure 27 The vertical storage devices are essentially the same. Therefore, the same reference numerals refer to the same elements, and their detailed descriptions are omitted here.

[0122] Reference Figures 28 to 30 Multiple fourth segmentation patterns 355 can be spaced apart from each other in the third direction between adjacent third segmentation patterns 350.

[0123] In other words, the fourth dividing patterns 355 spaced apart from each other in the second direction can form a column of fourth dividing patterns, and multiple columns of fourth dividing patterns can be spaced apart from each other in the third direction between adjacent third dividing patterns 350.

[0124] As described above, a vertical memory device according to an exemplary embodiment of the present invention may include a second to fourth segmentation pattern between gate electrode structures and a second support layer on the gate electrode structures. Therefore, the gate electrode structures may not bend or collapse.

[0125] While the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

[0126] This application claims priority to Korean Patent Application No. 10-2019-0136325, filed on October 30, 2019, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A vertical storage device, comprising: A gate electrode structure, each of the gate electrode structures including gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to the upper surface of the substrate, wherein each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, and the gate electrode structures are spaced apart from each other in a third direction parallel to the upper surface of the substrate and intersecting the second direction. A channel, each of the channels extending through one of the gate electrode structures in the first direction; The first segmentation pattern extends in the second direction between the third-adjacent first gate electrode structures in the gate electrode structure; The second and third dividing patterns are alternately arranged in the second direction between the second gate electrode structures that are adjacent to each other in the third direction in the gate electrode structure; as well as A first support layer on the gate electrode structure, wherein the first support layer is at the same height as the upper portion of the first segmented pattern and the upper portion of the second segmented pattern, and contacts the upper portions of the first segmented pattern and the upper portions of the second segmented pattern. In the plan view, the upper portions of the first dividing pattern and the upper portions of the second dividing pattern are arranged in a Z-shaped pattern in the second direction. The third segmentation pattern is spaced apart from and overlaps with the upper portion of the second segmentation pattern in the first direction.

2. The vertical storage device of claim 1, wherein each of the upper portions of the first segmentation pattern partially overlaps with the upper portion of the second segmentation pattern in the third direction.

3. The vertical storage device of claim 1, wherein the first segmentation pattern is one of a plurality of first segmentation patterns spaced apart from each other in the third direction, and The second segmentation pattern is disposed among the plurality of first segmentation patterns between adjacent first segmentation patterns that are upwardly adjacent to the third party.

4. The vertical storage device of claim 3, wherein the second segmentation pattern is one of a plurality of second segmentation patterns spaced apart from each other in the third direction between the adjacent first segmentation patterns.

5. The vertical storage device of claim 1, wherein the first segmentation pattern includes a lower portion extending in the second direction, and The upper portions of the first segmented pattern are spaced apart from each other in the second direction, and each of the upper portions of the first segmented pattern contacts the upper surface of the lower portion of the first segmented pattern.

6. The vertical storage device of claim 5, wherein the width of each of the upper portions of the first segmented pattern in the third direction is greater than the width of the lower portion of the first segmented pattern in the third direction.

7. The vertical storage device of claim 5, wherein the distance between the upper surface of the lower portion of the first segmented pattern and the substrate is greater than the distance between the upper surface of the third segmented pattern and the substrate.

8. The vertical storage device of claim 5, further comprising a metal oxide pattern covering the sidewalls of each of the upper portions of the first segmented pattern.

9. The vertical storage device of claim 8, further comprising a blocking pattern covering the lower and upper surfaces and sidewalls of each of the gate electrodes. The blocking pattern comprises the same material as the metal oxide pattern.

10. The vertical storage device of claim 1, wherein the second segmentation pattern comprises lower portions spaced apart from each other in the second direction and connected to the third segmentation pattern; and The upper portions of the second segmented pattern commonly contact the upper surfaces of adjacent lower portions in the second direction.

11. The vertical storage device of claim 10, wherein the width of the upper portion of the second segmented pattern in the third direction is greater than the width of the lower portion of the second segmented pattern in the third direction.

12. The vertical storage device of claim 10, wherein the distance between the upper surface of the lower portion of the second segmented pattern and the substrate is greater than the distance between the upper surface of the third segmented pattern and the substrate.

13. The vertical storage device of claim 1, wherein the second segmentation pattern comprises lower portions spaced apart from each other in the second direction and connected to the third segmentation pattern; and The upper portion of the second segmented pattern contacts the upper surface of the lower portion.

14. The vertical storage device of claim 1, wherein the second segmentation pattern comprises lower portions spaced apart from each other in the second direction and connected to the third segmentation pattern; and The upper portions of the second segmented pattern are spaced apart from each other in each of the lower portions, and each of the upper portions contacts the upper surface of the corresponding one of the lower portions.

15. A vertical storage device, comprising: A gate electrode structure, each of the gate electrode structures including gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to the upper surface of the substrate, wherein each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, and the gate electrode structures are spaced apart from each other in a third direction parallel to the upper surface of the substrate and intersecting the second direction. A channel, each of the channels extending through one of the gate electrode structures in the first direction; The first segmentation pattern includes: A first lower portion extends in the second direction between adjacent first gate electrode structures in the third-direction upward direction of the gate electrode structure, such that the first gate electrode structures in the gate electrode structure are separated from each other; and The first upper portions are spaced apart from each other in the second direction and contact the upper surface of the first lower portions; The second segmentation pattern includes: The second lower portion is spaced apart from each other in the second direction and disposed between the second gate electrode structures in the gate electrode structure; and The second upper portion contacts the upper surface of the second lower portion; A third dividing pattern is disposed between the second lower portions of the second dividing pattern; and A support layer is provided on the gate electrode structure and faces the sidewalls of the first upper portion of the first segmented pattern and the second upper portion of the second segmented pattern, respectively. The third segmentation pattern is spaced apart from and overlaps with the second upper portion of the second segmentation pattern in the first direction.

16. The vertical storage device of claim 15, wherein the first upper portion of the first segmentation pattern and the second upper portion of the second segmentation pattern are at the same height.

17. The vertical storage device of claim 15, wherein the width of the first upper portion of the first segmented pattern in the third direction is greater than the width of the first lower portion of the first segmented pattern in the third direction, and the width of the second upper portion of the second segmented pattern in the third direction is greater than the width of the second lower portion of the second segmented pattern in the third direction.

18. A vertical storage device, comprising: Common source plate on the substrate; The channel connection pattern and the first support layer are sequentially stacked on the common source plate in a first direction perpendicular to the upper surface of the substrate; A gate electrode structure, each of the gate electrode structures including gate electrodes spaced apart from each other in a first direction on a first support layer, wherein each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, and the gate electrode structures are spaced apart from each other in a third direction parallel to the upper surface of the substrate and intersecting the second direction. Each of the channels extends in the first direction through one of the gate electrode structures, the first support layer, and the channel connection pattern on the common source plate, wherein the channels are electrically connected to each other. A first segmentation pattern extends in the second direction between adjacent first gate electrode structures in the third direction of the gate electrode structure, so that the first gate electrode structures in the gate electrode structure are separated from each other. The second and third dividing patterns are alternately arranged in the second direction between the second gate electrode structures that are adjacent to each other in the third direction in the gate electrode structure, so that the second gate electrode structures in the gate electrode structure are separated from each other; as well as A second support layer on the gate electrode structure, wherein the second support layer is at the same height as the upper portion of the first segmentation pattern and the upper portion of the second segmentation pattern. The upper portions of the first dividing pattern and the upper portions of the second dividing pattern are arranged in a Z-shaped pattern in the second direction. The third segmentation pattern is spaced apart from and overlaps with the upper portion of the second segmentation pattern in the first direction.

19. The vertical storage device of claim 18, further comprising a charge storage structure covering the outer wall of each of the channels.

Images