Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a manufacturing method thereof, and a display device, the display substrate comprising: a plurality of sub-pixels, each sub-pixel comprising a light-emitting region and a non-light-emitting region, each sub-pixel being provided with a driving circuit; the driving circuit comprising: a storage capacitor and a plurality of transistors; for each sub-pixel, the plurality of transistors are located in the non-light-emitting region, the storage capacitor is a transparent capacitor, and the positive projection of the storage capacitor on the substrate overlaps with the light-emitting region, the first electrode of the storage capacitor is arranged in the same layer as the active layer of the plurality of transistors, and is arranged in a different layer from the source-drain electrodes of the plurality of transistors, and the second electrode of the storage capacitor is located on the side of the first electrode close to the substrate; the first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor. The present application can reduce the area occupied by each sub-pixel and realize a high PPI of the display substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Device (OLED) display is a display technology different from traditional liquid crystal display (LCD). It has the advantages of active luminescence, good temperature characteristics, low power consumption, fast response, flexibility, ultra-lightness and low cost. It has become one of the important discoveries of the new generation of display devices and has received more and more attention.

[0003] OLED display substrates can be divided into three types according to the light emission direction: bottom-emitting OLED, top-emitting OLED and double-sided OLED. Among them, bottom-emitting OLED refers to the light in the OLED device being emitted toward the substrate. The inventors have found that in the related art, the bottom-emitting OLED display substrate is limited by the pixel opening area, so that the area occupied by each sub-pixel is large, which leads to a low number of pixels per inch (PPI) per unit area in the bottom-emitting OLED display substrate, and it is impossible to achieve a high PPI. Summary of the invention

[0004] The present application provides a display substrate and a manufacturing method thereof, and a display device, which can reduce the area occupied by each sub-pixel, thereby achieving a high PPI of the display substrate.

[0005] The present application provides a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on the substrate, each sub-pixel comprising a light-emitting region and a non-light-emitting region, and a driving circuit is arranged in each sub-pixel; the driving circuit comprises: a storage capacitor and a plurality of transistors; the plurality of transistors comprises: a switch transistor, a driving transistor and a sensing transistor;

[0006] For each sub-pixel, the multiple transistors are located in a non-luminescent area, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on the substrate overlaps with the luminescent area, a first electrode of the storage capacitor is arranged in the same layer as an active layer of the multiple transistors, and in a different layer from source and drain electrodes of the multiple transistors, and a second electrode of the storage capacitor is located on a side of the first electrode close to the substrate;

[0007] The first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor.

[0008] Optionally, for each sub-pixel, the active layer of each transistor includes: a channel region, a first conductive region, and a second conductive region;

[0009] The first conductive region and the second conductive region are respectively arranged at two sides of the channel region, the second electrode of the transistor is connected to the first conductive region, and the first electrode of the transistor is connected to the second conductive region;

[0010] The second conductive region of the driving transistor is connected to the second electrode; the second conductive region of the sensing transistor is connected to the second electrode.

[0011] Optionally, the display substrate further comprises: a buffer layer disposed on a side of the active layer of the transistor close to the substrate, the buffer layer comprising a first via hole and a second via hole exposing the second electrode;

[0012] The second conductive region of the driving transistor is connected to the second electrode through the first via hole, and the second conductive region of the sensing transistor is connected to the second electrode through the second via hole.

[0013] Optionally, the driving transistor further comprises: a light shielding layer disposed on a side of the buffer layer close to the substrate;

[0014] The second electrode is arranged on a side of the buffer layer close to the substrate, the orthographic projection of the second electrode on the substrate covers the orthographic projection of the light shielding layer on the substrate, and the surface of the light shielding layer close to the second electrode is completely in contact with the second electrode;

[0015] The light shielding layer is arranged on a side of the second electrode close to the substrate, or the second electrode is arranged on a side of the light shielding layer close to the substrate.

[0016] Optionally, the display substrate further comprises: a plurality of rows of gate lines and a plurality of columns of data lines arranged on the substrate; each sub-pixel is defined by the intersection of the gate line and the data line, and the sub-pixels correspond to the gate line and the data line one by one, respectively, and the gate line comprises: a first gate line and a second gate line,

[0017] The first gate line and the second gate line are arranged in the same layer as the gate electrode of the transistor, and the data line is arranged in the same layer as the source and drain electrodes of the transistor.

[0018] Optionally, for each sub-pixel, the first electrode is respectively connected to the first electrode of the switch transistor and the gate electrode of the drive transistor;

[0019] The gate electrode of the switch transistor is connected to the first gate line among the gate lines corresponding to the sub-pixel; the second electrode of the switch transistor is connected to the data line corresponding to the sub-pixel, and the gate electrode of the sensing transistor is connected to the second gate line among the gate lines corresponding to the sub-pixel.

[0020] Optionally, for each sub-pixel, the non-luminous region includes: a first non-luminous region and a second non-luminous region, wherein the first non-luminous region and the second non-luminous region are located at two sides of the luminous region and are arranged along an extending direction of the data line;

[0021] The sensing transistor and the second gate line are both located in the first non-luminescent region, and the switching transistor, the driving transistor and the first gate line are all located in the second non-luminescent region.

[0022] Optionally, the display substrate further comprises: power lines and sensing lines arranged in the same layer as the data lines, and each pixel comprises: four sub-pixels arranged along the extending direction of the gate lines, and each pixel corresponds to two columns of power lines and one column of sensing lines;

[0023] For each pixel, the sensing line corresponding to the pixel is located between the second sub-pixel and the third sub-pixel, a column of power lines corresponding to the pixel is located on a side of the first sub-pixel away from the second sub-pixel, and another column of power lines corresponding to the pixel is located on a side of the fourth sub-pixel away from the third sub-pixel;

[0024] The data line corresponding to the first sub-pixel is located on a side of the first sub-pixel close to the second sub-pixel; the data line corresponding to the second sub-pixel is located on a side of the second sub-pixel close to the first sub-pixel; the data line corresponding to the third sub-pixel is located on a side of the third sub-pixel close to the fourth sub-pixel, and the data line corresponding to the fourth sub-pixel is located on a side of the fourth sub-pixel close to the third sub-pixel;

[0025] The display substrate further comprises: a power connection line arranged in the same layer as the gate electrode of the transistor and a sensing connection line arranged in the same layer as the light shielding layer, each pixel corresponds to two power connection lines arranged along the extension direction of the gate line and two sensing connection lines arranged along the extension direction of the gate line; the power connection lines correspond to the power lines respectively; the power connection lines are connected to the corresponding power lines; and the two sensing connection lines are connected to the sensing lines;

[0026] The second electrode of the driving transistor of the second sub-pixel is connected to a power connection line;

[0027] The second electrode of the driving transistor of the third sub-pixel is connected to another power connection line;

[0028] The second electrode of the sensing transistor of the first sub-pixel is connected to a sensing connection line through the active layer of the sensing transistor;

[0029] The second electrode of the sensing transistor of the fourth sub-pixel is connected to another sensing connection line through the active layer of the sensing transistor.

[0030] Optionally, for each sub-pixel, the buffer layer is further provided with a third via hole, and the third via hole exposes the sensing connection line;

[0031] The first conductive region of the sensing transistor is connected to the sensing connection line through a third via hole.

[0032] Optionally, the display substrate further comprises: a gate insulating layer disposed between the gate electrode of the transistor and the active layer of the transistor, and an interlayer insulating layer disposed between the source and drain electrodes of the transistor and the active layer of the transistor;

[0033] The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrode of the transistor on the substrate.

[0034] Optionally, the interlayer insulating layer is provided with a via, the via is located in the second non-luminous area, and the via simultaneously exposes the gate electrode and the first electrode of the driving transistor; the first electrode of the switching transistor is connected to the gate electrode and the first electrode of the driving transistor through the via.

[0035] Optionally, the first electrode is made of the same material as the conductive region, and the conductive region includes the first conductive region or the second conductive region;

[0036] The first electrode is made of a material including a transparent metal oxide, and the second electrode is made of a transparent conductive material.

[0037] Optionally, each sub-pixel is further provided with a light-emitting element and a filter of the same color as the sub-pixel; the light-emitting element comprises: an anode, an organic light-emitting layer and a cathode arranged in sequence, the anode is connected to the first electrode of the sensing transistor, the anode is a transmission electrode, and the cathode is a reflection electrode;

[0038] The orthographic projection of the light-emitting element on the substrate overlaps with the light-emitting area, and the filter is located in the light-emitting area and is arranged near the light-emitting element. Base On one side, the orthographic projection of the anode on the substrate covers the orthographic projection of the filter on the substrate.

[0039] Optionally, the display substrate further comprises a passivation layer and a planarization layer arranged on a side of the source and drain electrodes of the transistor away from the substrate;

[0040] The passivation layer is arranged on a side of the filter close to the substrate, and the flat layer is arranged between the light emitting element and the filter; the passivation layer is provided with a fourth via hole exposing the first electrode of the sensing transistor, and the flat layer is provided with a fifth via hole exposing the fourth via hole;

[0041] The anode is connected to the first electrode of the sensing transistor through a fourth via hole and a fifth via hole;

[0042] The orthographic projection of the fifth via hole on the substrate does not completely overlap with the orthographic projection of the second via hole on the substrate.

[0043] In a second aspect, the present application also provides a display device, comprising the above-mentioned display substrate.

[0044] In a third aspect, the present application further provides a method for manufacturing a display substrate, which is used to manufacture the above-mentioned display substrate, and the method comprises:

[0045] providing a substrate;

[0046] A plurality of sub-pixels are formed on a substrate, each sub-pixel includes a light-emitting area and a non-light-emitting area, and a driving circuit is provided in each sub-pixel; the driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors include: a switch transistor, a driving transistor and a sensing transistor;

[0047] For each sub-pixel, the multiple transistors are located in a non-luminescent area, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on the substrate overlaps with the luminescent area, a first electrode of the storage capacitor is arranged in the same layer as an active layer of the multiple transistors, and in a different layer from source and drain electrodes of the multiple transistors, and a second electrode of the storage capacitor is located on a side of the first electrode close to the substrate;

[0048] The first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor.

[0049] Optionally, the display substrate further comprises: a gate line, a data line, a power line, and a sensing line, the gate line comprises: a first gate line and a second gate line, and the plurality of sub-pixels on the substrate comprises:

[0050] forming a light shielding layer and a second electrode on the substrate;

[0051] forming active layers and first electrodes of a plurality of transistors on the light shielding layer and the second electrode;

[0052] forming gate electrodes of the plurality of transistors, a first gate line, and a second gate line on the active layers and the first electrodes of the plurality of transistors;

[0053] Forming a data line, a power line, a sensing line and source and drain electrodes of a plurality of transistors on the gate electrode of the transistor, the first gate line and the second gate line;

[0054] A filter and a light emitting element are sequentially formed on the data line, the power line, the sensing line and the source and drain electrodes of a plurality of transistors.

[0055] Optionally, forming a light shielding layer and a second electrode on the substrate comprises:

[0056] A light shielding layer and a second electrode are sequentially formed on the substrate, or the second electrode and the light shielding layer are sequentially formed on the substrate, or the second electrode and the light shielding layer are simultaneously formed on the substrate.

[0057] Optionally, the simultaneously forming a second electrode and a light shielding layer on the substrate comprises:

[0058] Depositing a light-shielding film and a transparent conductive film on a substrate in sequence;

[0059] The second electrode and the light shielding layer are formed simultaneously by using a half-tone mask.

[0060] Optionally, forming an active layer and a first electrode of a plurality of transistors on the light shielding layer and the second electrode comprises:

[0061] A buffer layer including a first via hole, a second via hole and a third via hole is formed on the light shielding layer and the second electrode; the first via hole and the second via hole expose the second electrode, and the third via hole exposes the sensing connection line;

[0062] Forming active layers and first electrodes of a plurality of transistors on the buffer layer by the same process;

[0063] Forming filters and light-emitting elements in sequence on data lines, power lines, sensing lines and source and drain electrodes of multiple transistors includes:

[0064] Forming a passivation layer including a fourth via hole on the data line, the power line, the sensing line and the source and drain electrodes of the plurality of transistors; the fourth via hole exposing the first electrode of the sensing transistor;

[0065] A filter and a planar layer including a fifth via hole are sequentially formed on the passivation layer; the fifth via hole exposes a seventh via hole;

[0066] A light emitting element is formed on the planar layer.

[0067] The present application provides a display substrate and a manufacturing method thereof, and a display device, wherein the display substrate comprises: a substrate and a plurality of sub-pixels arranged on the substrate, each sub-pixel comprises a light-emitting area and a non-light-emitting area, and a driving circuit is arranged in each sub-pixel; the driving circuit comprises: a storage capacitor and a plurality of transistors; the plurality of transistors comprises: a switching transistor, a driving transistor and a sensing transistor; for each sub-pixel, the plurality of transistors are located in the non-light-emitting area, the storage capacitor is a transparent capacitor, and the positive projection of the storage capacitor on the substrate has an overlapping area with the light-emitting area, the first electrode of the storage capacitor is arranged in the same layer as the active layer of the plurality of transistors, and is arranged in a different layer from the source and drain electrodes of the plurality of transistors, and the second electrode of the storage capacitor is located on a side of the first electrode close to the substrate; the first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor. The present application arranges an overlapping area between the orthographic projection of a transparent storage capacitor on the substrate and the light-emitting area, and connects the first electrode of a part of the transistor active layer to the second electrode of the storage capacitor. This not only reduces the thickness and size of the via hole connecting the first electrode and the second electrode of the transistor in each sub-pixel in the related art, but also greatly reduces the area ratio of the storage capacitor in the non-light-emitting area in the related art, thereby reducing the area occupied by each sub-pixel and achieving a high PPI for the display substrate.

[0068] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0070] Figure 1 is the equivalent circuit diagram of the driving circuit;

[0071] Figure 2A A cross-sectional view of a display substrate provided in an embodiment of the present application;

[0072] Figure 2B Another cross-sectional view of a display substrate provided in an embodiment of the present application;

[0073] Figure 3 A top view of a display substrate provided in an embodiment of the present application;

[0074] Figure 4 Another top view of the display substrate provided in the embodiment of the present application;

[0075] Figure 5 Another schematic diagram of a local structure provided in an embodiment of the present application;

[0076] Figure 6 Another top view of the display substrate provided in the embodiment of the present application;

[0077] Figure 7 Another top view of the display substrate provided in the embodiment of the present application;

[0078] Figure 8 A flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0079] Figures 9A to 9H A schematic diagram of manufacturing a light shielding layer and a second electrode provided in an embodiment of the present application;

[0080] Fig.10 A schematic diagram of step 100 of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0081] Fig.11 A schematic diagram of step 200 of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0082] Fig.12 A schematic diagram of step 300 of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0083] Fig.13 A schematic diagram of step 400 of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0084] Fig.14 A schematic diagram of step 500 of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0085] Fig.15 A schematic diagram of step 600 of a method for manufacturing a display substrate provided in an embodiment of the present application;

[0086] Fig.16 A schematic diagram of step 700 of a method for manufacturing a display substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0087] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0088] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0089] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0090] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connecting" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0091] In this embodiment, the display substrate includes a plurality of sub-pixels, and each sub-pixel includes a driving circuit and a light-emitting element. Figure 1 The equivalent circuit diagram of the driving circuit is shown in FIG. 1 , which illustrates a 3T1C driving circuit. Figure 1 As shown, the driving circuit is electrically connected to the first gate line G1, the sensing line Sense, the power line VDD, the data line Data and the second gate line G2, and includes: a switching transistor T1, a driving transistor T2, a sensing transistor T3 and a storage capacitor Cst.

[0092] Specifically, the gate electrode of the switching transistor T1 in the driving circuit is connected to the first gate line G1, the first electrode of the switching transistor T1 is connected to the node N1, the second electrode of the switching transistor T1 is connected to the data line Data, the gate electrode of the driving transistor T2 is connected to the node N1, the first electrode of the driving transistor T2 is connected to the node N2, the second electrode of the driving transistor T2 is connected to the power line VDD, the gate electrode of the sensing transistor T3 is connected to the second gate line G2, the first electrode of the sensing transistor T3 is connected to the node N2, the second electrode of the sensing transistor T3 is connected to the sensing line Sense, the anode of the light-emitting element OLED is connected to the node N2, and the cathode of the light-emitting element OLED is connected to the low power line VSS, and is configured to emit light of corresponding brightness in response to the current of the first electrode of the driving transistor. When the driving circuit turns on the switching transistor T1 through the first gate line G1, the data voltage Vdata provided by the data line Data is stored in the storage capacitor Cst via the switching transistor T1, thereby controlling the driving transistor T2 to generate current to drive the organic light emitting diode OLED to emit light. In addition, the sensing transistor T3 can respond to the sensing timing to extract the threshold voltage Vth and mobility of the driving transistor T2. The storage capacitor Cst is used to maintain the voltage difference between the node N1 and the node N2 within a frame of light emission period.

[0093] The first electrode refers to the source electrode, and the second electrode refers to the drain electrode.

[0094] Some embodiments of the present application provide a display substrate, Figure 2A A side view of a display substrate provided in an embodiment of the present application, Figure 2B Another side view of the display substrate provided in the embodiment of the present application, as shown in FIG. Figure 2A and Figure 2B As shown, the display substrate provided by the embodiment of the present application includes: a substrate 10 and a plurality of sub-pixels arranged on the substrate 10, each sub-pixel includes a light-emitting area AA and a non-light-emitting area NA, and a driving circuit is arranged in each sub-pixel; the driving circuit includes: a storage capacitor Cst and a plurality of transistors; the plurality of transistors include: a switching transistor T1, a driving transistor T2 and a sensing transistor T3.

[0095] For each sub-pixel, multiple transistors are located in the non-luminous area NA, the storage capacitor Cst is a transparent capacitor, and the orthographic projection of the storage capacitor Cst on the substrate 10 has an overlapping area with the luminous area AA, the first electrode C1 of the storage capacitor Cst is arranged in the same layer as the active layer of the multiple transistors, and is arranged in a different layer from the source and drain electrodes of the multiple transistors, and the second electrode C2 of the storage capacitor Cst is located on the side of the first electrode C1 close to the substrate 10; the first electrode 23 of the driving transistor T2 is connected to the second electrode C2 through the active layer 21 of the driving transistor T2, and the first electrode 43 of the sensing transistor T3 is connected to the second electrode C2 through the active layer 41 of the sensing transistor T3.

[0096] Specifically, the sub-pixel array arrangement on the substrate needs to be explained as follows: Figure 2A and Figure 2B This is explained using a sub-pixel as an example. Figure 2A and Figure 2B It is a side view from different angles.

[0097] Optionally, the substrate 10 may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be but is not limited to one or more of glass and metal foil; the flexible substrate may be but is not limited to one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0098] Specifically, Figure 2A and Figure 2BAs shown, the switching transistor T1 in the embodiment of the present application includes: an active layer 31, a gate electrode 32, a first electrode 33 and a second electrode 34 arranged in sequence on a substrate 10, the driving transistor T2 includes: an active layer 21, a gate electrode 22, a first electrode 23 and a second electrode 24 arranged in sequence on the substrate 10, and the sensing transistor T3 includes: an active layer 41, a gate electrode 42, a first electrode 43 and a second electrode 44 arranged in sequence on the substrate 10.

[0099] Optionally, the display substrate provided in the embodiment of the present application is a bottom emission OLED display substrate.

[0100] The storage capacitor in the embodiment of the present application is a transparent capacitor, which does not affect the light emission effect of the display substrate and can ensure smooth light emission.

[0101] Specifically, each sub-pixel is further provided with a light-emitting element, and optionally, the light-emitting element is an OLED.

[0102] The display substrate provided by the embodiment of the present application comprises: a substrate and a plurality of sub-pixels arranged on the substrate, each sub-pixel comprises a light-emitting area and a non-light-emitting area, and a driving circuit is arranged in each sub-pixel; the driving circuit comprises: a storage capacitor and a plurality of transistors; the plurality of transistors comprises: a switching transistor, a driving transistor and a sensing transistor; for each sub-pixel, the plurality of transistors are located in the non-light-emitting area, the storage capacitor is a transparent capacitor, and the positive projection of the storage capacitor on the substrate overlaps with the light-emitting area, the first electrode of the storage capacitor is arranged in the same layer as the active layer of the plurality of transistors, and is arranged in a different layer from the source and drain electrodes of the plurality of transistors, and the second electrode of the storage capacitor is located on the side of the first electrode close to the substrate; the first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor. The present application arranges an overlapping area between the orthographic projection of a transparent storage capacitor on the substrate and the light-emitting area, and connects the first electrode of a part of the transistor active layer to the second electrode of the storage capacitor. This not only reduces the thickness and size of the via hole connecting the first electrode and the second electrode of the transistor in each sub-pixel in the related art, but also greatly reduces the area ratio of the storage capacitor in the non-light-emitting area in the related art while ensuring the aperture ratio, thereby reducing the area occupied by each sub-pixel and achieving a high PPI of the display substrate.

[0103] Alternatively, if Figure 2A and Figure 2B As shown, for each sub-pixel, the active layer of each transistor includes: a channel region A1, a first conductive region A2 and a second conductive region A3.

[0104] The first conductive region A2 and the second conductive region A3 are respectively arranged on both sides of the channel region A1, the second electrode of the transistor is connected to the first conductive region A2, and the first electrode of the transistor is connected to the second conductive region A3; the second conductive region A3 of the driving transistor T2 is connected to the second electrode C2; ​​the second conductive region A3 of the sensing transistor T3 is connected to the second electrode C2.

[0105] Specifically, for each transistor, an orthographic projection of the active layer of the transistor on the substrate and an orthographic projection of the gate electrode of the transistor on the substrate have an overlapping area.

[0106] Optionally, Figure 3 A top view of a display substrate provided in an embodiment of the present application, as shown in FIG. Figure 3 As shown, the display substrate provided in the embodiment of the present application further includes: a buffer layer 12 disposed on a side of the active layer of the transistor close to the substrate 10 , and the buffer layer 12 includes a first via hole V1 and a second via hole V2 exposing the second electrode C2 .

[0107] Specifically, the second conductive region A3 of the driving transistor T2 is connected to the second electrode C2 through the first via hole V1 , and the second conductive region A3 of the sensing transistor T3 is connected to the second electrode C2 through the second via hole V2 .

[0108] Alternatively, if Figure 2A and Figure 2B As shown, the driving transistor T2 provided in the embodiment of the present application further includes: a light shielding layer 11 arranged on a side of the buffer layer 12 close to the substrate 10 .

[0109] Specifically, the second electrode C2 is arranged on the side of the buffer layer 12 close to the substrate 10, the orthographic projection of the second electrode C2 on the substrate 10 covers the orthographic projection of the shading layer 11 on the substrate 10, and the surface of the shading layer 11 close to the second electrode C2 is completely in contact with the second electrode C2.

[0110] Optionally, the light shielding layer 11 is disposed on a side of the second electrode C2 close to the substrate 10, or the second electrode C2 is disposed on a side of the light shielding layer 11 close to the substrate 10. It should be noted that FIG. 2 is illustrated by taking the light shielding layer 11 disposed on a side of the second electrode C2 close to the substrate 10 as an example. When the second electrode C2 is disposed on a side of the light shielding layer 11 close to the substrate 10, the second conductive region A2 of the driving transistor T2 and the second conductive region A2 of the sensing transistor T3 are connected to the second electrode C2 through the light shielding layer 11.

[0111] In the embodiment of the present application, the surface of the light-shielding layer 11 close to the second electrode C2 is completely in contact with the second electrode C2, thereby avoiding the need to provide an insulating layer between the light-shielding layer and the second electrode. This not only reduces the number of layers and thickness of the display substrate, but also reduces the number of times the mask is used, simplifies the manufacturing process, and reduces the manufacturing cost of the display substrate.

[0112] Specifically, the orthographic projection of the light shielding layer 11 on the substrate 10 covers the orthographic projection of the channel region A1 of the active layer 31 of the driving transistor T2 on the substrate 10 .

[0113] Optionally, the light shielding layer 11 is made of metal, such as silver, aluminum or other metals, which is not limited in the embodiment of the present application.

[0114] Optionally, Figure 4 A top view of a display substrate provided in an embodiment of the present application, such as Figure 4 As shown, the display substrate provided by the embodiment of the present application further includes: a plurality of rows of gate lines and a plurality of columns of data lines arranged on the substrate; each sub-pixel is defined by the intersection of the gate line and the data line, and the sub-pixels correspond to the gate line and the data line one by one, respectively, and the gate line includes: a first gate line G1 and a second gate line G2. It should be noted that Figure 4 The following is an example of four sub-pixels. Figure 2A yes Figure 4 The cross-sectional view along the AA direction, Figure 2B yes Figure 4 Cross-sectional view along BB direction.

[0115] Specifically, the first gate line G1 and the second gate line G2 are disposed at the same layer as the gate electrode of the transistor, and the data line Data is disposed at the same layer as the source and drain electrodes of the transistor.

[0116] Optionally, for each sub-pixel, the first electrode C1 is respectively connected to the first electrode 33 of the switching transistor T1 and the gate electrode 22 of the driving transistor T2, and the second electrode C2 is respectively connected to the first electrode 23 of the driving transistor T2 and the first electrode 43 of the sensing transistor T3; the gate electrode 22 of the switching transistor T1 is connected to the first gate line G1 among the gate lines corresponding to the sub-pixel; the second electrode 34 of the switching transistor T1 is connected to the data line Data corresponding to the sub-pixel, and the gate electrode of the sensing transistor T3 is connected to the second gate line G2 among the gate lines corresponding to the sub-pixel.

[0117] Alternatively, if Figure 4 As shown, for each sub-pixel, the non-luminous region includes: a first non-luminous region and a second non-luminous region, the first non-luminous region and the second non-luminous region are located on both sides of the luminous region AA and are arranged along the extension direction of the data line Data.

[0118] Specifically, the sensing transistor T3 and the second gate line G2 are both located in the first non-luminescent region, and the switching transistor T1 , the driving transistor T2 and the first gate line G1 are all located in the second non-luminescent region.

[0119] Alternatively, if Figure 3 As shown, the display substrate further includes: a power line VDD and a sensing line Sense arranged in the same layer as the data line Data, and each pixel includes: four sub-pixels arranged along the extension direction of the gate line, and each pixel corresponds to two columns of power lines and one column of sensing lines.

[0120] Specifically, the pixel structures of the second sub-pixel and the third sub-pixel are symmetrically arranged, and the first sub-pixel and the fourth sub-pixel are symmetrically arranged.

[0121] For each pixel, the sensing line Sense corresponding to the pixel is located between the second sub-pixel P2 and the third sub-pixel P3, a column of power lines VDD corresponding to the pixel is located on the side of the first sub-pixel P1 away from the second sub-pixel P2, and another column of power lines VDD corresponding to the pixel is located on the side of the fourth sub-pixel P4 away from the third sub-pixel P3.

[0122] The data line Data corresponding to the first sub-pixel P1 is located on the side of the first sub-pixel P1 close to the second sub-pixel P2; the data line corresponding to the second sub-pixel P2 is located on the side of the second sub-pixel P2 close to the first sub-pixel P1; the data line corresponding to the third sub-pixel P3 is located on the side of the third sub-pixel P3 close to the fourth sub-pixel P4, and the data line corresponding to the fourth sub-pixel P4 is located on the side of the fourth sub-pixel P4 close to the third sub-pixel P3.

[0123] Specifically, Figure 4 As shown, the display substrate provided by the embodiment of the present application also includes: a power connection line VL arranged in the same layer as the gate electrode of the transistor and a sensing connection line SL arranged in the same layer as the light shielding layer 11, each pixel corresponds to two power connection lines arranged along the extension direction of the gate line and two sensing connection lines SL arranged along the extension direction of the gate line; the power connection lines VL correspond to the power lines VDD respectively; the power connection lines VL are connected to the corresponding power lines; and the two sensing connection lines SL are connected to the sensing lines Sense.

[0124] Specifically, the second electrode of the driving transistor of the second sub-pixel P2 is connected to a power connection line VL; the second electrode of the driving transistor of the third sub-pixel P3 is connected to another power connection line VL; the second electrode of the sensing transistor of the first sub-pixel P1 is connected to a sensing connection line SL through the active layer of the sensing transistor; the second electrode of the sensing transistor of the fourth sub-pixel P4 is connected to another sensing connection line SL through the active layer of the sensing transistor.

[0125] Optionally, the sensing connection line SL may be a single-layer structure or a double-layer structure. When the sensing connection line SL is a single-layer structure, the sensing connection line is disposed in the same layer as the light shielding layer or the second electrode. When the sensing connection line SL is a double-layer structure, the first layer of the sensing connection line is disposed in the same layer as the light shielding layer, and the second layer is disposed in the same layer as the second electrode. It should be noted that: Figure 3 The description is made by taking the case where the sensing connection line and the light shielding layer are arranged on the same layer as an example.

[0126] Alternatively, if Figure 2A and Figure 2B As shown, the display substrate provided in the embodiment of the present application further includes: a gate insulating layer 13 arranged between the gate electrode of the transistor and the active layer of the transistor, and an interlayer insulating layer 14 arranged between the source and drain electrodes of the transistor and the active layer of the transistor.

[0127] The orthographic projection of the gate insulating layer 13 on the substrate 10 coincides with the orthographic projection of the gate electrode of the transistor on the substrate 10 .

[0128] Optionally, via holes exposing the conductive region of the active layer are provided on the interlayer insulating layer 14 , and the source and drain electrodes of the plurality of transistors are connected to the conductive region of the active layer through the via holes.

[0129] Optionally, the buffer layer 12 , the gate insulating layer 13 and the interlayer insulating layer 14 are made of silicon oxide, silicon nitride or a composite of silicon oxide and silicon nitride, which is not limited in any way in the embodiments of the present application.

[0130] Alternatively, if Figure 3 As shown, for each sub-pixel, the buffer layer 13 is further provided with a third via hole V3 , and the third via hole exposes the sensing connection line SL; the first conductive region of the sensing transistor T3 is connected to the sensing connection line SL through the third via hole V3 .

[0131] Optionally, Figure 5 A schematic diagram of a partial structure replacement provided in an embodiment of the present application; Figure 5 As shown, the interlayer insulating layer 14 in the display substrate provided in the embodiment of the present application includes a via V, which is located on the second side of the light-emitting area. The via V simultaneously exposes the gate electrode 22 and the first electrode C1 of the driving transistor; the first electrode 33 of the switching transistor T1 is connected to the gate electrode 22 and the first electrode C1 of the driving transistor T2 through the via V.

[0132] Optionally, the via hole V is a semi-buried hole, and the via hole V on the interlayer insulating layer can be made by using a half-tone mask.

[0133] Optionally, the first electrode C1 is made of the same material as the conductive region, and the conductive region includes the first conductive region or the second conductive region.

[0134] Optionally, the first electrode C1 is made of a conductive active layer, including a transparent metal oxide, wherein the transparent metal oxide includes indium gallium zinc oxide (IGZO for short), etc., and the embodiment of the present application does not impose any limitation on this.

[0135] Optionally, the second electrode C2 is made of a transparent conductive material, and the transparent conductive material includes indium tin oxide (ITO for short), zinc tin oxide, etc., which is not limited in the embodiment of the present application.

[0136] Optionally, Figure 6 This is another top view of the display substrate provided in the embodiment of the present application. Figure 7 Another top view of the display substrate provided in the embodiment of the present application is shown in FIG. Figure 6 and Figure 7 As shown, each sub-pixel is also provided with a light-emitting element and a filter 50 of the same color as the sub-pixel; the light-emitting element includes: an anode 61, an organic light-emitting layer 62 and a cathode 63 arranged in sequence, the anode 61 is connected to the first electrode 44 of the sensing transistor T3, the anode 61 is a transmissive electrode, and the cathode 63 is a reflective electrode.

[0137] Optionally, the anode 61 may be made of a transparent conductive material, such as indium tin oxide ITO, zinc tin oxide, etc., which is not limited in any way in the embodiment of the present application.

[0138] Optionally, the cathode 63 is made of metal, such as silver, aluminum, etc., which is not limited in the embodiment of the present application.

[0139] Specifically, the orthographic projection of the light-emitting element on the substrate 10 overlaps with the light-emitting area AA, the filter 50 is located in the light-emitting area AA and is arranged on the side of the light-emitting element close to the substrate 10, and the orthographic projection of the anode 61 on the substrate 10 covers the orthographic projection of the filter 50 on the substrate 10.

[0140] Alternatively, if Figure 2A and Figure 2B As shown, the display substrate provided by the embodiment of the present application also includes: a passivation layer 15 arranged on the side of the source and drain electrodes of the transistor away from the substrate 10, a planarization layer 16 arranged between the anode 61 and the filter 50, and a pixel defining layer 17 arranged on the side of the planarization layer 16 away from the substrate 10 for defining a sub-pixel area.

[0141] Specifically, Figure 6As shown, the passivation layer 15 is arranged on the side of the filter 50 close to the substrate 10, and the flat layer 16 is arranged between the light-emitting element and the filter 50; the passivation layer 16 is provided with a fourth via hole V4 exposing the first electrode 43 of the sensing transistor T3, and the flat layer 16 is provided with a fifth via hole V5 exposing the fourth via hole V4.

[0142] The anode 61 is connected to the first electrode 43 of the sensing transistor T3 through the fourth via hole V4 and the fifth via hole V5 ; the orthographic projection of the fifth via hole V5 on the substrate 10 does not completely overlap with the orthographic projection of the second via hole V2 on the substrate 10 .

[0143] Alternatively, if Figure 2A and Figure 2B As shown, the display substrate provided in the embodiment of the present application further includes: a support portion 70 disposed on a side of the light emitting element away from the substrate 10 , and a cover plate 80 disposed on a side of the support portion 70 away from the substrate 10 .

[0144] Specifically, the cover plate 80 is used to protect the light emitting element. Optionally, the cover plate 80 may be a glass cover plate.

[0145] Based on the same inventive concept, an embodiment of the present application further provides a display device, including a display substrate.

[0146] Specifically, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as limitations on the present invention. The implementation of the display device can refer to the above-mentioned embodiment of the embedded touch screen, and the repeated parts will not be described in detail.

[0147] Among them, the display substrate is the display substrate provided by the aforementioned embodiment, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0148] Based on the same inventive concept, some embodiments of the present application further provide a method for manufacturing a display substrate, which is used to manufacture a display substrate. Figure 8 A flow chart of a method for manufacturing a display substrate provided in an embodiment of the present application, such as Figure 8 As shown, the method for manufacturing a display substrate provided in an embodiment of the present application specifically includes the following steps:

[0149] Step S1, providing a substrate.

[0150] Optionally, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be but not limited to one or more of glass and metal foil; the flexible substrate can be but not limited to one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0151] Step S2: forming a plurality of sub-pixels on a substrate.

[0152] Specifically, regarding the arrangement of the sub-pixel array on the substrate, it should be noted that FIG. 2 is illustrated by taking one sub-pixel as an example.

[0153] Specifically, each sub-pixel includes a light-emitting area and a non-light-emitting area, and a driving circuit is provided in each sub-pixel; the driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors include: a switching transistor, a driving transistor and a sensing transistor.

[0154] For each sub-pixel, multiple transistors are located in the non-luminous area, the storage capacitor is a transparent capacitor, and the positive projection of the storage capacitor on the substrate has an overlapping area with the luminous area, the first electrode of the storage capacitor is arranged in the same layer as the active layer of the multiple transistors, and the second electrode of the storage capacitor is located on the side of the first electrode close to the substrate.

[0155] The first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor.

[0156] Among them, the display substrate is the display substrate provided by the aforementioned embodiment, and its implementation principle and implementation effect are similar, which will not be repeated here.

[0157] Optionally, the display substrate further includes: gate lines, data lines, power lines and sensing lines, the gate lines include: first gate lines and second gate lines, and step S2 specifically includes: forming a light-shielding layer and a second electrode on the substrate; forming an active layer and a first electrode of multiple transistors on the light-shielding layer and the second electrode; forming gate electrodes, a first gate line and a second gate line of multiple transistors on the active layer and the first electrode of the multiple transistors; forming data lines, power lines, sensing lines and source-drain electrodes of multiple transistors on the gate electrodes, the first gate lines and the second gate lines of the transistors; and forming filters and light-emitting elements in sequence on the data lines, power lines, sensing lines and source-drain electrodes of multiple transistors.

[0158] Optionally, forming the light shielding layer and the second electrode on the substrate includes: sequentially forming the light shielding layer and the second electrode on the substrate, or sequentially forming the second electrode and the light shielding layer on the substrate, or simultaneously forming the second electrode and the light shielding layer on the substrate.

[0159] Specifically, sequentially forming the light shielding layer and the second electrode on the substrate includes: forming the light shielding layer on the substrate using a first mask, and forming the second electrode on the light shielding layer using a second mask.

[0160] Specifically, sequentially forming the second electrode and the light shielding layer on the substrate includes: forming the second electrode on the substrate by a patterning process using a second mask, and forming the light shielding layer on the second electrode using a first mask.

[0161] Specifically, forming the second electrode and the light shielding layer on the substrate simultaneously includes: depositing a light shielding film and a transparent conductive film on the substrate in sequence, and using a half-tone mask to simultaneously form the second electrode and the light shielding layer.

[0162] Among them, the patterning process includes: photoresist coating, exposure, development, etching and photoresist stripping processes.

[0163] Specifically, forming an active layer and a first electrode of multiple transistors on a light-shielding layer and a second electrode includes: forming a buffer layer including a first via, a second via, and a third via on the light-shielding layer and the second electrode; the first via and the second via expose the second electrode, and the third via exposes the sensing connection line; and forming an active layer and a first electrode of multiple transistors on the buffer layer using the same process.

[0164] Specifically, forming a filter and a light-emitting element in sequence on a data line, a power line, a sensing line and source-drain electrodes of a plurality of transistors includes: forming a passivation layer including a fourth via hole on the data line, the power line, the sensing line and source-drain electrodes of a plurality of transistors; the fourth via hole exposes the first electrode of the sensing transistor; forming a filter and a planar layer including a fifth via hole in sequence on the passivation layer; the fifth via hole exposes the seventh via hole; and forming a light-emitting element on the planar layer.

[0165] In the following, the light shielding layer is disposed on the side of the second electrode close to the substrate as an example. Figures 9A to 9F The manufacturing process of the light shielding layer and the second electrode is further described as follows:

[0166] Step 110, depositing a light shielding film 110 on the substrate, coating a photoresist 101 on the light shielding film 110, and exposing the photoresist through a first mask M1, as shown in the following example. Fig.9A shown.

[0167] Step 120: Develop the photoresist 101, as follows: Fig. 9B shown.

[0168] Step 130, etching away the light shielding film not covered by the photoresist 101, such as Fig. 9C shown.

[0169] Step 140: stripping the photoresist 101 to form a light shielding layer 11, as shown in the following example: Fig.9D shown.

[0170] Step 150: depositing a transparent conductive film 120 on the light shielding layer 11, coating a photoresist 101 on the transparent conductive film 120, and exposing the photoresist through a second mask M2, as shown in the following example. Fig.9E shown.

[0171] Step 160: Develop the photoresist 101, as follows: Fig.9F shown.

[0172] Step 170, etching away the transparent conductive film not covered by the photoresist 101, such as Figure 9G shown.

[0173] Step 180: stripping the photoresist 101 to form a second electrode C2. Figure 9H shown.

[0174] Optionally, forming an active layer and a first electrode of multiple transistors on the light-shielding layer and the second electrode includes: forming a buffer layer including a first via, a second via and a third via on the light-shielding layer and the second electrode; and forming an active layer and a first electrode of multiple transistors on the buffer layer using the same process.

[0175] Specifically, the first via hole and the second via hole expose the second electrode, and the third via hole exposes the sensing connection line.

[0176] Taking four sub-pixels, the sensing connection line is a single-layer structure, and is arranged in the same layer as the light shielding layer, and the light shielding layer is arranged on the side of the second electrode close to the substrate as an example, the following is combined with Figure 10 to Figure 16 The manufacturing method of the display substrate provided in the embodiment of the present application is further described as follows:

[0177] Step 100: forming a light shielding layer 11 and a sensing connection line SL on a substrate 10, as follows: Fig.10 shown.

[0178] Step 200: forming a second electrode C2 and a buffer layer (not shown) on the light shielding layer 11 and the sensing connection line SL in sequence, as follows: Fig.11 shown.

[0179] The buffer layer is provided with a first via hole V1 and a second via hole V2 exposing the second electrode C2, and a third via hole V3 exposing the sensing connection line SL.

[0180] Step 300: forming a first electrode C1, an active layer 31 of a switch transistor, an active layer 21 of a drive transistor, and an active layer 41 of a sensing transistor on the buffer layer, as follows: Fig.12 shown.

[0181] Step 400: Form a gate insulating layer on the active layer 31 of the switch transistor, the active layer 21 of the drive transistor and the active layer 41 of the sensing transistor, and form a gate electrode 32 of the switch transistor, a gate electrode 22 of the drive transistor and the active layer 42 of the sensing transistor, a first gate line G1, a second gate line G2 and a power connection line VL on the gate insulating layer. Fig.13 shown.

[0182] Step 500, forming an interlayer insulating layer on the gate electrode of the transistor, the first gate line, the second gate line and the power connection line, forming a data line Data, a power line VDD, a sensing line Sense, a first electrode 33 and a second electrode 34 of the switch transistor, a first electrode 23 and a second electrode 24 of the drive transistor, and a first electrode 43 and a second electrode 44 of the sensing transistor on the interlayer insulating layer, specifically as follows Fig.14 shown.

[0183] Step 600: forming a passivation layer including a fourth via hole V4 on the data line, the power line, the sensing line and the source and drain electrodes of the plurality of transistors, forming a filter 50 on the passivation layer, and forming a flat layer including a fifth via hole V5 on the filter 50, as shown in FIG. Fig.15 shown.

[0184] Step 700: forming an anode 61 on the flat layer, as follows: Fig.16 shown.

[0185] Step 800: forming a pixel defining layer, an organic light emitting layer and a cathode in sequence on the anode, and disposing a support portion and a cover plate in sequence on the cathode.

[0186] The drawings of the embodiments of the present invention only involve the structures involved in the embodiments of the present invention, and other structures may refer to the general design.

[0187] For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0188] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: include: A substrate and a plurality of sub-pixels arranged on the substrate, each sub-pixel comprising a light-emitting region and a non-light-emitting region, and each sub-pixel being provided with a driving circuit; The driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors include: a switch transistor, a driving transistor and a sensing transistor; For each sub-pixel, the multiple transistors are located in a non-luminescent area, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on the substrate overlaps with the luminescent area, a first electrode of the storage capacitor is arranged in the same layer as an active layer of the multiple transistors, and in a different layer from source and drain electrodes of the multiple transistors, and a second electrode of the storage capacitor is located on a side of the first electrode close to the substrate; The first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor; For each sub-pixel, the first electrode is connected to the first electrode of the switch transistor and the gate electrode of the drive transistor respectively.

2. The display substrate according to claim 1, characterized in that: For each sub-pixel, the active layer of each transistor includes: a channel region, a first conductive region, and a second conductive region; The first conductive region and the second conductive region are respectively arranged at two sides of the channel region, the second electrode of the transistor is connected to the first conductive region, and the first electrode of the transistor is connected to the second conductive region; The second conductive region of the driving transistor is connected to the second electrode; the second conductive region of the sensing transistor is connected to the second electrode.

3. The display substrate according to claim 2, characterized in that: The display substrate further comprises: a buffer layer disposed on a side of the active layer of the transistor close to the substrate, the buffer layer comprising a first via hole and a second via hole exposing the second electrode; The second conductive region of the driving transistor is connected to the second electrode through the first via hole, and the second conductive region of the sensing transistor is connected to the second electrode through the second via hole.

4. The display substrate according to claim 3, characterized in that: The driving transistor further includes: a light shielding layer disposed on a side of the buffer layer close to the substrate; The second electrode is arranged on a side of the buffer layer close to the substrate, the orthographic projection of the second electrode on the substrate covers the orthographic projection of the light shielding layer on the substrate, and the surface of the light shielding layer close to the second electrode is completely in contact with the second electrode; The light shielding layer is arranged on a side of the second electrode close to the substrate, or the second electrode is arranged on a side of the light shielding layer close to the substrate.

5. The display substrate according to claim 4, characterized in that: The display substrate further comprises: a plurality of rows of gate lines and a plurality of columns of data lines arranged on the substrate; each sub-pixel is defined by the intersection of the gate line and the data line, and the sub-pixels correspond to the gate line and the data line one by one, respectively, and the gate line comprises: a first gate line and a second gate line, The first gate line and the second gate line are arranged in the same layer as the gate electrode of the transistor, and the data line is arranged in the same layer as the source and drain electrodes of the transistor.

6. The display substrate according to claim 5, characterized in that: The gate electrode of the switch transistor is connected to the first gate line among the gate lines corresponding to the sub-pixel; the second electrode of the switch transistor is connected to the data line corresponding to the sub-pixel, and the gate electrode of the sensing transistor is connected to the second gate line among the gate lines corresponding to the sub-pixel.

7. The display substrate according to claim 6, characterized in that: For each sub-pixel, the non-luminous region includes: a first non-luminous region and a second non-luminous region, wherein the first non-luminous region and the second non-luminous region are located at two sides of the luminous region and are arranged along the extending direction of the data line; The sensing transistor and the second gate line are both located in the first non-luminescent region, and the switching transistor, the driving transistor and the first gate line are all located in the second non-luminescent region.

8. The display substrate according to claim 5, characterized in that: The display substrate further comprises: power lines and sensing lines arranged in the same layer as the data lines, each pixel comprises: a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel arranged along the extension direction of the gate line, and each pixel corresponds to two columns of power lines and one column of sensing lines; For each pixel, the sensing line corresponding to the pixel is located between the second sub-pixel and the third sub-pixel, a column of power lines corresponding to the pixel is located on a side of the first sub-pixel away from the second sub-pixel, and another column of power lines corresponding to the pixel is located on a side of the fourth sub-pixel away from the third sub-pixel; The data line corresponding to the first sub-pixel is located on a side of the first sub-pixel close to the second sub-pixel; the data line corresponding to the second sub-pixel is located on a side of the second sub-pixel close to the first sub-pixel; the data line corresponding to the third sub-pixel is located on a side of the third sub-pixel close to the fourth sub-pixel, and the data line corresponding to the fourth sub-pixel is located on a side of the fourth sub-pixel close to the third sub-pixel; The display substrate further comprises: a power connection line arranged in the same layer as the gate electrode of the transistor and a sensing connection line arranged in the same layer as the light shielding layer, each pixel corresponds to two power connection lines arranged along the extension direction of the gate line and two sensing connection lines arranged along the extension direction of the gate line; the power connection lines correspond to the power lines respectively; the power connection lines are connected to the corresponding power lines; and the two sensing connection lines are connected to the sensing lines; The second electrode of the driving transistor of the second sub-pixel is connected to a power connection line; The second electrode of the driving transistor of the third sub-pixel is connected to another power connection line; The second electrode of the sensing transistor of the first sub-pixel is connected to a sensing connection line through the active layer of the sensing transistor; The second electrode of the sensing transistor of the fourth sub-pixel is connected to another sensing connection line through the active layer of the sensing transistor.

9. The display substrate according to claim 8, characterized in that: The buffer layer is further provided with a third via hole, and the third via hole exposes the sensing connection line; The first conductive region of the sensing transistor is connected to the sensing connection line through a third via hole.

10. The display substrate according to claim 7, characterized in that: The display substrate further includes: a gate insulating layer disposed between a gate electrode of the transistor and an active layer of the transistor, and an interlayer insulating layer disposed between a source-drain electrode of the transistor and the active layer of the transistor; The orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrode of the transistor on the substrate.

11. The display substrate according to claim 10, characterized in that: The interlayer insulating layer is provided with a via hole, the via hole is located in the second non-luminous area, and the via hole simultaneously exposes the gate electrode and the first electrode of the driving transistor; the first electrode of the switching transistor is connected to the gate electrode and the first electrode of the driving transistor through the via hole.

12. The display substrate according to claim 2, characterized in that: The first electrode is made of the same material as the conductive region, and the conductive region includes the first conductive region or the second conductive region; The first electrode is made of a material including a transparent metal oxide, and the second electrode is made of a transparent conductive material.

13. The display substrate according to claim 3, characterized in that: Each sub-pixel is also provided with a light-emitting element and a filter of the same color as the sub-pixel; the light-emitting element comprises: an anode, an organic light-emitting layer and a cathode arranged in sequence, the anode is connected to the first electrode of the sensing transistor, the anode is a transmission electrode, and the cathode is a reflection electrode; The orthographic projection of the light-emitting element on the substrate overlaps with the light-emitting area. The filter is located in the light-emitting area and is arranged on the side of the light-emitting element close to the substrate. The orthographic projection of the anode on the substrate covers the orthographic projection of the filter on the substrate.

14. The display substrate according to claim 13, characterized in that: The display substrate further comprises a passivation layer and a planarization layer arranged on a side of the source and drain electrodes of the transistor away from the substrate; The passivation layer is arranged on a side of the filter close to the substrate, and the flat layer is arranged between the light emitting element and the filter; the passivation layer is provided with a fourth via hole exposing the first electrode of the sensing transistor, and the flat layer is provided with a fifth via hole exposing the fourth via hole; The anode is connected to the first electrode of the sensing transistor through a fourth via hole and a fifth via hole; The orthographic projection of the fifth via hole on the substrate does not completely overlap with the orthographic projection of the second via hole on the substrate.

15. A display device, characterized in that: It comprises the display substrate as claimed in any one of claims 1 to 14.

16. A method for manufacturing a display substrate, characterized in that: For manufacturing the display substrate according to any one of claims 1 to 14, the method comprises: providing a substrate; A plurality of sub-pixels are formed on a substrate, each sub-pixel includes a light-emitting area and a non-light-emitting area, and a driving circuit is provided in each sub-pixel; the driving circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors include: a switch transistor, a driving transistor and a sensing transistor; For each sub-pixel, the multiple transistors are located in a non-luminescent area, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on the substrate overlaps with the luminescent area, a first electrode of the storage capacitor is arranged in the same layer as an active layer of the multiple transistors, and in a different layer from source and drain electrodes of the multiple transistors, and a second electrode of the storage capacitor is located on a side of the first electrode close to the substrate; The first electrode of the driving transistor is connected to the second electrode through the active layer of the driving transistor, and the first electrode of the sensing transistor is connected to the second electrode through the active layer of the sensing transistor.

17. The method according to claim 16, characterized in that The display substrate further comprises: a gate line, a data line, a power line, and a sensing line, the gate line comprises: a first gate line and a second gate line, and the plurality of sub-pixels on the substrate comprises: forming a light shielding layer and a second electrode on the substrate; forming active layers and first electrodes of a plurality of transistors on the light shielding layer and the second electrode; forming gate electrodes of the plurality of transistors, a first gate line, and a second gate line on the active layers and the first electrodes of the plurality of transistors; Forming a data line, a power line, a sensing line and source and drain electrodes of a plurality of transistors on the gate electrode of the transistor, the first gate line and the second gate line; A filter and a light emitting element are sequentially formed on the data line, the power line, the sensing line and the source and drain electrodes of a plurality of transistors.

18. The method according to claim 17, characterized in that The step of forming a light shielding layer and a second electrode on the substrate comprises: A light shielding layer and a second electrode are sequentially formed on the substrate, or the second electrode and the light shielding layer are sequentially formed on the substrate, or the second electrode and the light shielding layer are simultaneously formed on the substrate.

19. The method according to claim 18, characterized in that The step of simultaneously forming a second electrode and a light shielding layer on the substrate comprises: Depositing a light-shielding film and a transparent conductive film on a substrate in sequence; The second electrode and the light shielding layer are formed simultaneously by using a half-tone mask.

20. The method according to claim 17, characterized in that The method of forming an active layer and a first electrode of a plurality of transistors on the light shielding layer and the second electrode comprises: A buffer layer including a first via hole, a second via hole and a third via hole is formed on the light shielding layer and the second electrode; the first via hole and the second via hole expose the second electrode, and the third via hole exposes the sensing connection line; Forming active layers and first electrodes of a plurality of transistors on the buffer layer by the same process; Forming filters and light-emitting elements in sequence on data lines, power lines, sensing lines and source and drain electrodes of multiple transistors includes: Forming a passivation layer including a fourth via hole on the data line, the power line, the sensing line and the source and drain electrodes of the plurality of transistors; the fourth via hole exposing the first electrode of the sensing transistor; A filter and a planar layer including a fifth via hole are sequentially formed on the passivation layer; the fifth via hole exposes a seventh via hole; A light emitting element is formed on the planar layer.

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