Laterally diffused metal oxide semiconductor (LDMOS) transistor

Abstract

The present invention is entitled "Laterally Diffused Metal Oxide Semiconductor Transistor". In general aspects, a laterally diffused metal oxide semiconductor (LDMOS) transistor may include: a substrate of a first conductivity type; a buried well region of a second conductivity type disposed in the substrate; a body region of the first conductivity type disposed on the buried well region, a drift region of the second conductivity type disposed in the body region, a drain implant of the second conductivity type disposed in the drift region; a source implant of the second conductivity type disposed in the body region; and a gate structure disposed on the drift region. The gate structure may include: a field plate including a RESURF dielectric layer; a gate dielectric layer; and a gate electrode disposed on the field plate and the gate dielectric layer. The LDMOS transistor may also include a drain contact extending through the field plate and defining an ohmic contact with the drain implant.

Description

Technical Field

[0001] The present description relates to laterally diffused metal oxide semiconductor (LDMOS) transistor devices and associated fabrication methods. Background Art

[0002] Producing laterally diffused metal oxide semiconductors (LDMOS), such as low voltage LDMOS transistors, presents a number of challenges. For example, it is desirable to reduce the cell pitch of LDMOS for cost and performance considerations. However, as the cell pitch decreases, producing LDMOS transistors with small cell pitches may result in an increase in the gate charge (Qg) and associated figure of merit (FoMv (e.g., drain to source on-resistance multiplied by Qg) of the transistor. Such increases in Qg and FoM are undesirable and may render such devices unsuitable for certain applications, such as power converter applications. In addition, current methods for reducing QD may also have disadvantages, such as performing etching operations that may result in a reduction in shallow trench isolation (STI) regions in other device type areas. For example, such loss of STI may result in increased leakage, such as in CMOS devices produced along with LDMOS devices (transistors) in hybrid semiconductor manufacturing processes (e.g., bipolar, complementary MOS (CMOS), and DMOS (BCD) semiconductor process platforms). Summary of the invention

[0003] In general aspects, a lateral diffused metal oxide semiconductor (LDMOS) transistor may include a substrate of a first conductivity type and a buried well region of a second conductivity type. The second conductivity type may be opposite to the first conductivity type. The LDMOS transistor may also include a body region of the first conductivity type, wherein the body region may be disposed on the buried well region. The LDMOS transistor may also include a drift region of the second conductivity type, wherein the drift region is disposed in the body region. The LDMOS transistor may also include a drain implant of the second conductivity type, wherein the drain implant may be disposed in the drift region. The LDMOS transistor may also include a source implant of the second conductivity type, wherein the source implant may be disposed in the body region. The LDMOS transistor may also include a gate structure disposed on the drift region. The gate structure may include: a field plate including a RESURF dielectric layer, a gate dielectric layer, and a gate electrode disposed on the field plate and the gate dielectric layer. The LDMOS transistor may also include a drain contact extending through the field plate and defining an ohmic contact with the drain implant. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a diagram showing a cross-sectional view of a laterally diffused metal oxide semiconductor (LDMOS) transistor with a RESURF dielectric layer field plate.

[0005] Figure 2 is a graph showing the gate charge of an LDMOS transistor with a RESURF dielectric layer field plate compared to the gate charge of a current LDMOS with a flat gate and field plate.

[0006] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A and 14B is a diagram showing a method for producing an LDMOS transistor (such as Figure 1 A series of cross-sectional views of operations of a semiconductor manufacturing process for an embodiment of an LDMOS transistor).

[0007] Fig.15 is shown to be usable to implement Figures 3 to 14B A flow chart of a method of a semiconductor manufacturing process is shown in FIG.

[0008] The same reference numerals in the various drawings indicate the same and / or similar elements. The elements shown in the various drawings are shown by way of illustration and may not necessarily be drawn to scale. In addition, the scales of the various drawings may differ from one another, depending at least in part on the specific views shown.

[0009] Reference characters in the various figures are provided for purposes of illustration and discussion. Reference characters for the same elements may not be repeated for similar elements in the same view. In addition, reference characters shown for a given element in one view may be omitted for that element in a related view. For example, reference characters for a given element shown in different views may not necessarily be discussed with respect to each of those views, or may, in some cases, be referenced with different reference characters. DETAILED DESCRIPTION

[0010] The present disclosure relates to laterally diffused metal oxide semiconductor (LDMOS) transistors (LDMOS devices) and associated methods of manufacture. The LDMOS devices described herein can be implemented with cell pitches comparable to current devices and can have reduced gate charge compared to those devices. Such gate charge reduction can be achieved through the implementation of one or more RESURF dielectric (RESURF oxide) field plates that are disposed above (above, over, vertically aligned with, etc.) an accumulation region of the LDMOS device or LDMOS segment (e.g., for each segment of the associated LDMOS device).

[0011] In some embodiments, the devices and processing methods described herein can be implemented using non-epitaxial processes (e.g., semiconductor manufacturing processes that do not include the formation of epitaxial semiconductor layers). The methods described herein can be used to produce fully isolated LDMOS devices. For example, in some embodiments, the LDMOS devices described herein can be isolated from other types of devices (such as bipolar devices and / or complementary MOS (CMOS) devices that can be generated using hybrid semiconductor manufacturing processes (on the same semiconductor die) using shallow trench isolation (STI), for example. For example, such isolated LDMOS devices can be produced using a bipolar CMOS DMOS (BCD) hybrid semiconductor manufacturing process platform.

[0012] The LDMOS devices described herein may have multiple self-aligned features. For example, in some embodiments, an LDMOS device according to the methods described herein may have a self-aligned drift region, wherein the drift region may be co-implanted with a deep body implant (e.g., implanted using the same photolithography mask). In embodiments, an LDMOS device described herein may have a drain implant contact (e.g., formed by a RESURF dielectric field plate) comprising self-aligned Ti / Si formed on top of the drain implant.

[0013] As indicated above, the LDMOS devices described herein may be implemented using a field plate (or multiple field plates) including a RESURF dielectric layer. In an exemplary embodiment, such a field plate (which may be part of a gate structure of an associated LDMOS device) may be placed above an accumulation region of the LDMOS (e.g., an accumulation region of a section of the LDMOS device). Using a RESURF dielectric field plate may reduce gate charge compared to LDMOS implementations without adversely affecting device breakdown voltage, device on-resistance (e.g., drain-to-source on-resistance), or hot carrier injection (HCI) performance. That is, simulation results indicate breakdown, on-resistance, and HCI performance consistent with current devices (e.g., based on impact ionization locations), but with reduced gate charge.

[0014] Using the processing methods described herein can prevent the loss of STI oxide in other device areas (such as CMOS devices that can be produced using the BCD semiconductor manufacturing process platform in conjunction with LDMOS devices). In some embodiments, the production of such LDMOS devices can be achieved using limited additional processing added to an existing semiconductor process flow (such as a process flow for producing CMOS devices). For example, in an exemplary embodiment, the CMOS process flow can be modified by adding operations for forming a body region (including a deep body region (e.g., a buried body region)) for forming an LDMOS device, and operations for forming a RESURF dielectric layer (structure, etc.) that can be used to form a RESURF dielectric layer field plate of the LDMOS device.

[0015] Figure 1 is a diagram showing a cross-sectional view of an LDMOS transistor (device) 100 including a RESURF dielectric field plate. In some embodiments, the LDMOS device 100 may be implemented as an n-channel (n-type) LDMOS (NLDMOS) device. In some embodiments, the LDMOS device 100 may be implemented as a p-channel (p-type) LDMOS (PLDMOS) device, wherein the conductivity type of each region and implant is reversed compared to an NLDMOS device embodiment. That is, the p-type material in the NLDMOS is reversed to the n-type material in the PLDMOS. Likewise, the n-type material in the NLDMOS is reversed to the p-type material in the PLDMOS.

[0016] In some embodiments, Figure 1 The LDMOS device 100 can be produced using a semiconductor process, such as a BCD hybrid semiconductor manufacturing process platform. Figures 3 to 15 Exemplary embodiments of such a manufacturing process are discussed, wherein Figures 3 to 14B is a cross-sectional view of semiconductor process operations that may be used to produce LDMOS 100 . Fig.15 It is shown that in some embodiments, Figures 3 to 14B The structure of LDMOS 100 is generally described, and more details about the components of LDMOS 100 and methods for producing embodiments of LDMOS 100 are further discussed below.

[0017] like Figure 1 As shown in FIG. 1 , the LDMOS may include adjacent segments, segment 100 a (left side) and segment 100 b (right side). Figure 1 The LDMOS 100 shown in FIG. 1 may be referred to as an LDMOS unit cell, wherein multiple LDMOS unit cells may be combined to form a larger LDMOS device. It should be understood that Figure 1The structure of the LDMOS device 100 can be extended to Figure 1 In order to establish the channel width of the LDMOS sections 100a and 100b. Figure 1 The exemplary embodiment of FIG. 1 shows adjacent sections 100 a and 100 b of the LDMOS 100 , so the following discussion describes the elements included in each section, with additional discussion of some elements shared between the sections 100 a and 100 b .

[0018] like Figure 1 As shown in , LDMOS 100 may be formed in a substrate 102, wherein the substrate 102 has a first conductivity type. For example, for NLDMOS, the substrate 102 may be a p-type substrate, and for PLDMOS, the substrate 102 may be an n-type substrate. LDMOS 100 may include a deep well region or a buried well region 104 having a second conductivity disposed in the substrate 102. The second conductivity type may be opposite to the first conductivity type, for example, n-type for NLDMOS devices and p-type for PLDMOS.

[0019] Figure 1 The LDMOS 100 of the embodiment may include a body region of a first conductivity type (e.g., p-type for NLDMOS), wherein the body region is disposed on a buried well region 104. In this example, the body region of the LDMOS 100 may include a buried (deep) body region 106 disposed on the buried well region 104, a surface body region 110 for each segment 100a and 100b, and a linking body region 112 for each segment of the LDMOS 100. Figure 1 As shown in FIG. 1 , the connecting body region 112 is disposed between the buried (deep) body region 106 and the surface body region 110 so as to connect the body regions of the first conductivity type to form a continuous body region of the first conductivity type of the LDMOS 100 .

[0020] Figure 1 The exemplary LDMOS 100 also includes a drift region 108 of a second conductivity type (eg, n-type for NLDMOS). Figure 1As shown in , the drift region 108 can be disposed in (within) the body region, but in some embodiments, the drift region 108 can be formed before at least one or more portions of the body region. For example, in some embodiments, the surface body region 110 and the connecting body region 112 can be formed after the drift region 108 and are described as being disposed in the drift region 108. In the LDMOS 100, the segments 100a and 100b (and the LDMOS 100 as a whole) can be isolated (e.g., using STI regions) from adjacent devices (e.g., in different device regions, such as bipolar and / or CMOS device regions) formed in the same semiconductor die.

[0021] like Figure 1 As further shown in FIG. 1 , for each of the segments 100a and 100b, the LDMOS 100 may include a source implant 122 of the second conductivity type disposed in the body region. The LDMOS 100 may also include a drain implant 124 of the second conductivity type disposed in the drift region 108. In some embodiments (such as Figure 1 In an LDMOS 100, the drain implant 124 may be shared by the segment 100a and the segment 100b. That is, the drain implant 124 may be a common drain implant for the segments of the LDMOS 100.

[0022] The LDMOS 100 may further include a gate structure disposed on the drift region 108, wherein the gate structure is formed across the two segments 100a and 100b and a corresponding gate electrode of each segment is defined from the gate structure. Figure 1 In an exemplary embodiment of the present invention, the gate structure includes: a field plate 130 including a RESURF dielectric layer, a gate dielectric layer 152 (thermal oxide layer), and a gate electrode 150 disposed on the field plate and the gate dielectric layer. In some embodiments, the RESURF dielectric layer of the field plate may include a thermal oxide layer 130b (which may be different from the gate oxide layer 152) and a deposited oxide layer 130a. Figure 1 As shown in , the field plate 130 may be disposed above (on, vertically aligned with, etc.) the corresponding accumulation region of each of the segments 100a and 100b (e.g., near or at the drain implant 124), which may reduce the total gate charge of the LDMOS 100 as compared to an LDMOS device having a flat gate and field plate structure.

[0023] The example LDMOS 100 also includes a drain contact 170 extending through the field plate 130, which may define an ohmic contact with the drain implant 124, such as using the methods described herein. Like the drain implant 124, the drain contact 170 may be shared by the LDMOS segments 100a and 100b. Figure 1As shown in FIG. 1 , the drain contact 170 includes a contact fill portion 170 a (eg, tungsten) and a metallization portion 170 b. For each of the segments 100 a and 100 b, the fill portion 170 a may be disposed between respective portions of the gate electrode 150 .

[0024] like Figure 1 As shown in FIG. 1 , the LDMOS 100 may include a heavy body implant 120 of a first conductivity type (eg, p-type for an NLDMOS device) for each of the segments 100a and 100b. Figure 1 As shown in , the heavy body implant 120 may be adjacent to the corresponding source implant 122. A contact 160 (e.g., an ohmic contact) may be formed to the source implant 122, the heavy body implant 120, and the surface body region 110. The contact 160 may include a silicide material 160a (such as cobalt silicide, etc.), a fill material 160b (e.g., tungsten, etc.), and a metallization material 160c (e.g., aluminum, copper, alloy, etc.). Figure 1 As shown in FIG. 1 , the contact filling materials 170 a and 160 b may extend through the interlayer dielectric material 140 .

[0025] Also like Figure 1 As shown in , and as e.g. Figure 7 As more clearly shown in FIG. 1 , each segment 100a and 100b may include a connection (source connection) implant 126 of the second conductivity type (e.g., n-type for NLDMOS). The connection implant 126 may reduce the resistance in the respective conductive paths between the channel regions of the segments 100a and 100b and their respective source implants 122. Figure 1 As further shown in FIG. 1 , the LDMOS 100 may include gate electrode sidewall spacers 154 that may be formed in conjunction with sidewall spacers formed in other device regions (e.g., such as CMOS regions for LDMOS produced in a hybrid process such as a BCD platform).

[0026] Figure 2 2 is a graph 200 showing a comparison of the gate charge of an LDMOS transistor including a RESURF dielectric field plate (such as the dielectric field plate described herein) with the gate charge of a current LDMOS transistor having a flat gate and field plate. In graph 200, lines 210 and 210a correspond to an LDMOS transistor having a RESURF dielectric field plate, and lines 220 and 220a correspond to an LDMOS transistor having a flat gate and field plate. In graph 200, time is represented on the x-axis and gate voltage is represented on the y-axis. Lines 210 and 220 represent the corresponding gate voltage and time for a given gate current. Lines 210a and 220b indicate the corresponding amount of time it takes for each device to reach a gate voltage (e.g., an operating gate voltage) of Vg.

[0027] As can be seen in graph 200, the LDMOS device (210) with a RESURF dielectric layer field plate reaches a gate voltage of Vg in a shorter time than the LDMOS device (220) with a flat field plate. Since Qg is given by the gate current multiplied by time, it can be seen that the gate charge associated with line 210a (RESURF dielectric layer field plate device) is less than the gate charge associated with line 220a (flat field plate device). In fact, in this example, the simulation results shown indicate that the Qg of the devices of lines 210 and 210a is more than 25% less than the Qg of the devices of lines 220 and 220a. In other words, the LDMOS device with a RESURF dielectric layer field plate (e.g., an embodiment of LDMOS 100) exhibits a reduction in Qg of more than 25% compared to an LDMOS device with a flat field plate (e.g., having comparable device dimensions, such as channel width and length).

[0028] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A and 14B ( Figures 3 to 14B ) is a diagram showing a method for producing an LDMOS transistor (such as Figure 1 1. A series of cross-sectional views of operations of a semiconductor manufacturing process for an embodiment of an LDMOS transistor 100 of FIG. 1. In some embodiments, these operations may be performed in an order corresponding to the order of the drawings, or may be performed in a different order as appropriate for a given manufacturing process.

[0029] exist Figures 3 to 14B In the example, two different process flows are shown, wherein in these examples, the two process flows are from Fig. 8A and Figure 8B The operations shown begin to diverge from each other. Figures 3 to 14B Two exemplary process flows are Figures 3 to 7 The process flow operations shown are the same for both processes. Figures 3 to 14B ( Fig. 9A and Fig. 9BThe process operations shown in the figure (except for the process operations shown in the figure) are particularly related to the process operations of the LDMOS device formed with isolation (STI isolation) using a hybrid semiconductor process platform (e.g., a BCD process). It should be understood that some elements (such as photolithography masks formed in other device areas) may not be shown in the figure. Figures 3 to 14B , and the process operations performed to define the LDMOS device may be performed in sequence or using additional process operations so as not to adversely affect devices in other device regions (eg, not etching such as Fig. 8A The RESURF dielectric layer field plate shown in , or using additional photomask etching as Figure 8B The RESURF dielectric layer field plate shown in FIG. 1 is used to prevent STI loss in the CMOS device area.

[0030] In addition, although from Fig. 8A and FIG. 8B to FIG. 14A 14B and 14C show separate diagrams of process operations for these exemplary embodiments, but some of the operations shown in those figures are sufficiently similar that they may be described together. Figures 3 to 14B The process flow operations may be used to produce either an n-channel (n-type) LDMOS transistor or a p-channel (p-type) LDMOS transistor, but for purposes of illustration and clarity, Figures 3 to 14B The description will be generally about producing NLDMOS transistors (devices). However, it should be understood that PLDMOS devices can also be used. Figures 3 to 14B The process flow is produced by reversing the respective polarity of each of the regions and implants described with respect to producing the NLDMOS device (i.e., replacing n-type with p-type and p-type with n-type). In addition, Figures 3 to 14B About the operation Fig.15 The method 1500 shown in FIG. 1 is further discussed in detail and described further below.

[0031] See also Figure 3 , the manufacturing process for producing LDMOS devices (and specifically, NLDMOS devices in these examples) may begin by forming STI regions 115 (eg, STI oxide) in p-type substrate 102. Figure 3, a shield oxide layer 310 may be formed on the surface of the substrate 102. After forming the STI regions 115 and the shield oxide layer 310, a deep (buried) n-well (DNW) region 104 may be formed in the substrate 102. In some embodiments, forming the DNW region 104 may include forming a photolithography mask (not shown) that is used as an implantation mask to define the DNW region 104. After forming the DNW region 104 (e.g., using a high energy implant through the shield oxide 310), an annealing operation may be performed that may activate the implantation of the DNW region 104 and repair damage to the substrate 102 caused by the high energy implantation operation.

[0032] See also Figure 4 , the photolithography mask used to define the DNW region 104 may be removed, and another photolithography mask (not shown) may be formed, wherein the new mask may be used to define areas where a p-type deep body region 106 and an n-type drift (n drift) region 108 are to be formed (e.g., for LDMOS devices and / or other devices being produced). Figure 4 In the illustrated operation, in this exemplary embodiment, the deep p body region 106 and the n drift region 108 are formed using the same photolithography mask. Thus, the deep p body region 106 and the n drift region 108 may be referred to as being co-implanted, but in this example, they are formed using respective p-type implants and n-type implants through the screen oxide 310. In some embodiments, another anneal may be performed after forming the deep p body region 106 and the n drift region 108.

[0033] See also Figure 5 , operations for forming RESURF dielectric field plate 130 are shown. These operations may include removing (etching) screen oxide 310, growing thermal oxide layer 130b (e.g., which may be part of a pad oxide layer), and forming deposited oxide layer 130a on thermal oxide layer 130b. Photolithography and etching operations may then be performed to pattern field plate 130 (e.g., deposited oxide layer 130a and thermal oxide layer 130b). In some embodiments (such as Figure 5 In the example of FIG. 1 , the deposited oxide layer 130a can be etched at a faster rate than the thermal oxide layer 130b. This difference in etching rate can result in a gap at the end of the field plate 130 (e.g., at Figure 5 The inclined profile 510 is shown at the left and right ends of the upper field plate 130 ).

[0034] See also Figure 6 , a thermal oxide may be grown to form a gate dielectric layer 152. Figure 6 As shown in , in this example, the gate dielectric layer 152 and the thermal oxide layer 130b of the field plate 130 may form a continuous dielectric (eg, thermal oxide) layer. Figure 6As further shown in FIG. 1 , polysilicon may be deposited to form a polysilicon portion 150a for a gate electrode of an NLDMOS. In some embodiments, an implant (p-type in this example) may be performed to dope the polysilicon used to define the gate dielectric polysilicon portion 150a so that the polysilicon has a high sheet resistance, such as for forming a polysilicon resistor in other area devices of a semiconductor die that also includes an LDMOS device (such as may be produced using a BCD process). Similarly, as shown in FIG. Figure 6 As shown in , a photolithography mask 610 may be formed, and the polysilicon may be etched to form (define, pattern, etc.) a polysilicon portion 150 a of the gate electrode 150 .

[0035] In some embodiments, the thickness of the field plate 130 can be adjusted (along the Figure 6 Line D in (D) to achieve the desired Qg, on-resistance and breakdown voltage. For example, in an exemplary embodiment, the total thickness of the field plate 130 can be about 1000 angstroms, wherein the thermal oxide layer 130b can be, for example, about 150 angstroms, and the deposited oxide layer 130a can be, for example, about 850 angstroms.

[0036] like Figure 7 As shown in FIG. 1 , when corresponding implants are performed to form surface p-body regions 110 , connecting p-body regions 112 and source n-connection implants 126 , Figure 6 The photolithography mask 610 may be used as an implantation mask. In some embodiments, the surface p-body region 110a may be formed using a steeply tilted angled implantation such that the surface p-body region 110 extends below the gate dielectric 152 and the gate electrode. The connecting p-body region 112 may be implanted such that it is disposed between the surface p-body region 110 and the deep p-body region 106, for example, to form a continuous p-body region for an LDMOS device. Figure 6 As shown in , the n-connect implant 126 may be configured to provide an n-type diffusion connection between the channel region of the LDMOS (eg, below the gate dielectric in the surface p-body region) and the source implant 122 and / or source contact 160 (to be formed later).

[0037] As mentioned above, Figures 3 to 14B An exemplary semiconductor manufacturing process from Fig. 8A and 8B The operation began to diverge. Fig. 8A and Figure 8B In both cases, the polysilicon portion 150a (of the gate electrode 150) is patterned to define adjacent regions for the LDMOS (such as Figure 1 100a and 100b) of the LDMOS segments shown in FIG. Fig. 8A In the exemplary embodiment shown in , the field plate 130 is not etched. Figure 8BIn the exemplary embodiment shown in FIG. 8 , a photolithographic mask 810 is defined and the mask 810 can be used to etch the field plate 130 through the deposited oxide 130a of the RESURF dielectric layer field plate 130 to the thermal oxide layer 130b (e.g., in the area where the drain implant 124 will be formed). In some embodiments, the drain implant 124 (such as Figure 1 ) can be formed as a self-aligned tilted (angled) drain implant through the thermal oxide 130b, for example, using a photolithographic mask 810 and an etched deposited oxide 130a of the field plate 130 to define such a self-aligned drain implant. Such a method can be used to produce adaptive RESURF LDMOS devices, such as Figure 1 LDMOS 100. In some embodiments, the photolithography mask can be removed after forming the self-aligned drain implant.

[0038] Fig. 9A and Fig. 9B Process operations that may be performed in a CMOS device region that is associated with the described LDMOS region, such as in the same semiconductor die produced using a hybrid semiconductor manufacturing process such as a BCD process, are shown. For example, Fig. 9A The formation of a p-well 910 and the formation of an n-type lightly doped drain region (NLDD) 915 are shown, which can be used to form an n-type CMOS transistor. Fig. 9B The formation of a p-well 920 and a p-type lightly doped drain region (PLDD) 925 is shown, which can be used to form a p-type CMOS transistor. Fig. 9A and Fig. 9B As shown in both, spacers 154 (e.g., gate electrode sidewall dielectric spacers) may also be formed on the sidewalls of the gate electrodes of the formed n-type MOS transistor and p-type MOS transistor. Similarly, spacers 154 (e.g., gate electrode sidewall dielectric spacers) of the LDMOS device Fig. 10A and 10B shown) can be used to form Fig. 9A and Fig. 9B The spacers 154 are formed by the same process operations as shown.

[0039] See also Fig. 10A and Fig. 10B , a source implant 122 and a shared or common drain implant 124 may be formed. For example, as discussed herein, the drain implant 124 may be formed by adjacent LDMOS segments (e.g., Figure 1 The LDMOS device 100 is shared by the sections 100a and 100b. Fig. 10A and Fig. 10BAs shown in both, in these exemplary embodiments, a photolithographic mask 1010 may be formed, and then one or more blanket implants may be performed to define a source implant 122 and a (shared) drain implant 124. Fig. 10A In an exemplary embodiment of , in which the field plate 130 is not etched in the region of the drain implant 124, a chain implant (implantation with two different energies) may be performed. Fig. 10A The chain implant may include a first blanket n-type implant at a first energy (eg, 50 keV) and a second blanket n-type implant at a second higher energy (eg, 100 keV). Fig. 10A In , since the field plate is not etched, only the second implant may have sufficient implant energy to penetrate the field plate to form the drain implant 124, wherein both the first n-type implant and the second n-type implant form the source implant 122 (because only the gate dielectric 152 is disposed on the source implant region). Fig. 10A In an embodiment, the source implant 122 may have a depth along line D that is greater than the depth of the drain implant.

[0040] exist Fig. 10B In embodiments where field plate 130 is etched in the region of drain implant 124, a single energy n-type implant (e.g., 50 keV) may be performed to form both source implant 122 and drain implant 124. In such embodiments, source implant 122 and drain implant 124 may have the same depth (approximately the same depth) along line D.

[0041] See also Fig.11A and Fig. 11B , removable Fig. 10A and Fig. 10B 1010, and may form a photolithography mask 1110. In these exemplary embodiments, the photolithography mask 1110 may be used as an implantation mask to define a heavy p body implant 120, which may be formed as a blanket p-type implant through the gate dielectric 152, wherein the heavy p body implant 120 is adjacent to a corresponding source implant 122 (and the channel region as the LDMOS device section is located on a corresponding opposite side of the source implant).

[0042] See also Fig. 12A and Fig. 12B , removable Fig.11A and Fig. 11B The silicide blocking oxide may be deposited and then patterned using photolithography. In this example, the patterned silicide blocking oxide may block (mask) silicon (including polysilicon) areas where silicide formation is not desired. After the deposition and patterning of the silicide blocking oxide, Fig. 12A and 12B In an embodiment, a silicide 1210 (eg, cobalt silicide (CoSi)) may be formed (eg, wherein the silicide 1210 may be Figure 1 160a of the LDMOS 100). For example, Fig. 12A and Fig. 12B In an embodiment, silicide 1210 (eg, CoSi) may be formed on source implant 122, heavy body implant 120, and surface body region 110. Fig. 12A and Fig. 12B As shown in , silicide 1210 may also be formed on the polysilicon of gate electrode 150 (eg, the gate electrode portions of segments 100a and 100b), which may reduce the gate resistance of the associated NLDMOS device. Fig. 12B In an embodiment in which the deposited portion 130 a of the field plate 130 is etched in the region of the drain implant 124 , a silicide 1210 (eg, CoSi) may also be formed on the drain implant 124 .

[0043] exist Fig.13A and Fig. 13B In an exemplary embodiment of FIG. 1 , an interlayer dielectric layer 140 may be formed and planarized (eg, using CMP), and a contact opening 142 may be defined (etched) in the interlayer dielectric 140 . Fig.13A and Fig. 13B In an embodiment, the etching process performed to form the contact opening 142 can be configured to terminate at the silicide formed on the source implant and the heavy p body implant. Fig.13A In embodiments of the present invention, the etching process used to form the contact opening 142 can be further configured to terminate at silicon (eg, of the drain implant 124). Fig. 13B In an embodiment of the present invention, the etching process used to form the contact opening 142 may also terminate on the silicide formed on the drain implant 124, as well as the silicide of the source implant and the heavy body implant.

[0044] Fig.14A and Fig. 14B The operations for contact formation and metallization used to accomplish these exemplary embodiments are shown. Figure 1 Like LDMOS 100, Fig.14A and Figure 14 also shows the use of Figures 3 to 14B The exemplary semiconductor manufacturing process implementation shown in FIG. 1 forms two sections 100 a and 100 b of a LDMOS transistor.

[0045] exist Fig.14A and Fig. 14BIn an exemplary embodiment of the present invention, a barrier metal (e.g., titanium (Ti) / titanium nitride (TiN)) layer may be formed (deposited, sputtered, etc.) in the contact opening 142, wherein the barrier metal layer may facilitate the formation of high-quality ohmic contacts to the source, body, and drain implants and prevent material diffusion between the silicide and the contact fill material (e.g., tungsten). A rapid thermal anneal may then be performed to reduce the contact resistance and induce a reaction between the barrier layer and the underlying material (e.g., a reaction that forms a diffusion barrier). In addition, in Fig.14A In the embodiment of the present invention, the annealing may form self-aligned titanium silicide TiSi in the contact opening 142 of the drain implant 124 .

[0046] for Fig.14A and Fig. 14B In an exemplary embodiment of both, a tungsten fill of the contact opening 142 may be performed (160b for the source / body contact and 170a for the drain contact), and then the tungsten fill may be planarized (e.g., using CMP) so that the top of the tungsten fill is aligned with the upper surface of the interlayer dielectric layer 140 (at Fig.14A and Fig. 14B orientation) are coplanar. Fig.14A and Fig. 14B For both embodiments, metallization (160c for the source / body contact and 170b for the drain contact) may be formed to provide electrical connection to the contact tungsten fill, which may complete the formation of the LDMOS device having segments 100a and 100b.

[0047] Fig.15 is shown to be usable to implement Figures 3 to 14B 1500 is a flow chart of a method 1500 of a semiconductor manufacturing process shown in FIG. Therefore, for illustrative purposes, further reference will be made in the discussion of method 1500. Figures 3 to 14B However, it should be noted that in some embodiments, the operations of method 1500 may be performed using other methods and / or in a manner similar to Fig.15 or Figures 3 to 14B In addition, for purposes of illustration, method 1500 will generally be described with reference to producing an n-type (n-channel) LDMOS transistor (NLDMOS). In some embodiments, method 1500 can be used to produce a p-type (p-channel) LDMOS (PLDMOS) transistor, such as by reversing the conductivity type of various regions and implants of the exemplary NLDMOS device.

[0048] In method 1500, in some embodiments, the operations of blocks 1505 and 1510 may correspond to Figure 3For example, at block 1505, a shallow trench isolation 115 for the LDMOS transistor may be formed in the substrate 102 (eg, a p-type substrate for an NLDMOS transistor). Additionally, at block 1505, a Figure 3 The shield oxide layer 310 of FIG. 15 can be formed. At block 1510, a deep well region (e.g., a deep n-well) 104 can be formed, wherein a photolithography mask can be used to define regions (e.g., active regions) of the LDMOS device such that the photolithography mask can prevent the formation of the deep well region 104 outside the defined regions. After the deep well region 104 is formed (e.g., using a high energy implant), an annealing operation can be performed, which can activate the implantation of the deep well region 104 and repair damage to the substrate 102 caused by the implantation operation.

[0049] In method 1500, the operation at block 1515 may correspond to Figure 4 . For example, the photolithography mask used to form the deep well region 104 may be removed, and another photolithography mask may be formed to define areas where the deep body region 106 (e.g., deep p-body region) and the drift region 108 (e.g., n-drift region) are to be formed (e.g., for LDMOS devices and / or other devices produced). As discussed above, because in this exemplary embodiment, the deep body region 106 and the drift region 108 are formed using the same photolithography mask, they may be referred to as being co-implanted, even though they are formed using respective p-type and n-type implants. In some embodiments, another anneal may be performed after forming the deep body region 106 and the drift region 108.

[0050] The operations at block 1520 of method 1500 may correspond to Figure 5 . For example, forming the RESURF dielectric field plate 130 at block 1520 may include removing the shield oxide 310, growing a thermal oxide 130b (e.g., a pad oxide), and forming a deposited oxide layer 130a on the thermal oxide layer 130b. Photolithography and etching operations may then be performed to pattern the field plate 130. As described above, the deposited oxide layer 130a may be etched at a faster rate than the thermal oxide layer 130b, which may result in a thin film at the ends of the field plate 130 (e.g., Figure 5 An inclined profile 510 is produced at the left and right ends of the orientation.

[0051] Blocks 1525 and 1530 of method 1500 may correspond to Figure 6 In this exemplary embodiment, at block 1525, a thermal oxide may be grown to form a gate dielectric layer 152 such that the gate dielectric layer 152 and the thermal oxide layer 130b of the field plate 130 form a continuous dielectric (eg, thermal oxide) layer, such as Figure 6At block 1530, polysilicon may be deposited to form a polysilicon portion 150a of the gate electrode 150 (eg, as shown in FIG. 15A ). Figure 1 ). In addition, at block 1530, in some embodiments, an implant (p-type) may be performed to dope the polysilicon with a high sheet resistance, such as for forming polysilicon resistors in other regions of a semiconductor die (produced using method 1500) that also includes an LDMOS device (e.g., such as in a CMOS region of a semiconductor die produced using a hybrid semiconductor process). Figure 6 As shown in FIG. 1 , a photolithography mask 610 may be formed at block 1530 , and the polysilicon may be etched to form a polysilicon portion 150 a of the gate electrode 150 .

[0052] At block 1535 of method 1500, Figure 6 The photolithography mask 610 may be retained and such as Figure 7 , is used as an implant mask to perform corresponding implants to form a surface body (e.g., p-body) region 110 (e.g., using an angled implant), a connecting body region 112, and a source connecting (n-connection) implant 126. As described herein, the connecting body region 112 can be disposed between the surface body region 110 and the deep body region 106 to form a continuous body region. Also as described herein, the connecting implant 126 can connect the channel region of the LDMOS to the source implant 122 and / or the source contact 160.

[0053] In method 1500, block 1540 may correspond to Fig. 8A Icon or Figure 8B For example, the polysilicon portion 150a (of the gate electrode 150) may be patterned to define adjacent regions for the LDMOS (such as Figure 1 as well as Fig.14A and Fig. 14B In some embodiments (such as Fig. 8A In the example shown in ), the field plate 130 is not etched at block 1540. Figure 8B In some embodiments shown in FIG. 1 , a photolithographic mask 810 may be formed at block 1540 and the field plate 130 may be etched through the RESURF dielectric layer 130a to the thermal oxide layer 130b (eg, in the region where the drain implant 124 will be formed).

[0054] Although in Fig.15 1540 and 1545, such as in a hybrid semiconductor manufacturing process, p-well and n-well formation may be performed, for example, after block 1540 and before block 1545, such as in Fig. 9A and Fig. 9BIn addition, spacers 154 (eg, gate electrode sidewall spacers) may also be formed (as shown in FIG. Fig. 9A and Fig. 9B ), including a spacer 154 of an LDMOS device produced using method 1500.

[0055] At block 1545 (which may correspond to Fig. 10A Icon or Fig. 10B ), a source implant 122 and a (shared or common) drain implant 124 may be formed. For example, drain implant 124 may be shared by adjacent LDMOS segments (eg, segments 100a and 100b described herein). Fig. 10A and Fig. 10B As shown in , a photolithographic mask 1010 may be formed and one or more blanket implants may be performed to define a source implant 122 and a (shared) drain implant 124. Fig. 10A In an embodiment where the field plate 130 is not etched in the region of the drain implant 124, at block 1545, a chain implant (implantation with two different energies) may be performed, such as described above with respect to Fig. 10A In Fig. 10B In an embodiment in which the field plate 130 is etched in the region of the drain region 124, at block 1545, a single energy implant may be performed to form the source implant 122 and the drain implant 124, such as described above with respect to Fig. 10B described.

[0056] In block 1550 of method 1500 (which may correspond to Fig.11A Icon or Fig. 11B ), the photolithography mask 1010 may be removed and a photolithography mask 1110 may be formed, wherein the photolithography mask 1110 may be used as an implantation mask to define a heavy body (heavy p-body) implant (heavy body region) 120, as shown in FIG. Fig.11A and Fig. 11B as shown in .

[0057] In block 1555 of method 1500 (which may correspond to Fig. 12A Icon or Fig. 12B ), a silicide 1210 may be formed (for example, wherein the silicide 1210 may be realized Figure 1 160a of the LDMOS 100). For example, in Fig. 12A and Fig. 12B In an embodiment, silicide 1210 (eg, CoSi) may be formed on source implant 122, heavy body implant 120, and surface body region 110. Fig. 12A and Fig. 12BAs shown in , silicide 1210 may also be formed on gate electrode 150 (eg, gate electrode portion), for example, to reduce gate resistance. Fig. 12B In embodiments where the field plate 130 is etched in the region of the drain implant 124 , a silicide 1210 (eg, CoSi) may also be formed on the drain implant 124 .

[0058] Blocks 1560 and 1565 of method 1500 may correspond to Fig.13A Icon or Fig. 13B In these exemplary embodiments, the interlayer dielectric layer 140 may be formed and planarized (eg, using CMP) at block 1560, and contact openings 142 may be defined in the interlayer dielectric 140 at block 1565. Fig.13A and Fig. 13B In an embodiment, the etching process performed to form the contact opening 142 can be configured to terminate at the silicide formed on the source region and the heavy body region (eg, at block 1555). Fig.13A In embodiments of the present invention, the etching process used to form the contact opening 142 can be further configured to terminate at silicon (eg, of the drain implant). Fig. 13B In an embodiment of the present invention, as with the silicide of the source and heavy body regions, the etching process used to form the contact opening 142 may also terminate on the silicide formed on the drain implant.

[0059] Blocks 1570 through 1585 of method 1500 may correspond to Fig.14A Icon or Fig. 14B . Figure 1 Like the LDMOS100, Fig.14A and Figure 14 also shows the use of Fig.15 The two sections 100a and 100b of the LDMOS transistor are formed by the method of. In these exemplary embodiments, at block 1570, a barrier metal (e.g., Ti / TiN) layer may be formed (deposited, sputtered, etc.) in the contact opening 142, wherein the barrier metal may facilitate the formation of high-quality ohmic contacts to the source, body, and drain implants. A rapid thermal anneal may then be performed at block 1575 to reduce the contact resistance. In addition, at Fig.14A In embodiments of the present invention, the annealing of block 1575 may form a self-aligned TiSi in the contact opening 142 for the drain implant. Fig.14A and Fig. 14B In both embodiments, a tungsten fill of the contact opening 142 may be performed (160b for the source / body contact and 170a for the drain contact), and the tungsten fill may then be planarized (e.g., using CMP) to be aligned with the upper surface of the interlayer dielectric layer 140 (at Fig.14A and Fig. 14B At block 1585, metallization (160c for source / body contacts and 170b for drain contacts) may be formed to provide electrical connection to the contact tungsten fill formed at block 1580, which may complete the formation of the LDMOS device having segments 100a and 100b.

[0060] The various devices and techniques described herein may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0061] It should also be understood that when an element such as a layer, region, or substrate is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to another element, or one or more intermediate elements may exist. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intermediate elements or layers.

[0062] Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in such a manner. The claims of the present application may be amended to recite exemplary relationships described in the specification or shown in the drawings.

[0063] As used in this specification, the singular may include the plural unless the context clearly indicates a particular case. In addition to the orientations shown in the drawings, spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include laterally adjacent (or laterally adjacent), vertically adjacent (or vertically adjacent), or horizontally adjacent (or horizontally adjacent), where adjacent may indicate that an intermediate element may be disposed between the elements described as adjacent.

[0064] Although certain features of the described embodiments have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of a specific implementation. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A laterally diffused metal oxide semiconductor (LDMOS) transistor, the laterally diffused metal oxide semiconductor transistor comprising: a substrate of a first conductivity type; a buried well region of a second conductivity type, the buried well region being disposed in the substrate, the second conductivity type being opposite to the first conductivity type; a body region of the first conductivity type, the body region being disposed on the buried well region; a drift region of the second conductivity type, the drift region being disposed in the main region; a drain implant of the second conductivity type, the drain implant being disposed in the drift region; a source implant of the second conductivity type, the source implant being disposed in the body region; A gate structure, wherein the gate structure is disposed on the drift region, and the gate structure comprises: a field plate comprising a RESURF dielectric layer; a gate dielectric layer; and a gate electrode disposed on the field plate and the gate dielectric layer; and A drain contact extends through the field plate and defines an ohmic contact with the drain implant.

2. The LDMOS transistor of claim 1 , wherein the body region comprises: a buried body region, the buried body region being disposed on the buried well region; Surface main body area; and a connecting body region, the connecting body region being arranged between the buried body region and the surface body region, The RESURF dielectric layer comprises: a first thermal oxide layer disposed on the drift region and the drain implant; and a deposited oxide layer disposed on the first thermal oxide layer, and The gate dielectric layer includes a second thermal oxide layer.

3. The LDMOS transistor according to claim 1 , further comprising: a heavy body implant of the first conductivity type, the heavy body implant disposed in the body region, the heavy body implant adjacent to the source implant; and A shallow trench isolation dielectric is disposed in the body region, the shallow trench isolation dielectric being adjacent to the heavy body implant.

4. The LDMOS transistor according to claim 1, further comprising: a heavy body implant of the first conductivity type, the heavy body implant disposed in the body region, the heavy body implant adjacent to the source implant; and A source contact defines an ohmic contact to the source implant, the body region, and the heavy body implant.

5. The LDMOS transistor of claim 1, wherein: The RESURF dielectric layer is disposed on an accumulation region of the LDMOS transistor; and The RESURF dielectric layer includes an inclined portion extending from an upper surface of the RESURF dielectric layer to the gate dielectric layer.

6. The LDMOS transistor of claim 1 , further comprising a connection implant of the second conductivity type, the connection implant being disposed in the body region, The drain implant is shared between a first section of the LDMOS transistor and a second section of the LDMOS transistor.

7. A laterally diffused metal oxide semiconductor (LDMOS) transistor, the laterally diffused metal oxide semiconductor transistor comprising: a substrate of a first conductivity type; a buried well region of a second conductivity type, the second conductivity type being opposite to the first conductivity type; a body region of the first conductivity type, the body region being disposed on the buried well region; a drift region of the second conductivity type, the drift region being disposed in the main region; a drain implant of the second conductivity type, the drain implant being disposed in the drift region; a first source implant of the second conductivity type, the first source implant being disposed in the body region, the first source implant defining a source region of a first section of the LDMOS transistor; a second source implant of the second conductivity type, the second source implant being disposed in the body region, the second source implant defining a source region of a second section of the LDMOS transistor; A gate structure, wherein the gate structure is disposed on the drift region, and the gate structure comprises: a field plate comprising a RESURF dielectric layer; a gate dielectric layer; and a gate electrode disposed on the field plate and the gate dielectric layer, the gate electrode comprising a first gate electrode portion of the first section of the LDMOS transistor and a second gate electrode portion of the second section of the LDMOS transistor; and A drain contact extends through the field plate between the first gate electrode portion and the second gate electrode portion, the drain contact and the drain implant being shared between the first section of the LDMOS transistor and the second section of the LDMOS transistor.

8. The LDMOS transistor according to claim 7, further comprising: a first source contact to said first source implant; and a second source contact to the second source implant, The drain contact comprises a first silicide material, and The first source contact and the second source contact include a second silicide material different from the first silicide material. 9 . The LDMOS transistor of claim 7 , wherein the RESURF dielectric layer is disposed on respective accumulation regions of the first section of the LDMOS transistor and the second section of the LDMOS transistor.

10. A method for forming a laterally diffused metal oxide semiconductor (LDMOS) transistor, the method comprising: forming a buried well region of a second conductivity type in a substrate of a first conductivity type, the second conductivity type being opposite to the first conductivity type; forming a deep body region of the first conductivity type in the substrate over the buried well region; forming a drift region of the second conductivity type on the deep body region; A gate structure is formed on the drift region, wherein the gate structure comprises: a field plate comprising a RESURF dielectric layer; a gate dielectric layer; and a gate electrode, the gate electrode being disposed on the field plate and the gate dielectric layer; In the drift region are formed: the surface body region of the first conductivity type; and a connection body region of the first conductivity type, the connection body region being disposed between the surface body region and the deep body region; forming a drain implant of the second conductivity type in the drift region; forming a source implant of the second conductivity type in the body region; and A drain contact is formed extending through the field plate, the drain contact defining an ohmic contact to the drain implant.

11. The method of claim 10, wherein forming the source implant and the drain implant comprises: forming the source implant using a first implant energy and a second implant energy, the second implant energy being greater than the first implant energy; as well as The drain implant is formed through the field plate using the second implant energy.

12. The method according to claim 10, further comprising: Before forming the buried well region, forming a shallow trench isolation region of the lateral diffused metal oxide semiconductor transistor, and Prior to forming the drain implant and the source implant, a connection implant of the second conductivity type is formed, the connection implant being disposed in the body region.

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