A Triple-Gate SiC Lateral MOSFET Power Device

Abstract

This invention provides a three-gate SiC lateral MOSFET power device, comprising a SiC substrate with a substrate groove; a SiC epitaxial layer with an epitaxial groove; the SiC epitaxial layer being disposed within the substrate groove; a P-type well region with a dielectric trench, the dielectric trench containing a channel region; the P-type well region being disposed within the epitaxial groove; a gate, the gate comprising two first side gates and a top gate, the two ends of the top gate being respectively connected to the side surface of one end of the gate, forming an inverted U-shaped structure, the top gate and the first side gates being surrounded by a high-k dielectric except for the top and the connection points, the inverted U-shaped structure being disposed within the dielectric trench and protruding from the dielectric trench; a drain and a source, the source and source being disposed within the dielectric trench and on both sides of the U-shaped structure; this invention solves the problems of high threshold voltage, high drive level during saturation operation, and high drive power consumption of SiC power MOSFETs.

Description

Technical Field

[0001] The invention relates to a three-gate SiC lateral MOSFET power device. Background Art

[0002] Silicon carbide (SiC) materials in SiC devices have attracted extensive attention and research due to their superior physical properties. Its high-temperature and high-power electronic devices have the advantages of high input impedance, fast switching speed, high operating frequency, high temperature and high pressure resistance, and have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] However, it still has technical and economic problems such as high threshold voltage, high driving voltage at saturation current, many material defects, low channel mobility, and high cost, which seriously restrict the development of SiC power devices. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a three-gate SiC lateral MOSFET power device to solve the problems of high threshold voltage, high driving level and high driving power consumption of SiC power MOSFET during saturation operation.

[0005] The present invention is implemented as follows: a three-gate SiC lateral MOSFET power device, comprising

[0006] A SiC substrate, wherein a substrate groove is provided on the SiC substrate;

[0007] A SiC epitaxial layer, wherein an epitaxial groove is provided in the SiC epitaxial layer; the SiC epitaxial layer is provided in the substrate groove;

[0008] a P-type well region, wherein a dielectric groove is provided in the P-type well region, and a channel region is provided in the dielectric groove; the P-type well region is provided in the epitaxial groove;

[0009] a gate, the gate comprising two first side gates and a top gate, the two ends of the top gate are respectively connected to the side of one end of the gate to form an inverted U-shaped structure, the top gate and the first side gate are surrounded by a high-k dielectric except for the top and the connection, and the inverted U-shaped structure is arranged in the dielectric groove and protrudes from the dielectric groove;

[0010] a drain electrode, the source electrode being disposed in the dielectric groove and disposed on one side of the U-shaped structure;

[0011] and a source electrode, wherein the source electrode is disposed in the dielectric groove and at the other side of the U-shaped structure.

[0012] Furthermore, the gate also includes at least one second side gate, which is evenly spaced inside the two side gates, and one end of the second side gate is connected to the top gate, and the second side gate is wrapped by a high-K dielectric outside the connection with the top gate.

[0013] Furthermore, the first side gate and the second side gate have the same thickness and width.

[0014] Furthermore, the longitudinal depth of the dielectric trench is less than the depth of the P-type well region.

[0015] Furthermore, the longitudinal depth of the first side gate is greater than or equal to the depth of the dielectric groove.

[0016] The advantages of the present invention are:

[0017] 1. It has three connected gate structures, including a planar gate and two trench gates. The three gates wrap the conductive channel from three directions and invert the channel region from three directions, so that the SiC lateral device can form a sufficient inversion layer carrier concentration under a lower gate voltage and have a lower threshold voltage under the same current conditions;

[0018] Second, when the three connected gate structures pass the threshold voltage and the gate voltage is gradually increased, a high-carrier concentration channel is formed around the gate, increasing the carrier concentration of the inversion layer, so that under the same gate voltage condition, the carrier concentration increases and the current carrying capacity increases;

[0019] 3. The three connected gate structures can achieve a sufficiently low specific on-resistance when the gate voltage is low, so that the gate drive voltage of the SiC lateral MOSFET power device is reduced when it is working in saturation, thereby reducing the driving energy consumption of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0021] Figure 1 It is a top view of a three-gate SiC lateral MOSFET power device of the present invention.

[0022] Figure 2 It is a front view of a cross-section of the top gate position of a three-gate SiC lateral MOSFET power device of the present invention.

[0023] Figure 3 It is a side view of a gate position of a three-gate SiC lateral MOSFET power device of the present invention.

[0024] Figure 4 It is a schematic diagram of the second embodiment. DETAILED DESCRIPTION

[0025] The present invention provides a three-gate SiC lateral MOSFET power device, which is used to solve the technical problems of high threshold voltage, high driving level and high driving power consumption of SiC power MOSFET during saturation operation, and achieves the beneficial effect of reducing the threshold voltage and driving voltage.

[0026] Embodiment 1

[0027] See also Figures 1 to 3 As shown, this embodiment provides a three-gate SiC lateral MOSFET power device, including

[0028] A SiC substrate, wherein a substrate groove is provided on the SiC substrate;

[0029] A SiC epitaxial layer, wherein an epitaxial groove is provided in the SiC epitaxial layer; the SiC epitaxial layer is provided in the substrate groove;

[0030] a P-type well region, wherein a dielectric groove is provided in the P-type well region, and a channel region is provided in the dielectric groove; the P-type well region is provided in the epitaxial groove;

[0031] a gate, the gate comprising two first side gates and a top gate, the two ends of the top gate are respectively connected to the side of one end of the gate to form an inverted U-shaped structure, the top gate and the first side gate are surrounded by a high-k dielectric except for the top and the connection, and the inverted U-shaped structure is arranged in the dielectric groove and protrudes from the dielectric groove;

[0032] a drain electrode, the source electrode being disposed in the dielectric groove and disposed on one side of the U-shaped structure;

[0033] and a source electrode, wherein the source electrode is disposed in the dielectric groove and at the other side of the U-shaped structure.

[0034] The gate also includes at least one second side gate, which is evenly spaced inside the two side gates, and one end of the second side gate is connected to the top gate. The second side gate is surrounded by a high-K dielectric outside the connection with the top gate, and is arranged in ascending order according to integers, thereby increasing the carrier density of the conductive channel and reducing the on-resistance.

[0035] The first side gate and the second side gate have the same thickness and width.

[0036] The longitudinal depth of the dielectric groove is less than the depth of the P-type well region.

[0037] The longitudinal depth of the first side gate is greater than or equal to the dielectric groove depth.

[0038] Used in SiC power devices and SiC power integrated circuits.

[0039] Due to the adoption of a three-gate structure, there are enough carriers to generate current at a lower gate voltage, so its threshold voltage is lower.

[0040] Due to the adoption of a three-gate structure, the carrier concentration is saturated at a relatively low gate voltage, and the specific on-resistance no longer decreases, so that the device can achieve a large current at a relatively low gate drive voltage, thereby reducing drive power consumption.

[0041] Embodiment 2

[0042] like Figure 4 As shown, based on the first embodiment, a multi-gate structure is adopted, that is, two first side gates and at least one second side gate, to further reduce the threshold voltage and improve the current carrying capacity.

[0043] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A three-gate SiC lateral MOSFET power device, characterized in that: include A SiC substrate, wherein a substrate groove is provided on the SiC substrate; A SiC epitaxial layer, wherein an epitaxial groove is provided in the SiC epitaxial layer; the SiC epitaxial layer is provided in the substrate groove; a P-type well region, wherein a dielectric groove is provided in the P-type well region, and a channel region is provided in the dielectric groove; the P-type well region is provided in the epitaxial groove; a gate, the gate comprising two first side gates and a top gate, the two ends of the top gate are respectively connected to the side surfaces of one end of the two first side gates to form an inverted U-shaped structure, the top gate and the first side gates are surrounded by a high-k dielectric except for the top and the connection, and the inverted U-shaped structure is arranged in the dielectric groove and protrudes from the dielectric groove; a drain electrode, the drain electrode being arranged in the dielectric groove and arranged on one side of the U-shaped structure, that is, a side where two first side gates and a top gate are connected; and a source electrode, wherein the source electrode is arranged in the dielectric groove and at the other side of the U-shaped structure, that is, the other side where two first side gates and a top gate are connected.

2. A three-gate SiC lateral MOSFET power device according to claim 1, characterized in that: The gate further includes at least one second side gate, which is evenly spaced between the two first side gates, and one end of the second side gate is connected to the top gate. The second side gate is wrapped by a high-K dielectric except for the connection with the top gate.

3. A three-gate SiC lateral MOSFET power device according to claim 2, characterized in that: The first side gate and the second side gate have the same thickness and width.

4. A three-gate SiC lateral MOSFET power device according to claim 1, characterized in that: The longitudinal depth of the dielectric groove is less than the depth of the P-type well region.

5. A three-gate SiC lateral MOSFET power device according to claim 1, characterized in that: The longitudinal depth of the first side gate is greater than or equal to the dielectric groove depth.

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