An HJT battery with high photoelectric conversion efficiency and its preparation method

Abstract

The present invention discloses an HJT battery with high photoelectric conversion efficiency and a preparation method thereof, belonging to the technical field of solar cells. The HJT battery of the present invention comprises an N-type crystalline silicon wafer, and an intrinsic amorphous silicon layer, a SiO2 layer, a C-doped SiO2 layer, an amorphous silicon-doped N-type layer, a TCO conductive layer and an electrode are sequentially arranged on the front surface of the N-type crystalline silicon wafer; an intrinsic amorphous silicon layer, a SiO2 layer, a C-doped SiO2 layer, an amorphous silicon-doped P-type layer, a TCO conductive layer and an electrode are sequentially arranged on the back surface of the N-type crystalline silicon wafer, and the amorphous silicon-doped P-type layer comprises a lightly doped B amorphous silicon layer and a heavily doped B amorphous silicon layer. The heterojunction solar cell prepared by the present invention can improve the photoelectric conversion efficiency to more than 24.3%, and the short-circuit current and open-circuit voltage are significantly improved, which can effectively improve the photoelectric conversion efficiency of the silicon heterojunction solar cell.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and more specifically, to an HJT cell with high photoelectric conversion efficiency and a preparation method thereof. Background Art

[0002] Currently, the mainstream battery products in the market are P-type monocrystalline PERC cells, and the efficiency of P-type PERC cells has reached its upper limit. However, with the market demand, the technology in the industry has been continuously developing. In recent years, N-type crystalline silicon solar cell technology has received increasing attention, mainly including passivated emitter rear surface cell (n-PERT), tunnel oxide passivated contact cell (TOPCon), and heterojunction cell (HJT). N-type crystalline silicon solar cells have further broken through and improved the conversion efficiency of crystalline silicon solar cells.

[0003] The HJT cell uses inexpensive amorphous silicon as the emitter layer. The emitter layer is doped amorphous silicon material. When depositing and preparing monocrystalline silicon, a temperature of about 200 °C can meet the preparation temperature requirements. The low-temperature process also ensures lower interface damage to the monocrystalline silicon substrate, and the existence of the intrinsic layer makes the interface passivation performance better. Heterojunction solar cells maintain the core advantage of high efficiency due to the large bandgap width of the heterostructure. However, there are still some technical problems that need to be overcome, such as the passivation characteristics of the amorphous silicon layer and the carrier transport characteristics in the structural layer, which will affect the photoelectric conversion efficiency of the HJT heterojunction cell. Therefore, how to study a preparation method for heterojunction cells with high light conversion efficiency is an urgent problem that those skilled in the art are facing currently.

[0004] The structure of the existing HJT cell is to make an amorphous silicon intrinsic layer and a doped layer on both sides of N-type monocrystalline silicon. The amorphous silicon intrinsic layer mainly passivates the surface defects of crystalline silicon, reduces surface defect states, and thus reduces carrier recombination. The amorphous silicon doped layer mainly forms a PIN junction and a field effect passivation layer with crystalline silicon. However, the existing technology uses B 2 H 6 gas doping to complete the p-type layer of the amorphous silicon doped layer. The p-type layer of the amorphous silicon doped layer formed by B 2 H 6 gas doping has poor thermal stability. B atoms are easy to diffuse into the amorphous silicon intrinsic layer, affecting the passivation effect of the intrinsic layer, resulting in a low open-circuit voltage of the solar cell, and further resulting in a low conversion efficiency of the solar cell; in addition, the p-type layer of the amorphous silicon doped layer formed by B 2 H 6 gas doping has a low bandgap width, will absorb more sunlight, increase the optical loss in the long wavelength band, result in a low short-circuit current of the solar cell, and lead to a low overall conversion efficiency of the solar cell.

[0005] After retrieval, the Chinese patent number is ZL 201811472120.6, and the patent name is: Emitter Structure of Crystalline Silicon Heterojunction Solar Cell and Its Preparation Method; this application case includes an N-type crystalline silicon wafer, and an amorphous silicon intrinsic layer is provided on both the front and back sides of the N-type crystalline silicon wafer. A TCO conductive film is provided on the outer side of the amorphous silicon intrinsic layer, and several Ag electrodes are provided on the outer side of the TCO conductive film. An amorphous silicon doped N-layer is provided between the amorphous silicon intrinsic layer and the TCO conductive film on one side of the N-type crystalline silicon wafer, and a TMB doped layer and a B2H6 doped layer are provided between the amorphous silicon intrinsic layer and the TCO conductive film on the other side. This application case uses TMB gas for doping, preventing the doping atom B from diffusing into the amorphous silicon intrinsic layer and improving the open circuit voltage; the TMB gas has a large band gap, and light can pass through the doped layer more effectively, improving the short circuit current; B 2 H 6 gas is used for doping, and the conductive performance of the doped layer is better; the photoelectric conversion efficiency of the HJT solar cell is improved. Although this application case uses a lightly doped B layer close to the amorphous silicon intrinsic layer, there will still be a part of B atoms diffusing into the amorphous silicon intrinsic layer, which will affect the film quality of the amorphous silicon intrinsic layer and still have a certain degree of reduction effect on the open circuit voltage. Summary of the Invention

[0006] 1. Technical Problems to be Solved by the Invention

[0007] To overcome the deficiencies of the above-mentioned prior art, the present invention provides an HJT battery with high photoelectric conversion efficiency and its preparation method; the present invention uses a hydrogenated amorphous silicon oxide thin film as the intrinsic passivation layer and a double-diffused B-doped p-type layer to prepare a heterojunction solar cell, and the photoelectric conversion efficiency can be increased to more than 24.3%. The short circuit current and open circuit voltage are significantly improved, and the photoelectric conversion efficiency of the silicon heterojunction solar cell can be effectively improved.

[0008] 2. Technical Solution

[0009] To achieve the above object, the technical solution provided by the present invention is as follows:

[0010] An HJT battery with high photoelectric conversion efficiency of the present invention includes an N-type crystalline silicon wafer, and an intrinsic amorphous silicon layer, a SiO 2 layer, a C-doped SiO 2 layer, an amorphous silicon doped N-type layer, a TCO conductive layer and an electrode are sequentially arranged on the front of the N-type crystalline silicon wafer;

[0011] An intrinsic amorphous silicon layer, a SiO 2 layer, a C-doped SiO 2 layer, an amorphous silicon doped P-type layer, a TCO conductive layer and an electrode are sequentially arranged on the back of the N-type crystalline silicon wafer.

[0012] Further, the intrinsic amorphous silicon layer may also be a hydrogenated intrinsic amorphous silicon thin film layer.

[0013] Further, the thickness of the intrinsic amorphous silicon layer or the hydrogenated intrinsic amorphous silicon thin film layer is 3 - 10 nm.

[0014] Further, the thickness of the SiO 2 layer and the C-doped SiO 2 layer is both 1 - 5 nm.

[0015] Further, the thickness of the amorphous silicon doped P-type layer is 10 - 30 nm; the amorphous silicon doped P-type layer includes a lightly doped B amorphous silicon layer and a heavily doped B amorphous silicon layer, the lightly doped B amorphous silicon layer is close to the C-doped SiO 2 layer, and the heavily doped B amorphous silicon layer is close to the TCO conductive layer.

[0016] Further, the lightly doped B amorphous silicon layer is formed by doping with TMB gas, with a thickness of 1 - 20 nm and a band gap of 1.7 - 1.8 eV.

[0017] Further, the heavily doped B amorphous silicon layer is formed by doping with B 2 H 6 gas, with a thickness of 1 - 20 nm and a band gap of 1.4 - 1.6 eV.

[0018] Further, the thickness of the amorphous silicon doped N-type layer is 10 - 30 nm; the amorphous silicon doped N-type layer includes a lightly doped P amorphous silicon layer and a heavily doped P amorphous silicon layer, the lightly doped P amorphous silicon layer is close to the C-doped SiO 2 layer, and the heavily doped P amorphous silicon layer is close to the TCO conductive layer; the thickness of the lightly doped P amorphous silicon layer is 1 - 20 nm, and the thickness of the heavily doped P amorphous silicon layer is 1 - 20 nm. The heavily doped P amorphous silicon layer can be prepared by plasma enhanced chemical vapor deposition or by coating a liquid phosphorus source on the lightly doped P amorphous silicon layer and forming it by laser heating and curing.

[0019] A preparation method of an HJT battery with high photoelectric conversion efficiency according to the present invention includes the following steps:

[0020] Step 1: Texturing and cleaning an N-type crystalline silicon wafer;

[0021] Step 2: Forming an intrinsic amorphous silicon layer or a hydrogenated intrinsic amorphous silicon thin film layer on both sides of the N-type crystalline silicon wafer by plasma enhanced chemical vapor deposition;

[0022] Step 3: Preparing a SiO 2 layer and a C-doped SiO 2 layer by plasma enhanced chemical vapor deposition;

[0023] Step 4: Use plasma enhanced chemical vapor deposition to prepare an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer; the amorphous silicon doped N-type layer includes a lightly doped P amorphous silicon layer (i.e., an N-type amorphous silicon layer doped with lightly doped P atoms) and a heavily doped P amorphous silicon layer (i.e., an N-type amorphous silicon layer doped with heavily doped P atoms), and the amorphous silicon doped P-type layer includes a P-type amorphous silicon layer doped with lightly doped B atoms formed by doping with TMB gas and a P-type amorphous silicon layer doped with heavily doped B atoms formed by doping with B 2 H 6 gas doping.

[0024] Step 5: Deposit a TCO conductive layer using reactive ion deposition or sputtering;

[0025] Step 6: Form positive and negative Ag electrodes by screen printing, and cure the positive and negative Ag electrodes to form a good ohmic contact with the TCO conductive film.

[0026] Furthermore, in Step 4, the deposition process of the doped layer is as follows: after the background vacuum in the vacuum chamber reaches 5×10 -4 Pa, under the condition that the temperature of the silicon wafer substrate is 100 - 300 °C, using H 2 , SiH 4 , and doped TMB, B 2 H 6 , PH 3 as reaction gases, with a deposition pressure of 10 - 300 Pa, grow the amorphous silicon doped N-type layer and the amorphous silicon doped P-type layer.

[0027] Furthermore, in Step 5, the deposition process of the doped layer is as follows: after the background vacuum in the vacuum chamber reaches 5×10 -4 Pa, under the condition that the temperature of the silicon wafer substrate is 100 - 300 °C, using H 2 , SiH 4 , and doped TMB, B 2 H 6 , PH 3 as reaction gases, with a deposition pressure of 10 - 300 Pa, grow the amorphous silicon doped N-type layer and the amorphous silicon doped P-type layer on the hydrogenated amorphous carbon silicon oxide film on the back side.

[0028] Furthermore, in Step 5, the process of depositing the TCO conductive layer is as follows: use magnetron sputtering to deposit a transparent conductive ITO film on the front and back sides, the thickness of this layer of film is 70 - 110 nm, the transmittance is above 98%, and the sheet resistance is 50 - 100 Ω / □.

[0029] Further, in step six, a layer of low-temperature conductive silver paste is printed on the TCO conductive layers on the front and back surfaces respectively by screen printing, and then sintered at a low temperature of 150-300 °C to form a good ohmic contact; the thickness of the Ag grid lines is 5-50 μm, the grid line width is 20-60 μm, and the spacing is 1-5 mm.

[0030] 3. Beneficial effects

[0031] Adopting the technical solution provided by the present invention, compared with the existing known technologies, it has the following remarkable effects:

[0032] (1) For a HJT battery with high photoelectric conversion efficiency of the present invention, the amorphous silicon layer on the surface of the silicon substrate is passivated by the SiO 2 layer for the broken bonds on the surface of the amorphous silicon layer, and the C-doped SiO 2 layer accommodates and blocks the doped atoms in the p-type and n-type lightly doped amorphous silicon layers, preventing them from diffusing into the amorphous silicon layer;

[0033] (2) For a HJT battery with high photoelectric conversion efficiency of the present invention, the p-type and n-type heavily doped amorphous silicon layers can form a good electrical contact with the TCO layer; the p-type layer of the backlight-side amorphous silicon doping layer adopts a double-layer stacked structure, and the p-type doping layer close to the C-doped SiO 2 layer is doped with TMB gas, preventing the doped atom B (boron) from diffusing into the amorphous silicon intrinsic layer, thus ensuring the passivation effect of the intrinsic amorphous silicon or hydrogenated intrinsic amorphous silicon on the substrate silicon and improving the open-circuit voltage Voc; the p-type doping layer close to the intrinsic amorphous silicon layer is doped with TMB gas, which has a larger bandgap than the amorphous silicon doping layer formed by B 2 H 6 gas doping, the doped atoms have good thermal stability, and the incident light can pass through the doping layer more effectively, thereby increasing the light absorption of the crystalline silicon and improving the short-circuit current Isc; the p-type doping layer close to the TCO layer side is heavily doped with B 2 H 6 gas, the doping layer has better conductivity, the series resistance Rs of the solar cell is lower, and thus the fill factor FF is higher; ultimately improving the photoelectric conversion efficiency of the HJT solar cell. Description of the drawings

[0034] Figure 1 is a schematic structural diagram of a HJT battery with high photoelectric conversion efficiency of the present invention.

[0035] 1. N-type crystalline silicon wafer; 201(301), intrinsic amorphous silicon layer; 202(302), SiO 2 layer; 203(303), C-doped SiO 2Layers; 401, lightly doped B amorphous silicon layer; 402, heavily doped B amorphous silicon layer; 501, lightly doped P amorphous silicon layer; 502, heavily doped P amorphous silicon layer; 6(7), TCO conductive layer; 8(9), electrode. Detailed implementation mode

[0036] To further understand the content of the present invention, the present invention will be described in detail with reference to the accompanying drawings and embodiments.

[0037] Embodiment 1

[0038] Combined with Figure 1 , a HJT battery with high photoelectric conversion efficiency in this embodiment includes an N-type crystalline silicon wafer 1. On the front side of the N-type crystalline silicon wafer 1, an intrinsic amorphous silicon layer 301, a SiO 2 layer 302, a C-doped SiO 2 layer 303, an amorphous silicon doped N-type layer, a TCO conductive layer 7 and an electrode 9 are sequentially arranged; on the back side of the N-type crystalline silicon wafer 1, an intrinsic amorphous silicon layer 201, a SiO 2 layer 202, a C-doped SiO 2 layer 203, an amorphous silicon doped P-type layer, a TCO conductive layer 6 and an electrode 8 are sequentially arranged. Among them:

[0039] The thickness of the intrinsic amorphous silicon layer is 3 nm.

[0040] The thicknesses of the SiO 2 layer and the C-doped SiO 2 layer are both 1 nm.

[0041] The thickness of the amorphous silicon doped P-type layer is 10 nm, the thickness of the amorphous silicon doped N-type layer is 10 nm; the thickness of the TCO conductive layer is 70 nm.

[0042] In this embodiment, the amorphous silicon layer on the surface of the silicon matrix is passivated by the SiO 2 layer for the broken bonds on the surface of the amorphous silicon layer, and the C-doped SiO 2 layer plays a role in accommodating and blocking the doping atoms in the lightly doped p-type and n-type amorphous silicon layers to prevent them from diffusing into the amorphous silicon layer.

[0043] Embodiment 2

[0044] A HJT battery with high photoelectric conversion efficiency in this embodiment is basically the same as Embodiment 1, and the difference lies in that: the thickness of the intrinsic amorphous silicon layer is 10 nm.

[0045] The thicknesses of the SiO 2 layer and the C-doped SiO 2 layer are both 5 nm.

[0046] The thickness of the doped amorphous silicon P-type layer is 30 nm, and the thickness of the doped amorphous silicon N-type layer is 30 nm; the thickness of the TCO conductive layer is 110 nm.

[0047] Example 3

[0048] A high-photovoltage-conversion-efficiency HJT cell of this example is basically the same as that of Example 1, and the difference lies in that: the thickness of the intrinsic amorphous silicon layer is 5 nm.

[0049] The described SiO 2 layer has a thickness of 3 nm, and the C-doped SiO 2 layer has a thickness of 4 nm.

[0050] The thickness of the doped amorphous silicon P-type layer is 20 nm, and the thickness of the doped amorphous silicon N-type layer is 25 nm; the thickness of the TCO conductive layer is 100 nm.

[0051] Example 4

[0052] Combined with Figure 1 , a high-photovoltage-conversion-efficiency HJT cell of this example includes an N-type crystalline silicon wafer 1. On the front side of the N-type crystalline silicon wafer 1, a hydrogenated intrinsic amorphous silicon thin film layer 301, a SiO 2 layer 302, a C-doped SiO 2 layer 303, a doped amorphous silicon N-type layer, a TCO conductive layer 7, and an electrode 9 are sequentially arranged; on the back side of the N-type crystalline silicon wafer 1, a hydrogenated intrinsic amorphous silicon thin film layer 201, a SiO 2 layer 202, a C-doped SiO 2 layer 203, a doped amorphous silicon P-type layer, a TCO conductive layer 6, and an electrode 8 are sequentially arranged. Among them:

[0053] The thickness of the hydrogenated intrinsic amorphous silicon thin film layer (i-a-Si:H) is 3 nm.

[0054] The thicknesses of the SiO 2 layer and the C-doped SiO 2 layer are both 1 nm. The C-doped SiO 2 layer accommodates a small amount of lightly doped B or lightly doped P atoms in the way of doping the same-group SiO 2 layer, avoiding unnecessary doping of the hydrogenated intrinsic amorphous silicon thin film layer (i-a-Si:H) and affecting the passivation quality.

[0055] The thickness of the doped amorphous silicon P-type layer is 20 nm. The doped amorphous silicon P-type layer includes a lightly doped B amorphous silicon layer 401 and a heavily doped B amorphous silicon layer 402. The lightly doped B amorphous silicon layer 401 is close to the C-doped SiO 2Layer 203, the heavily boron-doped amorphous silicon layer 402 is close to the TCO conductive layer 6. By changing the doping source and doping concentration, the bandgap width of the doped layer can be modulated to form a doped layer with a large bandgap width and high thermal stability on the light-receiving surface, which is beneficial for more incident light to pass through the doped layer on the light-receiving surface, and more light waves are effectively absorbed to generate photo-generated carriers. Specifically in this embodiment, the lightly boron-doped amorphous silicon layer 401 is doped with TMB gas, has a thickness of 1 nm, and a bandgap width of 1.8 eV. The heavily boron-doped amorphous silicon layer 402 is doped with 2 H 6 gas, has a thickness of 19 nm, and a bandgap width of 1.6 eV.

[0056] The thickness of the doped N-type amorphous silicon layer is 20 nm; this doped N-type amorphous silicon layer includes a lightly phosphorus-doped amorphous silicon layer 501 and a heavily phosphorus-doped amorphous silicon layer 502. The lightly phosphorus-doped amorphous silicon layer 501 is close to the C-doped SiO 2 layer 303, and the heavily phosphorus-doped amorphous silicon layer 502 is close to the TCO conductive layer 7; the thickness of the lightly phosphorus-doped amorphous silicon layer 501 is 1 nm, and the thickness of the heavily phosphorus-doped amorphous silicon layer 502 is 19 nm.

[0057] The thickness of the TCO conductive layer is 70 nm.

[0058] In this embodiment, the heavily doped p-type and n-type amorphous silicon layers and the TCO layer can form good electrical contact; the p-type layer of the amorphous silicon doped layer on the backlight side adopts a double-layer stacked structure. The p-type doped layer close to the C-doped SiO 2 layer is doped with TMB gas to prevent the doping atom B (boron) from diffusing into the intrinsic amorphous silicon layer, thereby ensuring the passivation effect of the intrinsic amorphous silicon or hydrogenated intrinsic amorphous silicon on the substrate silicon and improving the open-circuit voltage Voc; the p-type doped layer close to the near-intrinsic amorphous silicon layer is doped with TMB gas, which has a larger bandgap width than the amorphous silicon doped layer formed by 2 H 6 gas doping, and the doping atoms have good thermal stability. Incident light can pass through this doped layer more effectively, thereby increasing the light absorption of crystalline silicon and improving the short-circuit current Isc; the p-type doped layer on the side close to the TCO layer is heavily doped with 2 H 6 gas, the conductive performance of the doped layer is better, the series resistance Rs of the solar cell is lower, and thus the fill factor FF is higher; ultimately, the photoelectric conversion efficiency of the HJT solar cell is improved.

[0059] The preparation process of the HJT battery with high photoelectric conversion efficiency in this embodiment is as follows:

[0060] Step 1: Texturize and clean the N-type crystalline silicon wafer 1;

[0061] Step 2: Form a hydrogenated intrinsic amorphous silicon thin film layer on both sides of the N-type crystalline silicon wafer 1 by plasma-enhanced chemical vapor deposition method;

[0062] Step 3: Use the plasma-enhanced chemical vapor deposition (PECVD) method to prepare a SiO 2 layer and a C-doped SiO 2 layer;

[0063] Step 4: Use plasma-enhanced chemical vapor deposition to prepare an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer; the amorphous silicon doped N-type layer includes a lightly doped P amorphous silicon layer (i.e., an N-type amorphous silicon layer doped with lightly doped P atoms) and a heavily doped P amorphous silicon layer (i.e., an N-type amorphous silicon layer doped with heavily doped P atoms), and the amorphous silicon doped P-type layer includes a P-type amorphous silicon layer doped with lightly doped B atoms formed by doping with TMB gas and a P-type amorphous silicon layer doped with heavily doped B atoms formed by doping with B 2 H 6 gas.

[0064] The deposition process of the doping layer is as follows: after the background vacuum in the vacuum chamber reaches 5×10 -4 Pa, at the condition of the silicon wafer substrate temperature of 100 °C, using H 2 , SiH 4 , and doped TMB, B 2 H 6 , PH 3 as reaction gases, with a deposition pressure of 10 Pa, grow an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer on the hydrogenated amorphous carbon silicon oxide thin film on the back side.

[0065] Step 5: Deposit a transparent conductive ITO thin film on the front and back by magnetron sputtering method, and the transmittance of this layer of film is above 98%, and the sheet resistance is 50 Ω / □.

[0066] Step 6: Screen-print a layer of low-temperature conductive silver paste on the front and back TCO conductive layers respectively, and then sinter at a low temperature of 150 °C to form a good ohmic contact; the thickness of the Ag grid line is 5 μm, the grid line width is 20 μm, and the spacing is 1 mm.

[0067] In this embodiment, a heterojunction solar cell is prepared with a hydrogenated amorphous silicon oxide thin film as the intrinsic passivation layer and a double-diffusion B-doped p-type layer, and the photoelectric conversion efficiency can be increased to above 24.3%, and the short-circuit current and open-circuit voltage are significantly improved, which can effectively improve the photoelectric conversion efficiency of the silicon heterojunction solar cell.

[0068] Example 5

[0069] A high-photoelectric conversion efficiency HJT battery in this embodiment is basically the same as that in Example 4, and the difference is as follows:

[0070] The thickness of the hydrogenated intrinsic amorphous silicon thin film layer (i-a-Si:H) is 10 nm.

[0071] The described SiO 2 layer and the C-doped SiO 2 layer both have a thickness of 5 nm.

[0072] The thickness of the doped p-type amorphous silicon layer is 10 nm, the thickness of the lightly doped B amorphous silicon layer 401 is 8 nm, and the bandgap is 1.7 eV. The thickness of the heavily doped B amorphous silicon layer 402 is 2 nm, and the bandgap is 1.4 eV.

[0073] The thickness of the doped n-type amorphous silicon layer is 10 nm, the thickness of the lightly doped P amorphous silicon layer 501 is 8 nm, and the thickness of the heavily doped P amorphous silicon layer 502 is 2 nm.

[0074] The preparation process of the HJT battery with high photoelectric conversion efficiency in this embodiment is as follows:

[0075] Step 1: Texturize and clean the n-type crystalline silicon wafer 1.

[0076] Step 2: Form a hydrogenated intrinsic amorphous silicon thin film layer on both sides of the n-type crystalline silicon wafer 1 by plasma-enhanced chemical vapor deposition.

[0077] Step 3: Use plasma-enhanced chemical vapor deposition (PECVD) to prepare the SiO 2 layer and the C-doped SiO 2 layer.

[0078] Step 4: Use plasma-enhanced chemical vapor deposition to prepare the doped n-type amorphous silicon layer and the doped p-type amorphous silicon layer; the deposition process of the doped layer is as follows: after the background vacuum in the vacuum chamber reaches 5×10 -4 Pa, at a silicon wafer substrate temperature of 150 °C, using H 2 , SiH 4 , and the doped TMB, B 2 H 6 , PH 3 as reaction gases, with a deposition pressure of 50 Pa, grow the doped n-type amorphous silicon layer and the doped p-type amorphous silicon layer on the hydrogenated amorphous carbon silicon oxide thin film on the back.

[0079] Step 5: Deposit a transparent conductive ITO thin film on the front and back by magnetron sputtering. The thickness of this layer of film is 80 nm, the transmittance is above 98%, and the sheet resistance is 50 Ω / □.

[0080] Step 6: Use screen printing to print a layer of low-temperature conductive silver paste on the TCO conductive layers on the front and back respectively, and then sinter at a low temperature of 150 °C to form a good ohmic contact; the thickness of the Ag grid lines is 15 μm, the grid line width is 30 μm, and the spacing is 3 mm.

[0081] Example 6

[0082] A high-photovoltaic conversion efficiency HJT cell in this example is basically the same as that in Example 4, and the difference lies in:

[0083] The thickness of the hydrogenated intrinsic amorphous silicon thin film layer (i-a-Si:H) is 6 nm.

[0084] The 2 SiO layer and the C-doped SiO 2 layer both have a thickness of 3 nm.

[0085] The thickness of the amorphous silicon doped P-type layer is 30 nm, the thickness of the lightly doped B amorphous silicon layer 401 is 18 nm, and the band gap is 1.75 eV. The thickness of the heavily doped B amorphous silicon layer 402 is 12 nm, and the band gap is 1.5 eV.

[0086] The thickness of the amorphous silicon doped N-type layer is 30 nm, the thickness of the lightly doped P amorphous silicon layer 501 is 18 nm, and the thickness of the heavily doped P amorphous silicon layer 502 is 12 nm.

[0087] The preparation process of the high-photovoltaic conversion efficiency HJT cell in this example is as follows:

[0088] Step 1: Perform texturing and cleaning on the N-type crystalline silicon wafer 1;

[0089] Step 2: Form a hydrogenated intrinsic amorphous silicon thin film layer on both sides of the N-type crystalline silicon wafer 1 by plasma-enhanced chemical vapor deposition;

[0090] Step 3: Use plasma-enhanced chemical vapor deposition (PECVD) method to prepare the SiO 2 layer and the C-doped SiO 2 layer;

[0091] Step 4: Use plasma-enhanced chemical vapor deposition to prepare the amorphous silicon doped N-type layer and the amorphous silicon doped P-type layer; the deposition process of the doped layer is: after the background vacuum in the vacuum chamber reaches 5×10 -4 Pa, under the condition of the silicon wafer substrate temperature of 300 °C, with H 2 , SiH 4 , and the doped TMB, B 2 H 6 , PH 3The reaction gas is used, and the deposition pressure is 300 Pa. An amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer are grown on the hydrogenated amorphous carbon silicon oxide film on the back surface.

[0092] Step Five: Deposit a transparent conductive ITO film on the front and back surfaces by reactive ion deposition. The thickness of this layer of film is 110 nm, the transmittance is above 98%, and the sheet resistance is 100 Ω / sq.

[0093] Step Six: Screen-print a layer of low-temperature conductive silver paste on the TCO conductive layers on the front and back surfaces respectively, and then sinter at a low temperature of 190 °C to form a good ohmic contact; the thickness of the Ag grid line is 50 μm, the grid line width is 60 μm, and the spacing is 5 mm.

[0094] The present invention and its embodiments are schematically described above. This description is not restrictive, and only one of the embodiments of the present invention is shown in the drawings. The actual structure is not limited thereto. Therefore, if those of ordinary skill in the art are inspired by it and design similar structural modes and embodiments to this technical solution without creative efforts without departing from the purpose of the present invention, they shall fall within the protection scope of the present invention.

Claims

1. A HJT cell with high photoelectric conversion efficiency, comprising an N-type crystalline silicon wafer (1), Characterized in that: On the front side of the N-type crystalline silicon wafer (1), an intrinsic amorphous silicon layer (301), a SiO 2 layer (302), a C-doped SiO 2 layer (303), an amorphous silicon doped N-type layer, a TCO conductive layer (7), and an electrode (9) are sequentially arranged; On the back surface of the N-type crystalline silicon wafer (1), an intrinsic amorphous silicon layer (201), a SiO 2 layer (202), a C-doped SiO 2 layer (203), an amorphous silicon doped P-type layer, a TCO conductive layer (6) and an electrode (8) are sequentially provided; The amorphous silicon doped N-type layer includes a lightly doped P amorphous silicon layer (501) and a heavily doped P amorphous silicon layer (502). The lightly doped P amorphous silicon layer (501) is close to the C-doped SiO 2 layer (303), and the heavily doped P amorphous silicon layer (502) is close to the TCO conductive layer (7); The amorphous silicon doped P-type layer includes a lightly doped B amorphous silicon layer (401) and a heavily doped B amorphous silicon layer (402). The lightly doped B amorphous silicon layer (401) is close to the C doped SiO 2 layer (203), and the heavily doped B amorphous silicon layer (402) is close to the TCO conductive layer (6).

2. A HJT cell with high photoelectric conversion efficiency according to claim 1, Characterized in that: The intrinsic amorphous silicon layer can also be a hydrogenated intrinsic amorphous silicon thin film layer.

3. A HJT cell with high photoelectric conversion efficiency according to claim 2, Characterized in that: The thickness of the intrinsic amorphous silicon layer or the hydrogenated intrinsic amorphous silicon thin film layer is 3 - 10 nm.

4. A HJT cell with high photoelectric conversion efficiency according to claim 3, Characterized in that: The described SiO 2 layer and the C-doped SiO 2 layer both have a thickness of 1 - 5 nm.

5. A HJT cell with high photoelectric conversion efficiency according to any one of claims 1 - 4, Characterized in that: The thickness of the amorphous silicon doped P-type layer is 10 - 30 nm.

6. A HJT cell with high photoelectric conversion efficiency according to claim 5, Characterized in that: The lightly doped B amorphous silicon layer (401) is formed by doping with TMB gas, with a thickness of 1 - 20 nm and a band gap of 1.7 - 1.8 eV.

7. A HJT cell with high photoelectric conversion efficiency according to claim 6, Characterized in that: The heavily doped B amorphous silicon layer (402) is formed by doping with B 2 H 6 gas, with a thickness of 1 - 20 nm and a band gap of 1.4 - 1.6 eV.

8. A HJT cell with high photoelectric conversion efficiency according to any one of claims 1 - 4, Characterized in that: The thickness of the amorphous silicon doped N-type layer is 10 - 30 nm; the thickness of the lightly doped P amorphous silicon layer (501) is 1 - 20 nm, and the thickness of the heavily doped P amorphous silicon layer (502) is 1 - 20 nm.

9. A HJT cell with high photoelectric conversion efficiency according to claim 7, Characterized in that: The thickness of the amorphous silicon doped N-type layer is 10 - 30 nm; the thickness of the lightly doped P amorphous silicon layer (501) is 1 - 20 nm, and the thickness of the heavily doped P amorphous silicon layer (502) is 1 - 20 nm.

10. A preparation method for a HJT cell with high photoelectric conversion efficiency according to any one of claims 1 - 9, Characterized in that, Comprising the following steps: Step 1: Texturing and cleaning the N-type crystalline silicon wafer (1); Step 2: Forming an intrinsic amorphous silicon layer or a hydrogenated intrinsic amorphous silicon thin film layer on both sides of the N-type crystalline silicon wafer (1) by plasma enhanced chemical vapor deposition; Step 3: Prepare the SiO layer and the C-doped SiO layer by plasma-enhanced chemical vapor deposition; 2 2 ​​ Step 4: Preparing an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer using plasma enhanced chemical vapor deposition; Step 5: Depositing a TCO conductive layer using reactive ion deposition or sputtering; Step 6: Forming front and back electrodes by screen printing.

11. A preparation method for a HJT cell with high photoelectric conversion efficiency according to claim 10, Characterized in that: In Step 4, the deposition process of the doping layer is as follows: After the background vacuum in the vacuum chamber reaches 5×10 -4 Pa, under the condition that the temperature of the silicon wafer substrate is 100 - 300 °C, using H 2 , SiH 4 , and the doped TMB, B 2 H 6 , PH 3 as reaction gases, the deposition pressure is 10 - 300 Pa, and an amorphous silicon doped N-type layer and an amorphous silicon doped P-type layer are grown.

12. A preparation method for a HJT cell with high photoelectric conversion efficiency according to claim 11, Characterized in that: In step 5, the process of depositing the TCO conductive layer is: depositing a transparent conductive ITO thin film on the front and back by magnetron sputtering, with the thickness of this layer being 70 - 110 nm, the transmittance being above 98%, and the sheet resistance being 50 - 100 Ω / □.

13. A preparation method for a HJT cell with high photoelectric conversion efficiency according to claim 12, It is characterized in that: In step six, a layer of low-temperature conductive silver paste is printed on the TCO conductive layers on the front and back respectively by screen printing, and then sintered at a low temperature of 150-300 °C to form a good ohmic contact; the thickness of the Ag grid line is 5-50 μm, the grid line width is 20-60 μm, and the spacing is 1-5 mm.

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