Semiconductor Structure and Method for Preparing the Same

Abstract

The present invention relates to a semiconductor structure and a method for manufacturing the same; the method includes the following steps: providing a substrate, which is divided into a plurality of chip regions; forming a protective layer on the substrate, the protective layer covering the sawing channels and the chip regions; performing exposure and development on the protective layer to form a plurality of grooves in the regions of the protective layer covering the chip regions, the depth of the grooves being less than the thickness of the protective layer. By forming a plurality of grooves in the regions of the protective layer covering the chip regions, the surface roughness and surface area of the protective layer can be increased, thereby improving the adhesion between the protective layer and the encapsulation layer during the subsequent packaging of the above semiconductor structure.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor device manufacturing, and particularly to a semiconductor structure and a method for preparing the same. Background Art

[0002] When manufacturing a semiconductor wafer, a protective layer (for example, Polyimide) is coated on the surface of the wafer to protect the chips formed in the wafer. At the same time, the protective layer can also be used as an adjacent material to the molding compound during the subsequent packaging. However, due to the existing protective layer being formed by a spin coating process, the upper surface of the protective layer is nearly a flat surface. Except for the openings of the test bond pads, the surfaces of most areas of the protective layer are flat surfaces. And the protective layer with a nearly flat surface has poor adhesion performance with the molding compound during the subsequent packaging, which easily leads to delamination between the protective layer and the molding compound, thus affecting the performance of the device. Summary of the Invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same to solve the problem that the surface of the protective layer on the wafer surface in the semiconductor structure in the prior art is nearly flat, resulting in poor adhesion performance between the protective layer and the molding compound, which easily leads to delamination between the protective layer and the molding compound, and further affects the performance of the device.

[0004] To achieve the above object, on the one hand, the present invention provides a method for preparing a semiconductor structure, including the following steps:

[0005] Provide a substrate, and the substrate is divided into several chip regions;

[0006] Form a protective layer on the substrate, and the protective layer covers the saw streets and the chip regions;

[0007] Expose and develop the protective layer to form several grooves in the area where the protective layer covers the chip regions, and the depth of the grooves is less than the thickness of the protective layer.

[0008] The above method for preparing a semiconductor structure can increase the surface roughness and surface area of the protective layer by forming several grooves in the area where the protective layer covers the chip regions, thereby improving the adhesion between the protective layer and the molding compound during the subsequent packaging.

[0009] In one embodiment, exposing and developing the protective layer to form several grooves in the area where the protective layer covers the chip regions includes the following steps:

[0010] Place a first photomask above the protective layer, and a plurality of first light-transmitting regions are formed in the region of the first photomask corresponding to the chip region;

[0011] Based on the first photomask, perform a first exposure on the protective layer at a first exposure dose or a first exposure energy;

[0012] Develop the exposed protective layer; after development, the thickness of the protective layer removed in the exposed area of the first exposure is less than the thickness of the protective layer.

[0013] In one embodiment, a dicing channel is further formed in the substrate, and the dicing channel divides the substrate into a plurality of the chip regions; test pads are formed in the dicing channel, and the protective layer covers the test pads; before development after the first exposure, the following steps are further included:

[0014] Remove the first photomask; place a second photomask above the protective layer, and a second light-transmitting region is formed in the region of the second photomask corresponding to the test pad;

[0015] Based on the second photomask, perform a second exposure on the protective layer at a second exposure dose or a second exposure energy; the second exposure dose is the minimum exposure dose at which the protective layer in the exposed area of the second exposure is completely removed after subsequent development, and the second exposure energy is the minimum exposure energy at which the protective layer in the exposed area of the second exposure is completely removed after subsequent development; the second exposure dose is greater than the first exposure dose, and the second exposure energy is greater than the first exposure energy.

[0016] In one embodiment, the steps of exposing and developing the protective layer to form a plurality of the grooves in the region where the protective layer covers the chip region include the following:

[0017] Place a photomask above the protective layer, and a plurality of light-transmitting patterns are formed in the region of the photomask corresponding to the chip region, and each of the light-transmitting patterns includes a plurality of first light-transmitting regions;

[0018] Based on the photomask, expose the protective layer;

[0019] Develop the exposed protective layer; after development, the thickness of the protective layer removed in the exposed area corresponding to the first light-transmitting region is less than the thickness of the protective layer.

[0020] In one embodiment, the plurality of first light-transmitting regions are arranged at intervals in a strip shape, in a grid shape, or in a random arrangement.

[0021] In one embodiment, a cutting path is formed in the substrate, and the cutting path divides the substrate into a plurality of chip areas; a test pad is formed in the cutting path, and the protective layer covers the test pad; a second light-transmitting area is formed in the area of the mask corresponding to the test pad; after development, the protective layer in the exposure area corresponding to the second light-transmitting area is completely removed.

[0022] In one embodiment, before forming the protective layer on the substrate, the step of forming a passivation layer on the upper surface of the substrate is also included; the protective layer is formed on the upper surface of the passivation layer; after exposure, the following steps are also included: curing the protective layer; etching and removing the passivation layer and part of the substrate in the area corresponding to the test pad to expose the test pad.

[0023] In one embodiment, after forming a plurality of the grooves in the area of the protective layer covering the chip area, the method further includes forming a plastic sealing layer on the upper surface of the protective layer; the thickness of the plastic sealing layer is greater than the depth of the grooves.

[0024] The present invention also provides a semiconductor structure, comprising:

[0025] A substrate, wherein the substrate is divided into a plurality of chip areas;

[0026] A protective layer is located on the substrate and covers the chip area; a plurality of grooves are formed in the area of the protective layer covering the chip area, and the depth of the grooves is less than the thickness of the protective layer.

[0027] The protective layer in the semiconductor structure above forms several grooves in the chip area, which can increase the surface roughness and surface area of the protective layer, thereby improving the adhesion between the protective layer and the plastic layer during the subsequent packaging.

[0028] In one embodiment, a plurality of the grooves are arranged in strips, in grids, or randomly.

[0029] In one embodiment, the protective layer includes a polyimide layer or a polybenzoxazole layer.

[0030] In one embodiment, a cutting line is formed in the substrate, and the cutting line divides the substrate into a plurality of chip areas; a test pad is formed in the cutting line, and an opening is formed in the protective layer, and the opening exposes the test pad.

[0031] In one embodiment, the semiconductor structure further includes a passivation layer, and the passivation layer is located on the upper surface of the substrate; the protective layer is located on the upper surface of the passivation layer.

[0032] In one embodiment, the semiconductor structure further includes a plastic encapsulation layer that covers the upper surface of the protective layer, and the thickness of the plastic encapsulation layer is greater than the depth of the groove.

[0033] In one embodiment, the depth of the groove is 1 / 3 to 3 / 4 of the thickness of the protective layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0035] Figure 2 is a top view structural schematic diagram of the structure obtained after providing a substrate in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0036] Figure 3 is along Figure 2 the cross-sectional structural schematic diagram in the A-A direction in;

[0037] Figure 4 is a cross-sectional structural schematic diagram of the structure obtained after forming a passivation layer on the upper surface of a substrate in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0038] Figure 5 is a cross-sectional structural schematic diagram of the structure obtained after forming a protective layer on the upper surface of the passivation layer in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0039] Figure 6 is a top view structural schematic diagram of the first photomask used in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0040] Figure 7 is a top view structural schematic diagram of the second photomask provided in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0041] Figure 8 is a top view structural schematic diagram of the structure obtained after performing two exposures and developing using the first photomask and the second photomask in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0042] Figure 9 is along Figure 8 the cross-sectional structural schematic diagram in the A-A direction in;

[0043] Figure 10 is a cross-sectional structural schematic diagram of the structure obtained after forming a plastic encapsulation layer on the upper surface of the exposed protective layer in a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0044] Figure 11 is a top view structural schematic diagram of the photomask used in a method for manufacturing a semiconductor structure according to another embodiment of the present invention;

[0045] Figure 12 For the manufacturing method of the semiconductor structure in another embodiment of the present invention, the top view structural schematic diagram of the structure obtained after exposure using the photomask as shown in Figure 11 is presented.

[0046] Explanation of reference numerals in the drawings:

[0047] 10 Substrate

[0048] 101 Sawing street

[0049] 102 Chip area

[0050] 111 Test pad

[0051] 112 Metal wire layer

[0052] 12 Protective layer

[0053] 121 Groove

[0054] 13 First photomask

[0055] 131, 151 First light-transmitting area

[0056] 14 Second photomask

[0057] 141, 152 Second light-transmitting area

[0058] 15 Photomask

[0059] 16 Passivation layer

[0060] 17 Encapsulation layer Detailed implementation manners

[0061] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0062] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element and integrated with it, or there may be intermediate elements present at the same time. The terms "installed", "one end", "the other end" and similar expressions used herein are for illustrative purposes only.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0064] In one embodiment, Figure 1 As shown, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0065] S11: providing a substrate, which is divided into several chip areas;

[0066] S12: forming a protective layer on the substrate, the protective layer and the chip area;

[0067] S13: exposing and developing the protective layer to form a plurality of grooves in the area where the protective layer covers the chip area, wherein the depth of the grooves is less than the thickness of the protective layer.

[0068] In one example, if Figure 2 and Figure 3 As shown, the substrate 10 provided in step S11 may include, but is not limited to, a silicon substrate. Slicing streets 101 are also formed within the substrate 10, dividing the substrate 10 into a plurality of chip regions 102. The number of scribe streets 101 within the substrate and the number of chip regions 102 isolated by the scribe streets 101 can be set according to actual needs and are not limited here.

[0069] In one example, a chip (not shown) may be formed in the chip region 102. Figure 2 and Figure 3 Only the metal lines 112 in the chip are shown schematically in the figure); a test structure (not shown) and a test pad 111 may be formed in the dicing street 101. The test pad 111 is electrically connected to the test structure for electrically leading out the test structure.

[0070] In one example, after step S11, the following steps are further included: forming a passivation layer 16 on the upper surface of the substrate 10, such as Figure 4 As shown, the passivation layer 16 covers the chip area 102. The passivation layer 16 may include a single layer structure or a stacked layer structure including multiple material layers. The passivation layer 16 may include, but is not limited to, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0071] In one example, if Figure 5 As shown, the protection layer 12 can be formed on the upper surface of the passivation layer 16 by using, but not limited to, a spin coating process.

[0072] In one example, the protective layer 12 may include any integrated circuit protective layer that can be exposed, developed and removed, such as a photosensitive material layer; specifically, the protective layer 12 may include but is not limited to a polyimide layer or a polybenzoxazole (PBO) layer.

[0073] In an optional example, step S13 may include the following steps:

[0074] S131: placing a first mask 13 above the protective layer 12, wherein the first mask 13 forms a plurality of first light-transmitting areas 131 in an area corresponding to the chip area 102; Figure 6 After the first mask 13 is placed on the protective layer 12, the orthographic projection of the mask 13 on the upper surface of the protective layer 12 can completely cover the upper surface of the mask 13;

[0075] S132: performing a first exposure on the protective layer 12 at a first exposure dose or a first exposure energy based on the first mask 13;

[0076] S133 : developing the exposed protective layer 12 ; after development, the thickness of the protective layer 12 removed from the first exposed area is less than the thickness of the protective layer 12 .

[0077] In one example, when the test pad 111 is formed in the dicing street 101, step S132 further includes the following steps between step S133:

[0078] Remove the first mask 13; place the second mask 14 above the protective layer 12, the second mask 14 corresponding to the test pad 111 is formed with a second light-transmitting area 141; the second mask 14 as Figure 7 After the second mask 14 is placed above the protective layer 12, the orthographic projection of the second mask 14 on the upper surface of the protective layer 12 can completely cover the upper surface of the protective layer 12;

[0079] The protective layer 12 is exposed for the second time based on the second mask 14 at a second exposure dose or a second exposure energy; the second exposure dose is the minimum exposure dose at which the protective layer 12 in the exposure area of the second exposure is completely removed after subsequent development, and the second exposure energy is the minimum exposure energy at which the protective layer 12 in the exposure area of the second exposure is completely removed after subsequent development; the second exposure dose is greater than the first exposure dose, and the second exposure energy is greater than the first exposure energy.

[0080] Based on the first exposure of the first mask 13 at the first exposure dose or the first exposure energy, since the first exposure dose or the first exposure energy is small, the exposure depth of the first light-transmitting area 131 is less than the thickness of the protective layer 12, that is, only a part of the depth of the protective layer 12 is removed during the development of the exposed area after the first exposure; that is, after the development, a plurality of grooves 121 corresponding to the first exposure areas 131 are formed in the area of the protective layer 12 covering the chip area 102, such as Figure 8 and Figure 9 As shown; based on the second mask 14, a second exposure is performed under a second exposure dose or a second exposure energy. Since the second exposure dose or the second exposure energy is larger, the protective layer 12 in the exposed area after the second exposure can be completely removed during the development process, that is, after development, the protective layer 12 in the area corresponding to the test pad 111 where an opening needs to be formed is completely removed.

[0081] In one example, the depth of the groove 121 can be set according to actual needs, but the depth of the groove 121 cannot be too deep or too shallow; preferably, in this embodiment, the depth of the groove 121 can be 1 / 3 to 3 / 4 of the thickness of the protective layer 12; if the depth of the groove 121 is less than 1 / 3 of the thickness of the protective layer 12, it will not play a role in enhancing the bonding; if the depth of the groove 121 is greater than 3 / 4 of the thickness of the protective layer 12, it may cause damage to the structural stability of the device itself.

[0082] In one example, several first light-transmitting areas 131 may be arranged in strips, crosses or randomly distributed; specifically, the irregular arrangement of several first light-transmitting areas 131 may be that the first light-transmitting areas 131 have the same shape, but several first light-transmitting areas 131 are arranged in a disorderly manner; or the first light-transmitting areas 131 may have different shapes, and several first light-transmitting areas 131 are arranged in a disorderly manner, and so on.

[0083] In one example, step S13 further includes the following steps:

[0084] S14: curing the protective layer 12; specifically, the protective layer 12 may be cured by, but is not limited to, a baking technique;

[0085] S15: Etching and removing the passivation layer 16 and a portion of the substrate 10 in the area corresponding to the test pad 111 to expose the test pad 111, that is, exposing the upper surface of the test pad 111 after etching; specifically, the passivation layer 16 and a portion of the substrate 10 in the area corresponding to the test pad 111 can be etched away by, but is not limited to, an etching process.

[0086] In one example, after step S15, the following steps may further be included: a step of forming a molding layer 17 on the upper surface of the protective layer 12; the thickness of the molding layer 17 is greater than the depth of the groove 121, as Figure 10 shown.

[0087] In another alternative example, as Figure 11 shown, step S13 may further include the following steps:

[0088] S131: Place the photomask 15 above the protective layer 16. A plurality of first light-transmitting regions 151 are formed in the region of the photomask 15 corresponding to the chip region 102; the photomask 15 is as Figure 11 shown; after the photomask 15 is placed above the protective layer 12, the orthographic projection of the photomask 15 on the upper surface of the protective layer 12 may completely cover the upper surface of the protective layer 12;

[0089] S132: Expose the protective layer 12 based on the photomask 15;

[0090] S133: Develop the exposed protective layer 12; the thickness of the protective layer 12 removed in the exposed region corresponding to the first light-transmitting region 151 after development is less than the thickness of the protective layer 12.

[0091] In one example, when a test pad 111 is formed in the scribe lane 101, a second light-transmitting region 152 is further formed in the region of the photomask 15 corresponding to the test pad 111; the protective layer 12 in the exposed region corresponding to the second light-transmitting region 152 is completely removed after development.

[0092] Due to the very small size of the first light-transmitting region 151, during the exposure process, due to the influence of diffraction of the exposure light, etc., the depth of the protective layer 12 exposed by the first light-transmitting region 151 is less than the depth of the protective layer 12 itself. During the development process, only a partial depth of the protective layer 12 in the exposed region of the first light-transmitting region 151 is removed. That is, after development, a plurality of grooves 121 corresponding one-to-one to the first light-transmitting regions 151 are formed in the portion of the protective layer 12 corresponding to the first light-transmitting regions 151, as Figure 12 shown.

[0093] By forming a plurality of grooves 121 in the chip region 102 covered by the protective layer 12 in the preparation method of the above semiconductor structure, the surface roughness and surface area of the protective layer 12 can be increased, so that the adhesion between the protective layer 12 and the molding layer 17 can be increased after the molding layer 17 is formed on the upper surface of the protective layer 12.

[0094] In another embodiment, please continue to refer to FIGS. 8 to Figure 10 and Figure 12The present invention also provides a semiconductor structure, which includes: a substrate 10, which is divided into a plurality of chip areas 102; a protective layer 12, which is located on the substrate 10 and covers the chip areas 102; a plurality of grooves 121 are formed in the area of the protective layer 12 covering the chip areas 102, and the depth of the grooves 121 is less than the thickness of the protective layer 12.

[0095] In one example, the substrate 10 may include, but is not limited to, a silicon substrate. Slicing streets 101 are formed within the substrate 10 , dividing the substrate 10 into a plurality of chip regions 102 . The number of scribe streets 101 within the substrate 10 and the number of chip regions 102 isolated by the scribe streets 101 can be set based on actual needs and are not limited herein.

[0096] In one example, a chip (not shown) may be formed in the chip region 102. Figure 8 and Figure 10 Only the metal lines 112 in the chip are shown schematically in the figure); a test structure (not shown) and a test pad 111 may be formed in the dicing street 101. The test pad 111 is electrically connected to the test structure for electrically leading out the test structure.

[0097] In one example, the protective layer 12 may include any integrated circuit protective layer that can be exposed, developed and removed, such as a photosensitive material layer; specifically, the protective layer 12 may include but is not limited to a polyimide layer or a polybenzoxazole (PBO) layer.

[0098] In one example, the plurality of grooves 121 may be arranged in strips at intervals, connected to each other in a grid-like distribution, or randomly distributed.

[0099] In one example, the depth of the groove 121 can be set according to actual needs, but the depth of the groove 121 cannot be too deep or too shallow; preferably, in this embodiment, the depth of the groove 121 can be 1 / 3 to 3 / 4 of the thickness of the protective layer 12; if the depth of the groove 121 is less than 1 / 3 of the thickness of the protective layer 12, it will not play a role in enhancing the bonding; if the depth of the groove 121 is greater than 3 / 4 of the thickness of the protective layer 12, it may cause damage to the structural stability of the device itself.

[0100] In one example, the semiconductor structure further includes a passivation layer 16, which is located on the upper surface of the substrate 10. The protective layer 12 is located on the upper surface of the passivation layer 16. The passivation layer 16 covers the dicing street 101 and the chip region 102. The passivation layer 16 may include a single layer structure or a stacked structure including multiple material layers. The passivation layer 16 may include, but is not limited to, at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0101] In one example, when test pads 111 are formed in the scribe lane 101, openings (not shown) are further formed in the protective layer 12. The openings penetrate through the protective layer 12, the passivation layer 16 and extend into the substrate 10 to expose the test pads 111.

[0102] In one example, the semiconductor structure further includes a molding layer 17. The molding layer 17 covers the upper surface of the protective layer 12, and the thickness of the molding layer 17 is greater than the depth of the groove 121.

[0103] The protective layer 12 in the above semiconductor structure covers a plurality of grooves 121 formed in the chip region 102, which can increase the surface roughness and surface area of the protective layer 12, so as to increase the adhesion between the protective layer 12 and the molding layer 17 after the molding layer 17 is formed on the upper surface of the protective layer 12.

[0104] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0105] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including the following steps: Providing a substrate, which is divided into a plurality of chip regions; Forming a protective layer on the substrate, and the protective layer covers the chip regions; Performing exposure and development on the protective layer to form a plurality of grooves in the area where the protective layer covers the chip regions, and the depth of the grooves is less than the thickness of the protective layer; wherein, performing exposure and development on the protective layer to form a plurality of the grooves in the area where the protective layer covers the chip regions includes the following steps: Placing a first photomask above the protective layer, and a plurality of first light-transmitting regions are formed in the area of the first photomask corresponding to the chip regions; Performing a first exposure on the protective layer based on the first photomask at a first exposure dose or a first exposure energy; Developing the exposed protective layer; the thickness of the protective layer removed in the exposed area after the first exposure is less than the thickness of the protective layer; wherein, a dicing channel is further formed in the substrate, and the substrate is divided into a plurality of the chip regions by the dicing channel; test pads are formed in the dicing channel, and the protective layer covers the test pads; before developing after the first exposure, the following steps are further included: Removing the first photomask; placing a second photomask above the protective layer, and a second light-transmitting region is formed in the area of the second photomask corresponding to the test pads; Performing a second exposure on the protective layer based on the second photomask at a second exposure dose or a second exposure energy; the second exposure dose is the minimum exposure dose at which the protective layer in the exposed area after the second exposure is completely removed after subsequent development, and the second exposure energy is the minimum exposure energy at which the protective layer in the exposed area after the second exposure is completely removed after subsequent development; the second exposure dose is greater than the first exposure dose, and the second exposure energy is greater than the first exposure energy; Wherein, after forming a plurality of the grooves in the area where the protective layer covers the chip regions, a step of forming a plastic encapsulation layer on the upper surface of the protective layer is further included; the thickness of the plastic encapsulation layer is greater than the depth of the grooves.

2. A method for preparing a semiconductor structure, characterized in that, Including the following steps: Providing a substrate, which is divided into a plurality of chip regions; Forming a protective layer on the substrate, and the protective layer covers the chip regions; Performing exposure and development on the protective layer to form a plurality of grooves in the area where the protective layer covers the chip regions, and the depth of the grooves is less than the thickness of the protective layer; Wherein, performing exposure and development on the protective layer to form a plurality of the grooves in the area where the protective layer covers the chip regions includes the following steps: Placing a photomask above the protective layer, and a plurality of light-transmitting patterns are formed in the area of the photomask corresponding to the chip regions, and each of the light-transmitting patterns includes a plurality of first light-transmitting regions; Performing exposure on the protective layer based on the photomask; Developing the exposed protective layer; the thickness of the protective layer removed in the exposed area corresponding to the first light-transmitting region after development is less than the thickness of the protective layer; Wherein, a scribe lane is further formed in the substrate, and the scribe lane divides the substrate into a plurality of the chip regions; test pads are formed in the scribe lane, and the protective layer covers the test pads; a second light-transmitting region is further formed in the region of the photomask corresponding to the test pads; after development, the protective layer in the exposed region corresponding to the second light-transmitting region is completely removed; Wherein, before forming the protective layer on the substrate, a step of forming a passivation layer on the upper surface of the substrate is further included; the protective layer is formed on the upper surface of the passivation layer; after exposure, the following steps are further included: curing the protective layer; etching away the passivation layer and a part of the substrate in the region corresponding to the test pads to expose the test pads; Wherein, after forming a plurality of the grooves in the region where the protective layer covers the chip regions, a step of forming a plastic-sealing layer on the upper surface of the protective layer is further included; the thickness of the plastic-sealing layer is greater than the depth of the grooves.

3. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that, The plurality of the first light-transmitting regions are arranged at intervals in a strip shape, in a grid pattern or in a random pattern.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein, Before forming the protective layer on the substrate, a step of forming a passivation layer on the upper surface of the substrate is further included; the protective layer is formed on the upper surface of the passivation layer; after exposure, the following steps are further included: curing the protective layer; etching away the passivation layer and a part of the substrate in the region corresponding to the test pads to expose the test pads.

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