Semiconductor device

Abstract

A semiconductor device includes an active structure on a substrate, the active structure including a silicon germanium pattern and a silicon pattern alternately and repeatedly stacked in a vertical direction perpendicular to an upper surface of the substrate; a semiconductor layer on a sidewall of the active structure facing in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source / drain region; and a gate structure on a surface of the active structure and the substrate, the gate structure extending in a second direction perpendicular to the first direction, wherein the silicon germanium pattern is silicon-rich silicon germanium.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2019-0140410, filed with the Korean Intellectual Property Office on November 5, 2019, is incorporated herein by reference in its entirety. Technical Field

[0003] The examples involve semiconductor devices. Background Technology

[0004] In semiconductor devices, fin field-effect transistors can be formed on active fin structures by alternately stacking different semiconductor materials in the active fin structure. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device comprising: an active structure on a substrate, the active structure comprising alternating and repeating silicon-germanium patterns and silicon patterns stacked in a vertical direction perpendicular to the upper surface of the substrate; a semiconductor layer on a sidewall of the active structure, the sidewall facing in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source / drain region; and a gate structure on the surface of the active structure and on the substrate, the gate structure extending in a second direction perpendicular to the first direction, wherein the silicon-germanium patterns are silicon-rich silicon-germanium.

[0006] An embodiment can be implemented by providing a semiconductor device comprising: an active structure on a substrate, the active structure comprising alternating and repeating stacked silicon-germanium patterns and silicon patterns in a vertical direction perpendicular to an upper surface of the substrate; a gate structure extending in a second direction on the upper surface of the active structure and on two sidewalls of the active structure facing each other in a second direction parallel to the upper surface of the substrate; and a silicon layer on two sidewalls of the active structure facing each other in a first direction perpendicular to the second direction, and on both sides of the gate structure in the first direction, the silicon layer being a source / drain region; wherein the silicon concentration in the silicon-germanium patterns is approximately 70% to approximately 85%.

[0007] An embodiment can be implemented by providing a semiconductor device comprising: a first active structure on a first region of a substrate, the first active structure including silicon patterns spaced apart from each other in a vertical direction perpendicular to the surface of the substrate; a first gate structure on the substrate and the first active structure, filling the gaps between the silicon patterns in the first active structure in the vertical direction; a second active structure on a second region of the substrate, the second active structure including silicon-germanium patterns and silicon patterns alternately and repeatedly stacked in the vertical direction; and a second gate structure on the surface of the second active structure and the substrate, wherein the silicon-germanium patterns in the second active structure are silicon-rich silicon-germanium. Attached Figure Description

[0008] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1A , Figure 1B , Figure 2 and Figure 3 Cross-sectional views, perspective views, and plan views of a semiconductor device according to an example embodiment are shown;

[0010] Figure 4 These are the energy bands of the first semiconductor pattern and the second semiconductor pattern;

[0011] Figures 5 to 8 A perspective view showing the silicon concentration in the first semiconductor pattern of each active structure is shown;

[0012] Figures 9 to 19 Cross-sectional views, plan views, and perspective views of various stages in a method for manufacturing a semiconductor device according to an example embodiment are shown;

[0013] Figure 20 and Figure 21 Cross-sectional and perspective views of a semiconductor device according to an example embodiment are shown;

[0014] Figure 22 and Figure 23 A perspective view showing the silicon concentration in the initial first semiconductor pattern in each active structure is shown;

[0015] Figure 24 A cross-sectional view of a semiconductor device according to an example embodiment is shown;

[0016] Figures 25 to 28 Cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an example embodiment are shown;

[0017] Figure 29 A cross-sectional view of a semiconductor device according to an example embodiment is shown;

[0018] Figure 30 and Figure 31 Perspective views of various stages in a method for manufacturing a semiconductor device according to an example embodiment are shown; and

[0019] Figure 32 and Figure 33 Cross-sectional and perspective views of various stages in a method for manufacturing a semiconductor device according to an example embodiment are shown. Detailed Implementation

[0020] In the following text, two directions that are substantially parallel to and intersect each other with the upper surface of the substrate may be referred to as the first direction and the second direction, respectively, and a direction that is substantially perpendicular to the upper surface of the substrate may be referred to as the vertical direction. In an example embodiment, the first direction and the second direction may be substantially perpendicular to each other.

[0021] Figure 1A , Figure 1B , Figure 2 and Figure 3 These are cross-sectional views, perspective views, and plan views of a semiconductor device according to an example embodiment. Figure 4 It is the energy band of the first semiconductor pattern and the second semiconductor pattern. Figures 5 to 8 It is a perspective view of the silicon concentration in the first semiconductor pattern of each active structure.

[0022] Figure 1A A cross-sectional view of the active structure cut along the first direction is shown. Figure 1B A cross-sectional view of the active structure cut along the second direction is shown.

[0023] refer to Figure 1A , Figure 1B , Figure 2 and Figure 3 The semiconductor device may be on substrate 100 and may include active structure 112, gate structure 146, third semiconductor layer 134, and insulating layer 136. The semiconductor device may also include isolation pattern 114 and spacers 130. As used herein, the terms “first,” “second,” etc., are for convenience of naming only and are not intended to require that the named elements be provided in a specific order (e.g., if a third layer is named, this does not mean that the first and second layers are indispensable).

[0024] Substrate 100 may include semiconductor materials such as silicon, germanium or silicon-germanium, or III-V compounds (e.g., GaAs, AlGaAs, InAs, InGaAs, etc.). As used herein, the term "or" is not an exclusive term; for example, "A or B" will include "A", "B", or "A and B".

[0025] The substrate 100 may include trenches extending in a first direction, and isolation patterns 114 may be present in the trenches. The isolation patterns 114 may serve as field regions, and the substrate 100 between the isolation patterns 114 may serve as active regions. The isolation patterns 114 may include, for example, oxides (e.g., silicon oxide).

[0026] The active structure 112 may include a first semiconductor pattern 104b and a second semiconductor pattern 110b that are alternately and repeatedly stacked in a vertical direction. The active structure 112 may have a cylindrical shape. Multiple active structures 112 may be spaced apart from each other in each of the first and / or second directions. The active structures 112 may be arranged to be aligned in each of the first and second directions.

[0027] The first semiconductor pattern 104b may include a material different from that of the second semiconductor pattern 110b. In an embodiment, the first semiconductor pattern 104b may include a material with high etch selectivity relative to the substrate 100 and the second semiconductor pattern 110b.

[0028] In one embodiment, the first semiconductor pattern 104b may include silicon-doped germanium silicon. In another embodiment, the first semiconductor pattern 104b may include silicon-rich germanium silicon. In another embodiment, the silicon concentration in the first semiconductor pattern 104b may be about 70% or higher. In another embodiment, the silicon concentration in the first semiconductor pattern 104b may be in the range of about 70% to about 85%, and the germanium concentration may be in the range of about 15% to about 30%. In another embodiment, the silicon-rich germanium silicon may contain relative amounts of silicon and germanium atoms, such that silicon is dominant. The second semiconductor pattern 110b may include silicon. In another embodiment, the second semiconductor pattern 110b may include monocrystalline silicon. Hereinafter, the first semiconductor pattern 104b is referred to as a germanium silicon pattern, and the second semiconductor pattern 110b is referred to as a silicon pattern.

[0029] In an embodiment, the silicon concentration in the silicon-germanium pattern 104b can vary depending on the vertical position of the silicon-germanium pattern 104b included in the active structure 112. In an embodiment, the silicon-germanium pattern 104b in the active structure 112 may have the highest silicon concentration at its top (e.g., vertically away from the substrate 100). In an embodiment, the silicon concentration in the silicon-germanium pattern 104b may decrease (e.g., gradually) from the top of the active structure 112 to the bottom of the active structure 112 (e.g., vertically closer to the substrate 100). In an embodiment, as... Figure 5 As shown, the silicon concentration in the silicon-germanium pattern 104b in the active structure 112 can decrease downwards in the vertical direction perpendicular to the surface of the substrate 100.

[0030] In some fin field-effect transistors, the upper part of the active fin can carry more on-current than the lower part of the active fin. In an embodiment, the on-current of the fin field-effect transistor can increase even more when the silicon concentration in the silicon-germanium pattern 104b(T) at the top of the active structure 112 increases.

[0031] In an implementation, the silicon concentration in the active structure 112 can vary depending on the internal location within each silicon-germanium pattern 104b (e.g., depending on the horizontal or lateral location within each silicon-germanium pattern 104b).

[0032] In the implementation method, such as Figure 6 As shown, the two sidewalls extending longitudinally in the first direction of each silicon-germanium pattern 104b can have the highest silicon concentration. The silicon concentration can gradually decrease from the sidewalls extending in the first direction to its center (e.g., in each silicon-germanium pattern 104b, the silicon concentration can decrease as it moves inward in the second direction).

[0033] In the implementation method, such as Figure 7 As shown, the two sidewalls extending longitudinally in the second direction of each silicon-germanium pattern 104b can have the highest silicon concentration. The silicon concentration can gradually decrease from the sidewalls extending in the second direction of each silicon-germanium pattern 104b to its center portion (e.g., in each silicon-germanium pattern 104b, the silicon concentration can decrease as it moves inward in the first direction).

[0034] In the implementation method, such as Figure 8 As shown, the sidewalls extending in each of the first and second directions of each silicon-germanium pattern 104b can have the highest silicon concentration. The silicon concentration can gradually decrease from the sidewalls extending in each of the first and second directions of each silicon-germanium pattern 104b to its center portion (e.g., in each silicon-germanium pattern 104b, the silicon concentration can decrease as it moves inward in each of the first and second directions).

[0035] In an embodiment, the silicon concentration doped in the silicon-germanium pattern 104b can be uniform in the vertical position of the silicon-germanium pattern 104b and in the internal position of each silicon-germanium pattern 104b.

[0036] The active structure 112 can be used as the channel region of a fin field-effect transistor.

[0037] Gate structure 146 may be formed on two sidewalls (e.g., facing each other) of active structure 112 in a second direction, and on the upper surface of active structure 112 and substrate 100. Gate structure 146 may extend in the second direction. In an embodiment, gate structure 146 may cover the two sidewalls and upper surface of active structure 112 arranged in the second direction. The upper surface of gate structure 146 may be higher than the upper surface of active structure 112 (e.g., farther from substrate 100 in the vertical direction).

[0038] Spacers 130 may be located on the sidewalls of the gate structure 146. Spacers 130 may include, for example, silicon nitride.

[0039] The gate structure 146 may include a gate insulating layer pattern 140, a gate pattern 142, and a hard mask 144.

[0040] The gate insulating layer pattern 140 can be conformally formed to cover the two sidewalls (facing in the second direction) and the top surface of the active structure 112. In one embodiment, the gate insulating layer pattern 140 can be formed on the inner sidewall of the spacer 130. Therefore, the gate insulating layer pattern 140 can surround the surface of the gate pattern 142. In another embodiment, a power function control pattern can be further formed between the gate insulating layer pattern 140 and the gate pattern 142.

[0041] In one embodiment, the thickness of the gate insulating layer pattern 140 (e.g., from its inner side to its outer side) can be greater than half the height of one of the silicon-germanium patterns 104b in the vertical direction. In this case, even if the silicon-germanium pattern 104b is to be removed, the gate pattern 142 may not be formed in the removed portion of the silicon-germanium pattern 104b because the gate insulating layer pattern 140 has sufficient thickness. In another embodiment, when the thickness of the gate insulating layer pattern 140 is greater than half the height of one of the silicon-germanium patterns 104b in the vertical direction, a multi-bridge channel transistor may not be formed.

[0042] The gate pattern 142 may be on the gate insulating layer pattern 140. The gate pattern 142 may be on the two sidewalls (facing in the second direction) and the top surface of the active structure 112.

[0043] Hard mask 144 can be on gate insulating layer pattern 140 and gate pattern 142.

[0044] The gate insulating layer pattern 140 may include, for example, a metal oxide with a high dielectric constant, such as hafnium oxide, tantalum oxide, zirconium oxide, etc. The work function control pattern may include, for example, titanium nitride, titanium oxynitride, silicon titanium nitride, silicon titanium oxynitride, aluminum titanium oxynitride, tantalum nitride, aluminum tantalum nitride, aluminum tantalum oxynitride, tungsten nitride, tungsten carbonitride, aluminum oxide, etc.

[0045] The grid pattern 142 may include, for example, metals such as titanium, aluminum, tungsten, their alloys, their nitrides or their carbides.

[0046] The hard mask 144 may include an insulating material, such as silicon nitride.

[0047] The outer wall of the spacer 130 can be aligned (e.g., coplanar) with the side wall of the active structure 112 in the vertical direction.

[0048] The third semiconductor layer 134 may be located on the surface of the active structure 112 and the substrate 100. The third semiconductor layer 134 may be located between the active structures 112 in a first direction. The third semiconductor layer 134 may serve as the source / drain region of a transistor. In one embodiment, the third semiconductor layer 134 may comprise a semiconductor material doped with impurities. In one embodiment, the third semiconductor layer 134 may comprise silicon. In one embodiment, the third semiconductor layer 134 may comprise silicon-germanium.

[0049] In an embodiment, the upper surface of the third semiconductor layer 134 (e.g., the surface facing away from the substrate 100 in the vertical direction) may be higher than the upper surface of the active structure 112 and lower than the upper surface of the hard mask 144 of the gate structure 146.

[0050] An insulating layer 136 may be present on the substrate 100 and the third semiconductor layer 134. The insulating layer 136 may fill the gap between the gate structures 146. The upper surface of the insulating layer 136 may be coplanar with the upper surface of the gate structures 146. The insulating layer 136 may include, for example, an oxide, such as silicon oxide.

[0051] In an embodiment, the semiconductor device may further include contact plugs and wiring electrically connected to the third semiconductor layer 134 and / or the gate structure 146.

[0052] As described above, the semiconductor device may include a fin field-effect transistor on the active structure 112. In an embodiment, the active structure 112 may include alternately stacked silicon-germanium patterns 104b and silicon patterns 110b made of different semiconductor materials. Therefore, band differences may occur between the silicon-germanium patterns 104b and silicon patterns 110b in the active structure 112.

[0053] like Figure 4 As shown, the active structure can have an alternating stack of silicon-germanium patterns and silicon patterns, resulting in a high potential barrier between the silicon-germanium patterns and the silicon patterns (see dashed lines). Therefore, channels can be formed only at the silicon patterns and almost not at the silicon-germanium patterns. Consequently, the on-current of the fin field-effect transistor can be significantly reduced.

[0054] In this embodiment, the silicon-germanium pattern 104b may be doped with silicon. The silicon-germanium pattern 104b may be silicon-rich silicon-germanium, thereby reducing the potential barrier between the silicon-germanium pattern 104b and the silicon pattern 110b. Therefore, the potential well can be reduced, or the slope of the potential well can be gentle (see solid line). Thus, a channel can be formed not only at the silicon pattern 110b, but also at a portion of the silicon-germanium pattern 104b, thereby increasing the on-state current of the fin field-effect transistor.

[0055] Figures 9 to 19 These are cross-sectional views, plan views, and perspective views of various stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0056] Figure 9 , Figure 11 , Figure 14 , Figure 15 , Figure 17 and Figure 18 It is a cross-sectional view. Figure 10 and Figure 12 It is a floor plan, and Figure 13 , Figure 16 and Figure 19 It is a perspective view.

[0057] refer to Figure 9 and Figure 10 The initial first semiconductor layer 102 and the second semiconductor layer 110 can be stacked alternately and repeatedly on the substrate 100 to form a stacked layer including the initial first semiconductor layer 102 and the second semiconductor layer 110. In this case, the uppermost layer of the stacked layer can be the second semiconductor layer 110.

[0058] In one embodiment, the second semiconductor layer 110 may comprise a material substantially the same as that of the substrate 100. The initial first semiconductor layer 102 may comprise a material different from that of the second semiconductor layer 110. In another embodiment, the initial first semiconductor layer 102 may comprise a material having high etch selectivity relative to the substrate 100 and the second semiconductor layer 110.

[0059] In one embodiment, the second semiconductor layer 110 may be a silicon layer, and the initial first semiconductor layer 102 may be a silicon-germanium layer. In another embodiment, the initial first semiconductor layer 102 may be a silicon-germanium layer comprising approximately 67% to approximately 70% silicon and approximately 30% to approximately 33% germanium. In yet another embodiment, the second semiconductor layer 110 may be monocrystalline silicon.

[0060] In this embodiment, the second semiconductor layer 110 and the initial first semiconductor layer 102 can be formed by an epitaxial growth process.

[0061] refer to Figure 11Silicon can be doped into the stacked layers, including the initial first semiconductor layer 102 and the second semiconductor layer 110, using an ion implantation process. Silicon ions can be implanted in a direction perpendicular to the upper surface of the initial first semiconductor layer 102 (e.g., vertically).

[0062] When performing an ion implantation process, the silicon concentration in the initial first semiconductor layer 102 can be increased to form the first semiconductor layer 104. In an embodiment, the first semiconductor layer 104 may be a silicon-rich silicon-germanium layer having a higher silicon concentration than that in the initial first semiconductor layer 102.

[0063] In this embodiment, silicon can be implanted vertically onto the surface of the substrate 100 using an ion implantation process. In this case, the first semiconductor layer 104 located at the top of the stacked layers can be doped to achieve the highest silicon concentration. Therefore, the first semiconductor layer 104 formed at the top of the stacked layers can have the highest silicon concentration. Furthermore, the silicon concentration in the first semiconductor pattern 104 can gradually decrease from the top to the bottom of the stacked layers. In this embodiment, when the ion implantation process is performed as described above, a reference can be fabricated using subsequent processes. Figure 5 The semiconductor device described.

[0064] Since the second semiconductor layer 110 is a silicon layer, its physical properties can remain unchanged after the ion implantation process is performed.

[0065] As described above, the first semiconductor layer 104 may be doped with silicon, thereby reducing the potential well between the first semiconductor layer 104 and the second semiconductor layer 110, or the slope of the potential well may be gentle.

[0066] refer to Figure 12 and Figure 13 A hard mask extending in the first direction can be formed on the uppermost second semiconductor layer 110, and the hard mask can be used as an etching mask to etch the upper part of the first semiconductor layer 104, the second semiconductor layer 110 and the substrate 100.

[0067] Therefore, a preliminary active structure 111 extending in a first direction can be formed on the substrate 100. The preliminary active structure 111 may include preliminary first semiconductor patterns 104a and preliminary second semiconductor patterns 110a that are stacked alternately and repeatedly. In an embodiment, a plurality of preliminary active structures 111 may be formed on the substrate 100 to be spaced apart from each other in a second direction. An opening 108 may be formed between the preliminary active structures 111.

[0068] An isolation pattern 114 can be formed on a substrate 100 between the initial active structures 111. The hard mask can then be removed.

[0069] refer to Figure 14 A dummy gate structure 128 extending in the second direction can be formed on the initial active structure 111 and the isolation pattern 114.

[0070] In one embodiment, the dummy gate structure 128 may include a dummy gate insulating layer 122, a dummy gate pattern 124, and a dummy hard mask 126. The dummy gate insulating layer 122 may include, for example, an oxide (e.g., silicon oxide), and the dummy gate pattern 124 may include, for example, polysilicon. The dummy hard mask 126 may include, for example, a nitride (e.g., silicon nitride).

[0071] In one embodiment, a plurality of dummy gate structures 128 may be arranged to be spaced apart from each other in a first direction.

[0072] refer to Figure 15 and Figure 16 Spacers 130 can be formed on the sidewall of the dummy grid structure 128.

[0073] Subsequently, the dummy gate structure 128 and spacer 130 can be used as etching masks to etch the initial active structure 111, thereby exposing the upper surface of the substrate 100.

[0074] Therefore, the initial active structure 111 can be cut to form an active structure 112. Each active structure 112 may include alternating and repeating stacked first semiconductor pattern 104b and second semiconductor pattern 110b.

[0075] Furthermore, the first opening 132 may be formed between the active structures 112 spaced apart from each other in the first direction, and the first opening 132 may extend in the second direction. The sidewalls of the first semiconductor pattern 104b and the second semiconductor pattern 110b, as well as the surface of the substrate 100, may be exposed through the first opening 132.

[0076] refer to Figure 17 The third semiconductor layer 134 can be formed on the surface of the substrate 100 exposed through the first opening 132 and on the sidewalls of the first semiconductor pattern 104b and the second semiconductor pattern 110b.

[0077] In one embodiment, the third semiconductor layer 134 can be formed by a selective epitaxial growth (SEG) process, while simultaneously doping impurities in situ.

[0078] In one embodiment, the third semiconductor layer 134 may be formed to fill the gaps between the active structures 112 spaced apart in the first direction.

[0079] In one embodiment, the upper surface of the third semiconductor layer 134 may be higher than the upper surface of the active structure 112 and lower than the lower surface of the dummy hard mask 126.

[0080] refer to Figure 18 and Figure 19 An insulating layer 136 can be formed to cover the active structure 112, the third semiconductor layer 134, and the dummy gate structure 128. The insulating layer 136 can then be planarized until the upper surface of the dummy gate pattern 124 is exposed. During the planarization process, the dummy hard mask 126 can be removed together, and the upper portion of the spacer 130 can be partially removed. The planarization process can be performed using chemical mechanical polishing (CMP) and / or etching-back processes.

[0081] Then, the dummy gate pattern 124 and the dummy gate insulating layer 122 below the dummy gate pattern 124 can be removed to form a second opening 138. The second opening 138 can extend in a second direction.

[0082] The (e.g., inner) sidewall of the longitudinally extending spacer 130 in the second direction may be exposed through the second opening 138. A portion of the sidewall of the active structure 112 facing in the second direction may be exposed through the second opening 138.

[0083] Refer again Figure 1A and Figures 1B to 3 A gate structure 146 that fills the second opening 138 can be formed on the substrate 100.

[0084] An oxide layer may be formed on the active structure 112 exposed through the second opening 138, and a gate insulating layer may be conformally formed on the oxide layer, the inner wall of the spacer 130, and the upper surface of the insulating layer 136. A gate electrode layer may be formed on the gate insulating layer to fill the second opening 138. In an embodiment, a work function control layer may also be formed between the gate insulating layer and the gate electrode layer.

[0085] The gate insulating layer, work function control layer, and gate electrode layer can be formed using CVD, ALD, or physical vapor deposition (PVD) processes.

[0086] Next, the gate electrode layer and the gate insulating layer can be planarized until the upper surface of the insulating layer 136 is exposed to form the gate insulating layer pattern 140 and the gate pattern 142, respectively. The upper portions of the gate insulating layer pattern 140 and the gate pattern 142 can be partially etched to form recesses, and a hard mask 144 can be formed in the recesses. Therefore, the hard mask 144 can cover the upper surfaces of the gate insulating layer pattern 140 and the gate pattern 142.

[0087] As described above, the active structure 112 may have a structure in which a first semiconductor pattern 104b and a second semiconductor pattern 110b are alternately stacked. A fin field-effect transistor can be formed on the active structure 112. In the active structure 112, the first semiconductor pattern 104b may include silicon-rich silicon-germanium, and the second semiconductor pattern 110b may include silicon. Therefore, the potential barrier between the first semiconductor pattern 104b and the second semiconductor pattern 110b can be reduced, thereby reducing the potential well or making the slope of the potential well gentler. Therefore, the on-state current of the fin field-effect transistor can be increased.

[0088] In the above method, silicon implantation into the reference can be performed in another stage. Figure 11 The ion implantation process in the preliminary first semiconductor layer is shown. In an embodiment, the ion implantation process for implanting silicon can be performed at least once in at least one of the stages of exposing the preliminary first semiconductor layer, the preliminary first semiconductor pattern, or the first semiconductor pattern. Depending on the ion implantation process for implanting silicon, the silicon concentration can vary depending on the position of the first semiconductor pattern 104b in the active structure 112.

[0089] In this implementation, an ion implantation process for silicon implantation can be performed after the initial active structure 111 is formed (see reference). Figure 12 and Figure 13 In the implementation method, in Figure 9 , Figure 10 , Figure 12 and Figure 13 Following the process shown, silicon ions can be implanted into the preliminary active structure 111.

[0090] In this embodiment, silicon ions can be implanted in a direction perpendicular to the upper surface of the preliminary active structure 111. In this case, the silicon concentration in the preliminary first semiconductor pattern 104a can gradually decrease from the top to the bottom of the preliminary active structure 111. Then, a reference can be performed. Figures 14 to 19 as well as Figure 1A and Figures 1B to 3 The subsequent processes shown are used to manufacture semiconductor devices. In the semiconductor device, each first semiconductor pattern 104b can have, as shown in the diagram... Figure 5 The silicon concentration shown.

[0091] In this embodiment, silicon ions can be implanted in a direction inclined relative to the upper surface of the initial active structure 111. Therefore, silicon ions can be implanted into the two sidewalls of the initial active structure 111 facing in the second direction. In this case, the silicon concentration in the initial first semiconductor pattern 104a can gradually decrease from the sidewalls of the initial active structure 111 in the second direction towards the center portion of the initial active structure 111. Then, a reference... Figures 14 to 19as well as Figure 1A and Figures 1B to 3 The subsequent processes shown are for manufacturing semiconductor devices. In the semiconductor device, each first semiconductor pattern 104b may have a reference... Figure 6 The silicon concentration shown.

[0092] In this implementation, an ion implantation process for silicon implantation can be performed after the active structure 112 is formed (see reference). Figure 15 and Figure 16 In the implementation method, in Figure 9 , Figure 10 and Figures 12 to 16 Following the process shown, silicon ions can be implanted into the active structure 112.

[0093] In one embodiment, silicon ions can be implanted in a direction inclined relative to the upper surface of the active structure 112. Therefore, silicon ions can be implanted into the two sidewalls of the active structure 112 exposed through the first opening 132, facing each other in the first direction (see [link to implementation]). Figure 16 In this case, the silicon concentration in the first semiconductor pattern 104b can gradually decrease from the two sidewalls of the active structure 112 in the first direction toward the central portion of the active structure 112. Then, a reference can be performed. Figures 17 to 19 as well as Figure 1A and Figures 1B to 3 The subsequent processes shown are for manufacturing semiconductor devices. In the semiconductor device, each first semiconductor pattern 104b may have a reference... Figure 7 The silicon concentration shown.

[0094] In this implementation, an ion implantation process for implanting silicon can be performed after the second opening 138 is formed (see reference). Figure 18 and Figure 19 In the implementation method, in Figure 9 and Figure 10 as well as Figures 12 to 19 Following the process shown, silicon ions can be implanted.

[0095] In this embodiment, silicon ions can be implanted in a direction inclined relative to the upper surface of the active structure 112. Therefore, silicon ions can be implanted into the sidewalls of the active structure 112 exposed through the second opening 138. In this case, the silicon concentration in the first semiconductor pattern 104b can gradually decrease from the sidewalls of the active structure 112 facing in the second direction toward the central portion of the active structure 112. Then, a reference can be performed. Figure 1A and Figures 1B to 3 The subsequent processes shown are for manufacturing semiconductor devices. In the semiconductor device, each first semiconductor pattern 104b may have a reference... Figure 6 The silicon concentration shown.

[0096] In one embodiment, silicon ions can be implanted into the sidewalls of the active structure 112 facing each of the first and second directions. In another embodiment, the ion implantation process can be performed two or more times. Therefore, each first semiconductor pattern 104b can have a reference... Figure 8 The silicon concentration shown.

[0097] Figure 20 and Figure 21 These are cross-sectional and perspective views of a semiconductor device according to an example embodiment. Figure 22 and Figure 23 It is a perspective view of the silicon concentration in the initial first semiconductor pattern in each active structure.

[0098] This semiconductor device can be compared with a reference. Figure 1A , Figure 1B and Figure 3 The semiconductor devices shown are the same or similar, except that they may not form a first opening and a third semiconductor layer.

[0099] refer to Figure 20 and Figure 21 The semiconductor device may include a preliminary active structure 111, a gate structure 146, and an insulating layer 136 formed on a substrate 100. The semiconductor device may also include an isolation pattern 114 and spacers 130. The semiconductor device may include a fin field-effect transistor formed on the preliminary active structure 111.

[0100] The preliminary active structure 111 may include preliminary first semiconductor patterns 104a and preliminary second semiconductor patterns 110a that are stacked alternately and repeatedly. The preliminary active structure 111 may have a linear shape extending in a first direction. The plurality of preliminary active structures 111 may be spaced apart from each other in a second direction.

[0101] In one embodiment, the initial first semiconductor pattern 104a may be a silicon-doped germanium pattern. Therefore, the initial first semiconductor pattern 104a may be a silicon-rich germanium pattern. In one embodiment, the silicon concentration in the initial first semiconductor pattern 104a may be approximately 70% or higher. In one embodiment, the silicon concentration in the initial first semiconductor pattern 104a may be in the range of approximately 70% to approximately 85%, and the germanium concentration may be in the range of approximately 15% to approximately 30%. In one embodiment, the initial second semiconductor pattern 110a may be a silicon pattern.

[0102] In an implementation, the silicon concentration can vary depending on the vertical position of the initial first semiconductor pattern 104a in the initial active structure 111 or the internal position within each initial first semiconductor pattern 104a.

[0103] In the implementation method, such as Figure 22 As shown, in the preliminary active structure 111, the silicon concentration in the preliminary first semiconductor pattern 104a can gradually decrease downward in the vertical direction toward the surface of the substrate 100.

[0104] In the implementation method, such as Figure 23 As shown, the two sidewalls extending longitudinally in the first direction of each preliminary first semiconductor pattern 104a can have the highest silicon concentration. Moreover, the silicon concentration can gradually decrease from the sidewalls extending in the first direction of each preliminary first semiconductor pattern 104b toward its center (e.g., inward in the second direction).

[0105] The gate structure 146 may be located on the two sidewalls and the top surface of the initial active structure 111 facing in the second direction, as well as on the substrate 100. The gate structure 146 may extend in the second direction. The spacer 130 may be located on the sidewalls of the gate structure 146.

[0106] A portion of the upper surface of the preliminary active structure 111 can be exposed through the gap between the gate structures 146 in the first direction. The preliminary active structure 111 between the gate structures 146 can be used as the source / drain region of a transistor. Therefore, the preliminary active structure 111 between the gate structures 146 can be doped with impurities.

[0107] The insulating layer 136 may be on the substrate 100 and the preliminary active structure 111. The insulating layer 136 may fill the gap between the gate structures 146. The upper surface of the insulating layer 136 may be coplanar with the upper surface of the gate structure 146.

[0108] The methods for manufacturing semiconductor devices can be referenced. Figures 9 to 19 as well as Figure 1A , Figure 1B and Figure 3 The method shown is similar, except that the first opening and the third semiconductor layer may not be formed.

[0109] The methods used to manufacture semiconductor devices are briefly described below.

[0110] First, you can execute the reference. Figures 9 to 14 The process shown is used to form a dummy gate structure 128. Spacers 130 can then be formed on the sidewalls of the dummy gate structure 128. The preliminary active structure 111 exposed through the gaps between the dummy gate structures 128 can be further doped with impurities. Therefore, the preliminary active structure 111 between the dummy gate structures 128 can be used as a source / drain region.

[0111] Then, it can be executed and referenced. Figure 18 and Figure 19 as well as Figure 1A , Figure 1B and Figure 3 The process shown is the same as the process used to manufacture Figure 20 and Figure 21 The semiconductor device shown.

[0112] As described above, when silicon ions are implanted into the preliminary first semiconductor layer 102 in the vertical direction, each preliminary first semiconductor pattern 104a in the preliminary active structure 111 can have the following characteristics as described in the reference diagram. Figure 22 The silicon concentration shown.

[0113] In this implementation, an ion implantation process for silicon implantation can be performed after the initial active structure 111 is formed (see reference). Figure 12 and Figure 13 ).

[0114] In one embodiment, silicon ions can be implanted in a direction perpendicular to the upper surface of the initial active structure 111 (e.g., in the vertical direction). In this case, each initial first semiconductor pattern 104a can have, for example, Figure 22 The silicon concentration shown.

[0115] In one embodiment, silicon ions can be implanted in a direction inclined relative to the upper surface of the initial active structure 111. In this case, each initial first semiconductor pattern 104a can have, for example, Figure 23 The silicon concentration shown.

[0116] In this implementation, an ion implantation process for implanting silicon can be performed after the second opening 138 is formed (see reference). Figure 18 and Figure 19 In this case, each preliminary first semiconductor pattern 104a can have, as shown in the figure below. Figure 23 The silicon concentration is shown. Alternatively, silicon may not be implanted into the initial first semiconductor pattern 104a corresponding to the source / drain regions.

[0117] Figure 24 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0118] refer to Figure 24 Semiconductor devices may include multi-bridge channel transistors on a first region of a substrate and fin field-effect transistors on a second region of a substrate.

[0119] The fin field-effect transistor in the second region can be with Figure 1A , Figures 1B to 3The fin field-effect transistors shown are substantially the same. In this embodiment, the active structure 112, gate structure 146, third semiconductor layer 134, and insulating layer 136 may be located on a second region of the substrate. The gate structure 146 may include a gate insulating layer pattern 140, a gate pattern 142, and a hard mask 144. The semiconductor device may also include an isolation pattern 114 and spacers 130. A detailed description of the fin field-effect transistors in the second region of the substrate 100 may be omitted.

[0120] The multi-bridge channel transistor in the first region of substrate 100 may include a first active structure, a first gate structure 166, a third semiconductor layer 134, and a lower spacer 152. The multi-bridge channel transistor in the first region of substrate 100 may also include an isolation pattern 114 and an upper spacer 130a.

[0121] The first active structure may include second semiconductor patterns 110b spaced apart from each other in a vertical direction. The first active structure may have the same shape as the second active structure with the first semiconductor patterns removed. The second semiconductor patterns 110b spaced apart in a vertical direction may each serve as a channel region of a transistor.

[0122] The lower spacer 152 can be placed on the upper and lower surfaces of the edges of the second semiconductor pattern 110b in the first direction to support the upper and lower surfaces of the second semiconductor pattern 110b. Therefore, in the first active structure, a gap can be formed between the second semiconductor patterns 110b in the vertical direction. The gap can be defined by the lower spacer 152 and the upper and lower surfaces of the second semiconductor pattern 110b.

[0123] In an embodiment, the vertical height of the gap may be substantially the same as the vertical height of the first semiconductor pattern 104b in the second active structure on the second region of the substrate 100.

[0124] The first gate structure 166 may cover the front and rear sides of the first active structure in the second direction to fill the gaps between the second semiconductor patterns 110b. Furthermore, the first gate structure 166 may be formed on the upper surface of the first active structure.

[0125] The first gate structure 166 may include a first gate insulating layer pattern 160, a first gate pattern 162, and a first hard mask 164. The first gate insulating layer pattern 160 and the first gate pattern 162 may be formed to fill gaps. The first gate insulating layer pattern 160 may surround the surface of the first gate pattern 162 within the gaps.

[0126] In one embodiment, the thickness of the first gate insulating layer pattern 160 may be less than the thickness of the gate insulating layer pattern 140 on the second region of the substrate 100. In another embodiment, the thickness of the first gate insulating layer pattern 160 may be less than half the vertical height of the first semiconductor pattern 104b. Furthermore, the thickness of the first gate insulating layer pattern 160 may be less than half the vertical height of the gap.

[0127] The first hard mask 164 may be located on the uppermost part of the first gate structure 166. The upper spacer 130a may be located on the sidewall of the first gate structure 166 above the gap. The first hard mask 164 and the upper spacer 130a may each have the same shape as the hard mask 144 and spacer 130 on the second region of the substrate 100. Furthermore, the first hard mask 164 and the upper spacer 130a may each comprise the same material as the hard mask 144 and spacer 130 on the second region of the substrate 100.

[0128] The third semiconductor layer 134 and the insulating layer 136 may be located on a first region of the substrate 100. The third semiconductor layer 134 and the insulating layer 136 on the first region of the substrate 100 may each have the same shape as the third semiconductor layer 134 and the insulating layer 136 on the second region of the substrate. The third semiconductor layer 134 and the insulating layer 136 on the first region of the substrate 100 may each comprise the same material as the third semiconductor layer 134 and the insulating layer 136 formed on the second region of the substrate.

[0129] As described above, a multi-channel transistor can be located on a first region of substrate 100. Furthermore, a fin field-effect transistor can be located on a second region of substrate 100, and the fin field-effect transistor can be located on an active structure in which a first semiconductor pattern 104b and a second semiconductor pattern 110b are repeatedly stacked. The thickness of the gate insulating layer pattern 140 of the fin field-effect transistor formed in the second region of substrate 100 can be greater than the thickness of the first gate insulating layer pattern 160 of the multi-channel transistor. Therefore, the operating voltage of the fin field-effect transistor can be higher than that of the multi-channel transistor. In this embodiment, the fin field-effect transistor can be used as an I / O device with a high operating voltage.

[0130] Figures 25 to 28 These are cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0131] refer to Figure 25 The first semiconductor layer 102 and the second semiconductor layer 110 can be stacked alternately and repeatedly to form a stacked layer on the substrate 100, including the first region and the second region. In this case, the uppermost layer of the stacked layer can be the second semiconductor layer 110.

[0132] In one embodiment, the second semiconductor layer 110 may include a silicon layer, and the initial first semiconductor layer 102 may include a silicon-germanium layer. In another embodiment, the initial first semiconductor layer 102 may have a silicon concentration of approximately 67% to 70% and a germanium concentration of approximately 30% to 33%.

[0133] An ion implantation mask 106 can be formed on the uppermost second semiconductor layer 110 to cover the uppermost second semiconductor layer 110 of the first region. Therefore, the uppermost second semiconductor layer 110 of the second region can be exposed. The ion implantation mask 106 may include, for example, a photoresist pattern.

[0134] Silicon ions can be implanted into the stacked layer of the second region using an ion implantation mask 106. Silicon ions can be implanted in a direction perpendicular to the upper surface of the initial first semiconductor layer 102 (e.g., vertical). When performing the ion implantation process, the silicon concentration in the initial first semiconductor layer 102 of the second region can be increased to form the first semiconductor layer 104. In an embodiment, the first semiconductor layer 104 can be formed of a silicon-rich silicon-germanium layer with a higher silicon concentration than that in the initial first semiconductor layer 102. In an embodiment, the silicon concentration in the first semiconductor layer 104 can be 70% or higher. In an embodiment, the first semiconductor layer 104 can have a silicon concentration of approximately 70% to 80% and a germanium concentration of approximately 15% to approximately 30%.

[0135] Meanwhile, the initial first semiconductor layer 102, which includes silicon and germanium but without silicon ion implantation, can be retained in the first region. The initial first semiconductor layer 102 can be used as a sacrificial layer.

[0136] As described above, the silicon implantation process can be performed in a separate stage, at which the initial active structure is exposed. In this embodiment, prior to performing the silicon implantation process, a process for forming an ion implantation mask to cover the structure formed on a first region of the substrate can be further performed.

[0137] Subsequently, a reference can be performed on the structure formed on the first and second regions of the substrate 100. Figures 12 to 16 The process is shown. Therefore, the first opening 132 (reference) Figure 26 The silicon germanium can be formed on a first region and a second region of the substrate 100, respectively. Through this process, a preliminary sacrificial pattern including silicon germanium but without implanted silicon ions can be formed on the first region of the substrate 100.

[0138] refer to Figure 26 A first blocking pattern 154 can be formed to cover the structure on the second region of the substrate 100, so that only the first region of the substrate 100 is exposed.

[0139] In a first region of the substrate, the two sidewalls of the initial sacrificial pattern exposed through the first opening 132 can be partially etched to form a first recess. The initial sacrificial pattern can be formed into a sacrificial pattern 102b by an etching process. The width of the sacrificial pattern 102b in the first direction can be smaller than the width of the second semiconductor pattern 110b in the first direction.

[0140] Subsequently, a lower spacer 152 may be formed in the first recess. The lower spacer 152 may include, for example, silicon nitride.

[0141] refer to Figure 27 The first blocking pattern 154 can be removed. Additionally, a reference can be performed on the structures formed on the first and second regions of the substrate 100. Figure 17 and Figure 18 The process shown.

[0142] Therefore, the dummy gate structure formed on the first and second regions of the substrate 100 can be removed to form the second opening 138.

[0143] In the first region, two sidewalls of a structure comprising alternating stacked sacrificial patterns 102b and a second semiconductor pattern 110b in the second direction can be exposed through the second opening 138. In the second region, the sidewalls of the active structure 112 in the second direction can be exposed through the second opening 138.

[0144] A second barrier pattern can be formed to cover the structure formed on the second region of the substrate 100. Then, on the first region, the sacrificial pattern 102b exposed through the second opening 138 can be selectively removed to form a gap 156. The gap 156 can communicate with the second opening 138. Therefore, the gap 156 and the second opening 138 can merge to extend in a second direction.

[0145] refer to Figure 28 and Figure 24 A first gate structure 166 can be formed on a first region of the substrate 100 to fill the second opening 138 and the gap 156. Furthermore, a gate structure 146 can be formed on a second region of the substrate 100 to fill the second opening 138.

[0146] In one embodiment, a first gate insulating layer 159 having a first thickness can be conformally formed on the inner walls of the substrate 100, the second semiconductor pattern 110b, and the upper spacer 130a and the lower spacer 152 exposed through the second opening 138 and the gap 156 in the first region.

[0147] In the second region, a gate insulating layer 139 having a second thickness greater than the first thickness can be formed on the surface of the active structure 112 exposed through the second opening 138.

[0148] Subsequently, a gate electrode layer can be formed on the first gate insulating layer 159 and the gate insulating layer 139 to fill the gap 156 and the second opening 138. In an embodiment, a function control layer can be further formed before forming the gate electrode layer.

[0149] Subsequently, the gate electrode layer, work function control layer, gate insulating layer, and first gate insulating layer can be planarized until the upper surface of insulating layer 136 is exposed. Additionally, the gate insulating layer, first gate insulating layer, and gate electrode layer can be partially etched to form recesses, and a hard mask can then be formed within these recesses.

[0150] Therefore, the first gate structure can be formed on a first region of the substrate, and the gate structure can be formed on a second region of the substrate. The first gate structure 166 may include a first gate insulating layer pattern 160, a first gate pattern 162, and a first hard mask 164. The gate structure 146 may include a gate insulating layer pattern 140, a gate pattern 142, and a hard mask 144.

[0151] Figure 29 This is a cross-sectional view of a semiconductor device according to an example embodiment.

[0152] Figure 29 A cross-sectional view of the active structure cut along the second direction is shown.

[0153] This semiconductor device can be compared with a reference. Figure 1A , Figure 1B and Figure 3 The semiconductor devices shown are the same or similar, except that a capping semiconductor pattern can also be formed on the sidewalls of the active structure in the second direction.

[0154] refer to Figure 29 The semiconductor device may include a source structure 112, a gate structure 146, an insulating layer 136, and a masking semiconductor pattern 170 on the substrate 100. The semiconductor device may also include an isolation pattern 114 and spacers 130.

[0155] For reference Figure 1A , Figure 1B and Figure 3 As shown, the active structure 112 may include alternating and repeatedly stacked first semiconductor pattern 104b and second semiconductor pattern 110b, and the first semiconductor pattern 104b and second semiconductor pattern 110b may include semiconductor materials different from each other. In an embodiment, the active structure 112 may include alternatingly stacked silicon-doped silicon-germanium pattern 104b and silicon pattern 110b.

[0156] The semiconductor pattern 170 can be applied to the sidewall of the active structure 112 facing in the second direction. The semiconductor pattern 170 can at least cover the sidewall of the active structure 112 facing in the second direction.

[0157] In one embodiment, the covering semiconductor pattern 170 may include a material substantially the same as that of the second semiconductor pattern 110b. The covering semiconductor pattern 170 may include silicon. In one embodiment, the covering semiconductor pattern 170 may include monocrystalline silicon. In another embodiment, the covering semiconductor pattern 170 may include polycrystalline silicon.

[0158] In one embodiment, the masking semiconductor pattern 170 may be formed on the sidewall of the active structure 112 facing in the second direction, and on the upper surface of the active structure 112. In another embodiment, the masking semiconductor pattern 170 may comprise a material substantially the same as the material of the uppermost second semiconductor pattern 110b, such that the masking semiconductor pattern 170 on the upper surface of the active structure 112 and the second semiconductor pattern 110b below it may be indistinguishable from each other (e.g., there is no obvious interface between them).

[0159] In one implementation, the masking semiconductor pattern 170 may be on the sidewalls of the active structure 112 in the second direction only, to have a spacer shape.

[0160] When the masking semiconductor pattern 170 is formed, the gate insulating layer pattern 140 included in the gate structure 146 can be formed conformally to cover the surface of the masking semiconductor pattern 170 and the upper surface of the active structure 112. Furthermore, the gate insulating layer pattern 140 can be formed on the inner sidewall of the spacer 130. In an embodiment, the masking semiconductor pattern 170 can be formed between the active structure 112 and the gate structure 146.

[0161] As described above, a masking semiconductor pattern 170 can be formed on the sidewall of the active structure 112 facing in the second direction, thereby increasing the on-current of the fin field-effect transistor.

[0162] Figure 30 and Figure 31 This is a perspective view of each stage in a method for manufacturing a semiconductor device according to an example embodiment.

[0163] First, you can execute the reference. Figures 9 to 13 The process shown is to form as Figure 30 The preliminary active structure 111 is shown.

[0164] refer to Figure 31 It can form a semiconductor pattern 170 to at least cover the sidewalls of the initial active structure 111.

[0165] In one embodiment, the masking semiconductor pattern 170 can be formed into grown silicon by performing a selective epitaxial growth (SEG) process. When performing the selective epitaxial growth process, a masking semiconductor pattern 170 including silicon can be formed on the sidewalls and top surface of the initial active structure 111.

[0166] In one embodiment, a silicon layer can be conformally formed on the sidewalls and top surface of the initial active structure 111 and the isolation pattern 114, and then the silicon layer can be anisotropically etched to form a masking semiconductor pattern 170. In this case, the masking semiconductor pattern 170 can be formed on the sidewall of the initial active structure 111 to have a spacer shape. The silicon layer may include polysilicon.

[0167] Then, it can be executed and referenced. Figures 14 to 19 as well as Figure 1A and Figures 1B to 3 The process shown is the same as the process used to manufacture Figure 29 The semiconductor device shown.

[0168] Figure 32 and Figure 33 These are cross-sectional and perspective views of various stages in a method for manufacturing a semiconductor device according to an example embodiment.

[0169] The methods for manufacturing semiconductor devices can be referenced. Figure 30 and Figure 31 The method shown is the same, except for the step of forming the masking semiconductor pattern.

[0170] First, you can execute the reference. Figures 9 to 19 The process shown is used to form a second opening that exposes the sidewall of the active structure 112 in the second direction, as... Figure 19 As shown.

[0171] refer to Figure 32 and Figure 33 A masking semiconductor pattern 170 can be formed on the sidewalls and top surface of the active structure 112 exposed through the second opening.

[0172] In one embodiment, the masking semiconductor pattern 170 can be formed into grown silicon by performing a selective epitaxial growth (SEG) process. When performing the selective epitaxial growth process, a masking semiconductor pattern 170 including silicon can be formed on the sidewalls and top surface of the active structure 112.

[0173] In this case, it is not necessary to form a masking semiconductor pattern 170 on the sidewall of the active structure 112 located directly below the spacer 130.

[0174] Then, it can be executed and referenced. Figure 1A , Figure 1B and Figure 3 The process shown is the same as the process used to form Figure 29 The semiconductor device shown.

[0175] By summarizing and reviewing, in a fin field-effect transistor, electrons can move only within a limited region included in the active fin structure, thus reducing the on-current (e.g., on-state current) of the fin field-effect transistor.

[0176] One or more embodiments may provide a semiconductor device having an active fin structure.

[0177] One or more embodiments may provide a semiconductor device with good characteristics.

[0178] The semiconductor device according to an example embodiment may include an active fin structure in which silicon patterns and silicon-germanium patterns are stacked repeatedly and alternately. The silicon-germanium patterns may include silicon-rich silicon-germanium (e.g., silicon-doped). In an embodiment, the silicon concentration in the silicon-germanium patterns may be increased, thereby reducing the potential barrier between the silicon and silicon-germanium patterns. Therefore, the potential well may be reduced, or the slope of the potential well may be gentle. Therefore, the area in which electrons move within the active fin structure may be increased, thereby increasing the transistor's on-current.

[0179] Example embodiments have been disclosed herein, and although specific terminology has been used, it is for descriptive purposes only and should be interpreted in a general descriptive sense, not for limiting purposes. In some instances, as will be appreciated by those skilled in the art upon which this application has been filed, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in other embodiments, unless expressly stated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: An active structure on a substrate, the active structure comprising alternating and repeating stacked silicon-germanium patterns and silicon patterns in a vertical direction perpendicular to the upper surface of the substrate; A semiconductor layer is located on the sidewall of the active structure, the sidewall facing in a first direction parallel to the upper surface of the substrate, the semiconductor layer being a source / drain region. as well as A gate structure is provided on the surface of the active structure and the substrate, the gate structure extending in a second direction perpendicular to the first direction. The silicon-germanium pattern is a silicon-rich silicon-germanium with a silicon concentration of 70% to 85%, and in: The silicon concentration in each silicon-germanium pattern in the active structure differs from the silicon concentration in other silicon-germanium patterns in the active structure, and the silicon concentration depends on the distance of each silicon-germanium pattern from the substrate in the vertical direction, or The silicon concentration in each silicon-germanium pattern varies depending on its horizontal position within the pattern.

2. The semiconductor device according to claim 1, wherein: The silicon concentration in each silicon-germanium pattern in the active structure differs from the silicon concentration in other silicon-germanium patterns in the active structure, and the silicon concentration depends on the distance of each silicon-germanium pattern from the substrate in the vertical direction. The silicon concentration in a silicon-germanium pattern farther from the substrate is higher than that in a silicon-germanium pattern closer to the substrate.

3. The semiconductor device according to claim 1, wherein: The silicon concentration in each silicon-germanium pattern varies depending on its horizontal position within the pattern. Each silicon-germanium pattern in the silicon-germanium pattern has the highest silicon concentration at the sidewall facing in the first direction, and The silicon concentration decreases from the sidewalls facing in the first direction toward the center portion of each silicon-germanium pattern in the silicon-germanium pattern.

4. The semiconductor device according to claim 1, wherein: The silicon concentration in each silicon-germanium pattern varies depending on its horizontal position within the pattern. Each of the silicon-germanium patterns has the highest silicon concentration at its sidewall facing in the second direction, and The silicon concentration decreases from the sidewalls facing in the second direction toward the center portion of each silicon-germanium pattern in the silicon-germanium pattern.

5. The semiconductor device according to claim 1, wherein: The gate structure is located on the upper surface of the active structure and on the two sidewalls facing in the second direction, and The gate structure includes a gate insulating layer pattern, a gate pattern, and a hard mask.

6. The semiconductor device according to claim 5, wherein, The thickness of the gate insulating layer pattern is greater than 1 / 2 of the height of one of the silicon-germanium patterns in the vertical direction.

7. The semiconductor device according to claim 1, wherein, The semiconductor layer includes a silicon layer.

8. The semiconductor device according to claim 1, further comprising: Spacers are located on the two sidewalls of the gate structure facing in the first direction.

9. The semiconductor device according to claim 1, further comprising: The semiconductor pattern is masked, covering the sidewalls of the active structure facing in the second direction.

10. The semiconductor device according to claim 9, wherein, The covered semiconductor pattern includes silicon.

11. A semiconductor device, comprising: An active structure on a substrate, the active structure comprising alternating and repeating stacked silicon-germanium patterns and silicon patterns in a vertical direction perpendicular to the upper surface of the substrate; A gate structure is provided on the upper surface of the active structure and on two sidewalls of the active structure facing each other in a second direction parallel to the upper surface of the substrate, the gate structure extending in the second direction; as well as The silicon layer is a source / drain region on the two sidewalls of the active structure facing in a first direction perpendicular to the second direction, and on both sides of the gate structure in the first direction. in: The silicon concentration in the silicon-germanium pattern is 70% to 85%. The gate structure is located on the upper surface of the active structure and on the two sidewalls facing in the second direction. The gate structure includes a gate insulating layer pattern, a gate pattern, and a hard mask, and The thickness of the gate insulating layer pattern is greater than 1 / 2 of the height of one of the silicon-germanium patterns in the vertical direction.

12. The semiconductor device according to claim 11, wherein: The silicon concentration in each silicon-germanium pattern in the active structure is different from the silicon concentration in the other silicon-germanium patterns in the active structure, and The silicon concentration depends on the distance of each silicon-germanium pattern in the silicon-germanium pattern from the substrate in the vertical direction.

13. The semiconductor device according to claim 11, wherein, The silicon concentration in each silicon-germanium pattern varies depending on its horizontal position within the pattern.

14. A semiconductor device, comprising: A first active structure, on a first region of a substrate, includes silicon patterns spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate. A first gate structure is provided on the substrate and the first active structure, and fills the gap between the silicon patterns in the vertical direction in the first active structure. A second active structure, on a second region of the substrate, comprises alternating and repeating silicon-germanium patterns and silicon patterns stacked in the vertical direction. as well as The second gate structure is located on the surface of the second active structure and on the substrate. in: The silicon-germanium pattern in the second active structure is a silicon-rich silicon-germanium with a silicon concentration of 70% to 85%. The first gate structure includes a first gate insulating layer pattern, a first gate pattern, and a hard mask. The second gate structure includes a second gate insulating layer pattern, a second gate pattern, and a hard mask. The thickness of the second gate insulating layer pattern is greater than the thickness of the first gate insulating layer pattern. The thickness of the first gate insulating layer pattern is less than half the height of one of the silicon-germanium patterns in the vertical direction, and The thickness of the second gate insulating layer pattern is greater than 1 / 2 of the height of one of the silicon-germanium patterns in the vertical direction.

Images