Voltage converter

Abstract

Embodiments of the present disclosure relate to voltage converters. In one embodiment, a voltage converter includes a first transistor coupled between an internal node and a first node that receives a supply voltage, a second transistor coupled between the internal node and a second node that receives a reference voltage, an inductor coupled between the internal node and an output node, a first circuit that controls the first transistor and the second transistor, and a second circuit configured to detect when a voltage of the internal node is equal to a voltage of the output node when the first transistor and the second transistor are in an off state to regulate a switching to an on state of the first transistor.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of French Patent Application No. 1912390, filed November 5, 2019, which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic systems and methods, and in particular embodiments to voltage converters. BACKGROUND

[0004] In a switched converter, the supply voltage of the converter is chopped by switching a switch to implement an energy accumulation phase in an inductive element and to implement a recovery phase of the energy accumulated in this inductive element, thereby recovering the charge connected at the output of the converter.

[0005] In a switched converter of PFM (Pulse Frequency Modulation) type, each operating period of the converter comprises an energy accumulation phase in an inductive element, followed by an energy recovery phase of the charge connected to the converter. During the energy accumulation phase, the current flowing through the inductive element increases. During the energy recovery phase, the current flowing through the inductive element decreases. For each operating period, it is desirable that the current flowing through the inductive element is zero at the beginning of the energy accumulation phase and at the end of the energy recovery phase.

[0006] Known switched converters, in particular of PFM type, have various drawbacks. SUMMARY

[0007] Some embodiments address all or some of the drawbacks of known switched converters, in particular of PFM type.

[0008] Some embodiments relate to a DC / DC voltage converter of switched mode power supply type, which converts a direct current (DC) supply voltage into a direct current (DC) output voltage. Some embodiments relate to a DC / DC voltage converter of step-down type, in which the value of the DC output voltage is lower than the value of the DC supply voltage.

[0009] One embodiment provides a voltage converter comprising:

[0010] a first MOS transistor connected between an internal node of the converter and a first node configured to receive a supply potential;

[0011] a second MOS transistor connected between an internal node of the converter and a second node configured to receive a reference potential; an inductor connected between the internal node of the converter and an output node; a first circuit configured to control the first MOS transistor and the second MOS transistor; and a second circuit configured to detect when the potential of the internal node is greater than the supply potential, when the potential of the internal node is less than the reference potential, and when the potential of the internal node is equal to the potential of the output node when the first transistor and the second transistor are in an off state, the detection of the potential of the internal node being equal to the potential of the output node causing a switching control to the on state of the first transistor adjusted by the first circuit.

[0012] According to one embodiment, the second circuit is configured to provide a first signal switching between a first state of the first signal and a second state of the first signal, the first state of the first signal when the first transistor and the second transistor are in the off state and the potential of the internal node is equal to the potential of the output node, the second state of the first signal when the first transistor and the second transistor are in the off state and the potential of the internal node is greater than the supply potential or less than the reference potential.

[0013] According to one embodiment, the first circuit is configured to adjust the control to the on state of the first transistor based on the first signal.

[0014] According to one embodiment, the second circuit comprises a third MOS transistor and a fourth MOS transistor coupled in series between the first node and the second node, the second circuit being configured so that the potential of the internal node determines the off or on state of each of the third transistor and the fourth transistor.

[0015] According to one embodiment, the second circuit is further configured so that the third transistor and the fourth transistor are in the same on or off state when the potential of the internal node is equal to the potential of the output node.

[0016] According to one embodiment, the first signal is determined based on the potential of the drain of the third transistor and the fourth transistor.

[0017] According to one embodiment, the second circuit comprises a combination circuit, one input of the combination circuit being coupled to the drain of the third transistor and the other input of the combination circuit being coupled to the drain of the fourth transistor, the combination circuit comprising an output configured to provide the first signal.

[0018] According to one embodiment, the combination circuit comprises an AND gate, one input of the AND gate being coupled to the drain of the third transistor, the other input of the AND gate being coupled to the drain of the fourth transistor through an inverter gate, and the other output of the AND gate being coupled to the output of the combination circuit.

[0019] According to one embodiment, the sources of the third and fourth transistors are configured to receive the potential of the internal node, or the gates of the third and fourth transistors are configured to receive the potential of the internal node.

[0020] According to one embodiment: the sources of the third and fourth transistors are configured to receive the potential of the internal node; the gates of the third and fourth transistors are configured to receive the potential of the output node; the drain of the third transistor is coupled to the first node; and the drain of the fourth transistor is coupled to the second node.

[0021] According to one embodiment, the first and fourth transistors are PMOS transistors, and the second and third transistors are NMOS transistors.

[0022] According to one embodiment: the gates of the third and fourth transistors are configured to receive the potential of the internal node; the source of the third transistor is coupled to the first node; the source of the fourth transistor is coupled to the second node; and the drain of the third transistor is coupled to the drain of the fourth transistor through at least one resistance.

[0023] According to one embodiment, the first and third transistors are PMOS transistors, and the second and fourth transistors are NMOS transistors.

[0024] According to one embodiment, the converter further comprises a third circuit configured to provide switching of the second signal between the first state of the second signal and the second state of the second signal based on the first signal, the third circuit being configured to: hold the second signal in the second state of the second signal during a first predetermined duration after controlling the second transistor to switch to the off state; switch the second signal to the first state of the second signal after the first duration, after switching the first signal to the first state of the first signal; and hold the second signal in the first state of the second signal during a second predetermined duration after switching the second signal to the first state of the second signal.

[0025] Another embodiment provides an electronic circuit comprising the disclosed converter. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above features and advantages and other features and advantages will be described in detail in the following description of specific embodiments given by way of example only, with reference to the accompanying drawings, in which:

[0027] Figure 1 One exemplary embodiment of a DC / DC voltage converter is shown very schematically;

[0028] Figure 2 A diagram is shown Figure 1a timing diagram illustrating exemplary operation of the converter of

[0029] Figure 3A and Figure 3B respectively show other timing diagrams illustrating Figure 1 expected or theoretical operation and actual or factual operation of the converter of

[0030] Figure 4 one embodiment of a DC / DC voltage converter is shown very schematically;

[0031] Figure 5 one embodiment of a part of the converter of Figure 4 is shown in circuit form;

[0032] Figure 6 one embodiment variant of a part of the converter of Figure 4 is shown in circuit form;

[0033] Figure 7 a timing diagram illustrating operation of the converter of Figure 4 is shown;

[0034] Figure 8 a more detailed embodiment of the converter of Figure 4 is shown; and

[0035] Figure 9 one embodiment of the converter of Figure 4 and Figure 8 is shown. DETAILED DESCRIPTION

[0036] In the various drawings, like features have been indicated by like reference numerals. In particular, structural and / or functional features that are common between various embodiments can have the same reference numerals and can be provided with the same structure, dimensions, and material properties.

[0037] For the sake of clarity, only the operations and elements that are useful in understanding the embodiments described herein are illustrated and described in detail. In particular, typical applications of a DC / DC converter for which the disclosed embodiments are compatible are not described in detail.

[0038] Unless otherwise stated, when two elements are referred to as being connected together, this means a direct connection with no intervening elements other than conductors; when two elements are referred to as being coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0039] In the following disclosure, when referring to absolute position qualifiers (e.g. the terms “front”, “back”, “upper”, “lower”, “left”, “right”, etc.) or relative position qualifiers (e.g. the terms “above”, “below”, “higher”, “lower”, etc.) or orientation qualifiers (e.g. “horizontal”, “vertical”, etc.), reference is made to the orientation shown in the figures, unless otherwise stated.

[0040] The expressions “about”, “approximately”, “substantially” and “in the order of” mean within 10%, preferably within 5%, unless otherwise stated.

[0041] In the following description, when referring to the voltage of a node, it is considered that this relates to the voltage between the node and a reference potential, which is typically ground, unless otherwise stated. Furthermore, when referring to the potential of a node, it is considered that this is referenced to the reference potential, unless otherwise indicated. The voltage and the potential of a given node will further be designated by the same reference sign.

[0042] Figure 1 One example of a voltage converter 1 of the type to which the disclosed embodiments are applicable is shown very schematically. In this example, the converter 1 is a DC / DC converter of the switched mode power supply type, which converts a direct current (DC) supply voltage into a direct current (DC) output voltage.

[0043] The converter 1 is configured to provide a direct current output potential Vout, which is referenced to a reference potential, which is typically ground GND. The converter comprises an output node 2, on which the potential Vout is available.

[0044] The converter 1 is powered by a direct current potential Vbat, which is referenced to a reference potential GND, which is typically ground. The converter 1 is then connected between a first conductive rail or node 3, which is placed at the potential Vbat, and a second conductive rail or node 5, which is placed at the reference potential GND.

[0045] The converter 1 is configured to provide the potential Vout at a value equal to a setpoint value. To this end, the converter 1 receives on an input node 7 a setpoint direct current potential Vref, which is referenced to the potential GND, the value of the setpoint direct current potential Vref representing the setpoint value of the potential Vout, preferably being equal to the setpoint value of the potential Vout.

[0046] In this example, the potentials Vout, Vbat and Vref are positive.

[0047] In this example, the converter 1 is of the step-down / buck type, i.e. the setpoint value of the potential Vout is smaller than the value of the potential Vbat. In other words, the value of the potential Vout is smaller than the value of the potential Vbat.

[0048] The converter 1 comprises a first MOS (Metal Oxide Semiconductor) transistor 9, preferably a PMOS transistor (P-channel MOS transistor). The MOS transistor 9 is connected between the rail 3 and an internal node 11. In other words, a first conductive terminal of the transistor 9 (e.g. its source) is connected to the rail 3 and a second conductive terminal of the transistor 9 (e.g. its drain) is connected to the node 11.

[0049] The converter 1 further comprises a second MOS transistor 13, preferably an NMOS transistor (N-channel MOS transistor). The transistor 13 is connected between the node 11 and the rail 5. In other words, a first conductive terminal of the transistor 13 (e.g. its source) is connected to the rail 5 and a second conductive terminal of the transistor 9 (e.g. its drain) is connected to the node 11.

[0050] Thus, the transistors 9 and 13 are connected in series between the rails 3 and 5 and are connected to each other at the internal node 11.

[0051] The converter 1 comprises an inductive element or inductance 15. The inductance 15 is connected between the node 11 and the node 2.

[0052] The converter 1 comprises a control circuit 17. The circuit 17 is configured to implement or control the operating cycle of the converter 1 to regulate the electric potential Vout so that its value is equal to the setpoint value Vref.

[0053] To this end, the circuit 17 comprises:

[0054] a terminal 171 coupled (preferably connected) to the node 7;

[0055] a terminal 172 coupled (preferably connected) to the node 2;

[0056] a terminal 173 coupled (preferably connected) to the rail 3;

[0057] a terminal 174 coupled (preferably connected) to the rail 5;

[0058] a terminal 175 coupled (preferably connected) to the control terminal or gate of the transistor 9; and

[0059] a terminal 177 coupled (preferably connected) to the control terminal or gate of the transistor 13.

[0060] The converter 1 comprises an output capacitance (not shown) connected between the node 2 and the rail 5. As an example, this capacitance is of the order of 2.2 pF to 20 pF, or even greater. This output capacitance acts as a filter. In other words, this output capacitance of the converter makes it possible to smooth the current present on the node 2 and to store the energy provided by the converter to the node 2.

[0061] Although not shown here, during operation, a charge is connected between node 2 and rail 5, so as to be powered by potential Vout. This charge comprises an input capacitance between node 2 and rail 5. Preferably, duration Ton depends on potential Vbat, and, for a given value of potential Vbat, duration Ton is constant.

[0062] In this example, converter 1 is configured to operate in pulse frequency modulation (discontinuous conduction mode). Circuit 17 is then configured to start an operating period of converter 1 when the value of potential Vout is lower than a setpoint value Vref and both transistors 9 and 13 are in the off state. More specifically, at the start of each operating period, circuit 17 is configured to control putting transistor 9 in the on state, transistor 13 being in the off state. Then, during a first duration Ton, energy is accumulated in inductance 15, first duration Ton being constant for example for each operating period, in each of which transistor 9 is kept in the on state by circuit 17, current IL then circulating in inductance 15. At the end of duration Ton, circuit 17 is configured to control putting transistor 9 in the off state and putting transistor 13 in the on state. Then, during a second duration Toff, energy is restored to the charge connected at the output of the converter by inductance 15, second duration Toff being constant for example for each operating period, in each of which transistor 13 is kept in the on state by circuit 17, current IL then circulating in inductance 15 decreasing. At the end of duration Toff, circuit 17 is configured to control putting transistor 13 in the off state.

[0063] Duration Toff is determined so that the instant at which circuit 17 controls putting transistor 13 in the off state corresponds to the instant at which the current IL circulating in the inductance is cancelled. However, in practice, as will be disclosed in more detail in the remainder of the description, this is not always the case, which is problematic.

[0064] Figure 2 a timing diagram illustrating Figure 1 the desired exemplary operation of converter 1.

[0065] Figure 2 the top timing diagram illustrates the evolution of potential Vout (in volts V) as a function of time t, Figure 2 the bottom timing diagram illustrates the corresponding evolution of current IL flowing in inductance 15 as a function of time t.

[0066] At instant tO, transistors 9 and 13 are in the off state, current IL is zero, and the value of potential Vout is greater than its setpoint value, which is in this example the value of potential Vref.

[0067] Between time instant tO and a subsequent time instant t2, the potential Vout decreases, for example due to the fact that a charge consumption current is connected to the converter 1.

[0068] At a time instant ti between tO and t2, the potential Vout becomes lower than its setpoint value Vref. This is detected by the circuit 17 of the converter 1, which then controls to put the transistor 9 in the conducting state. At time instant t2, the transistor 9 is conducting.

[0069] Therefore, from time instant t2, one terminal of the inductance 15 is connected to the node 2, while one terminal is coupled to the rail 3 via the transistor 9. The current IL circulating through the inductance 15 increases.

[0070] As a result, from time instant t2, the current IL is provided to the node 2, and the capacitance (not shown in the figure) between the node 2 and the rail 5 is charged. The potential Vout increases and is again higher than its setpoint value Vref. Figure 1

[0071] At a subsequent time instant t3, t3 being equal to t2 + Ton, the circuit 17 controls to put the transistor 13 in the conducting state and to put the transistor 9 in the non-conducting state. At time instant t3, the current in the inductance has a maximum value ILp.

[0072] Therefore, from time instant t3, one terminal of the inductance 15 is connected to the node 2, and one terminal is connected to the rail 5 via the transistor 13. The current IL circulating through the inductance 15 decreases.

[0073] Although the current IL decreases from time instant t3, as long as it is not zero, the capacitance between the node 2 and the rail 5 continues to be charged, and the potential Vout continues to increase if the current drawn by the charge is less than the current IL provided to the node 2.

[0074] At a subsequent time instant t4, t4 being equal to t3 + Toff, the circuit 17 controls to put the transistor 13 in the non-conducting state. It is considered here that the converter 1 operates as it should, and that the current IL is then zero at time instant t4. In practice, however, this is not always the case.

[0075] From time instant t4, the current IL is zero, and the potential Vout decreases, similarly to what happens at time instant tO.

[0076] Although not shown here, when the value of the potential Vout returns below its setpoint value Vref at a time instant subsequent to t4, the circuit 17 implements a new operating period as described with respect to the successive time instants t2, t3 and t4.

[0077] Figure 3A and Figure 3B A diagram is shown​Figure 1 the operation of the converter 1. More specifically, Figure 3A an ideal or theoretical example of the evolution of the current IL is shown. Figure 3B an example of the actual evolution of the current IL is shown. Figure 3A and Figure 3B These two timing diagrams illustrate an exemplary operation in which, for several successive operation periods, the voltage Vout is less than the voltage Vref at the end of each operation period of the converter 1.

[0078] At the instant t30, although not illustrated in Figure 3A the voltage Vout is less than the voltage Vref. The operation period begins with the switching of the transistor 9 into the conducting state. As a result, the current IL increases until the subsequent instant t31, which is equal to t30 + Ton.

[0079] At the instant t31, the current IL reaches its maximum value ILp. Moreover, the transistors 9 and 13 are switched into the off state and into the conducting state, respectively. As a result, the current decreases until the subsequent instant t32, which is equal to t31 + Toff.

[0080] In this ideal exemplary operation, the transistor 13 is switched into the off state at the instant t32 and the current IL is cancelled at the instant t32.

[0081] At the instant t32, the voltage Vout is less than the voltage Vref and the transistor 9 is switched into the conducting state, which marks the beginning of a new operation period. The current IL then increases until the subsequent instant t33, which is equal to t32 + Ton.

[0082] At the instant t33, the current IL reaches the value ILp. Moreover, the transistors 9 and 13 are switched into the off state and into the conducting state, respectively. As a result, the current decreases until the subsequent instant t34, which is equal to t33 + Toff.

[0083] In this ideal exemplary operation, the transistor 13 is switched into the off state at the instant t34 and the current IL is cancelled at the instant t34.

[0084] At the instant t34, the voltage Vout is less than the voltage Vref and the transistor 13 is switched into the conducting state, which marks the beginning of a new operation period. The current IL increases until the subsequent instant t35, which is equal to t34 + Ton.

[0085] At the instant t35, the current IL reaches the value ILp. Moreover, the transistors 9 and 13 are switched into the off state and into the conducting state, respectively. As a result, the current decreases until the subsequent instant t36, which is equal to t35 + Toff.

[0086] In this ideal exemplary operation, transistor 13 is switched to the off state at time t36, and the current IL is canceled out at time t36.

[0087] At time t36, the voltage Vout is less than the voltage Vref, and a new operating cycle begins.

[0088] exist Figure 3A In the exemplary theoretical operation shown in the timing diagram, at the end of each operating cycle, when the current IL is canceled out, a switch to the off state of transistor 13 occurs. Therefore, when a new operating cycle immediately follows one, the current IL increases from zero in that new operating cycle.

[0089] Figure 3B The timing diagram illustrates a corresponding practical example of converter 1. In this practical example, the following scenario is considered: transistor 13 does not immediately switch to the off state at the end of the elapsed duration Toff since its last switch to the on state.

[0090] At time t40, the voltage Vout is less than the voltage Vref, and the operating cycle begins from the switching to the on state of transistor 9. As a result, the current IL increases until the subsequent time t41, where t41 equals t40 + Ton.

[0091] At time t41, the current IL reaches its maximum value ILp. Furthermore, transistors 9 and 13 are switched to the off and on states, respectively. As a result, the current decreases until the subsequent time t42, where t42 equals t41 + Toff. The current is then canceled out at time t42. However, switching transistor 13 to the off state is only effective at time t43, which is after time t42. Therefore, between times t42 and t43, the current IL is negative and decreases. In other words, before time t42, the current circulates from node 11 to node 2 in inductor 15; it is canceled out at time t42; and after time t42, it circulates from node 2 to node 11 in inductor 15.

[0092] At time t43, the voltage Vout is less than the voltage Vref, and at time t43, transistor 9 is switched to the on state, marking the start of a new operating cycle. The current IL then increases until the subsequent time t44, where t44 equals t43 + Ton.

[0093] At time t44, the current IL reaches a value ILp' which is lower than the maximum value ILp, due to the fact that the duration Ton is constant in each cycle. Moreover, the transistors 9 and 13 are switched to the off state and to the on state, respectively. As a consequence, the current IL decreases until the subsequent time t46, equal to t44 + Toff, at which time t45 comprised between time t44 and t46 the current IL is cancelled. Moreover, the switching of the transistor 13 to the off state is effective only at time t47, subsequent to time t46. Therefore, between time t45 and t47, the current IL is negative and decreases to a value lower (or greater in absolute value) than the value reached at time t43.

[0094] At time t47, the voltage Vout is lower than the voltage Vref, at which time t47 the transistor 9 is switched to the on state, marking the beginning of a new operating cycle. The current IL then increases until the subsequent time t48, equal to t47 + Ton.

[0095] At time t48, the current IL reaches a value ILp" which is lower than the value ILp'. Moreover, the transistors 9 and 13 are switched to the off state and to the on state, respectively. As a consequence, the current IL decreases until the subsequent time t50, equal to t48 + Toff, at which time t49 comprised between time t48 and t50 the current IL is cancelled. Moreover, the switching of the transistor 13 to the off state is effective only at time t51, subsequent to time t50. Therefore, between time t49 and t51, the current IL is negative and decreases to a value lower (or greater in absolute value) than the value reached at time t47.

[0096] Because, in each operating cycle shown in the timing diagram of Figure 3B the maximum value reached by the current IL (times t41, t44 and t48) is lower and lower, the converter 1 does not provide enough energy to the node 2 to regulate the voltage Vout to its value Vref, for example lower and lower, which is problematic. Moreover, in each operating cycle shown in the timing diagram of Figure 3B the negative value reached by the current IL (times t43, t47 and t51) is lower and lower (or greater in absolute value), therefore the converter 1 draws more and more energy on the node 2, which is not desirable. In theory, the maximum value of the current IL can decrease to infinity, but in practice, before that the transistor 13 is destroyed by the negative value of the current IL, so that the transistor 13 cannot circulate across its conducting terminals.

[0097] With reference to the timing diagram of Figure 3B an actual operating example is described, in which the switching to the off state of the transistor 13 occurs after the cancellation of the current IL.

[0098] In another practical example of operation, not illustrated, in each operating period of a plurality of successive periods implemented one after the other, transistor 13 is switched to the off state while current IL is not zero and is still positive. In this case, in each of these operating periods, current IL increases from a value that is increasingly higher, as a result of which current IL reaches a maximum value that is increasingly higher, and the operating period ends with a value of current IL that is increasingly higher, non-zero and positive. This operation is not as cumbersome as that described with respect to the timing diagram of Figure 3B , because after a number of operating periods, voltage Vout will regain its setpoint value Vref. As a result, the subsequent operating periods will not be performed immediately, which will leave time for the cancellation current IL. However, with respect to the ideal operation described with respect to the timing diagram of Figure 3A , such an operation will cause a higher consumption of converter 1, which is undesirable.

[0099] In some embodiments, the inventors propose to make the start of an operating period subject to the condition that current IL in inductance 15 is zero. In other words, when at the end of an operating period transistor 13 is switched to the off state while current IL is not zero, the inventors propose to delay the start of the subsequent operating period as long as current IL has not returned to the zero value.

[0100] More specifically, the inventors have observed that when transistor 13 is switched to the off state while transistor 9 is off and current IL is non-zero and positive, current IL circulates in the intrinsic or body diode of transistor 13. As a result, the potential of node 11 is negative and equal to -Vdiode, Vdiode being the value (in absolute value) of the voltage across the terminals of the body diode of transistor 13 when current IL circulates in this body diode. The inventors have also observed that when transistor 13 is switched to the off state while transistor 9 is off and current IL is non-zero and negative, current IL next circulates in the intrinsic or body diode of transistor 9. As a result, the potential of node 11 is positive and equal to Vbat + Vdiode, where Vdiode is the value (in absolute value) of the voltage across the terminals of the body diode of transistor 9 when current IL circulates in this body diode. Furthermore, when the potential of node 11 is equal to the potential of node 2, current IL is zero.

[0101] Accordingly, in some embodiments, the inventors suggest exploiting all three states in which the potential of node 11 can vary as a function of current IL when transistors 9 and 13 are in the off state. More specifically, in some embodiments, the inventors suggest detecting, among the three states of the potential of node 11, the state in which the potential of node 11 is equal to the potential of node 2, which means that current IL is then zero. To this end, in some embodiments, the inventors propose a circuit configured to detect, when transistors 9 and 13 are in the off state, when the potential of node 11 is greater than the supply potential Vbat, when the potential of node 11 is less than the reference potential GND, and when the potential of node 11 is equal to the potential of node 2, so that the start of the operating period is subjected to the following detection: the potential of node 11 is equal to the potential of node 2. According to one embodiment, the circuit is configured to provide a signal that switches between a first state, for example a high state when transistors 9 and 13 are in the off state and the potential of node 11 is equal to the potential of the output node, and a second state, for example a low state when transistors 9 and 13 are in the off state and the potential of node 11 is greater than or less than the potential Vbat. The switching of transistor 9 to the on state is then adjusted on the basis of this signal.

[0102] Figure 4 One embodiment of a DC / DC voltage converter 4 comprising such a circuit is illustrated very schematically. Converter 4 comprises many functional or structural elements in common with converter 1 of Figure 1 and will not be repeated here, only the differences between the two converters 1 and 4 being highlighted here.

[0103] With respect to converter 1, converter 4 comprises an additional circuit 40. Circuit 40 is configured to detect, when transistors 9 and 13 are in the off state, when the potential of node 11 is greater than the supply potential Vbat, when the potential of node 11 is less than the reference potential GND, and when the potential of node 11 is equal to the potential of node 2.

[0104] More specifically, circuit 40 is configured to provide, on one of its outputs 41, a signal sig that switches between a first state, for example a high state, for example equal to the potential Vbat of rail 3, and a second state, for example a low state, for example equal to the potential GND of rail 5, the first state being the state in which transistors 9 and 13 are in the off state and circuit 40 detects that the potential of node 11 is equal to the potential of node 2 Vout, the second state being the state in which transistors 9 and 13 are in the off state and circuit 40 detects that the potential of internal node 11 is equal to Vbat + Vdiode (and thus greater than the potential Vbat of rail 3), or equal to -Vdiode (and thus less than the potential GND of rail 5).

[0105] The circuit 40 comprises an input 42 coupled, preferably connected, to the node 11. The input 42 is configured to receive the potential of the node 11, noted V11 in the rest of the disclosure.

[0106] According to a preferred embodiment, not illustrated, the circuit 40 comprises an additional input coupled, preferably connected, to the node 2. This additional input is then configured to receive the potential Vout and is coupled, preferably connected, to the node 2.

[0107] Although not illustrated here, the circuit 40 is preferably powered by the potential Vbat. The circuit 40 then comprises two power supply terminals connected to the rails 3 and 5, respectively.

[0108] In Figure 4 In the illustrated embodiment, the output signal sig of the circuit 40 is directly provided to the input 179 of the circuit 17. The circuit 17 is then configured to regulate the start of each operating period of the converter 4 based on the signal sig. In other words, the circuit 17 is then configured to switch the transistor 9 to the on state at the start of each operating period based on the state of the signal sig. In other words, the circuit 17 is configured to determine, based on the signal sig, whether the current IL in the inductance 15 is zero and to control the switching to the on state of the transistor 9 only when the current IL is zero.

[0109] Figure 5 An embodiment of a part of the converter 4 in the form of a circuit is illustrated. Figure 4 More specifically, Figure 5 An embodiment of the circuit 40 of the converter 4 is illustrated.

[0110] In this embodiment, the circuit 40 comprises an additional input, noted 50 here, configured to receive the potential Vout of the node 2.

[0111] The circuit 40 comprises two MOS transistors 51 and 52 coupled in series between the rails 3 and 5. The circuit 40 is configured so that the potential V11 of the node 11 determines the on or off state of each of the transistors 51 and 52. More specifically, the circuit 40 is configured so that when the potential V11 is equal to the potential Vout, both transistors 51 and 52 are in the same state, in this embodiment the off state. Conversely, the circuit 40 is configured so that when the potential V11 is equal to Vbat+Vdiode and when the potential V11 is equal to -Vdiode, the transistors 51 and 52 are in different on and off states. The transistors 51 and 52 are considered to be in different off and on states if one of these transistors is in the off state while the other of these transistors is in the on state.

[0112] The transistor 51 is connected between the rail 3 and an internal node 53 of the circuit 40, the transistor 52 is connected between the node 53 and the rail 5. More specifically, the transistors 51 and 52 are respectively an NMOS transistor and a PMOS transistor. The transistor 51 comprises a conductive terminal (here its source, coupled, preferably connected to the node 53), another conductive terminal (here its drain, coupled to the rail 3 by means of the resistance R1), and a control terminal or gate (coupled, preferably connected to the input 50 of the circuit 40). The transistor 52 comprises a conductive terminal (here its source, coupled, preferably connected to the node 53), another conductive terminal (here its drain, coupled to the rail 5 by means of the resistance R2), and a control terminal or gate (coupled, preferably connected to the input 50 of the circuit 40). In other words, the control terminals of the transistors 51 and 52 are connected to each other and are configured to receive the potential Vout of the node 2, the sources of the transistors 51 and 52 are coupled, preferably connected to each other and are configured to receive the potential V11 of the node 11.

[0113] The circuit 40 further comprises a combinational circuit 55, i.e. a circuit comprising one or more logic gates. The circuit 55 is configured to provide a signal sig based on the potentials of the drains of the transistors 51 and 52. The circuit 55 comprises a first input 551 connected to the drain of the transistor 51, a second input 552 connected to the drain of the transistor 52, and an output 553 connected to the output 41 of the circuit 40. The output 553 of the circuit 55 is configured to provide the signal sig.

[0114] According to one embodiment, the circuit 55 comprises an AND logic gate 554. An input of the gate 554 is coupled, preferably connected to the input 551 of the circuit 55, and thus to the drain of the transistor 51. The other input of the gate 554 is coupled to the input 52 of the circuit 55, and thus to the drain of the transistor 52, by using an inverter gate 555. The output of the gate 554 is coupled, preferably connected to the output 553 of the circuit 50, and thus to the output 41 of the circuit 40.

[0115] Figure 5 The operation of the circuit 40 of Fig. 4 is as follows.

[0116] When the potential V11 is equal to Vbat + Vdiode, the transistor 51 is off due to the fact that its gate is at a potential Vout lower than the potential Vbat + Vdiode of its source. In addition, the transistor 52 is on due to the fact that its gate is at a potential Vout greater than the potential Vbat + Vdiode of its source. As a result, the drain potential of the transistor 51 is closer to the potential Vbat than to the potential GND and is then considered to be at a high level or state. In addition, the drain potential of the transistor 52 is also closer to the potential Vbat than to the potential GND and is then considered to be at a high level or state. The gate 554 thus provides the signal sig at a high level or state.

[0117] When the potential V11 is equal to -Vdiode, the transistor 51 is on due to the fact that its gate is at a potential Vout greater than the potential -Vdiode of its source. In addition, the transistor 52 is off due to the fact that its gate is at a potential Vout lower than the potential -Vdiode of its source. As a result, the drain potential of the transistor 51 is closer to the potential GND than to the potential Vbat and is then considered to be at a low level or state. In addition, the drain potential of the transistor 52 is also closer to the potential GND than to the potential Vbat and is then considered to be at a low level or state. The gate 554 thus provides the signal sig at a low level or state.

[0118] When the potential V11 is equal to the potential Vout of the node 2, the transistors 51 and 52 are both off due to the fact that their gates are at the same potential as their sources. As a result, the drain potential of the transistor 51 is closer to the potential Vbat than to the potential GND and is then considered to be at a high state. Conversely, the drain potential of the transistor 52 is closer to the potential GND than to the potential Vbat and is then considered to be at a low state. The gate 554 provides the signal sig at a high level or state.

[0119] Thus, when the circuit 40 of Figure 4 is provided in the converter 4, Figure 5 the condition for the switching of the transistor 9 to the on state is that the signal sig is at a high state.

[0120] The person skilled in the art is able to determine the values of the resistors R1 and R2 to obtain the operation disclosed above.

[0121] In one embodiment variant not shown, the circuit 55 can be implemented using other logic gates, for example using a NAND gate instead of the gate 554. In the latter example, the high state and the low state of the signal sig are then inverted and the operation of the converter 4 is adapted accordingly.

[0122] In another embodiment variant not shown, it is provided that when this circuit 40 is not used, for example when Figure 4When one or the other of transistors 9 and 13 of converter 4 is in the on state, Figure 5 The input 42 of circuit 40 is disconnected. As an example, then at node 11 of converter 4 and... Figure 5 A switch is provided between inputs 42 of circuit 40. Converter 4 then includes a circuit configured to: place the switch in an open state when one of transistors 9 and 13 is turned on, and place the switch in a closed state when one of transistors 9 and 13 is turned off. Specifically, the circuit can generate control signals for the switch based on control signals for transistors 9 and 13 provided by circuit 17.

[0123] Figure 6 It is shown in circuit form Figure 4 A variant of an embodiment of converter 4. More specifically, Figure 6 A variant embodiment of the circuit 40 of converter 4 is shown.

[0124] In this embodiment, circuit 40 does not include an additional input configured to receive the potential Vout of node 2.

[0125] Circuit 40 includes two MOS transistors 61 and 62 series coupled between rails 3 and 5. Circuit 40 is configured such that the potential V11 of node 11 determines the on or off state of each of transistors 61 and 62. More specifically, circuit 40 is configured such that when potential V11 equals potential Vout, both transistors 61 and 62 are in the same state, which is the on state in this embodiment. Conversely, circuit 40 is configured such that when potential V11 equals Vbat + Vdiode and when potential V11 equals -Vdiode, transistors 61 and 62 are in different on and off states.

[0126] The transistor 61 is connected between the rail 3 and a transistor 62, which is connected between the transistor 61 and the rail 5. In other words, the transistor 61 couples the rail 3 through its conductive terminal to a conductive terminal of the transistor 62, which couples the rail 5 through its conductive terminal to a conductive terminal of the transistor 61. More specifically, the transistors 61 and 62 are a PMOS transistor and an NMOS transistor, respectively. The transistor 61 comprises a conductive terminal, here its source, which is coupled, preferably connected, to the rail 3, another conductive terminal, here its drain, which is coupled, here through the use of a resistor R, to the transistor 62, and a control terminal or gate, which is coupled, preferably connected, to the input 42 of the circuit 40. The transistor 62 comprises a conductive terminal, here its source, which is coupled, preferably connected, to the rail 5, another conductive terminal, here its drain, which is coupled, here through the resistor R, to the transistor 61, and a control terminal or gate, which is coupled, preferably connected, to the input 42 of the circuit 40. In other words, the control terminals of the transistors 61 and 62 are connected to each other and configured to receive the potential V11 of the node 11, and the drains of the transistors 61 and 62 are coupled to each other through the resistor R. In a not shown embodiment variant, the resistor R is replaced by several resistors R in series between the transistors 61 and 62.

[0127] The circuit 40 further comprises a combination circuit 55. The circuit 55 is here configured to provide the signal sig based on the potentials of the drains of the transistors 61 and 62. A first input 551 of the circuit 55 is coupled, e.g. connected, to the drain of the transistor 61, a second input 552 of the circuit 55 is coupled, e.g. connected, to the drain of the transistor 62, and an output 553 of the circuit 55 is connected to the output 41 of the circuit 40.

[0128] Figure 6 The operation of the circuit 40 of Fig. 4 is as follows.

[0129] When the potential V11 is equal to Vbat + Vdiode, the transistor 61 is off due to the fact that its gate is at a potential V11 which is greater than the potential Vbat of its source. Moreover, the transistor 62 is on due to the fact that its gate is at a potential V11 which is greater than the potential GND of its source. As a result, the drain potential of the transistor 61 is closer to the potential GND than to the potential Vbat, and is then considered to be in a low state. Moreover, the drain potential of the transistor 62 is also closer to the potential GND than to the potential Vbat due to the fact that the transistor 62 is on, and is then considered to be in a low state. Thus, the gate 554 provides the signal sig in a low state.

[0130] When the potential V11 is equal to -Vdiode, the transistor 61 is on due to the fact that its gate is at a potential -Vdiode lower than its source potential Vbat. Moreover, the transistor 62 is off due to the fact that its gate is at a potential -Vdiode lower than its source potential GND. As a result, the drain potential of the transistor 61 is closer to the potential Vbat than to the potential GND, and is then considered in a high state, due to the fact that the transistor 61 is on. Moreover, the drain potential of the transistor 62 is closer to the potential Vbat than to the potential GND, and is then considered in a high state. Therefore, the gate 554 provides the signal sig in a low state.

[0131] When the potential V11 is equal to the potential Vout of the node 2, both transistors 61 and 62 are on. In particular, the transistor 61 is on due to the fact that its gate is at a potential Vout lower than its source potential Vbat, and the transistor 62 is on due to the fact that its gate is at a potential Vout greater than its source potential GND. As a result, the drain potential of the transistor 61 is closer to the potential Vbat than to the potential GND, and is then considered in a high state. On the contrary, the drain potential of the transistor 62 is closer to the potential GND than to the potential Vbat, and is then considered in a low state. Therefore, the gate 554 provides the signal sig in a high state.

[0132] Therefore, when in the converter 4 of Figure 4 the circuit 40 of Figure 6 is provided, the condition for the switching to the on state of the transistor 9 is that the signal sig is in a high state.

[0133] The person skilled in the art is able to determine the value of the resistance R or resistances to be coupled in series to each other with the transistors 61 and 62 to obtain the operations disclosed above.

[0134] In one embodiment variant not shown, the circuit 55 can be implemented using other logic gates, for example using a NAND gate instead of the gate 554. In the latter example, the high and low states of the signal sig are then inverted, and the operation of the converter 4 is adapted accordingly.

[0135] In yet another embodiment variant not shown, there is provided a switch 56 to be coupled between the node 2 and the gate of the transistor 61, when the circuit 40 is not used, for example when Figure 4 the transistor 9 and 13 of the converter 4 are in the on state, the transistor 61 is off and the transistor 62 is on. Figure 6Circuit 40 is then deactivated. As an example, a switch is provided between the drain of transistor 61 and resistor R, and another switch is provided between the drain of transistor 62 and resistor R. Converter 4 includes a circuit configured to turn these switches off when one of transistors 9 and 13 is on, and to turn them off when one of transistors 9 and 13 is off. Specifically, this circuit can generate control signals for the switches based on control signals for transistors 9 and 13 provided by circuit 17.

[0136] Figure 7 The illustration is shown. Figure 4 The timing diagram of the converter's operation. More specifically, Figure 7 The timing diagram illustrates the following situation, where, for several consecutive operating cycles, at the end of each operating cycle of converter 4, the voltage Vout is less than the voltage Vref. Further consider an example where transistor 13 is switched off while the current IL is negative.

[0137] At time t70, although Figure 7 Not shown in the diagram, but the voltage Vout is less than Vref, and circuit 17 determines that the current IL is zero based on the signal sig. The operating cycle then begins from switching to the on state of transistor 9. As a result, the current IL increases until the subsequent time t71, where t71 equals t70 + Ton.

[0138] At time t71, the current IL reaches its maximum value ILp. Furthermore, transistors 9 and 13 are switched to the off and on states, respectively, by circuit 17. As a result, the current decreases until the subsequent time t72, where t72 equals t71 + Toff. The current is then canceled out at time t72. However, switching transistor 13 to the off state is only effective at time t73, after time t72. Therefore, between times t72 and t73, the current IL is negative and decreases.

[0139] At time t73, the voltage Vout is less than the voltage Vref. However, circuit 17 determines that the current IL is not zero based on the signal sig. Therefore, at time t73, circuit 17 does not switch transistor 9 to the on state. The current IL circulating through the body diode of transistor 13 then gradually increases until it reaches zero at time t74, after time t73. At time t74, circuit 17 determines that the current IL is zero based on the signal sig, and since the voltage Vout is less than the voltage Vref, circuit 17 switches transistor 9 to the on state, marking the start of a new operating cycle. The current IL then increases until the subsequent time t75, where t75 equals t74 + Ton.

[0140] At time t75, the current IL reaches the value ILp. Moreover, the transistors 9 and 13 are switched to the off state and to the on state, respectively. As a result, the current IL decreases until a subsequent time t76, t76 being equal to t75 + Toff. The switching of the transistor 13 to the off state is only effective at a time t77 following time t76. Therefore, between times t76 and t77, the current IL is negative and decreases.

[0141] At time t77, the voltage Vout is lower than the voltage Vref. However, the circuit 17 determines, on the basis of the signal sig, that the current IL is not zero. Therefore, at time t77, the circuit 17 does not switch the transistor 9 to the on state. The current IL, which circulates through the body diode of the transistor 13, then increases gradually until it is zero at a time t78 following time t77. At time t78, the circuit 17 determines, on the basis of the signal sig, that the current IL is zero and, since the voltage Vout is lower than the voltage Vref, the circuit 17 switches the transistor 9 to the on state, which marks the beginning of a new operating period. The current IL then increases until a subsequent time t79, t79 being equal to t78 + Ton.

[0142] At time t79, the current IL reaches the value ILp. Moreover, the transistors 9 and 13 are switched to the off state and to the on state, respectively. As a result, the current IL decreases until a subsequent time t80, t80 being equal to t79 + Toff.

[0143] With respect to the timing diagram described with respect to Figure 3B Although the switching to the off state of the transistor 13 occurs while the current IL is negative, the circuit 17 is able to delay the implementation of the new operating period (switching of the transistor 9 to the on state) until the current IL has a zero value, thanks to the circuit 40 and the signal sig it provides, with respect to the timing diagram described with respect to

[0144] Although Figure 7 The timing diagram described with respect to the converter 4 operates in the case where the switching to the off state of the transistor 13 occurs while the current IL is negative, the circuit 40 also has an advantage in the case where the transistor 13 is switched to the off state while the current IL is still positive, for example because the duration Toff is too short with respect to the duration Ton.

[0145] For example, when transistor 13 switches to the off state while the current IL is positive and the voltage Vout is lower than the voltage Vref, the circuit 17 determines, on the basis of the signal sig, that the current IL is not zero. The circuit 17 therefore does not switch transistor 9 to the on state. The current IL circulating in the body diode of transistor 9 then decreases until it is cancelled. The circuit 17 determines, on the basis of the signal sig, that the current IL is zero, and if the voltage Vout is still lower than the voltage Vref, the circuit 17 controls the start of a new operating period by switching transistor 9 to the on state. In such an operating state, as described with respect to Figure 7 , in each operating period, the current IL reaches the same maximum value ILp, and the voltage Vout is kept regulated to its setpoint value.

[0146] Figure 8 A more detailed embodiment of the converter of Figure 4 is shown. Here only the details not illustrated in Figure 4 are highlighted, which relate to the circuit 17 of the converter 4, delimited by the dashed box in Figure 8 .

[0147] The circuit 17 comprises a finite state machine 300. The finite state machine 300 can be implemented, for example, using custom combinational logic coupled to a memory. Other implementations can also be possible, for example using a programmable general purpose controller.

[0148] The finite state machine 300 is configured to provide the control signals of the transistors 9 and 13 to the respective terminals 175 and 177, to perform the operations disclosed with respect to Figures 4 to 7 . To determine the control signals of the transistors 9 and 13, the finite state machine 300 receives several signals. As an example, the finite state machine 300 is implemented by a circuit. The circuit 300 is powered by the potential Vbat and is connected between the rails 3 and 5, these connections not being described in detail in Figure 8 , so as not to overload this figure.

[0149] Circuit 17 includes a comparator 302 configured to provide a signal START at its output, the signal START representing a comparison of the value of potential Vout with its setpoint value. The output of comparator 302 is coupled, for example, to circuit 300. When the value of potential Vout is lower than its setpoint value, the signal START is in a first state (e.g., a high state), and when the value of potential Vout is higher than its setpoint value, the signal START is in a second state (e.g., a low state). Comparator 302 includes a first input (e.g., an inverting input (-)) and a second input (e.g., a non-inverting input (+)), the first input being configured to receive a potential whose value represents the value of potential Vout, and the second input being configured to receive a potential whose value represents the setpoint value of potential Vout.

[0150] In this example, when the value of potential Vref is equal to the setpoint value of potential Vout, comparator 302 is configured to compare potential Vref with potential Vout. The first input of comparator 302 is connected to node 2, and the second input of comparator 302 is connected to terminal 171 of circuit 17.

[0151] In this embodiment, the duration Ton is determined by comparing the potential ramp RP with either potential Vref or potential Vout, the latter of which can be considered equal to potential Vref. Therefore, circuit 17 includes a ramp generator 304 and a comparator 306, the ramp generator 304 being configured to provide the potential ramp RP, and the comparator 306 being configured to compare the ramp RP with potential Vref or Vout (potential Vref in this example). Potential RP is referenced to a reference potential GND.

[0152] Generator 304 is powered by potential Vbat and is connected between rails 3 and 5. These connections are... Figure 8 The details are not shown in the accompanying drawing to avoid overloading the drawing.

[0153] Generator 304 is controlled by circuit 300 using signal cmdP. More specifically, when the START signal is in a first state indicating that the value of potential VOUT is less than its setpoint value, if both transistors 9 and 11 are in the off state and if circuit 300 determines that current IL is zero based on the received signal sig, circuit 300 controls transistor 9 to be turned on, and simultaneously controls the initiation or start of potential ramp RP via signal cmdP. As an example, signal cmdP is determined based on the control signal provided by circuit 300 to transistor 9, or is the same as the control signal provided by circuit 300 to transistor 9.

[0154] According to one embodiment, each potential ramp RP is an incremental ramp starting from the reference potential GND.

[0155] The ramp RP is transmitted to a first input (e.g. non-inverted input (+)) of the comparator 306, a second input (e.g. inverted input (-)) of the comparator 306 receives the potential Vref, and the output of the comparator 306 provides the signal COMP to the circuit 300.

[0156] According to Figure 8 The potential ramp RP is transmitted to the comparator 306 by using a selection circuit 308 comprising two inputs, an output and a control terminal, according to the preferred embodiment illustrated. The control terminal of the circuit 308 receives the signal sel from the circuit 300. According to the state of the signal sel, the circuit 308 transmits on its output the signal present on one or the other of its inputs.

[0157] More specifically, at the instant at which the circuit 300 controls the placing of the transistor 9 in the conducting state and the start of the potential ramp RP, the circuit 300 places the signal sel in the first state, so that the comparator 306 receives the potential ramp RP.

[0158] Thus, as long as the signal sel remains in its first state, the signal COMP is in the first state (e.g. low state), and the potential RP is lower than the potential Vref, and as soon as the potential RP becomes greater than the potential Vref, the signal COMP switches to the second state (e.g. high state).

[0159] The switching of the signal COMP from its first state to its second state marks the end of the duration Ton. The circuit 300 then controls the placing of the transistor 9 in the off state and the placing of the transistor 13 in the conducting state. Preferably, the circuit 300 controls the end of the potential ramp RP simultaneously via the signal cmdP.

[0160] In this embodiment, the duration Toff is determined by comparing the potential ramp RN with the potential Vref or the potential Vout, and more specifically in this example with the potential Vref. Thus, the circuit 17 comprises a ramp generator 310 configured to provide the potential ramp RN.

[0161] The generator 310 is powered by the potential Vbat and is connected between the rails 3 and 5, these connections not being shown in detail in the figure in order not to overload it. The generator 310 is controlled by the circuit 300 by means of the signal cmdN. Figure 8

[0162] ​More specifically, at the end of the duration Ton, when the circuit 300 controls the transistor 9 to be in the off state and the transistor 13 to be in the on state, the circuit 300 also controls the start of the potential ramp RN via the signal cmdN. As an example, the signal cmdN is determined on the basis of, or identical to, the control signal provided by the circuit 300 to the transistor 13.

[0163] According to one embodiment, each potential ramp RN is a ramp decreasing from the supply potential Vbat.

[0164] According to Figure 8 In the illustrated embodiment, the comparison of the ramp RN with the potential Vref is implemented by the comparator 306. The ramp RN is then transmitted to the second input of the circuit 308. Moreover, the circuit 300 is configured to switch the signal sel to its second state while controlling the transistor 9 to be in the off state and the transistor 13 to be in the on state, so that the ramp RN is transmitted to the comparator 306.

[0165] Thus, in the embodiment where each ramp RN is a ramp decreasing from the potential Vbat, the signal COMP is in its second state (e.g. high state) as long as the signal sel remains in its second state, while the potential RN is greater than the potential Vref, and switches to its first state (e.g. low state RN) as soon as the potential becomes lower than the potential Vref.

[0166] The switching of the signal COMP from its second state to its first state marks the end of the duration Toff. The circuit 300 then controls the transistor 13 to be in the off state. Preferably, the circuit 300 controls the end of the potential ramp RN via the signal cmdN at the same time.

[0167] In an embodiment variant not illustrated, the comparison of the potential ramp RP with the potential Vref is performed by the comparator 306, and the comparison of the potential ramp RN with the potential Vref is performed using an additional comparator provided in the circuit 17. This additional comparator then receives the potential ramp RN on a first input (e.g. non-inverted input (+)) and the potential Vref on a second input (e.g. inverted input (-)), the output of the additional comparator providing the circuit 300 with a representative comparison signal of the potential ramp RN with the potential Vref. In this variant, the circuit 308 is omitted and the circuit 300 does not generate the signal sel. The person skilled in the art is able to adapt the disclosure of the converter 4 provided above to this embodiment variant. Figure 8

[0168] ​In another embodiment variant, not illustrated, the ramp RP is a decreasing potential ramp from the potential Vbat and / or the potential ramp RN is an increasing potential ramp from the potential GND. The skilled person is able to adapt the converter 4 for this case.

[0169] Moreover, although exemplary embodiments have been disclosed in which the ramps RP and RN are compared with the potential Vref, the skilled person is able to implement a case in which the ramps RP and RN are compared with the potential Vout.

[0170] In the previously disclosed embodiments and variants, when the transistor 13 is switched to the off state while the current IL is negative, the potential V11 varies from the value GND (transistor 13 on) to the value Vbat + Vdiode (transistor 13 off). During the transition from the value GND to the value Vbat + Vdiode, the potential V11 takes or crosses the value of the potential Vout, which can cause the signal sig to switch to its first state, but in fact the current IL is not at a stable zero value. For example, in order not to restart a new operating period, it can be desirable not to consider the switching of the signal sig to the first state. In fact, this can cause a new operating period to start while the current IL does not have a stable zero value (for example, while the current IL is negative). Moreover, a similar switching of the signal sig to its first state can occur when the transistor 13 is switched to the off state while the current IL is still positive.

[0171] According to one embodiment, the converter 4 is configured to filter the switching operation of the signal sig to its first state during a predetermined time delay duration from the switching of the transistor 13 to the off state. In other words, the converter 4 is configured to consider the switching of the signal sig to its first state only after the end of the time delay duration. For example, this time delay duration is of the order of 10 ns, for example equal to 10 ns.

[0172] According to one example, the circuit 17 (for example, its circuit 300) is configured to consider the switching operation of the signal sig only after the time delay duration has elapsed.

[0173] According to another example, the converter 4 comprises a circuit 17 not illustrated in the figures, for example, a circuit 300 not illustrated in the figures. Figure 4 and Figure 8The additional circuit is configured to generate a filtered signal on the basis of the signal sig, the filtered signal corresponding to the signal sig with the difference that there are no any switches during the time delay duration. In other words, the additional circuit is configured to provide, outside the time delay period, a filtered signal that switches after each switch of the signal sig, and to maintain the state of the filtered signal throughout the time delay duration. In other words, the filtered signal switches from a first state to a second state each time the signal sig switches from its first state to its second state, and switches from its second state to its first state each time the signal sig switches from its second state to its first state, except during the time delay duration in which the filtered signal remains in the second state. The circuit 17 is then configured to adjust the switching to the on state of the transistor 9 in dependence on the state of the filtered signal. The filtered signal is obtained on the basis of the signal sig, the circuit 17 being in fact configured to adjust the switching to the on state of the transistor 9 on the basis of the signal sig.

[0174] The skilled person is able to provide other embodiments, for example by implementing a filtering function of the switching operation of the signal sig during the time delay duration, so that it can be avoided to take into account the switching of the signal sig to the first state not representing the current IL having a stable zero value.

[0175] Moreover, as similarly in the previously described embodiments and variants, the potential V11 of the node 11 can in fact have oscillations around the value of the potential Vout when the current IL in the inductance 15 is cancelled. As a result, the signal sig or the above disclosed filtered signal can also have oscillations, for example as long as the potential V11 does not have a stable value equal to the value of the potential Vout.

[0176] According to one embodiment, the converter 4 is configured to store, after the time delay duration, the first state of the signal sig or of the corresponding filtered signal of the first switch.

[0177] According to one example, the storage is performed by the circuit 300, for example directly by the finite state machine of the circuit 300.

[0178] According to another example, the converter 4 comprises a circuit 300 not shown in the figure, the circuit 300 being configured to store the first state of the signal sig or of the corresponding filtered signal of the first switch, after the time delay duration. Figure 4 and Figure 8The additional circuitry, illustrated in Fig. 6, is configured to perform the stored function. The additional circuitry is configured to provide, after the time delay duration, the additional signal switched to the first state when the signal sig or the filtered signal is switched to its first state, and then to maintain the first state of the additional signal during a predetermined duration, for example at least until the transistor 9 is controlled to the on state, or at least until the transistor 13 is switched to the on state. As an example, the circuit 17 (e.g. its circuit 300) receives the additional signal and causes the switching of the transistor 9 (the start of the new operating period) to be subject to the fact that the additional signal is in its first state. The additional signal is obtained on the basis of the signal sig, or in turn on the basis of the filtered signal, the switching of the transistor 9 to the on state being in fact regulated on the basis of, or in other words by, the signal sig.

[0179] The skilled person is able to provide other embodiments, for example other embodiments of the function for storing the first switching of the signal sig or of the filtered signal to the first state after the time delay duration, so that any oscillations of the signal sig can be taken into account when the current IL is cancelled.

[0180] According to one embodiment, the converter 4 comprises a circuit configured to implement the filtering function and the storing function as described above. The circuit is then configured to provide, on the basis of the signal sig, a signal sig' switched between a first state and a second state (e.g. low and high, respectively); to maintain the signal sig' in its second state during a predetermined time delay duration after the control transistor 13 is switched to the off state; to switch the signal sig' to its first state during the first switching of the signal sig to its first state as soon as the time delay duration has elapsed; and to maintain the signal sig' in its first state during a predetermined duration, after which the switching of the signal sig' to its first state takes place after the time delay duration, for example while maintaining at least the first state of the signal sig' until the transistor 9 or even the transistor 13 is switched to the on state in the next operating period.

[0181] In such embodiments, the circuit 17 is then configured to make the switching of the transistor 9 to the conductive state subject to the first state of the signal sig'. Since the signal sig' is obtained on the basis of the signal sig, the switching of the transistor 9 to the conductive state is indeed regulated on the basis of the signal sig. Moreover, in such embodiments, it can be provided that the circuit 300 receives, between the signal sig' and the signal START, a signal START' resulting from a logic operation, for example an AND logic, such that the signal START' is in a state, such as a high state, only when the voltage Vout is lower than the voltage Vref and the signal sig' is in its first state, and is in another state, for example a low state, otherwise. In this case, the circuit 300 starts a new operating cycle as soon as the signal START' is in a state indicating that the voltage Vout is less than Vref and the signal sig' is in its first state.

[0182] Figure 9 An embodiment of a circuit 90 configured to generate the signal sig' as described above is shown.

[0183] The circuit 90 comprises a D flip-flop 92. The data input D of the flip-flop 92 is coupled, preferably connected, to the potential V corresponding to the first state of the signal sig'. The output Q of the flip-flop 92 provides the signal sig'. The synchronous input clk of the flip-flop 92 is coupled, preferably connected, to the output 41 of the circuit 40 receiving the signal sig. Figure 4 Figure 5 Figure 6 and Figure 8 The flip-flop 92 further comprises an initialization input R configured to receive an initialization signal init. When the initialization signal is in an inactive state, for example a low state, the level of the input D is copied on the output Q each time the signal sig is switched from its second state to its first state, and when the signal init is in an active state, for example a high state, the output Q of the flip-flop 92 is forced to the level corresponding to the second state of the signal sig'.

[0184] ​​As an example, when transistor 13 is in the on state, signal init is in the active state, and as long as the time delay duration after transistor 13 switches to the off state has not been completed, signal init is in the inactive state, for example. Thus, when transistor 13 is on, signal init is active, and signal sig’ is in its second state. Moreover, when transistor 9 is off but the time delay duration has not been completed, signal init is active and signal sig’ remains in its second state. Once the time delay is completed, as soon as signal sig switches from its second state to its first state, the output Q of flip-flop 92 switches to the potential V, with the result that signal sig’ switches to its first state, which remains as long as signal init remains inactive.

[0185] Based on the above disclosed operation, it will be understood that signal init can be obtained on the basis of the control signal of transistor 13, which is available on output 177 of circuit 17 Figure 4 and Figure 8 ). For example, signal init corresponds to the control signal of transistor 13 to which a delay equal to the time delay duration is applied.

[0186] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these embodiments can be combined, and will easily think of other variants.

[0187] Finally, based on the functional description provided above, it is within the ability of the person skilled in the art to implement a practical implementation of the embodiments and variants described herein. In particular, the person skilled in the art is able to design a circuit(s) implementing a filtering function applied to signal sig to take into account any first switching of signal sig to its first state when the current IL in the inductance does not have a zero value and a stable value, and implementing a filtering function to take into account any oscillations of signal sig when the current IL is cancelled.

Claims

1. A voltage converter, comprising: A first transistor is coupled between a first node and an internal node of the voltage converter, the first node being configured to receive a power supply voltage. A second transistor is coupled between the internal node and the second node, the second node being configured to receive a reference voltage. An inductor is coupled between the output node of the voltage converter and the internal node; A first circuit is configured to control the first transistor and the second transistor; as well as A second circuit is configured to detect when the internal node voltage of the internal node equals the output voltage of the output node when the first transistor and the second transistor are turned off, wherein the first circuit is configured to turn on the first transistor when the second circuit detects that the internal node voltage equals the output voltage.

2. The voltage converter of claim 1, wherein the second circuit is configured to provide a first signal, wherein the first signal is configured to: When the first transistor and the second transistor are turned off and the internal node voltage is greater than the power supply voltage or less than the reference voltage, the signal switches from a first state to a second state; and When the first transistor and the second transistor are turned off and the internal node voltage is equal to the output voltage, the signal switches from the second state to the first state.

3. The voltage converter of claim 2, wherein the first circuit is configured to turn on the first transistor based on the first signal.

4. The voltage converter of claim 2, wherein the second circuit includes a third transistor and a fourth transistor, the third transistor and the fourth transistor being coupled in series between the first node and the second node, the second circuit being configured such that the internal node voltage determines the off or on state of each of the third transistor and the fourth transistor.

5. The voltage converter of claim 4, wherein the second circuit is further configured such that when the internal node voltage is equal to the output voltage, the third transistor and the fourth transistor are in the same on or off state.

6. The voltage converter of claim 4, wherein the third transistor and the fourth transistor are metal-oxide-semiconductor (MOS) transistors, and wherein the first signal is determined based on the drain voltages of the third transistor and the fourth transistor.

7. The voltage converter of claim 4, wherein the second circuit includes a combination circuit having: a first input coupled to a first current path terminal of the third transistor, a second input coupled to a first current path terminal of the fourth transistor, and an output configured to provide the first signal.

8. The voltage converter of claim 7, wherein the combinational circuit includes an AND gate having: a first input coupled to the first current path terminal of the third transistor, a second input coupled to the first current path terminal of the fourth transistor via an inverter gate, and an output coupled to the output of the combinational circuit.

9. The voltage converter of claim 4, wherein the third transistor and the fourth transistor are metal-oxide-semiconductor (MOS) transistors, and wherein the source terminals of the third transistor and the fourth transistor are configured to receive the internal node voltage.

10. The voltage converter of claim 9, wherein the gate terminals of the third transistor and the fourth transistor are configured to receive the output voltage, wherein the drain terminal of the third transistor is coupled to the first node, and wherein the drain of the fourth transistor is coupled to the second node.

11. The voltage converter of claim 10, wherein the first transistor and the fourth transistor are p-type transistors, and wherein the second transistor and the third transistor are n-type transistors.

12. The voltage converter of claim 4, wherein the control terminals of the third transistor and the fourth transistor are configured to receive the internal node voltage.

13. The voltage converter of claim 12, wherein the first current path terminal of the third transistor is coupled to the first node, the first current path terminal of the fourth transistor is coupled to the second node, and the second current path terminal of the third transistor is coupled to the second current path terminal of the fourth transistor via a resistor.

14. The voltage converter of claim 13, wherein the first transistor and the third transistor are p-type transistors, and wherein the second transistor and the fourth transistor are n-type transistors.

15. The voltage converter of claim 14, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are metal-oxide-semiconductor (MOS) transistors.

16. The voltage converter of claim 2, further comprising a third circuit configured to provide a second signal based on the first signal, the second signal being configured to switch between a first state and a second state of the second signal, wherein the third circuit is configured to: During a first predetermined duration after the second transistor is turned off, the second signal is maintained in the second state of the second signal; After the first predetermined duration, after the first signal switches to the first state of the first signal, the second signal switches to the first state of the second signal; and During a second predetermined duration after the second signal switches to the first state of the second signal, the second signal is maintained in the first state of the second signal.

17. A method of operating a voltage converter, the method comprising: Receive power supply voltage at the first rail; The reference voltage is received at the second rail. An regulated output voltage is delivered at the output node by controlling a first transistor and a second transistor, wherein the first transistor is coupled between the first rail and the internal node, wherein the second transistor is coupled between the internal node and the second rail, and wherein the internal node is coupled to the output node via an inductor. When the first transistor and the second transistor are turned off, detect when the internal node voltage of the internal node is equal to the regulated output voltage; as well as When the internal node voltage is detected to be equal to the regulated output voltage while the first transistor and the second transistor are off, the first transistor is turned on.

18. The method of claim 17, wherein controlling the first transistor and the second transistor comprises: At each operating cycle of the voltage converter, the following sequence is performed sequentially: Set the first transistor to the ON state; Set the first transistor to the off state and the second transistor to the on state; and Set the second transistor to the off state.

19. An electronic circuit, comprising: A first circuit has: a first output configured to be coupled to a control terminal of a first transistor, a second output configured to be coupled to a control terminal of a second transistor, and a first input configured to be coupled to the first transistor and the second transistor via an inductor; as well as The second circuit has: a first input configured to be coupled to the first input of the first circuit via the inductor, a second input coupled to the first input of the first circuit, and an output coupled to the second input of the first circuit, the second circuit being configured to assert an output signal at the output of the second circuit when the first transistor and the second transistor are turned off and a first voltage at the first input of the second circuit is equal to a second voltage at the second input of the second circuit, and wherein the first circuit is configured to turn on the first transistor when the output signal of the second circuit is asserted.

20. The electronic circuit of claim 19, wherein the second circuit comprises: The third transistor has a current path coupled between a first node and a second node, the first node being configured to receive a power supply voltage and the second node being configured to receive a reference voltage. as well as A fourth transistor has a current path coupled between the current path of the first transistor and the second node, wherein a first internal node is coupled to the first input of the second circuit, the first internal node is coupled between the current path of the third transistor and the current path of the fourth transistor, and wherein the control terminals of the third transistor and the fourth transistor are coupled to the second input of the second circuit.

21. The electronic circuit of claim 20, wherein the second circuit further comprises: A first resistor is coupled between the current path of the third transistor and the first node; And a second resistor, which is coupled between the current path of the fourth transistor and the second node.

22. The electronic circuit of claim 20, wherein the second circuit further comprises a logic circuit having: a first input coupled to a second internal node, a second input coupled to a third internal node, and an output coupled to the output of the second circuit, the second internal node being coupled between the current path of the third transistor and the first node, and the third internal node being coupled between the current path of the fourth transistor and the second node.

23. The electronic circuit of claim 19, wherein the first circuit comprises: A first comparator has an input coupled to the first input of the first circuit; as well as A finite state machine having: a first output coupled to the first output of the first circuit, a second output coupled to the second output of the first circuit, a first input coupled to the output of the first comparator, and a second input coupled to the second input of the first circuit.

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