Dram testing method, apparatus, readable storage medium, and electronic device
By conducting two rounds of testing on the DRAM, traversing all memory cells and comparing data, the problem of low fault coverage in existing technologies is solved, and more reliable test results are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-02-20
- Publication Date
- 2026-03-24
AI Technical Summary
Existing technologies have low fault coverage in DRAM testing, making it difficult to detect defects in memory cells and resulting in unreliable test results.
A two-round testing method is adopted. Starting from the first and last addresses of the DRAM, all memory cells are traversed in two rounds, with preset test cells as the unit. Data read and write operations are performed, and the read data is compared with the written data. The preset test data for the first round is the inverse of the second round. The final test result is determined by the results of the two rounds of testing.
It improves fault coverage, enhances the reliability of test results, can detect chip defects that are difficult to find, and improves product quality.
Smart Images
Figure CN112802532B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of DRAM chip testing, and in particular to a DRAM testing method and device, a readable storage medium and an electronic device. BACKGROUND
[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems, which can be applied to Double Data Rate (DDR) modules for personal computers or servers and Low Power Double Data Rate (LPDDR) chips for embedded ARM architecture.
[0003] The basic storage unit of LPDDR is a cell, and computers and embedded systems store and read data by writing high or low levels in the cell.
[0004] In addition, current DRAMs use burst read and write methods for efficient access rates, that is, read and write operations in a storage array are performed in units of burst length (BL), and a plurality of bit (such as 8 bits, 16 bits, or 32 bits) column addresses are read and written at a time, and data composed of 0 and 1 is accessed in each burst length. For example, the addressed row is 0, and the burst length is 8 bits, so 1 bit of data is written to each bit in the space from 0 column to 7 column in row 0, a total of 8 bits, the second burst length is from 8 column to 15 column in row 0, and so on. When the storage locations in a row are all written, the memory controller (MC) positions the address of the next row and continues the same operation.
[0005] Writing a value different from the value of the surrounding cell to the storage cell, such as writing 1 to a cell and 0 to the surrounding cell, will cause a potential difference to accelerate the leakage of the storage cell. If the storage cell has a defect, such leakage will cause the value stored in the cell to jump, such as from 0 to 1 or from 1 to 0. In addition, the memory controller accesses the storage cell by first activating (ACT) the row (Row) and then accessing a column, and then pre-charging (PRE) the row. After a series of complete operations, the next row can be accessed. After a number of ACT-PRE processes, some defective rows will lose their stored content. SUMMARY
[0006] The technical problem solved by the present application is to provide a DRAM testing method, device, readable storage medium and electronic equipment, which can improve the coverage rate of faults in testing DRAM.
[0007] To solve the above technical problems, the present application adopts a technical solution:
[0008] A DRAM testing method comprises the steps of:
[0009] Two rounds of testing are performed on the DRAM to be tested, and first and second comparison results are obtained respectively;
[0010] The testing comprises:
[0011] The preset test data is written into the DRAM to be tested until all the memory cells of the DRAM to be tested are written with data;
[0012] Starting from the first address and the last address of the DRAM to be tested, preset test units are traversed from the beginning to the middle until all the memory cells of the DRAM to be tested are traversed;
[0013] For the target test unit traversed, data read-write operation is performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data;
[0014] The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing;
[0015] The test result of the DRAM to be tested is obtained according to the first and second comparison results.
[0016] To solve the above technical problems, the present application adopts another technical solution:
[0017] A DRAM testing device comprises:
[0018] A data read-write module is configured to perform two rounds of testing on the DRAM to be tested, and first and second comparison results are obtained respectively;
[0019] The testing comprises:
[0020] The preset test data is written into the DRAM to be tested until all the memory cells of the DRAM to be tested are written with data;
[0021] Starting from the first address and the last address of the DRAM to be tested, preset test units are traversed from the beginning to the middle until all the memory cells of the DRAM to be tested are traversed;
[0022] For the target preset test unit traversed, data read-write operation is performed on the target preset test unit based on the preset test data, and the read data is compared with the corresponding written data;
[0023] The preset test data of the first round of tests is the inverse of the preset test data of the second round of tests;
[0024] The test module is configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0025] To solve the above technical problems, another technical solution adopted by the present application is:
[0026] A computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to implement each step of the DRAM test method.
[0027] To solve the above technical problems, another technical solution adopted by the present application is:
[0028] An electronic device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor executes the computer program to implement each step of the DRAM test method.
[0029] The present application has the following advantages:
[0030] The present application has the following advantages: BRIEF DESCRIPTION OF DRAWINGS
[0031] Figure 1 A step flow chart of a DRAM test method according to an embodiment of the present application;
[0032] Figure 2 A structural schematic diagram of a DRAM testing device according to an embodiment of the present application;
[0033] Figure 3 A structural schematic diagram of an electronic device according to an embodiment of the present application;
[0034] Figure 4 A schematic diagram of preset test data and the inverse of the preset test data in a DRAM testing method according to an embodiment of the present application;
[0035] Figure 5 A flowchart of a DRAM testing method according to an embodiment of the present application;
[0036] Figure 6 A first round of testing schematic diagram in which a preset test unit includes two preset operation bits in a DRAM testing method according to an embodiment of the present application;
[0037] Figure 7 A second round of testing schematic diagram in which a preset test unit includes two preset operation bits in a DRAM testing method according to an embodiment of the present application;
[0038] Figure 8 A first round of testing schematic diagram in which a preset test unit includes four preset operation bits in a DRAM testing method according to an embodiment of the present application;
[0039] Figure 9 A second round of testing schematic diagram in which a preset test unit includes four preset operation bits in a DRAM testing method according to an embodiment of the present application. DETAILED DESCRIPTION
[0040] To make the technical content, the achieved purposes and effects of the present application clear, the following will be described in detail in combination with the embodiments and the accompanying drawings.
[0041] Please refer to Figure 1 The present application provides a DRAM testing method, which comprises the following steps:
[0042] Two rounds of testing are performed on the DRAM to be tested, and a first comparison result and a second comparison result are obtained respectively;
[0043] The testing comprises:
[0044] The preset test data is written into the DRAM to be tested until all the storage units of the DRAM to be tested are written with data;
[0045] The preset test unit is taken as a unit to traverse from the first address and the last address of the DRAM to be tested to the middle until all the storage units of the DRAM to be tested are traversed;
[0046] For the target test unit traversed, data read-write operation is performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data;
[0047] The preset test data of the first round of tests is the inverse of the preset test data of the second round of tests;
[0048] The test result of the DRAM to be tested is obtained according to the first comparison result and the second comparison result.
[0049] As can be seen from the above description, the beneficial effects of the present application are that: by performing two rounds of tests on the DRAM to be tested, starting from the first address and the last address of the DRAM to be tested to the middle, all the storage units of the DRAM to be tested are traversed, for the target test unit traversed, data read-write operation is performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data, the final test result is obtained through the comparison results of the two rounds of tests, since the storage unit with defects will lose the stored content after multiple ACT-PRE operations, starting from the first address and the last address of the DRAM to be tested to the middle, all the storage units of the DRAM to be tested are traversed, the first and last address jump access is realized, the ACT-PRE operation of simulating the activation of the row, accessing a column, and then pre-charging the row is realized, the previous test blind area is covered, and the chip defects that are difficult to be found in the prior art are detected, the fault coverage is improved, the reliability of the test result is enhanced, and the product yield is improved.
[0050] Further, the writing of the preset test data into the DRAM to be tested until all the storage units of the DRAM to be tested are written with data comprises:
[0051] The preset test data is written into the low address of each preset read-write unit of the DRAM to be tested in units of a preset burst length until all the storage units of the DRAM to be tested are written with data.
[0052] As can be seen from the above description, by writing the preset test data into the DRAM to be tested in units of a burst length, the data writing speed can be improved, and the time complexity is low, which is suitable for mass production testing.
[0053] Further, the starting from the first address and the last address of the DRAM to be tested to the middle in units of a preset test unit until all the storage units of the DRAM to be tested are traversed comprises:
[0054] starting from the first address of the untraversed storage region of the DRAM to be tested to traverse a preset test unit in the middle, and then jumping to the last address of the untraversed storage region of the DRAM to be tested, starting from the last address to traverse a preset test unit in the middle;
[0055] returning to the step of starting from the first address of the untraversed storage region of the DRAM to be tested to traverse a preset test unit in the middle until all storage units of the DRAM to be tested are traversed.
[0056] As can be seen from the above description, starting from the first address of the untraversed storage region of the DRAM to be tested to traverse a preset test unit in the middle, and then starting from the last address to traverse a preset test unit in the middle, the first and last address jump access is realized, the ACT-PRE operation is simulated, the previous test blind area can be covered, and the chip defects that are difficult to be found in the prior art can be detected, so that the multi-storage unit fault is triggered, and the fault coverage is improved.
[0057] Further, the starting from the first address and the last address of the DRAM to be tested to traverse a preset test unit in the middle is performed twice in sequence until all storage units of the DRAM to be tested are traversed.
[0058] The preset test unit includes a plurality of preset operation units.
[0059] The data read-write operation based on the preset test data to the target test unit, and the comparison of the read data with the corresponding written data for the traversed target test unit include:
[0060] For the first target test unit traversed in the first traversal, the data of each preset operation unit in the first target test unit is read, and the read data is compared with the corresponding written data.
[0061] For each preset operation unit, after the comparison, it is judged whether the preset operation unit is at an odd position of the preset test unit, and if so, the inverse of the preset test data is written to the preset operation unit.
[0062] For the second target test unit traversed in the second traversal, the data of each preset operation unit in the second target test unit is read, and the read data is compared with the corresponding written data.
[0063] For each preset operation unit, after the comparison, it is judged whether the preset operation unit is at an even position of the preset test unit, and if so, the inverse of the preset test data is written to the preset operation unit.
[0064] From the above description, it can be seen that the twice traversal of the DRAM, due to the writing of different levels of values to the storage unit and the surrounding unit, can cause a potential difference, for the target test unit in the first traversal, reading the data of each preset operation unit and writing the inverse of the preset test data to the preset operation unit at the odd position, for the target test unit in the second traversal, reading the data of each preset operation unit and writing the inverse of the preset test data to the preset operation unit at the even position, can well simulate this potential difference, cover the previous test blind area and detect the chip defects that are difficult to be found in the prior art, and ensure the reliability and accuracy of the test.
[0065] Further, the second round of testing further comprises the steps of:
[0066] reading the data of all preset test units of the DRAM to be tested, and comparing the read data with the corresponding written data.
[0067] From the above description, it can be seen that finally reading the data of all preset test units of the DRAM to be tested can again detect whether the data in the storage unit after the test meets the expectation, thereby improving the accuracy of the test and enhancing the reliability of the test result.
[0068] Further, the preset read-write unit comprises a row or a column.
[0069] From the above description, it can be seen that the test personnel can set the first preset read-write unit to be a row or a column according to the needs, and the flexibility is high.
[0070] Further, the test result of the DRAM to be tested according to the first comparison result and the second comparison result comprises:
[0071] If the first comparison result and the second comparison result are consistent, the test result is successful, otherwise, the test result is failed.
[0072] From the above description, it can be seen that by obtaining the first comparison result and the second comparison result through two rounds of testing, chip defects that are difficult to be found can be detected, the fault coverage rate during the test is improved, and the reliability of the test is ensured.
[0073] Please refer to Figure 2 , another embodiment of the present application provides a DRAM test device, comprising:
[0074] a data read-write module, configured to test the DRAM to be tested in two rounds to obtain a first comparison result and a second comparison result respectively;
[0075] The test comprises:
[0076] write preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested are written with data;
[0077] traverse from the first address and the last address of the DRAM to be tested to the middle of the DRAM to be tested in preset test units until all memory cells of the DRAM to be tested are traversed;
[0078] for the target preset test unit traversed, perform data read-write operation on the target preset test unit based on the preset test data, and compare the read data with the corresponding written data;
[0079] the preset test data of the first round of test is the inverse of the preset test data of the second round of test;
[0080] a test module configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result.
[0081] Another embodiment of the present application provides a computer readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement each step of the DRAM test method.
[0082] Please refer to Figure 3 Another embodiment of the present application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements each step of the DRAM test method when executing the computer program.
[0083] The above DRAM test method, device, computer readable storage medium and electronic device can be applied to the test of any type of DRAM, such as each generation of DDR and LPDDR products, which will be described in detail in the specific embodiments:
[0084] Embodiment one
[0085] Please refer to Figure 1 The DRAM test method of the present embodiment includes the following steps:
[0086] S1, performing two rounds of test on the DRAM to be tested to obtain a first comparison result and a second comparison result;
[0087] The test includes:
[0088] S11, writing preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested are written with data;
[0089] Specifically, the preset test data is written starting from the low address of each preset read / write cell of the DRAM under test, in units of a preset burst length, until all memory cells of the DRAM under test are written with data.
[0090] The preset read / write unit can be flexibly configured according to actual needs, such as being set as a column or a row;
[0091] The burst length (BL) is defined by the JEDEC standard, but it can also be set arbitrarily. This means that multiple bits (e.g., 8 bits or 16 bits) are used for reading and writing at the same time. For example, when writing data based on rows, if the address is row 0 and the burst length is 8 bits, the first 8 bits of the data to be written are written simultaneously starting at the position of row 0, column 0. Then, the second burst length is used to write bits 9-16 of the data to be written, and so on until the storage location of row 0 is completely written. Then, the address of the next row is repositioned and the operation of the previous row is continued until the data is written to the entire disk. Reading data is a similar operation.
[0092] In this embodiment, the preset read / write unit is a row, such as... Figure 6 As shown in (a);
[0093] For example, start writing preset test data from the first column of the first row. After writing the first row, start writing preset test data from the first column of the second row, and so on, until data is written to each row of the DRAM to be tested.
[0094] S12. Starting from the first and last addresses of the DRAM to be tested and traversing towards the middle in units of preset test units until all memory units of the DRAM to be tested have been traversed.
[0095] Specifically, starting from the first address of the untraversed memory region in the DRAM to be tested, traverse one preset test unit towards the middle, then jump to the last address of the untraversed memory region in the DRAM to be tested, and traverse one preset test unit from the last address towards the middle.
[0096] Return to the step of traversing one preset test cell from the first address of the untraversed memory region in the DRAM to be tested towards the middle, until all memory cells of the DRAM to be tested have been traversed;
[0097] The process is executed twice in sequence, starting from the first and last addresses of the DRAM under test and moving towards the middle, in units of preset test units, until all memory units of the DRAM under test have been traversed.
[0098] The preset test unit includes multiple preset operation units;
[0099] Among them, there can be more than two preset operation units. In this embodiment, the preset test unit includes two preset operation units.
[0100] For example, if the memory array has 4 rows and 4 columns, start from the 0th column of the 0th row of the untraversed memory area in the DRAM to be tested and traverse towards the middle one preset test cell. Then start from the 3rd column of the 3rd row and traverse towards the middle one preset test cell. If a preset test cell includes 2 preset operation units, then start from the 2nd column of the 0th row of the DRAM to be tested and traverse towards the middle one preset test cell. Then start from the 1st column of the 3rd row and traverse towards the middle one preset test cell. If a preset test cell includes 3 preset operation units, then start from the 3rd column of the 0th row of the DRAM to be tested and traverse towards the middle one preset test cell. Then start from the 0th column of the 3rd row and traverse towards the middle one preset test cell. And so on, until all memory cells of the DRAM to be tested have been traversed.
[0101] The above traversal of the DRAM to be tested is performed twice;
[0102] S13. For the target test unit that has been traversed, perform data read and write operations on the target test unit based on the preset test data, and compare the read data with the corresponding written data.
[0103] Specifically, for the first target test unit traversed in the first traversal, the data of each preset operation unit in the first target test unit is read, and the read data is compared with the corresponding written data;
[0104] For each preset operation unit, after the comparison is performed, it is determined whether the preset operation unit is in an odd position of the preset test unit. If so, the inverse of the preset test data is written to the preset operation unit.
[0105] Wherein, if the preset operation unit is located at an even position of the preset test unit, no write operation is performed on the preset operation unit;
[0106] For example, if a preset test unit includes two preset operation units, then for the target test unit traversed in the first traversal, the data of the two preset operation units is read, the read data is compared with the corresponding written data, and then the inverse of the preset test data is written to the first preset operation unit in the preset test unit, and no write operation is performed on its second preset operation bit.
[0107] If a preset test unit includes 4 preset operation units, then for the target test unit traversed in the first traversal, the data of the 4 preset operation units is read, the read data is compared with the corresponding written data, and then the inverse of the preset test data is written to the first and third preset operation units in the preset test unit, and no write operation is performed on its second and fourth preset operation bits.
[0108] For the second target test unit traversed in the second traversal, read the data of each preset operation unit in the second target test unit, and compare the read data with the corresponding written data.
[0109] For each preset operation unit, after the comparison is performed, it is determined whether the preset operation unit is in an even position of the preset test unit. If so, the inverse of the preset test data is written to the preset operation unit.
[0110] Wherein, if the preset operation unit is located at an odd position of the preset test unit, no write operation is performed on the preset operation unit;
[0111] For example, if a preset test unit includes two preset operation units, then for the target test unit traversed in the first traversal, the data of the two preset operation units is read, the read data is compared with the corresponding written data, and then the inverse of the preset test data is written to the second preset operation unit in the preset test unit, and no write operation is performed on its first preset operation bit.
[0112] If a preset test unit includes 5 preset operation units, then for the target test unit traversed in the first traversal, the data of the 5 preset operation units is read, the read data is compared with the corresponding written data, and then the inverse of the preset test data is written to the second and fourth preset operation units in the preset test unit. No write operation is performed on its first, third and fifth preset operation bits.
[0113] After the first round of testing is completed, the second round of testing will be conducted. The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing.
[0114] The second round of testing also includes the following steps:
[0115] Read the data from all preset test units of the DRAM to be tested, and compare the read data with the corresponding written data;
[0116] For example, if the storage array has 4 rows and 4 columns, and a preset test unit includes 2 preset operation units, then there are 8 preset test units in the storage array. Read the data from these 8 preset test units and compare the read data with the corresponding written data.
[0117] S2. Obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result;
[0118] If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.
[0119] In this embodiment, specific references are made. Figures 4-7 First, the first round of testing was performed on the DRAM to be tested:
[0120] like Figure 4 , 5 As shown, the test data to be written is defined as / D = 10101010……1010, and its inverse is D = 01010101……0101. Assuming the preset burst length is BL = 8 bits, then / D = 10101010, D = 01010101;
[0121] S1. The address is row 0, column 0. Start writing test data / D from the memory cell corresponding to row 0, column 0, following the BL instruction. After writing row 0, start writing test data / D from row 1, column 0, and so on, until the entire memory array is written with data. Figure 6 As shown in (a);
[0122] After the data is written, the data in the DRAM to be tested is as follows: Figure 6 As shown in (d);
[0123] Perform the first traversal, such as Figure 6 As shown in (b), starting from the first address (R0, C0) of the untraced memory area, a preset test unit is traversed towards the middle. Data from two preset operation units in the preset test unit is read, the read data is compared with / D, and then D is written to the preset operation unit on (R0, C0).
[0124] Starting from the last address (R3, C3) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the two preset operation units in the preset test unit, compare the read data with / D, and then write D to the preset operation unit at (R3, C3);
[0125] Starting from the first address (R0, C2) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the two preset operation units in the preset test unit, compare the read data with / D, and then write D to the preset operation unit at (R0, C2);
[0126] Starting from the last address (R3, C1) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the two preset operation units in the preset test unit, compare the read data with / D, and then write D to the preset operation unit at (R3, C1);
[0127] And so on, that is, according to Figure 6 (b) Iterate through the numbers (1) to (16) until all memory cells of the DRAM to be tested have been traversed;
[0128] After the first traversal, the DRAM data to be tested is as follows: Figure 6 As shown in (e);
[0129] Perform a second traversal, such as Figure 6 As shown in (c), starting from the first address (R0, C0) of the untraversed memory area, a preset test unit is traversed towards the middle. Data from two preset operation units in the preset test unit is read. The data read from the preset operation unit on (R0, C0) is compared with D. The data read from the preset operation unit on (R0, C1) is compared with / D. Then, D is written to the preset operation unit on (R0, C1).
[0130] Starting from the last address (R3, C3) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the two preset operation units in the preset test unit, compare the data read from the preset operation unit at (R3, C3) with D, compare the data read from the preset operation unit at (R3, C2) with / D, and then write D to the preset operation unit at (R3, C2).
[0131] Starting from the first address (R0, C2) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the two preset operation units in the preset test unit, compare the data read from the preset operation unit at (R0, C2) with D, compare the data read from the preset operation unit at (R0, C3) with / D, and then write D to the preset operation unit at (R0, C3).
[0132] Starting from the last address (R3, C1) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the two preset operation units in the preset test unit, compare the data read from the preset operation unit at (R3, C1) with D, compare the data read from the preset operation unit at (R3, C0) with / D, and then write D to the preset operation unit at (R3, C0).
[0133] And so on, that is, according to Figure 6 (c) Iterate through the numbers (1) to (16) until all memory cells of the DRAM to be tested have been traversed.
[0134] After the second traversal, the DRAM data to be tested is as follows: Figure 7 As shown in (f);
[0135] Obtain the first comparison result;
[0136] In the second round of testing, the test data to be written is defined as D = 10101010, and its inverse / D = 01010101:
[0137] Perform the first traversal, such as Figure 7 As shown in (a), starting from the first address (R0, C0) of the untraversed memory area, a preset test unit is traversed towards the middle. Data from two preset operation units in the preset test unit is read, the read data is compared with D, and then / D is written to the preset operation unit on (R0, C0).
[0138] Starting from the last address (R3, C3) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the two preset operation units in the preset test unit, compare the read data with D, and then write / D to the preset operation unit at (R3, C3);
[0139] Starting from the first address (R0, C2) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the two preset operation units in the preset test unit, compare the read data with D, and then write / D to the preset operation unit at (R0, C2);
[0140] Starting from the last address (R3, C1) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the two preset operation units in the preset test unit, compare the read data with D, and then write / D to the preset operation unit at (R3, C1);
[0141] And so on, that is, according to Figure 7(a) Iterate through the numbers (1) to (16) until all memory cells of the DRAM to be tested have been traversed.
[0142] After the first traversal, the DRAM data to be tested is as follows: Figure 7 As shown in (d);
[0143] Perform a second traversal, such as Figure 7 As shown in (b), starting from the first address (R0, C0) of the untraversed memory area, a preset test unit is traversed towards the middle. Data from two preset operation units in the preset test unit is read. The data read from the preset operation unit on (R0, C0) is compared with / D. The data read from the preset operation unit on (R0, C1) is compared with D. Then / D is written to the preset operation unit on (R0, C1).
[0144] Starting from the last address (R3, C3) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the two preset operation units in the preset test unit, compare the data read from the preset operation unit at (R3, C3) with / D, compare the data read from the preset operation unit at (R3, C2) with D, and then write / D to the preset operation unit at (R3, C2).
[0145] Starting from the first address (R0, C2) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the two preset operation units in the preset test unit, compare the data read from the preset operation unit at (R0, C2) with / D, compare the data read from the preset operation unit at (R0, C3) with D, and then write / D to the preset operation unit at (R0, C3).
[0146] Starting from the last address (R3, C1) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the two preset operation units in the preset test unit, compare the data read from the preset operation unit at (R3, C1) with / D, compare the data read from the preset operation unit at (R3, C0) with D, and then write / D to the preset operation unit at (R3, C0).
[0147] And so on, that is, according to Figure 7 (b) Iterate through the numbers (1) to (16) until all memory cells of the DRAM to be tested have been traversed;
[0148] After the second traversal, the DRAM data to be tested is as follows: Figure 7 As shown in (e);
[0149] Read data from all preset test units, and compare the read data with / D, such as... Figures 8-9 As shown in (c);
[0150] A second comparison result was obtained;
[0151] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.
[0152] Example 2
[0153] Please refer to Figure 8 The difference between this embodiment and Embodiment 1 is that the preset read / write unit is a column, and the preset test unit includes 4 preset operation units, specifically:
[0154] like Figure 8 As shown in (a), the address is the 0th column and the 0th row. Starting from the storage cell corresponding to the 0th column and the 0th row, write test data / D according to BL. That is, write test data / D from the 0th column and the 0th row to the 0th column and the 3rd column. After writing, start writing test data / D from the 1st row of the 0th column. After writing all rows from the 0th column to the 3rd column, the entire storage array is now filled with data.
[0155] After the data is written, the data in the DRAM to be tested is as follows: Figure 8 As shown in (d);
[0156] Perform the first traversal, such as Figure 8 As shown in (b), starting from the first address (R0, C0) of the untraversed memory area, a preset test unit is traversed towards the middle. Data from the four preset operation units in the preset test unit is read, the read data is compared with / D, and then D is written to the preset operation units on (R0, C0) and (R0, C2).
[0157] Starting from the last address (R3, C3) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the 4 preset operation units in the preset test unit, compare the read data with / D, and then write D to the preset operation units at (R3, C3) and (R3, C1).
[0158] Starting from the first address (R1, C0) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the 4 preset operation units in the preset test unit, compare the read data with / D, and then write D to the preset operation units at (R1, C0) and (R1, C2).
[0159] Starting from the last address (R2, C3) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the 4 preset operation units in the preset test unit, compare the read data with / D, and then write D to the preset operation units at (R2, C3) and (R2, C1);
[0160] After the first traversal, the DRAM data to be tested is as follows: Figure 8 As shown in (e);
[0161] Perform a second traversal, such as Figure 8 As shown in (c), starting from the first address (R0, C0) of the untraversed memory area, a preset test unit is traversed towards the middle. Data from the four preset operation units in the preset test unit is read. The data read from the preset operation units on (R0, C0) and (R0, C2) is compared with D. The data read from the preset operation units on (R0, C1) and (R0, C3) is compared with / D. Then, D is written to the preset operation units on (R0, C1) and (R0, C3).
[0162] Starting from the last address (R3, C3) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the 4 preset operation units in the preset test unit, compare the data read from the preset operation units at (R3, C3) and (R3, C1) with D, compare the data read from the preset operation units at (R3, C2) and (R3, C0) with / D, and then write D to the preset operation units at (R3, C2) and (R3, C0).
[0163] Starting from the first address (R1, C0) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the four preset operation units in the preset test unit, compare the data read from the preset operation units at (R1, C0) and (R1, C2) with D, compare the data read from the preset operation units at (R1, C1) and (R1, C3) with / D, and then write D to the preset operation units at (R1, C1) and (R1, C3).
[0164] Starting from the last address (R2, C3) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the 4 preset operation units in the preset test unit, compare the data read from the preset operation units at (R2, C3) and (R2, C1) with D, compare the data read from the preset operation units at (R2, C2) and (R2, C0) with / D, and then write D to the preset operation units at (R2, C2) and (R2, C0).
[0165] After the second traversal, the DRAM data to be tested is as follows: Figure 9 As shown in (f);
[0166] Obtain the first comparison result;
[0167] In the second round of testing, the test data to be written is defined as D = 10101010, and its inverse / D = 01010101:
[0168] Perform the first traversal, such as Figure 9 As shown in (a), starting from the first address (R0, C0) of the untraversed memory area, a preset test unit is traversed towards the middle. Data from the four preset operation units in the preset test unit is read, the read data is compared with D, and then / D is written to the preset operation units on (R0, C0) and (R0, C2).
[0169] Starting from the last address (R3, C3) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the 4 preset operation units in the preset test unit, compare the read data with D, and then write / D to the preset operation units at (R3, C3) and (R3, C1).
[0170] Starting from the first address (R1, C0) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the 4 preset operation units in the preset test unit, compare the read data with D, and then write / D to the preset operation units at (R1, C0) and (R1, C2);
[0171] Starting from the last address (R2, C3) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the 4 preset operation units in the preset test unit, compare the read data with D, and then write / D to the preset operation units at (R2, C3) and (R2, C1);
[0172] After the first traversal, the DRAM data to be tested is as follows: Figure 9 As shown in (d);
[0173] Perform a second traversal, such as Figure 9 As shown in (b), starting from the first address (R0, C0) of the untraversed memory area, a preset test unit is traversed towards the middle. Data from the four preset operation units in the preset test unit is read. The data read from the preset operation units on (R0, C0) and (R0, C2) is compared with / D. The data read from the preset operation units on (R0, C1) and (R0, C3) is compared with D. Then / D is written to the preset operation units on (R0, C1) and (R0, C3).
[0174] Starting from the last address (R3, C3) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the four preset operation units in the preset test unit, compare the data read from the preset operation units at (R3, C3) and (R3, C1) with / D, compare the data read from the preset operation units at (R3, C2) and (R3, C0) with D, and then write / D to the preset operation units at (R3, C2) and (R3, C0).
[0175] Starting from the first address (R1, C0) of the untraversed memory area, traverse a preset test unit towards the middle, read the data of the four preset operation units in the preset test unit, compare the data read from the preset operation units at (R1, C0) and (R1, C2) with / D, compare the data read from the preset operation units at (R1, C1) and (R1, C3) with D, and then write / D to the preset operation units at (R1, C1) and (R1, C3).
[0176] Starting from the last address (R2, C3) of the untraversed memory area, traverse towards the middle to a preset test unit, read the data of the 4 preset operation units in the preset test unit, compare the data read from the preset operation units at (R2, C3) and (R2, C1) with / D, compare the data read from the preset operation units at (R2, C2) and (R2, C0) with D, and then write / D to the preset operation units at (R2, C2) and (R2, C0).
[0177] After the second traversal, the DRAM data to be tested is as follows: Figure 9 As shown in (e);
[0178] Read data from all preset test units, and compare the read data with / D, such as... Figure 2 As shown in (c);
[0179] A second comparison result was obtained;
[0180] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.
[0181] Example 3
[0182] Please refer to Figure 3 A DRAM testing apparatus, comprising:
[0183] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.
[0184] The test includes:
[0185] Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data;
[0186] Starting from the first and last addresses of the DRAM under test, the system traverses towards the middle in units of preset test units until all memory cells of the DRAM under test have been traversed.
[0187] For each target preset test unit traversed, data read and write operations are performed on the target preset test unit based on the preset test data, and the read data is compared with the corresponding written data.
[0188] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;
[0189] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.
[0190] Example 4
[0191] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the various steps of the DRAM testing method in Embodiment 1 or Embodiment 2.
[0192] Example 5
[0193] Please refer to An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps of the DRAM testing method in Embodiment 1 or Embodiment 2.
[0194] In summary, the DRAM testing method, apparatus, readable storage medium, and electronic device provided by this invention perform two rounds of testing on the DRAM to be tested. During the process of writing preset test data to the DRAM to be tested, writing is performed in units of a preset burst length, which can improve data writing speed and reduce time complexity, facilitating mass production testing. Starting from the first address of an untraversed memory region in the DRAM to be tested, a preset test unit is traversed towards the middle, and then another preset test unit is traversed from the last address towards the middle. This operation is repeated until all memory units of the DRAM to be tested have been traversed, achieving address jump access and simulating the ACT-PRE operation. The above traversal is performed twice in sequence. Because writing a different voltage level to a memory unit than its surrounding units creates a potential difference, for the target test unit in the first traversal... The system reads data from each preset operation unit and writes the inverse of the preset test data to the preset operation unit at the odd position. For the target test unit in the second traversal, it reads data from each preset operation unit and writes the inverse of the preset test data to the preset operation unit at the even position. This can effectively simulate the potential difference. In the second round of testing, it also reads data from all preset test units of the DRAM under test and compares the read data with the corresponding written data. This allows for another check whether the data in the memory unit after testing meets expectations, improving the reliability and accuracy of the test. By implementing address jump access to the DRAM under test, it covers the previous test blind spots and detects chip defects that are difficult to detect in the existing technology, improving fault coverage and enhancing the reliability of test results, thereby improving product quality.
[0195] In the embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple components or modules may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices, components, or modules may be electrical, mechanical, or other forms.
[0196] The components described as separate parts may or may not be physically separate. The components shown as components may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the components can be selected to achieve the purpose of this embodiment according to actual needs.
[0197] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each component can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.
[0198] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0199] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.
[0200] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0201] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A DRAM testing method, characterized in that, Including the following steps: The DRAM to be tested was subjected to two rounds of testing, and the first comparison result and the second comparison result were obtained respectively. The test includes: Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data; Starting from the first and last addresses of the DRAM under test, the system traverses towards the middle in units of preset test units until all memory cells of the DRAM under test have been traversed. For each target test unit traversed, data read and write operations are performed on the target test unit based on the preset test data, and the read data is compared with the corresponding written data. The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing; The test results of the DRAM to be tested are obtained based on the first comparison result and the second comparison result; Specifically, the process of traversing the DRAM under test from the first and last addresses to the middle, in units of a preset test unit, is executed twice in sequence until all memory units of the DRAM under test have been traversed. The preset test unit includes multiple preset operation units; The step of performing data read / write operations on the target test unit based on the preset test data, and comparing the read data with the corresponding written data, includes: For the first target test unit traversed in the first traversal, read the data of each preset operation unit in the first target test unit, and compare the read data with the corresponding written data. For each preset operation unit, after the comparison is performed, it is determined whether the preset operation unit is in an odd position of the preset test unit. If so, the inverse of the preset test data is written to the preset operation unit. For the second target test unit traversed in the second traversal, read the data of each preset operation unit in the second target test unit, and compare the read data with the corresponding written data. For each preset operation unit, after the comparison is performed, it is determined whether the preset operation unit is in an even position of the preset test unit. If so, the inverse of the preset test data is written to the preset operation unit.
2. The DRAM testing method according to claim 1, characterized in that, The step of writing preset test data to the DRAM under test until all memory cells of the DRAM under test have been written with data includes: The preset test data is written starting from the low-order address of each preset read / write cell of the DRAM under test, in units of a preset burst length, until all memory cells of the DRAM under test have been written with data.
3. The DRAM testing method according to claim 1, characterized in that, The step of traversing the DRAM under test from its first and last addresses inwards until all memory cells of the DRAM under test have been traversed, using preset test units as units, includes: Starting from the first address of the untraversed memory region in the DRAM to be tested, traverse one preset test unit towards the middle, then jump to the last address of the untraversed memory region in the DRAM to be tested, and traverse one preset test unit from the last address towards the middle. Return to the step of traversing one preset test cell from the first address of the untraversed memory region in the DRAM to be tested, until all memory cells of the DRAM to be tested have been traversed.
4. A DRAM testing method according to any one of claims 1 to 2, characterized in that, The second round of testing also includes the following steps: Read the data from all preset test cells of the DRAM to be tested, and compare the read data with the corresponding written data.
5. A DRAM testing method according to claim 2, characterized in that, The preset read / write unit includes rows or columns.
6. A DRAM testing method according to any one of claims 1 to 2, characterized in that, The process of obtaining the test results of the DRAM to be tested based on the first comparison result and the second comparison result includes: If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.
7. A DRAM testing apparatus, characterized in that, include: The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively. The test includes: Preset test data is written to the DRAM to be tested until all memory cells of the DRAM to be tested have been written with data; Starting from the first and last addresses of the DRAM under test, the system traverses towards the middle in units of preset test units until all memory cells of the DRAM under test have been traversed. For each target preset test unit traversed, data read and write operations are performed on the target preset test unit based on the preset test data, and the read data is compared with the corresponding written data. The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing; The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result; Specifically, the process of traversing the DRAM under test from the first and last addresses to the middle, in units of a preset test unit, is executed twice in sequence until all memory units of the DRAM under test have been traversed. The preset test unit includes multiple preset operation units; The step of performing data read / write operations on the target test unit based on the preset test data, and comparing the read data with the corresponding written data, includes: For the first target test unit traversed in the first traversal, read the data of each preset operation unit in the first target test unit, and compare the read data with the corresponding written data. For each preset operation unit, after the comparison is performed, it is determined whether the preset operation unit is in an odd position of the preset test unit. If so, the inverse of the preset test data is written to the preset operation unit. For the second target test unit traversed in the second traversal, read the data of each preset operation unit in the second target test unit, and compare the read data with the corresponding written data. For each preset operation unit, after the comparison is performed, it is determined whether the preset operation unit is in an even position of the preset test unit. If so, the inverse of the preset test data is written to the preset operation unit.
8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the various steps of the DRAM testing method as described in any one of claims 1 to 6.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements each step of the DRAM testing method as described in any one of claims 1 to 6.
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