Command fusion, splitting method and nvme controller

Abstract

The application provides a command fusion and splitting method and an NVMe controller. The data processing method comprises the following steps: acquiring a first command, wherein the first command comprises a read command and a write command; performing splitting or merging processing on data carried by the first command according to the type of the first command, to obtain a first message; and outputting the first message. When facing different types of commands, the method can flexibly perform splitting or merging processing on the commands in advance, reduces the interaction between the NVMe controller and an external unit, and thus improves the data transmission efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to storage technology, and in particular, to command fusion, splitting method and NVMe controller. BACKGROUND

[0002] Figure 1 A block diagram of a solid state storage device is shown. The solid state storage device 102 is coupled to a host for providing storage capability to the host. The host and the solid state storage device 102 can be coupled in various ways, including but not limited to connecting the host and the solid state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fibre Channel, wireless communication network, etc. The host can be an information processing device capable of communicating with the storage device through the above-mentioned ways, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 can be adapted to exchange data with the host through, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is configured to control data transmission between the interface 103, the NVM chip 105, and the DRAM 110, and is also configured to perform storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access data of the DRAM 110. The DRAM can store the FTL table and / or buffered IO command data.

[0006] The control component 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) coupled to the NVM chip 105 and configured to issue commands to the NVM chip 105 in a manner complying with an interface protocol of the NVM chip 105, to operate the NVM chip 105, and to receive results of execution of the commands output from the NVM chip 105. Known NVM chip interface protocols include “Toggle”, “ONFI”, and the like.

[0007] For example, the control component 104 is an NVMe controller, so the interface 103 is adapted to the NVMe protocol. According to the NVMe protocol, the command processed by the control component 104 is a command with a data length of 64 bytes, so the length of the command produced by the host is usually 64 bytes. However, the length of the message that can be processed by the CPU is usually less than 64 bytes (e.g., 16 bytes). Therefore, when the CPU receives a command with a length of 64 bytes, the CPU needs to receive the command multiple times, and a large amount of time is occupied for command transmission. After the CPU receives a complete read command or write command, the CPU can process the command, which also wastes a large amount of waiting time. SUMMARY

[0008] According to a first aspect of the present application, a first data processing method according to the first aspect of the present application is provided to solve the problem that the CPU in the control component needs too much time to receive a command in the prior art. The method includes: obtaining a first command, the first command including a read command and a write command; performing splitting or merging processing on data carried by the first command according to a type of the first command, to obtain a first message; and outputting the first message.

[0009] According to the first data processing method of the first aspect of the present application, the second data processing method of the first aspect of the present application is provided, wherein the data carried by the first command is split or merged according to the type of the first command to obtain a first message, including: saving the first command when the first command is a read command; obtaining a second command, the second command including a read command and a write command; if the second command is a read command, merging the data carried by the first command and the data carried by the second command to obtain the first message; wherein the first message includes data carried by two read commands.

[0010] According to the second data processing method of the first aspect of the present application, the third data processing method of the first aspect of the present application is provided, wherein if the second command is a write command, and a read command is obtained within a preset time period after the second command is obtained, the data carried by the obtained read command and the data carried by the first command are merged to obtain the first message.

[0011] According to the second or third data processing method of the first aspect of the present application, the fourth data processing method of the first aspect of the present application is provided, wherein if the second command is a write command, the data carried by the first command is not split or merged, and the first command is outputted.

[0012] According to one of the first to fourth data processing methods of the first aspect of the present application, the fifth data processing method of the first aspect of the present application is provided, wherein the data carried by the first command is split or merged according to the type of the first command to obtain a first message, further including: when the first command is a write command, splitting the data carried by the first command into N first messages, the N being an integer greater than or equal to 2; and the outputting the first message includes: sequentially outputting the N first messages, each of the N first messages having the same or different message types.

[0013] According to the fifth data processing method of the first aspect of the present application, the sixth data processing method of the first aspect of the present application is provided, wherein the sequentially outputting the N first messages includes: continuously outputting any two adjacent first messages in the N first messages; or outputting any two adjacent first messages in the N first messages with a predetermined time interval; or outputting a second first message after a first first message is outputted for a time T1, and outputting any two adjacent first messages in the second first message to the Nth first message with a time interval T2, T2 being less than T1, and T1 and T2 both being greater than zero.

[0014] According to the fifth or sixth data processing method of the first aspect of the present application, the seventh data processing method of the first aspect of the present application is provided, and before the data carried by the first command is split into N first messages, the method further comprises: judging the data length of the data carried by the first command; if the data length is less than or equal to a first preset threshold, the data carried by the first command is not split; if the data length is greater than the first preset threshold, the data carried by the first command is split.

[0015] According to the seventh data processing method of the first aspect of the present application, the eighth data processing method of the first aspect of the present application is provided, and if the data length is less than a second preset threshold, the data carried by the first command and the data carried by a third command are merged to obtain the first message, wherein the third command is a write command obtained within a preset time period after the first command is obtained, and the data length of the data carried by the third command is less than the second preset threshold.

[0016] According to the seventh or eighth data processing method of the first aspect of the present application, the ninth data processing method of the first aspect of the present application is provided, and the first preset threshold is greater than or equal to twice the second preset threshold.

[0017] According to one of the fifth to ninth data processing methods of the first aspect of the present application, the tenth data processing method of the first aspect of the present application is provided, and the first message carries an identifier, and the identifier is used to represent the message type of the first message, wherein the message types of the first first message and the Nth first message in the N first messages are different.

[0018] According to one of the fifth to tenth data processing methods of the first aspect of the present application, the eleventh data processing method of the first aspect of the present application is provided, and the data length of each first message in the N first messages is equal.

[0019] According to the second aspect of the present application, the first NVMe controller of the second aspect of the present application is provided, comprising a processor, a DMA unit and a cache area, wherein the DMA unit obtains a first command and stores the first command in the cache area, the first command comprising a read command and a write command; the processor splits or merges the data carried by the first command according to the type of the first command to obtain a first message, and outputs the first message.

[0020] According to the first NVMe controller of the second aspect of the present application, the second NVMe controller of the second aspect of the present application is provided, when the first command is a read command, the processor saves the first command to the cache area; the DMA unit obtains a second command from the host, the second command including a read command and a write command; if the second command is a read command, the processor merges the data carried by the first command and the data carried by the second command to obtain the first message; the processor outputs the first message, the first message including the data carried by the two read commands.

[0021] According to the second NVMe controller of the second aspect of the present application, the third NVMe controller of the second aspect of the present application is provided, if the second command is a write command, the DMA unit obtains a read command within a preset time period after obtaining the second command, the processor merges the data carried by the obtained read command and the data carried by the first command to obtain the first message.

[0022] According to the second or third NVMe controller of the second aspect of the present application, the fourth NVMe controller of the second aspect of the present application is provided, if the second command is a write command, the processor does not split or merge the data carried by the first command, and outputs the first command.

[0023] According to one of the first to fourth NVMe controllers of the second aspect of the present application, the fifth NVMe controller of the second aspect of the present application is provided, the processor splits or merges the data carried by the first command according to the type of the first command to obtain a first message, and further comprising: when the first command is a write command, the processor splits the data carried by the first command into N first messages, the N being an integer greater than or equal to 2; the processor sequentially outputs the N first messages, each of the N first messages having the same or different message types.

[0024] According to the fifth NVMe controller of the second aspect of the present application, the sixth NVMe controller of the second aspect of the present application is provided, the sequentially outputting the N first messages comprises: the DMA unit continuously outputs any two adjacent first messages in the N first messages; or, the DMA unit outputs any two adjacent first messages in the N first messages with a predetermined time interval; or, the DMA unit outputs a second first message after T1 time after outputting a first first message in the N first messages, and the time interval between the output of any two adjacent first messages in the second first message to the Nth first message is T2, T2 is less than T1, and T1 and T2 are both greater than zero.

[0025] According to the fifth or sixth NVMe controller of the second aspect of the application, the seventh NVMe controller of the second aspect of the application is provided, and before the processor splits the data carried by the first command into the N first messages, the processor judges the data length of the data carried by the first command; if the data length is less than or equal to a first preset threshold, the processor does not split the data carried by the first command; if the data length is greater than the first preset threshold, the processor splits the data carried by the first command.

[0026] According to the seventh NVMe controller of the second aspect of the application, the eighth NVMe controller of the second aspect of the application is provided, and if the data length is less than a second preset threshold, the processor merges the data carried by the first command and the data carried by a third command to obtain the first message, wherein the third command is a write command obtained by the DMA unit within a preset time period after the first command is obtained, and the data length of the data carried by the third command is less than the second preset threshold.

[0027] According to the seventh or eighth NVMe controller of the second aspect of the application, the ninth NVMe controller of the second aspect of the application is provided, and the first preset threshold is greater than or equal to twice the second preset threshold.

[0028] According to one of the fifth to ninth NVMe controllers of the second aspect of the application, the tenth NVMe controller of the second aspect of the application is provided, and the first message carries an identifier, and the identifier is used to represent the message type of the first message, wherein the message types of the first first message and the Nth first message in the N first messages are different.

[0029] According to one of the fifth to tenth NVMe controllers of the second aspect of the application, the eleventh NVMe controller of the second aspect of the application is provided, and the data length of each first message in the N first messages is equal. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0031] Figure 1 A block diagram of the storage device in the prior art;

[0032] Figure 2AA schematic diagram of a data format of a write command in the prior art;

[0033] Figure 2B A schematic diagram of a data format of a read command in the prior art;

[0034] Figure 3 A flowchart of a data processing method provided by an embodiment of the application;

[0035] Figures 4A-4D A schematic diagram of a data format of a first message provided by an embodiment of the application;

[0036] Figure 5 A structural schematic diagram of an NVMe controller provided by an embodiment of the application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the application will be clearly and completely described in connection with the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0038] The terms “first”, “second”, and “third” and the like in the specification of the application, claims, and drawings are used to distinguish different objects, rather than to define a particular order. In addition, the terms “include” and “have” and their various variations are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or units, but can optionally include steps or modules that are not listed, or can optionally include other steps or modules inherent to the process, method, product, or device.

[0039] “Embodiment” mentioned in the application means that a specific feature, structure, or property described in connection with the embodiment can be included in at least one embodiment of the application. The phrase appears at various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment to other embodiments. A person of ordinary skill in the art explicitly or implicitly understands that the embodiments described in the application can be combined with other embodiments.

[0040] “Multiple” in the application means two or more. “And / or” describes the association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which means that A exists alone, A and B exist simultaneously, or B exists alone. The character “ / ” generally represents that the associated objects before and after it are in an “or” relationship.

[0041] For the convenience of understanding, the format of the command and the method of processing the command in the prior art are introduced first.

[0042] Figure 2A A data format of the NVMe write command in the prior art is given, Figure 2B A data format of the NVMe read command in the prior art is given.

[0043] As shown in Figure 2A and 2B , the write command 210 and the read command 220 both adopt a fixed data format, and the data length of the read command 220 and the write command 210 is a fixed value, for example, 64 bytes. The write command 210 includes a reserved bit 211, a command type 212, a namespace 213, a metadata pointer 214, a data pointer 215, a starting logical address 216 and a logical block number 217. Among them, there is no valid data in the reserved bit 211. The command type 212 is used to indicate the type of the command, including read (Read), write (Write), compare (Compare), flush (Flush) and the like. For example, the value of the command type 212 in the write command 210 is 01000000. The namespace 213 is used to indicate the namespace to be written. The starting logical address 216 is the starting logical block of the SSD to be written, and the logical block number 217 indicates how many logical blocks to be written. The metadata pointer 214 and the data pointer 215 are used to indicate the location of the data to be written in the host.

[0044] The read command 220 includes a reserved bit 221, a command type 222, a namespace 223, a metadata pointer 224, a data pointer 225, a starting logical address 226 and a logical block number 227. Among them, the reserved bit 221, the command type 222 in the read command 220 are similar to the write command 210, and will not be described here. The namespace 223 is used to indicate the namespace to be read, and the starting logical address 226 and the logical block number 227 are used to indicate a plurality of logical blocks to be read. The metadata pointer 224 and the data pointer 225 indicate the location of the data in the host after the data is read out. As can be seen, in order to comply with the NVMe protocol, the read command and the write command in the prior art both set a plurality of reserved bits, and the amount of data occupied by the real valid information in the command is not large.

[0045] The data bus width inside the control component of the storage device is limited (for example, 128 bits), and cannot carry a complete read command or write command in one bus transmission. Transmitting a read command or write command of, for example, 64 bytes requires multiple bus transmissions, which increases the command processing delay of the control component. Embodiments of the present application provide a data processing method for splitting or merging the data carried by the command, to improve the command transmission efficiency inside the control component without affecting the processing of the command, and transmit more commands in fewer bus transmission cycles.

[0046] Referring to Figure 3 , Figure 3 A block diagram according to an embodiment of the present application is provided.

[0047] Taking a write command issued by the host 300 as an example, the NVMe controller 310 of the storage device obtains the write command from the host 300 and sends the write command to the CPU 320. The CPU 320 parses and processes the write command. For example, the CPU 320 receives the write command in Figure 2A , parses the write command, and learns that the logical block quantity is 7, so that 8 cache spaces with a capacity of 4K are allocated for the data to be written. The cache spaces temporarily store the data to be written before the data is written to the NVM chip 330. The CPU 320 also learns the host address of the data to be written in the host through the metadata pointer and the data pointer, so that the CPU 320 controls the NVMe controller 310 to access the host address and carry the data to be written to the cache space. After the data to be written is carried to the cache space, the CPU 320 instructs the media interface controller to write the data to the NVM chip 330. The method of processing the read command is similar to the method of processing the write command, which will not be described here.

[0048] Embodiments of the present application will be described below with reference to the accompanying drawings.

[0049] Figure 5 A structural diagram of an NVMe controller is given. Referring to Figure 5 , the NVMe controller 500 includes a processor 501, a DMA unit 502, and a cache area 503. The processor 501 is coupled to the DMA unit 502 and the cache area 503, respectively. The NVMe controller 500 is also coupled to the host 60 to exchange commands according to the NVMe protocol with the host.

[0050] The NVMe controller 500 is also coupled to the processor 550. The NVMe controller 500 parses the NVMe command and provides a first message parsed according to the NVMe command to the processor 550, so that the processor 550 further processes according to the first message to perform the operation indicated by the NVMe command.

[0051] The processor 550 is also coupled to the media interface controller and instructs the media interface controller to access the NVM chip in the storage device.

[0052] Optionally, the processor 550 is integrated in the media interface controller.

[0053] The following describes an example in which the NVMe controller 500 performs a data processing method, but this does not mean that the data processing method in this embodiment can only be performed by the NVMe controller 500. The data processing method can also be performed by other electronic devices having similar structures and / or functions to the NVMe controller 500, which is not limited herein.

[0054] Figure 4A As shown in the flowchart of the data processing method of this embodiment, Figure 4A the data processing method in this embodiment includes the following steps:

[0055] Step S401: Obtain a first command from a host, the first command including a read command and a write command.

[0056] Step S402: According to the type of the first command, split or merge the data carried by the first command to obtain a first message.

[0057] Step S403: Output the first message.

[0058] First, step S401 is performed.

[0059] For example, in response to the host 60 providing one or more commands to the storage device, the processor 501 controls the DMA unit 502 to obtain a first command from the host 60, the first command being a read command or a write command. The DMA unit 502 stores the obtained first command in the cache area 503.

[0060] Step S402 is then performed.

[0061] After the processor 501 analyzes the first command, it knows the type of the first command and, according to the type, splits or merges the data carried by the first command to obtain a first message formed after the data is merged or split.

[0062] Table 1

[0063] Command Type Write Read Processing Mode Split Merge

[0064] Table 1 shows the relationship between the type of the first command and the processing method of the processor 501 for the data carried by the first command. When the first command is a write command, the data carried by the write command is split. When the first command is a read command, the data carried by the read command is merged.

[0065] In one embodiment, the processor 501 determines that the first command is a read command, and the processor 501 continues to control the DMA unit to obtain a second command from the host 60, which is a read command or a write command. According to the type of the second command, the processor 501 includes the following processing manners:

[0066] Manner 1, when the second command is a read command, the processor 501 merges the data carried by the second command and the data carried by the first command into a first message, i.e., the first message includes the data carried by the two read commands.

[0067] Manner 2, when the second command is a write command, the processor 501 does not perform merging processing on the data carried by the first command, and sends the first command to the processor 550.

[0068] Manner 3, when the second command is a write command, the processor 501 performs timing, and if a read command is obtained again within a preset time length, the processor 501 merges the data carried by the obtained read command and the data carried by the first command into a first message.

[0069] For the above-mentioned manner 1, for example, two commands obtained from the host 60 in succession are read commands 220, the processor 501 parses the two read commands 220 and extracts the required data therefrom, including the reserved bit 221, the starting logical address 226, the logical block quantity 227 and the namespace 223, and generates an identifier corresponding to the two read commands, a command identifier and an end identifier, and generates a first message.

[0070] Referring to Figure 4B , FIG. 4 shows a schematic diagram of the first message, wherein the first command and the second command are read commands in Figure 2B , and the merged first message 410 is obtained. The first message 410 includes the reserved bit 221, the starting logical address 226 (including 226-1 and 226-2), the logical block quantity 227, the namespace 223, the identifier 411, the command identifier 412 and the end identifier 413. Among them, the reserved bit 221, the starting logical address 226, the logical block quantity 227 and the namespace 223 in the first message 410 have the same functions as in the above-mentioned read command 220, and the description thereof can be referred to in the above, and will not be described here. For the starting logical address in Figure 4B , the starting logical address includes 226-1 and 226-2 because, for example, Figure 4B , one line represents 32 bits, and the length of the starting logical address 226 exceeds 32 bits, so the starting logical address 226 is placed in two parts, and for the starting logical address 226 with a length less than 32 bits, it can be placed in one line. And Figure 4B , the proportion of each data in the figure does not represent the actual data length proportion, and the length of the starting logical address 226 is adjusted according to actual needs, which is not limited here.

[0071] Optionally, the length of the first message is consistent with the bus width inside the control component, so that the transmission of one first message from the processor 501 to other processors can be completed within one bus cycle.

[0072] The identifier 411 represents the message type of the first message, which is divided into at least four types according to different read / write commands and splitting / merging. For example, the identifier 411 takes values of 0, 1, 2 and 3, when taking the value of 0, it represents that two write commands are merged; when taking the value of 1, it represents that one write command is split and the current message is the first one of N first messages; when taking the value of 2, it represents that one write command is split and the current message is one of the second to Nth one of N first messages; when taking the value of 3, it represents that two read commands are merged.

[0073] The command identifier 412 is used to distinguish different commands and correctly associate the command response with the command when returning the command response. For example, the two command identifiers 412 in the first message 410 take different values, which represents that they are two different commands. The end identifier 413 represents that there is no other read command after the end identifier 413 in the current first message.

[0074] For the above-mentioned mode 3, for example, the DMA unit 502 obtains the No. 1 read command first, and then obtains the No. 1 write command next time, then the processor 501 starts timing or countdown for a preset time length, such as 10us. During the timing process, if the DMA unit 502 obtains the No. 2 read command, the data carried by the No. 1 read command and the No. 2 read command are merged to obtain a first message, and the specific merging method and the first message can be referred to the description in the above-mentioned mode 1, which will not be described here. If the DMA unit 502 does not obtain the No. 2 read command until the timing ends, the processor 501 stops waiting and sends the No. 1 read command to the processor 550 to prevent too long waiting time from occupying too many resources.

[0075] For the above-mentioned mode 2, continue to use the previous example, if the DMA unit 502 obtains a write command next time after obtaining the No. 1 read command, the processor 501 does not split or merge the data carried by the No. 1 read command, and outputs the No. 1 read command.

[0076] Optionally, before the intervention of the processor 501, the DMA unit 502 moves multiple commands to the cache area 503. Thus, the processor 501 implements splitting or merging on multiple commands without waiting for further commands through the timing process.

[0077] Continuing to refer to Table 1, in some embodiments, the processor 501 determines that the first command is a write command, and the processor 501 adopts the following processing mode for the data carried by the write command:

[0078] In the manner a, the processor 501 splits the data carried by the write command into N first messages, N being an integer greater than or equal to 2. The processor 501 outputs the N first messages in sequence, wherein each of the N first messages has the same or different message type.

[0079] In the manner b, the processor 501 judges the data length of the data carried by the write command; if the data length is less than or equal to a first preset threshold, the data carried by the write command is not split; if the data length is greater than the first preset threshold, the data carried by the write command is split.

[0080] In the manner c, after judging that the data length is less than the first preset threshold, the processor 501 continues to judge whether the data length is less than a second threshold; if the data length is less than the second preset threshold, the data carried by the write command and the data carried by a third command are merged to obtain a first message, wherein the third command is a write command obtained within a preset time period after the write command, and the data length of the data carried by the third command is less than the second preset threshold.

[0081] Figure 4C A schematic diagram of splitting the write command into three first messages is given. Taking N = 3 as an example, Figure 4C A schematic diagram of the first message 420, the first message 430 and the first message 440 is given in FIG. 4B. The first message 420 includes the reserved bit 211, the namespace 213, the start logical address 216 (including 216-1 and 216-2), the identifier 421, the message identifier 422, the count value 423 and the cache index 424 (including 424-1, 424-2, 424-3 and 424-4). The first message 430 and the first message 440 each include the identifier 431, the message identifier 422 and the reserved bit 211. The first message 430 further includes the cache index 434 (including 434-1, 434-2, …, 434-7), and the first message 440 further includes the cache index 444 (including 444-1, 444-2, …, 444-7). The reserved bit 211, the namespace 213 and the start logical address 216 are directly parsed from the write command, which are the same as the logical address 216 described above in combination with FIG. 4A, and will not be described again here. The identifier 421 and the identifier 431 have the same meaning as the identifier 411 described above, and will not be described again here, the difference is that the values of the identifier 421, the identifier 411 and the identifier 431 are different. For example, the value of the identifier 421 is 1, and the value of the identifier 431 is 2. Figure 2A

[0082] ​Since the data carried by the write command can be more, multiple first messages can be split out. In order to ensure that the device receiving the first message can distinguish the first message corresponding to different write commands, the embodiment adopts message identifier 422 to represent the write command to which the first message belongs, that is, the first messages corresponding to different write commands have different values of the message identifier 422.

[0083] The cache index 424, the cache index 434 and the cache index 444 in the embodiment are used to indicate the cache space allocated for the write command by the NVMe controller 500 after the write command is acquired. The cache space includes multiple cache blocks, the number of the allocated cache blocks is related to the starting logical address 216 and the logical block number 217, that is, related to the length of the data to be written into the NVM chip 330. The length of the cache block is a preset fixed value, such as 4K. If the data to be written is 22K, 6 cache blocks will be allocated. The cache index 424 in the embodiment indicates that it includes 5 cache blocks. The count value 423 indicates the number of cache indexes. Unlike the first message 410, the first messages 420-440 do not include an end identifier, so the count value 423 is used to determine whether the first messages split out by the write command have all been acquired. It should be noted that the data carried by the first command in the embodiment is not limited to the data contained in the first command itself, but also includes the cache index. The data to be written refers to the data stored in the host and waiting to be written into the NVM chip.

[0084] For the above-mentioned mode a, for example, the processor 501 requests to allocate 20 cache blocks after parsing the write command. Since the first first message can only carry the index of 5 cache blocks, each first message starting from the second first message can carry the index of 7 cache blocks, so it is determined that 4 first messages need to be split out. Alternatively, when the number of allocated cache blocks is less than 5, the processor 501 generates a first message according to the write command. For example, when the number of cache blocks is less than the maximum number of cache indexes that can be carried by the first message 420, the processor 501 only generates one first message.

[0085] For the above-mentioned manner b and manner c, the processor 501 judges the data length of the data carried by the write command after parsing the write command, and then determines what kind of processing is needed for the data carried by the write command. Alternatively, in the embodiment, the first preset threshold is greater than or equal to twice the second preset threshold. For example, the bus bit width of the control component limits the maximum transmission of 16 bytes of data in one bus transmission, so as to improve the message transmission efficiency between components, and the size of each message exchanged between the processor 501 and the processor 505 is 16 bytes. Accordingly, the first preset threshold is set to 16 bytes, and the second preset threshold is set to 8 bytes. For example, the data length of the data carried by the write command is 12 bytes, and the processor 501 does not split the data carried by the write command. For another example, the data length is 20 bytes, and the processor 501 splits the data carried by the write command. The specific splitting method can be referred to the above-mentioned manner a, and will not be described here. For another example, the data length is 4 bytes, and the processor 501 judges that the 4 bytes of the data length is less than the 16 bytes of the first threshold, and further judges that the 4 bytes of the data length is less than the 8 bytes of the second threshold. The processor 501 merges the data carried by the write command and the data carried by the third command to construct a first message. That is, when the data lengths of the data carried by two write commands are both less than the second preset threshold, the processor 501 merges the data carried by the two write commands to obtain a first message. The specific merging method can be referred to the above-mentioned manner 1 to manner 3, and will not be described here. The above-mentioned manner b and manner c can also be used for read commands, which will not be expanded here.

[0086] Figure 4D A schematic diagram of the first message obtained by merging the data carried by the write command in the embodiment is shown in FIG. 4. Figure 4D In FIG. 4, the first message 450 includes the reserved bit 211, the namespace 213 (including 213-1 and 213-2), the real logical address 216 (including 216-10, 216-11, 216-20 and 216-21), the logical block number 217 (including 217-1 and 217-2), the identifier 451, the command number 452 (including 452-1 and 452-2) and the cache index 454 (including 454-1 and 454-2). The command number 452 indicates how many pieces of data of the write command (in the embodiment, one piece of data of the write command) are carried by the first message 450. The identifier 451 indicates the message type of the first message. The reserved bit 211, the namespace 213 (including 213-1 and 213-2), the real logical address 216 (including 216-10, 216-11, 216-20 and 216-21) and the logical block number 217 (including 217-1 and 217-2) are all information obtained from the write command, wherein the suffixes "-1", "-2", "-11", "-10", "-20" and "-21" of the reference numerals are used to distinguish different write commands.

[0087] In some embodiments, the first message carries an identifier, which is used to represent the message type of the first message, wherein the first message and the Nth message of the N first messages are of different message types.

[0088] Optionally, the length of the first message in the present application is a fixed value, for example, 4 double words. Specifically, whether the first message is obtained by merging the data carried by two read commands or any one of the N first messages split from the write command, the length of the first message is the same, which conforms to the bus bit width inside the control component. For example, the bus bit width is 128 bits (one bus transmission can carry 128 bits of data), and the length of the first message is 128 bits. The length of the first message can be set according to the bus bit width, which is not limited herein.

[0089] After step S402 is performed, step S403 is performed.

[0090] The processor 501 outputs the first message. For example, in the present embodiment, the first message is sent to the processor 550.

[0091] Optionally, when the N first messages are split, the DMA unit 502 outputs the N first messages in sequence.

[0092] For example, N=5, the DMA unit 502 outputs any two adjacent first messages of the five first messages continuously, wherein there is no time interval between any two adjacent first messages. For another example, the DMA unit 502 outputs any two adjacent first messages of the five first messages with a predetermined time interval, that is, there is a fixed time interval between any two adjacent first messages. For another example, the DMA unit 502 outputs the second first message after T1 time after outputting the first first message of the five first messages, and the time interval between the output of any two adjacent first messages of the second first message to the fifth first message is T2, T2 is less than T1, and T1 and T2 are both greater than zero. That is, the first first message is sent, and then the second first message is sent after a longer T1 time, and the second first message is sent, and then the third first message is sent with a shorter T2 time interval. Thus, more actual time is left for the device receiving the first message to analyze the first first message, and for the second to Nth first messages carrying relatively less information, only a shorter T2 needs to be reserved.

[0093] Continuing to refer to Figure 5The NVMe controller 500 in the embodiment includes a processor 501, a DMA unit 502, and a cache area 503. In the embodiment, the NVMe controller 500 can perform the data processing method in the above-described embodiment. For details of the execution manner, refer to the description in the method embodiment, which will not be repeated here.

[0094] The DMA unit 502 obtains the first command from the host 60 and stores the first command in the cache area 503. The first command includes a read command and a write command. The host is coupled with the NVMe controller. The processor splits or merges the data carried by the first command according to the type of the first command to obtain a first message and outputs the first message.

[0095] In one embodiment, when the first command is a read command, the processor 501 stores the first command in the cache area, for example. The processor 501 controls the DMA unit 502 to obtain a second command from the host 60. The second command includes a read command and a write command. If the second command is a read command, the processor 501 merges the data carried by the first command and the data carried by the second command to obtain a first message. The processor 501 outputs the first message. The first message includes the data carried by the two read commands.

[0096] In some embodiments, if the second command is a write command, the DMA unit 502 obtains a read command within a preset time period after obtaining the second command. The processor 501 merges the data carried by the obtained read command and the data carried by the first command to obtain a first message.

[0097] In yet some embodiments, if the second command is a write command, the processor 501 does not split or merge the data carried by the first command and outputs the first command.

[0098] In some embodiments, the processor 501 splits or merges the data carried by the first command according to the type of the first command to obtain a first message. When the first command is a write command, the processor 501 splits the data carried by the first command into N first messages, where N is greater than or equal to 2. The processor 501 outputs the N first messages in sequence. Each of the N first messages has the same or different message type.

[0099] In one embodiment, the DMA unit 502 sends the N first messages in sequence, including: the DMA unit 502 outputs any two adjacent first messages in the N first messages continuously; or, the DMA unit 502 outputs any two adjacent first messages in the N first messages with a predetermined time interval; or, the DMA unit 502 outputs a first first message, and then outputs a second first message after T1 time, and the time interval between the output of any two adjacent first messages in the second first message to the Nth first message is T2, T2 is less than T1, and T1 and T2 are both greater than zero.

[0100] Optionally, before the processor 501 splits the data carried by the first command into the N first messages, the processor 501 judges the data length of the data carried by the first command; if the data length is less than or equal to a first preset threshold, the processor 501 does not split the data carried by the first command; if the data length is greater than the first preset threshold, the processor 501 splits the data carried by the first command.

[0101] Optionally, if the data length is less than a second preset threshold, the processor 501 merges the data carried by the first command and the data carried by a third command to obtain a first message, wherein the third command is a write command obtained by the DMA unit 502 within a preset time after the first command is obtained, and the data length of the data carried by the third command is less than the second preset threshold.

[0102] In some embodiments, the first preset threshold is greater than or equal to twice the second preset threshold.

[0103] In some embodiments, the first message carries an identifier, and the identifier is used to represent the message type of the first message, wherein the message type of the first first message and the Nth first message in the N first messages are different.

[0104] In all embodiments, the data length of each first message in the N first messages is equal.

[0105] Although the examples described with reference to the present application are only for the purpose of explanation and not for the limitation of the present application, changes, additions and / or deletions to the embodiments can be made without departing from the scope of the present application.

[0106] The above description is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A data processing method, characterized in that, include: Obtain the first command, which includes a read command and a write command; Depending on the type of the first command, the data carried by the first command is split or merged to obtain the first message; Output the first message; Specifically, based on the type of the first command, the data carried by the first command is split or merged to obtain the first message, including: When the first command is a read command, the first command is saved; Obtain the second command, which includes a read command and a write command; If the second command is a read command, then the data carried by the first command and the data carried by the second command are merged to obtain the first message; The first message includes data carried by two read commands.

2. The method as described in claim 1, characterized in that, If the second command is a write command, and a read command is obtained within a preset time after the second command is obtained, the data carried by the obtained read command is merged with the data carried by the first command to obtain the first message.

3. The method as described in claim 1, characterized in that, The step of splitting or merging the data carried by the first command according to the type of the first command to obtain the first message further includes: When the first command is a write command, the data carried by the first command is split into N first messages, where N is an integer greater than or equal to 2; The first output message includes: The N first messages are output sequentially, and each of the N first messages has the same or different message types.

4. The method as described in claim 3, characterized in that, Before the data carried by the first command is split into N first messages, the method further includes: Determine the data length of the data carried by the first command; If the data length is less than or equal to the first preset threshold, the data carried by the first command will not be split. If the data length is greater than the first preset threshold, then the data carried by the first command is split.

5. The method as described in claim 4, characterized in that, If the data length is less than the second preset threshold, the data carried by the first command and the data carried by the third command are merged to obtain the first message. The third command is a write command obtained within a preset time after obtaining the first command, and the data length carried by the third command is less than the second preset threshold.

6. The method according to any one of claims 3-5, characterized in that, The first message carries an identifier, which is used to characterize the message type of the first message, wherein the message types of the first first message and the Nth first message are different.

7. An NVMe controller, characterized in that, This includes the processor, DMA unit, and cache. The DMA unit acquires a first command and stores the first command in the cache area, wherein the first command includes a read command and a write command; The processor splits or merges the data carried by the first command according to the type of the first command to obtain the first message and outputs the first message; When the first command is a read command, the processor saves the first command to the cache area; The DMA unit acquires a second command, which includes a read command and a write command. If the second command is a read command, the processor merges the data carried by the first command and the data carried by the second command to obtain the first message; The processor outputs the first message, which includes data carried by two read commands.

8. The NVMe controller as described in claim 7, characterized in that, The processor, based on the type of the first command, splits or merges the data carried by the first command to obtain the first message, and further includes: When the first command is a write command, the processor splits the data carried by the first command into N first messages, where N is an integer greater than or equal to 2; The processor sequentially outputs the N first messages, each of the N first messages having the same or different message types.

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