Stereo memory device

Abstract

The present invention discloses a three-dimensional memory element, comprising a plurality of conductive layers and a plurality of insulating layers, which are stacked alternately to form a multi-layer stacked structure. The multi-layer stacked structure has a step region and a non-step region, the step region comprises a plurality of steps, each step comprises a pair of adjacent conductive layers and insulating layers. A plurality of memory structures are located in the non-step region, each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure comprises a trunk and a plurality of side branches, the side branches extend outward from the trunk in the step region, wherein the trunk passes through the memory structures in the non-step region.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a three-dimensional memory device with high storage density. Background Art

[0002] Memory components are important data storage components in portable electronic devices, such as MP3 players, digital cameras, laptops, smart phones, etc. With the increase in various applications and the improvement of functions, the demand for memory components is also trending towards smaller size and larger storage capacity. In order to meet this demand, designers are currently developing a three-dimensional memory component that includes multiple memory cell hierarchical stacks, such as a vertical channel three-dimensional NAND flash memory component.

[0003] However, as the critical dimensions of components are miniaturized to the limit of the general memory cell technology field, how to obtain higher storage capacity in a smaller component size while taking into account the operational stability of the component has become an important issue facing this technology field. Therefore, there is a need to provide an advanced three-dimensional memory component and a manufacturing method thereof to solve the problems faced by the prior art. Summary of the invention

[0004] An embodiment of the present specification discloses a three-dimensional memory element, which includes a plurality of conductive layers and a plurality of insulating layers, which are stacked alternately to form a multi-layer stacked structure. The multi-layer stacked structure has a stepped region and a non-stepped region, the stepped region includes a plurality of steps, each step includes a pair of adjacent conductive layers and insulating layers. A plurality of memory structures are located in the non-stepped region, each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a trunk and a plurality of side branches, the side branches extend outward from the trunk in the stepped region, wherein the trunk passes through the memory structures in the non-stepped region.

[0005] In other embodiments of the present specification, the fishbone dielectric structure is a dielectric structure that does not contain a conductive material.

[0006] In other embodiments of the present specification, each side branch extends along a side wall of a step in the step region.

[0007] In other embodiments of the present specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the step region, wherein a pair of adjacent metal pillars are separated by one of the side branches.

[0008] In other embodiments of the present specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the step region, wherein a pair of adjacent metal pillars are separated by a trunk.

[0009] In other embodiments of the present specification, each side branch extends vertically outward from the main trunk.

[0010] In other embodiments of the present specification, a pair of adjacent side branches extend outward from two opposite sides of the main trunk.

[0011] Another embodiment of the present specification discloses a three-dimensional memory element, which includes a plurality of conductive layers and a plurality of insulating layers, which are stacked alternately to form a multi-layer stacked structure, wherein the multi-layer stacked structure has a stepped region and a non-stepped region, the stepped region includes a plurality of steps, each step includes a pair of adjacent conductive layers and insulating layers. A plurality of memory structures are located in the non-stepped region, each memory structure passes through the conductive layers and the insulating layers. At least one dielectric pillar is located in each of the stepped regions, wherein at least one dielectric pillar is a dielectric structure that does not contain a conductive material.

[0012] In other embodiments of the present specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the step region, and at least one dielectric pillar is located between a pair of adjacent ones of the metal pillars.

[0013] In other embodiments of the present specification, the three-dimensional memory device further includes a plurality of metal pillars connected to the steps in the step region, and each metal pillar is located in a central region of each step.

[0014] In summary, the three-dimensional semiconductor memory includes forming a dielectric pillar or a fishbone dielectric structure in the step region. The dielectric pillar or the fishbone dielectric structure is used as a support structure to support the remaining insulating layer so that the insulating layer does not collapse due to the gap therebetween. The dielectric pillar or the fishbone dielectric structure is also located between the metal pillars or metal contacts in the step region to avoid bridging in the case of overlapping offset in the metal pillars or metal contacts.

[0015] The above description will be described in detail below with reference to implementation examples, and a further explanation will be provided for the technical solution of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the accompanying drawings are described as follows:

[0017] Figure 1 to Figure 6 is a three-dimensional diagram illustrating a method for manufacturing a semiconductor memory device in multiple steps according to an embodiment of the present invention; and

[0018] Figure 7 to Figure 15 FIG. 4 is a three-dimensional diagram illustrating a method for manufacturing a semiconductor memory device in multiple steps according to another embodiment of the present invention.

[0019]

Explanation of symbols

[0020] In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the attached symbols are explained as follows:

[0021] 107: Insulation layer

[0022] 108: Conductive layer

[0023] 109: Insulation layer

[0024] 110: Non-step area

[0025] 110a: Memory structure

[0026] 112: Staircase area

[0027] 112a-112d: Stage

[0028] 114: Channel

[0029] 116: Fishbone dielectric structure

[0030] 116a: Trunk

[0031] 116b: Side branch

[0032] 118: Channel

[0033] 119: Dielectric wall

[0034] 122: Metal pillar

[0035] D1: Direction

[0036] D2: Direction

[0037] H: Height

[0038] 201: Substrate

[0039] 207: Insulation layer

[0040] 208: Conductive layer

[0041] 209: Insulation layer

[0042] 210: Non-step area

[0043] 210a: Memory Structure

[0044] 211: Vertical hole

[0045] 212: Staircase area

[0046] 212a-212d: Stage

[0047] 213: Vertical hole

[0048] 214: Passivation layer

[0049] 215: Mask layer

[0050] 217: Dielectric Pillar

[0051] 218: Channel

[0052] 219: Dielectric Wall

[0053] 220: Common source line

[0054] 222: Metal Column DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0056] This specification provides a method for manufacturing a three-dimensional memory element, which can obtain a higher storage capacity in a smaller element size while taking into account the operational stability of the element. In order to make the above-mentioned embodiments and other purposes, features and advantages of this specification more clearly understandable, a memory element and its manufacturing method are specifically cited as a preferred embodiment, and are described in detail with the accompanying drawings.

[0057] However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention may still be implemented using other features, components, methods and parameters. The preferred embodiments are only intended to illustrate the technical features of the present invention and are not intended to limit the claims of the present invention. Those skilled in the art will be able to make equal modifications and changes based on the description of the following specification without departing from the spirit of the present invention. In different embodiments and drawings, the same components will be represented by the same component symbols.

[0058] Please refer to Figure 1 to Figure 6 , which is a three-dimensional diagram of a semiconductor memory device manufacturing method in multiple steps according to an embodiment of the present invention. The semiconductor memory device is formed into a multi-layer stacked structure by alternately depositing two different insulating layers (107, 109).

[0059] In this embodiment, the two different insulating layers (107, 109) may be a silicon nitride layer and a silicon oxide layer, respectively. In other embodiments of the present invention, the two different insulating layers may be two dielectric materials, such as two dielectric materials of silicon oxide, silicon nitride, silicon oxynitride, silicate, etc. In some embodiments of the present specification, the two different insulating layers (107, 109) are selected from two dielectric materials, and the two dielectric materials have a relatively strong etching resistance and a relatively weak etching resistance to a predetermined etchant.

[0060] refer to Figure 2The multi-layer stacked structure is subjected to an etching step to form a stepped region 112 and a non-stepped region 110. The stepped region 112 includes a plurality of steps (112a-112d). Each step (112a-112d) includes a pair of adjacent two different insulating layers (107, 109).

[0061] A plurality of memory structures 110a are formed in the non-step region 110, and each memory structure 110a passes through a plurality of different insulating layers (107, 109) in the non-step region 110. From a top view, each memory structure 110a has an O-shaped, elliptical, egg-shaped or rounded rectangular circumference, but is not limited thereto.

[0062] Each memory structure 110a includes a storage layer and a channel layer. In some embodiments of the present specification, the storage layer may be a composite layer of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer (i.e., an ONO structure), but the structure of the storage layer is not limited thereto. In other embodiments of the present specification, the composite layer of the storage layer may also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride-oxide, i.e., ONONO) structure, a silicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (silicon-oxide-nitride-oxide-silicon, i.e., SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, a tantalum nitride, aluminum oxide, silicon nitride, silicon oxide-silicon oxide-silicon oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide-silicon oxide-silicon oxide-silicon) structure, a silicon-oxide-nitride-oxide-silicon (silicon-oxide-nitride-oxide-silicon, i.e., SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide-silicon oxide-silicon) structure, a silicon-oxide-nitride-oxide-silicon (SONOS ... The present invention relates to a group of semiconductor devices that are composed of a metal-oxide, silicon, TANOS structure and a metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structure. In this embodiment, the storage layer may be an ONO composite layer, and the channel layer may be a polysilicon layer.

[0063] The etching process is performed to form a channel 114 along a direction D1 crossing the step region 112 and the non-step region 110. The memory structure 110a crossed or divided by the channel 114 forms a semi-cylindrical three-dimensional semiconductor memory element, thereby increasing the storage density of the memory structure.

[0064] Reference Figure 3 , a dielectric material, such as an oxide material, is formed in the trench 114 to form a fishbone dielectric structure 116. Each fishbone dielectric structure 116 includes a trunk 116a and a plurality of side branches 116b. In the step region 112, the side branches 116b extend from the trunk to the outside 116a. The trunk 116a also passes through the memory structure 110a in the non-step region 110. The memory structure 110a passed through by the trunk 116a forms a semi-cylindrical three-dimensional semiconductor memory element, thereby increasing the storage density of the memory structure.

[0065] In some embodiments, the fishbone dielectric structure 116 is a dielectric structure that does not contain a conductive material, but is not limited thereto. In some embodiments, each side branch 116b extends along the sidewall of the corresponding step (112a-112d) of the step region 112, but is not limited thereto. In some embodiments, each side branch 116b contacts the sidewall of the corresponding step (112a-112d) of the step region 112, but is not limited thereto. In some embodiments, each side branch 116b extends vertically outward from the main trunk 116a, that is, extends along the direction D2, but is not limited thereto. In some embodiments, a pair of adjacent side branches 116b extends outward from two opposite sides of the main trunk 116a, but is not limited thereto. In some embodiments, the side branches 116b extend symmetrically from the main trunk 116a in the step region 112, but are not limited thereto. In some embodiments, the main trunk 116a and the side branches 116b have substantially the same height H in the step region 112, but are not limited thereto. In some embodiments, the stem 116 a has substantially the same height H in the step region 112 and the non-step region 110 , but is not limited thereto.

[0066] Please refer to Figure 4 , an etching process is performed to form a trench 118 along a direction D1, the trench 118 being between adjacent fishbone dielectric structures 116 and between adjacent rows of memory structures 110a in the non-step region 110. The trench 118 is used as a processing window for the gate replacement step. A wet etching process is performed to remove the insulating layer 109 in the multi-layer stack structure until the sidewalls of the memory structure 110a are exposed. The etchant of the wet etching process etches the insulating layer 109 much faster than the etching speed for the insulating layer 107, so that almost all the insulating layers 109 between the insulating layers 107 are removed, thereby forming gaps between the remaining (unetched) insulating layers 107. The fishbone dielectric structure 116 is used as a support structure to support the remaining insulating layer 107 so that the insulating layer 107 does not collapse due to the gaps therebetween.

[0067] Reference Figure 5, a conductive material is deposited through the trench 118 to form a conductive layer 108 to fill the gaps between the remaining (unetched) insulating layers 107. Each conductive layer 108 should reach or contact the exposed sidewalls of the memory structure 110a. The conductive material may include a metal, such as Cu, Al, W, or a metal alloy thereof. An etching process is performed to remove excess conductive material to space adjacent conductive layers 108 from each other to prevent bridging between adjacent conductive layers 108. Thereafter, a dielectric wall 119 is formed along a direction D1 by depositing a dielectric material into the trench 118, which is located between adjacent fishbone dielectric structures 116 and between adjacent rows of memory structures 110a in the non-step region 110. After the gate replacement process, that is, the insulating layer 109 is replaced by the conductive layer 108, the multi-layer stacked structure includes alternately stacked insulating layers 107 and conductive layers 108, and each step (112a-112d) includes a pair of adjacent alternately stacked insulating layers 107 and conductive layers 108. In some embodiments, the conductive layer 108 is made of tungsten and the insulating layer 107 is made of silicon oxide, but is not limited thereto.

[0068] Reference Figure 6 , forming a plurality of metal pillars 122 contacting each step (112a-112d) of the step region 112. Each metal pillar 122 contacts the conductive layer 108 of each step (112a-112d). In some embodiments, a pair of adjacent metal pillars 112 are separated by a corresponding one of the side branches 116b. In some embodiments, a pair of adjacent metal pillars 112 are separated by a corresponding trunk 116a. In some embodiments, each metal pillar 122 is located in a region surrounded by a corresponding trunk 116a, two side branches 116b and a dielectric wall 119. Therefore, even in the case of overlapping offset of adjacent metal pillars, the adjacent trunk 116a, two side branches 116b and dielectric walls make it difficult for the overlapping offset adjacent metal pillars 112 to bridge.

[0069] exist Figure 2 to Figure 6 In the figure, the step region 112 is actually covered by a passivation layer, which is omitted in order to clearly show the details of the step region 112. The metal pillar 112 and the fishbone dielectric structure 116 are embedded in the passivation layer.

[0070] Please refer to Figure 7 to Figure 15 , which depicts a three-dimensional diagram of a semiconductor memory device manufacturing method in multiple steps according to another embodiment of the present invention. Figure 7In the embodiment, the multilayer stacked structure includes insulating layers (207, 209) alternately stacked on a substrate 201. The multilayer stacked structure is etched to form a step region 212 and a non-step region 210. The step region 212 includes a plurality of steps (212a-212d). Each step (212a-212d) includes a pair of adjacent two different insulating layers (207, 209).

[0071] In this embodiment, the two different insulating layers (207, 209) may be a silicon nitride layer and a silicon oxide layer, respectively. In other embodiments of the present invention, the two different insulating layers may be two dielectric materials, such as two dielectric materials of silicon oxide, silicon nitride, silicon oxynitride, silicate, etc. In some embodiments of the present specification, the two different insulating layers (207, 209) are selected from two dielectric materials, and the two dielectric materials have a relatively strong etching resistance and a relatively weak etching resistance to a predetermined etchant.

[0072] exist Figure 8 In the embodiment, a passivation layer 214 is deposited to cover the step region 212 .

[0073] exist Fig. 9 In the embodiment, an etching process is performed to form a vertical hole 211 in the non-step region 210, and a vertical hole 213 in the step region 212. In some embodiments, the vertical hole 213 is formed along the sidewall of each step (212a-212d), but is not limited thereto.

[0074] exist Fig.10 In the embodiment, a mask layer 215 is formed on the non-step region 210 to cover the vertical hole 211 .

[0075] exist Fig.11 In the embodiment, a dielectric pillar 217 is formed in the vertical hole 213, and the mask layer 215 is removed. In some embodiments, the dielectric pillar 217 is made of a dielectric material that does not contain a conductive material (e.g., oxide), but is not limited thereto. In some embodiments, the dielectric pillar 217 contacts the sidewall of the corresponding step (212a-212d).

[0076] exist Fig.12 In the embodiment, memory structure 210a is formed in vertical hole 211 in non-step region 210. Each memory structure 210a is different from memory structure 210a in that memory structure 210a is not penetrated or divided by dielectric structure, so that gate-all-around transistors are formed in memory structure 210a.

[0077] Each memory structure 210a includes a storage layer and a channel layer. In some embodiments of the present specification, the storage layer may be a composite layer of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer (i.e., an ONO structure), but the structure of the storage layer is not limited thereto. In other embodiments of the present specification, the composite layer of the storage layer may also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride-oxide, i.e., ONONO) structure, a silicon-silicon oxide-silicon nitride-silicon oxide-silicon oxide (silicon-oxide-nitride-oxide-silicon, i.e., SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, a tantalum nitride, aluminum oxide, silicon nitride, silicon oxide-silicon oxide-silicon oxide-silicon oxide (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide-silicon ... The present invention relates to a group of semiconductor devices that are composed of a metal-oxide, silicon, TANOS structure and a metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structure. In this embodiment, the storage layer may be an ONO composite layer, and the channel layer may be a polysilicon layer.

[0078] like Fig.13 As shown, the trench 218 is etched to serve as a processing window for the gate replacement step. A wet etching process is performed to remove the insulating layer 209 in the multi-layer stack structure until the sidewalls of the memory structure 210a are exposed. The etchant of the wet etching process etches the insulating layer 209 much faster than the etching speed for the insulating layer 207, so that almost all the insulating layers 209 between the insulating layers 207 are removed, thereby forming gaps between the remaining (unetched) insulating layers 207. The dielectric pillars 217 are used as a support structure to support the remaining insulating layer 207 so that the insulating layer 207 does not collapse due to the gaps therebetween.

[0079] exist Fig.14In the embodiment of the present invention, a conductive material is deposited through the trench 218 to form a conductive layer 208 to fill the gaps between the remaining (unetched) insulating layers 207. Each conductive layer 208 should reach or contact the exposed sidewalls of the memory structure 210a. The conductive material may include a metal, such as Cu, Al, W, or a metal alloy thereof. An etching process is performed to remove excess conductive material so that adjacent conductive layers 208 are spaced apart from each other to prevent bridging between adjacent conductive layers 208. Thereafter, a dielectric wall 219 is formed by depositing a dielectric material into the trench 218. After the gate replacement process, that is, the insulating layer 209 is replaced by the conductive layer 208, the multi-layer stack structure includes alternately stacked insulating layers 207 and conductive layers 208, and each step (212a-212d) includes a pair of adjacent alternately stacked insulating layers 207 and conductive layers 208. In some embodiments, the conductive layer 208 is made of tungsten and the insulating layer 207 is made of silicon oxide, but is not limited thereto.

[0080] exist Fig.15 In the embodiment, a plurality of metal pillars 222 are formed, which contact each step (212a-212d) of the step region 212, and a common source line 220 is formed to contact the substrate 201. Each metal pillar 222 contacts the conductive layer 208 of each step (212a-212d). In some embodiments, each metal pillar 222 is located in the central region of each step (212a-212d), but is not limited thereto. In some embodiments, a corresponding dielectric pillar 217 is located between a pair of adjacent metal pillars 222, but is not limited thereto. Therefore, in the case of overlapping offset in adjacent metal pillars, adjacent metal pillars 212 are not easily bridged.

[0081] According to the aforementioned embodiment, the three-dimensional semiconductor memory includes forming a dielectric pillar or a fishbone dielectric structure in the step region. The dielectric pillar or the fishbone dielectric structure is used as a support structure to support the remaining insulating layer so that the insulating layer does not collapse due to the gap therebetween. The dielectric pillar or the fishbone dielectric structure is also located between the metal pillars or metal contacts in the step region to avoid bridging in the case of overlapping offsets in the metal pillars or metal contacts.

[0082] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional memory element, comprising: A plurality of conductive layers and a plurality of insulating layers are alternately stacked to form a multi-layer stacked structure, wherein the multi-layer stacked structure has a stepped region and a non-stepped region, the stepped region includes a plurality of steps, and each step includes a pair of adjacent conductive layers and insulating layers; A plurality of memory structures are located in the non-step region, each of the memory structures passes through the conductive layers and the insulating layers; and A fishbone dielectric structure includes a trunk and a plurality of side branches, wherein the trunk passes through the step region and the non-step region and extends in a direction perpendicular to the side walls of the plurality of steps in the step region, and the side branches extend outward from the trunk in the step region, wherein the trunk passes through the memory structures in the non-step region. 2 . The three-dimensional memory device according to claim 1 , wherein the herringbone dielectric structure is a dielectric structure that does not contain a conductive material. 3 . The three-dimensional memory device according to claim 1 , wherein each of the side branches extends along a sidewall of a step in the step region. 4 . The three-dimensional memory device according to claim 1 , further comprising a plurality of metal pillars connected to the steps in the step region, wherein a pair of adjacent metal pillars are separated by one of the side branches. 5 . The three-dimensional memory device according to claim 1 , further comprising a plurality of metal pillars connected to the steps in the step region, wherein a pair of adjacent metal pillars are separated by the trunk. 6 . The three-dimensional memory device according to claim 1 , wherein each of the side branches extends vertically outward from the main trunk. 7 . The three-dimensional memory device according to claim 1 , wherein a pair of adjacent side branches extend outward from two opposite sides of the main trunk.

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