Light emitting device, method for manufacturing light emitting device and display device having the same

Abstract

The present application relates to a light emitting device, a method for manufacturing a light emitting device, and a display device. A light emitting device according to an embodiment of the present application includes: a substrate; a first electrode disposed on the substrate; a first insulating layer disposed on the substrate to cover at least one region of the first electrode; a second electrode disposed on the first insulating layer to be spaced apart from the first electrode; and at least one light emitting diode electrically connected between the first electrode and the second electrode. The first electrode and the second electrode have a first insulating layer interposed therebetween, are arranged on different layers on the substrate, and are spaced apart from each other by a predetermined distance in a plan view so as not to overlap.

Description

Technical Field

[0001] Various embodiments of the present disclosure are directed to a light emitting device, a method of manufacturing the light emitting device, and a display apparatus having the light emitting device. Background Art

[0002] Recently, a technology for manufacturing ultra-small light-emitting diodes using materials having a reliable inorganic crystal structure and manufacturing light-emitting devices using the light-emitting diodes has been developed. For example, a technology for manufacturing ultra-small light-emitting diodes having a small size ranging from nanometers to micrometers and forming a light source of a light-emitting device using the ultra-small light-emitting diodes has been developed. Such light-emitting devices can be provided in various electronic devices, such as display devices and lighting devices. Summary of the invention

[0003] Technical issues

[0004] Various embodiments of the present disclosure relate to a light emitting device including a light emitting diode, a method of manufacturing the light emitting device, and a display apparatus including the light emitting device.

[0005] Technical Solution

[0006] According to aspects of the present disclosure, a light emitting device includes: a substrate; a first electrode disposed on the substrate; a first insulating layer disposed on the substrate and configured to cover at least one region of the first electrode; a second electrode disposed on the first insulating layer and spaced apart from the first electrode; and at least one light emitting diode electrically connected between the first electrode and the second electrode. The first electrode and the second electrode are disposed on different layers on the substrate, and the first insulating layer is interposed between the first electrode and the second electrode, and the first electrode and the second electrode are spaced apart from each other by a predetermined distance so as not to overlap each other in a plan view.

[0007] In an embodiment, the light emitting device may further include: a first partition wall disposed between the substrate and one region of the first electrode; and a second partition wall disposed between the substrate and one region of the second electrode.

[0008] In an embodiment, the first partition wall and the second partition wall may be disposed on the same layer on the substrate. A region of the first insulating layer may be interposed between the second partition wall and the second electrode.

[0009] In an embodiment, the light emitting device may include a display element layer and a circuit element layer, the display element layer including a first electrode, a second electrode and a light emitting diode, and the circuit element layer is disposed between the display element layer and the substrate. The circuit element layer may include: a first circuit element or a first power line electrically connected to the first electrode and including a region overlapping the second electrode; and a second circuit element or a second power line electrically connected to the second electrode and including a region overlapping the first electrode.

[0010] In an embodiment, an overlapping surface area between the first circuit element or the first power line and the second electrode may be greater than an overlapping surface area between the second circuit element or the second power line and the first electrode.

[0011] In an embodiment, the light emitting device may further include: a first contact electrode, disposed on at least one region of the first electrode and a first end of the light emitting diode, and configured to electrically connect the first end to the first electrode; and a second contact electrode, disposed on at least one region of the second electrode and a second end of the light emitting diode, and configured to electrically connect the second end to the second electrode.

[0012] In an embodiment, the first insulating layer may include an opening in which a region of the first electrode is exposed. The first contact electrode may contact the exposed region of the first electrode and the first end of the light emitting diode.

[0013] In an embodiment, the light emitting device may further include a second insulating layer disposed on the second contact electrode and configured to cover the second contact electrode. One end of the second insulating layer may be interposed between the first contact electrode and the second contact electrode.

[0014] In an implementation, the light emitting device may further include a third insulating layer disposed on a region of the second electrode.

[0015] In an embodiment, the light emitting device may further include at least one of the following items: a fourth insulating layer disposed on the first electrode, the second electrode and an area of ​​the light emitting diode; and a fifth insulating layer configured to cover the first contact electrode and including an end inserted between the first contact electrode and the second contact electrode.

[0016] In an embodiment, the light emitting device may further include a sixth insulating layer, which is partially disposed on the first electrode, the second electrode and a region of the light emitting diode and is configured to expose a region of each of the first electrode and the second electrode and the first end and the second end of the light emitting diode.

[0017] In an embodiment, one end of the first contact electrode may be disposed on a region of the sixth insulating layer disposed on the light emitting diode. One end of the second contact electrode may be disposed on a region of the sixth insulating layer disposed on the light emitting diode to face the first contact electrode.

[0018] In an embodiment, the light emitting device may further include at least one encapsulation layer configured to cover one surface of the substrate on which the first contact electrode and the second contact electrode are disposed.

[0019] In an embodiment, the light emitting diode may include a rod type light emitting diode oriented in a horizontal direction between the first electrode and the second electrode.

[0020] According to aspects of the present disclosure, a method for manufacturing a light-emitting device includes: forming a first electrode on a substrate; forming a first insulating layer on the substrate to cover at least the first electrode; forming a second electrode on the first insulating layer at a position spaced a predetermined distance from the first electrode; providing a light-emitting diode on the substrate including the first electrode and the second electrode, and aligning the light-emitting diode between the first electrode and the second electrode; and forming a first contact electrode and a second contact electrode, the first contact electrode electrically connecting a first end of the light-emitting diode to the first electrode, and the second contact electrode electrically connecting a second end of the light-emitting diode to the second electrode.

[0021] In an embodiment, forming the first contact electrode may include: forming a first contact portion by etching the first insulating layer to expose a region of the first electrode; and forming the first contact electrode on at least one region of the first electrode including the first contact portion and on the first end of the light emitting diode.

[0022] In an implementation, forming the second contact electrode may include forming the second contact electrode on at least one region of the second electrode and the second end of the light emitting diode.

[0023] In an implementation, the first contact electrode and the second contact electrode may be sequentially formed on the substrate, or the first contact electrode and the second contact electrode may be simultaneously formed on the substrate.

[0024] In an embodiment, the method may further include, after forming the second electrode, forming a third insulating layer configured to cover the second electrode. The light emitting diode may be provided on the substrate having the third insulating layer formed thereon.

[0025] According to aspects of the present disclosure, a display device includes: a substrate including a display area; and a pixel disposed in the display area. The pixel includes: a first electrode disposed on the substrate; a first insulating layer disposed on the substrate and configured to cover at least one area of ​​the first electrode; a second electrode disposed on the first insulating layer and spaced apart from the first electrode by a predetermined distance in a plan view; and at least one light emitting diode electrically connected between the first electrode and the second electrode.

[0026] Beneficial Effects

[0027] In the light emitting device, the method of manufacturing the light emitting device, and the display device including the light emitting device according to the embodiment of the present disclosure, a short circuit defect between the first electrode and the second electrode can be prevented, and the light emitting diode can be stably arranged between the first electrode and the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b 1 and 2 are a perspective view and a cross-sectional view respectively showing a light emitting diode according to an embodiment of the present disclosure.

[0031] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 5a to Figure 5c 1 and 2 are circuit diagrams each showing a light emitting device according to an embodiment of the present disclosure, and, for example, show different embodiments of active pixels including the light emitting device.

[0033] Figure 6 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an example of a pixel formed by the light emitting device.

[0034] Figure 7a and Figure 7b are cross-sectional views each showing a light emitting device according to an embodiment of the present disclosure, and for example, showing a light emitting device corresponding to Figure 6 Different embodiments of the cross section along line II'.

[0035] Figure 8 1 is a plan view showing a light emitting device according to an embodiment of the present disclosure, for example, showing an example of a pixel including the light emitting device.

[0036] Figure 9a and Figure 9b are cross-sectional views each showing a light emitting device according to an embodiment of the present disclosure, and for example, showing a light emitting device corresponding to Figure 8 Different embodiments of the cross section along line II-II'.

[0037] Figures 10a to 10k is a cross-sectional view showing a method of manufacturing a light emitting device according to an embodiment of the present disclosure, and for example shows a method of manufacturing a light emitting device according to Figure 9a A method for a light emitting device of an embodiment of the present invention.

[0038] Fig.11 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a light emitting device corresponding to Figure 8 An embodiment of a cross section of line II-II'.

[0039] Fig.12 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a light emitting device corresponding to Figure 8 An embodiment of a cross section of line II-II'.

[0040] Figures 13a to 13i is a cross-sectional view showing a method of manufacturing a light emitting device according to an embodiment of the present disclosure, and for example shows a method of manufacturing a light emitting device according to Fig.12 A method for a light emitting device of an embodiment of the present invention.

[0041] Fig.14 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a light emitting device corresponding to Figure 8 An embodiment of a cross section of line II-II'.

[0042] Figures 15a to 15e is a cross-sectional view showing a method of manufacturing a light emitting device according to an embodiment of the present disclosure, and for example shows a method of manufacturing a light emitting device according to Fig.14 A method for a light emitting device of an embodiment of the present invention. DETAILED DESCRIPTION

[0043] Reference will now be made in detail to various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below, and which may be variously modified in many different forms. However, the present disclosure is not limited to the following embodiments and may be modified in various forms.

[0044] In order to clearly explain the present disclosure, some elements that are not directly related to the features of the present disclosure may be omitted in the accompanying drawings. In addition, the size, ratio, etc. of some elements in the accompanying drawings may be slightly exaggerated. It should be noted that in all the accompanying drawings, the same reference numerals are used to represent the same or similar elements, and repeated explanations will be omitted.

[0045] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when a first component or part is disposed on a second component or part, the first component or part may not only be directly disposed on the second component or part, but a third component or part may be interposed between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or directions depending on the viewing angle or direction.

[0046] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings so as to describe the present disclosure in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0047] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 is a perspective view and a cross-sectional view showing a light emitting diode LD according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod type light emitting diode LD is illustrated, but the type and / or shape of the light emitting diode LD according to the present disclosure is not limited thereto.

[0048] Ginseng Figure 1a and Figure 1b The light emitting diode LD according to the embodiment of the present disclosure may include a first conductive type semiconductor layer 11 (also referred to as a "first semiconductor layer"), a second conductive type semiconductor layer 13 (also referred to as a "second semiconductor layer"), and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting diode LD may be configured by a stacked body formed by sequentially stacking the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13.

[0049] In an embodiment, the light emitting diode LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting diode LD extends is defined as a longitudinal direction, the light emitting diode LD may have a first end and a second end in the longitudinal direction.

[0050] In an embodiment, one of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a first end of the light emitting diode LD, and the other of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 may be disposed on a second end of the light emitting diode LD.

[0051] In an embodiment, the light emitting diode LD may be a rod-type light emitting diode manufactured in the form of a rod. In this specification, the term "rod-type shape" includes a rod-like shape and a bar-like shape, such as a cylindrical shape and a prism shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting diode LD may be greater than its diameter D (or the width of its cross section).

[0052] In an embodiment, the light emitting diode LD may have a small size corresponding to a nanometer size or a micrometer size, for example, a diameter D and / or a length L corresponding to a micrometer to nanometer range. However, in the present disclosure, the size of the light emitting diode LD is not limited thereto. For example, the size of the light emitting diode LD may be changed in various ways according to the design conditions of various devices (for example, display devices), wherein the various devices use a light emitting device using the light emitting diode LD as a light source.

[0053] The first conductive type semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first conductive type semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material used to form the first conductive type semiconductor layer 11 is not limited thereto, and the first conductive type semiconductor layer 11 may be formed of various other materials.

[0054] The active layer 12 may be disposed on the first conductive semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0055] If an electric field of a predetermined voltage or more is applied to opposite ends of the light emitting diode LD, the light emitting diode LD emits light by recombination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting diode LD can be controlled based on the aforementioned principle, the light emitting diode LD can be used as a light source for various light emitting devices and pixels of a display device.

[0056] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a p-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a second conductive dopant such as Mg. However, the material forming the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0057] In an embodiment, the light emitting diode LD may further include an insulating film INF disposed on the surface of the light emitting diode LD. In an embodiment, the insulating film INF may be formed on the surface of the light emitting diode LD to surround at least the outer peripheral surface of the active layer 12. In addition, the insulating film INF may also surround an area of ​​each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting diode LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive semiconductor layer 11 and the second conductive semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting diode LD in the longitudinal direction, for example, the insulating film INF may expose the two base sides (top surface and bottom surface) of the cylinder without covering the two base sides.

[0058] In an embodiment, the insulating film INF may include SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0059] In an embodiment, in addition to the first conductive semiconductor layer 11, the active layer 12, the second conductive semiconductor layer 13 and / or the insulating film INF, the light emitting diode LD may further include additional components. For example, the light emitting diode LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer and / or at least one electrode layer disposed on one end of the first conductive semiconductor layer 11, the active layer 12 and / or the second conductive semiconductor layer 13.

[0060] For example, Figure 2a and Figure 2bAs shown in , the light emitting diode LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. In an embodiment, as shown in Figure 3a and Figure 3b As shown in , the light emitting diode LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11 .

[0061] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, Cr, Ti, Al, Au, Ni, ITO, IZO, ITZO, and oxides or alloys thereof may be used alone or in combination with each other. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Therefore, light generated from the light emitting diode LD may be emitted from the light emitting diode LD after passing through the electrode layers 14 and 15.

[0062] In an embodiment, the insulating film INF may or may not at least partially surround the outer peripheral surface of the electrode layers 14 and 15. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to allow the opposite ends of the light emitting diode LD having different polarities to be exposed, and, for example, may allow at least one region of each of the electrode layers 14 and 15 to be exposed. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0063] If the insulating film INF is provided on the surface of the light emitting diode LD, specifically, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode (e.g., at least one contact electrode connected to the opposite end of the light emitting diode LD among the contact electrodes) not shown. Therefore, the electrical stability of the light emitting diode LD can be ensured.

[0064] In addition, due to the insulating film INF formed on the surface of the light emitting diode LD, the occurrence of defects on the surface of the light emitting diode LD can be minimized, and thus the life and efficiency of the light emitting diode LD can be improved. In addition, if the insulating film INF is formed on each light emitting diode LD, even in the case where a plurality of light emitting diodes LD are arranged adjacent to each other, the light emitting diode LD can be prevented from being unexpectedly short-circuited.

[0065] In an embodiment of the present disclosure, the light emitting diode LD may be manufactured by a surface treatment process. For example, the light emitting diode LD may be surface treated (e.g., by a coating process) so that when a plurality of light emitting diodes LD are mixed with a fluid solution and then supplied to each light emitting region (e.g., the light emitting region of each pixel), the light emitting diodes LD may be evenly distributed, rather than unevenly aggregated in the solution.

[0066] The above-mentioned light emitting diode LD can be used in various devices including display devices that require light sources. For example, at least one ultra-small light emitting diode LD (for example, a plurality of ultra-small light emitting diodes LD each having a size in the range of nanometers to micrometers) can be provided in each pixel region of the display panel to form a light source (or light source unit) of the corresponding pixel. In addition, the application field of the light emitting diode LD according to the present disclosure is not limited to display devices. For example, the light emitting diode LD can also be used in various devices that require light sources, such as lighting equipment.

[0067] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device (specifically, a display panel PNL provided in the display device) is shown as a reference device that can be used. Figures 1a to 3b The light emitting diode LD is described as an example of a device of a light source. For example, each of the pixels PXL of the display panel PNL may include a light emitting device. The light emitting device may include at least one light emitting diode LD.

[0068] To explain, Figure 4 The structure of the display panel PNL according to the embodiment is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided on the display panel PNL.

[0069] Reference Figure 4 , the display panel PNL according to an embodiment of the present disclosure may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. In detail, the display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed in the display area DA on the substrate SUB.

[0070] In an embodiment, the display area DA may be disposed in the central area of ​​the display panel PNL, and the non-display area NDA may be disposed in the peripheral area of ​​the display panel PNL to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0071] The substrate SUB may form a base of the display panel PNL. In an embodiment, the substrate SUB may be a rigid substrate or a flexible substrate, and its material or properties are not particularly limited. For example, the substrate SUB may be a rigid substrate made of glass or reinforced glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the substrate SUB may be a transparent substrate, but is not limited thereto. For example, the substrate SUB may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0072] One area on the substrate SUB is defined as a display area DA on which the pixels PXL are disposed, and another area thereof is defined as a non-display area NDA. For example, the substrate SUB may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0073] In an embodiment, the pixels PXL may be distributed and arranged in the display area DA. In an embodiment, the pixels PXL may be arranged in the display area DA in a strip shape. However, the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in the display area DA in various well-known shapes.

[0074] Each pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or power (eg, a first power and a second power), and may include, for example, a first light source according to a predetermined control signal (eg, a scan signal and a data signal) and / or a first power and a second power. Figures 1a to 3b The light emitting diode LD of any one of the embodiments of the present invention. For example, each pixel PXL may include at least one light emitting diode LD having a small size ranging from nanometer level to micrometer level. For example, each pixel PXL may include a plurality of rod-type light emitting diodes connected in parallel between pixel electrodes and / or power lines. A plurality of rod-type light emitting diodes may form a light emitting device of each pixel PXL (e.g., a light source or a light source unit of each pixel PXL).

[0075] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL applicable to the display device according to the present disclosure is not particularly limited. For example, each pixel PXL may have the same structure as that of a pixel of various known passive or active light-emitting display devices.

[0076] Figure 5a to Figure 5c Each is a circuit diagram showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, different embodiments of an active pixel PXL including a light emitting device. In the embodiment, Figure 5a to Figure 5c Each pixel PXL shown in FIG. 1 may be set to Figure 4 The pixels PXL may have substantially the same or similar structures.

[0077] Reference Figure 5a The pixel PXL according to the embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal and a pixel circuit PXC configured to drive the light source unit LSU. The light source unit LSU may form a light emitting device according to the embodiment of the present disclosure.

[0078] In an embodiment, the light source unit LSU may include a plurality of light emitting diodes LD connected in parallel to each other between a first power source VDD and a second power source VSS. Here, the first power source VDD and the second power source VSS may have different potentials so that the light emitting diode LD may emit light. For example, the first power source VDD may be set as a high potential power source, and the second power source VSS may be set as a low potential power source. Here, during at least one light emitting cycle of the pixel PXL, the potential difference between the first power source VDD and the second power source VSS may be set to a voltage equal to or greater than a threshold voltage of the light emitting diode LD.

[0079] although Figure 5a An embodiment is shown in which the light emitting diodes LD of the light source unit LSU forming each pixel PXL are connected in parallel to each other between the first power supply VDD and the second power supply VSS in the same direction (e.g., forward direction), but the present disclosure is not limited thereto. For example, in an embodiment, some of the light emitting diodes LD may be connected to each other between the first power supply VDD and the second power supply VSS in a first direction (e.g., forward direction), and the other light emitting diodes LD may be connected to each other in a second direction (e.g., reverse direction). Alternatively, in an embodiment, at least one pixel PXL may include only a single light emitting diode LD.

[0080] In an embodiment, a first end of the light emitting diode LD forming each light source unit LSU may be commonly connected to a corresponding pixel circuit PXC through a first electrode of the light source unit LSU, and may be commonly connected to a first power source VDD through the pixel circuit PXC and a first power line PL1. A second end of the light emitting diode LD may be commonly connected to a second power source VSS through a second electrode of the light source unit LSU and a second power line PL2.

[0081] Each light source unit LSU may emit light having brightness corresponding to a driving current supplied thereto through a corresponding pixel circuit PXC. Thus, a predetermined image may be displayed in the display area DA.

[0082] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed in the i-th row (where i is a natural number) and the j-th column (where j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. The pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0083] The first transistor T1 (driving transistor) is connected between the first power source VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 can control the driving current to be supplied to the light source unit LSU in response to the voltage of the first node N1.

[0084] The second transistor T2 (switching transistor) may be connected between the data line Dj and the first node N1. A gate electrode of the second transistor T2 is connected to the scan line Si.

[0085] When a scan signal of a gate-on voltage (e.g., a low voltage) is provided from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj. During each frame period, a data signal of a corresponding frame is provided to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Therefore, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0086] One electrode of the storage capacitor Cst is connected to the first power source VDD and the other electrode thereof is connected to the first node N1. The storage capacitor Cst may store a voltage corresponding to a data signal supplied to the first node N1 during each frame period and may maintain the stored voltage until a data signal of a subsequent frame is supplied.

[0087] Despite Figure 5aIn the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, any one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0088] For example, Figure 5b As shown, both the first transistor T1 and the second transistor T2 can be formed by N-type transistors. In addition to the changes in the connection positions of some circuit elements and the changes in the transistor types, Figure 5b The configuration and operation of the pixel PXL shown in FIG. 1 are substantially similar to those of FIG. Figure 5a Therefore, the configuration and operation of the pixel PXL will be omitted. Figure 5b A detailed description of the pixel PXL.

[0089] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5b In other words, the pixel circuit PXC may be formed by a well-known pixel circuit, which may have various structures and / or may be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a well-known pixel circuit. Figure 5c The embodiment shown in FIG. 1 is configured in the same manner as that shown in FIG.

[0090] refer to Figure 5c , the pixel circuit PXC can be connected not only to the i-th scan line Si of the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged in the i-th row of the display area DA can also be connected to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0091] The first transistor T1 is connected between the first power source VDD and the first electrode of the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0092] The second transistor T2 is connected between the data line Dj and one electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding i-th scan line Si. When a scan signal of a gate-on voltage is provided from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj to one electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the data line Dj may be transmitted to the first transistor T1.

[0093] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding i-th scan line Si. When a scan signal of a gate-on voltage is provided from the i-th scan line Si, the third transistor T3 can be turned on to electrically connect the first transistor T1 in a diode form.

[0094] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When the scan signal of the gate-on voltage is provided to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be the minimum voltage of the data signal or a smaller voltage.

[0095] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal of the gate cut-off voltage (for example, a high voltage) is provided to the i-th emission control line Ei, the fifth transistor T5 can be turned off, and the fifth transistor T5 can be turned on in other cases.

[0096] The sixth transistor T6 is connected between the first transistor T1 and the second node N2, and the second node N2 is electrically connected to the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal of the gate-off voltage is provided to the i-th emission control line Ei, the sixth transistor T6 can be turned off, and the sixth transistor T6 can be turned on in other cases.

[0097] The seventh transistor T7 is connected between the second node N2 and the initialization power supply Vint, and the second node N2 is electrically connected to the first electrode of the light source unit LSU. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.

[0098] The storage capacitor Cst is connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0099] Although in Figure 5c The transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0100] The structure of the pixel PXL applicable to the present disclosure is not limited to Figure 5a to Figure 5c , and each pixel PXL may have various known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a known pixel circuit, which may have various structures and / or be operated by various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode and the second electrode of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0101] Figure 6 is a plan view showing a light emitting device according to an embodiment of the present disclosure, and, for example, shows an example of a pixel PXL including the light emitting device. In the embodiment, Figure 6 A light emitting device (e.g., a pixel PXL of a passive light emitting display device) including first and second power lines PL1 and PL2 (or signal lines such as scan lines and data lines) or directly connected to the first and second power lines PL1 and PL2 is shown. However, the light emitting device according to the present disclosure is not limited to Figure 6 For example, in the embodiments of the present disclosure, the light emitting device can be connected via at least one circuit element (e.g., Figure 5a to Figure 5c The pixel circuit PXC) is connected to the first power line PL1 and / or the second power line PL2, a connection line, a signal line, etc.

[0102] refer to Figure 6 , the pixel PXL according to an embodiment of the present disclosure may include a first electrode ELT1 and a second electrode ELT2 spaced apart from each other, at least one light emitting diode LD disposed between the first electrode ELT1 and the second electrode ELT2 (for example, a plurality of light emitting diodes LD arranged in parallel to each other), and a first contact electrode CNE1 and a second contact electrode CNE2 electrically connecting (or coupling) the light emitting diode LD between the first electrode ELT1 and the second electrode ELT2. The pixel PXL may also include a first connection electrode CNL1 connecting the first electrode ELT1 to the first power line PL1 and a second connection electrode CNL2 connecting the second electrode ELT2 to the second power line PL2. In an embodiment, the first connection electrode CNL1 and the second connection electrode CNL2 may be connected to the first electrode ELT1 and the second electrode ELT2, respectively and as a whole, or may be electrically connected (or coupled) to the first electrode ELT1 and the second electrode ELT2 via at least one contact hole or the like. In the case where the first connection electrode CNL1 and the second connection electrode CNL2 are respectively and integrally connected to the first electrode ELT1 and the second electrode ELT2, each of the first connection electrode CNL1 and the second connection electrode CNL2 can be regarded as a region of the corresponding electrode of the first electrode ELT1 and the second electrode ELT2. The pixel PXL may also include a first partition wall PW1 (also referred to as a "first wall", "first bank" or "first pattern") overlapping the first electrode ELT1 and a second partition wall PW2 (also referred to as a "second wall", "second bank" or "second pattern") overlapping the second electrode ELT2.

[0103] In an embodiment, the first partition wall PW1 and the second partition wall PW2, the first electrode ELT1 and the second electrode ELT2, the light emitting diode LD and / or the first contact electrode CNE1 and the second contact electrode CNE2 may form a light emitting device according to an embodiment of the present disclosure. For example, the first partition wall PW1 and the second partition wall PW2, the first electrode ELT1 and the second electrode ELT2, the light emitting diode LD and / or the first contact electrode CNE1 and the second contact electrode CNE2 may form a light source unit (for example, a pixel PXL) according to an embodiment of the present disclosure. Figure 5a to Figure 5c of LSU).

[0104] The first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other and arranged so that they at least partially face each other. For example, the first electrode ELT1 and the second electrode ELT2 may be arranged parallel to each other at positions spaced apart from each other by a predetermined distance on one surface of a substrate, the substrate being arranged to form a base of a pixel PXL (or a light-emitting device). For example, in a predetermined emission area, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other by a predetermined distance in a first direction DR1, and the first electrode ELT1 and the second electrode ELT2 may each extend in a second direction DR2 intersecting with the first direction DR1. However, the present disclosure is not limited thereto. For example, the shapes and / or mutual arrangement relationships of the first electrode ELT1 and the second electrode ELT2 may be changed in various ways.

[0105] In an embodiment, each of the first electrode ELT1 and the second electrode ELT2 may have a single layer or a multilayer structure. For example, each first electrode ELT1 may have a multilayer structure including a first reflective electrode and a first conductive capping layer. Each second electrode ELT2 may have a multilayer structure including a second reflective electrode and a second conductive capping layer.

[0106] In an embodiment, the first electrode ELT1 may be connected to the first power line PL1 through the first connection electrode CNL1. In an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may extend in different directions. For example, in the case where the first connection electrode CNL1 extends in a first direction DR1 (e.g., in a horizontal direction), the first electrode ELT1 may extend in a second direction DR2 (e.g., in a vertical direction) intersecting the first direction DR1.

[0107] In an embodiment, the first electrode ELT1 may be integrally connected to the first connection electrode CNL1. For example, the first electrode ELT1 may be bifurcated from the first connection electrode CNL1 in at least one manner. However, the present disclosure is not limited thereto. For example, in an embodiment, the first electrode ELT1 and the first connection electrode CNL1 may be separately formed and electrically connected to each other through at least one contact hole, at least one through hole, etc.

[0108] In an embodiment, the first electrode ELT1 and / or the first connection electrode CNL1 may be integrally connected to the first power line PL1. In an embodiment, the first electrode ELT1 and / or the first connection electrode CNL1 may be formed separately from the first power line PL1 and electrically connected to the first power line PL1 via at least one contact hole and / or at least one circuit element. Therefore, the first power to be supplied to the first power line PL1 may be transmitted to the first electrode ELT1.

[0109] In an embodiment, the second electrode ELT2 may be connected to the second power line PL2 through the second connection electrode CNL2. In an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may extend in different directions. For example, when the second connection electrode CNL2 extends in the first direction DR1, the second electrode ELT2 may extend in the second direction DR2 crossing the first direction DR1.

[0110] In an embodiment, the second electrode ELT2 may be integrally connected to the second connection electrode CNL2. For example, the second electrode ELT2 may be bifurcated from the second connection electrode CNL2 in at least one manner. However, the present disclosure is not limited thereto. For example, in an embodiment, the second electrode ELT2 and the second connection electrode CNL2 may be formed separately and electrically connected to each other through at least one contact hole, at least one through hole, etc.

[0111] In an embodiment, the second electrode ELT2 and / or the second connection electrode CNL2 may be integrally connected to the second power line PL2. In an embodiment, the second electrode ELT2 and / or the second connection electrode CNL2 may be formed separately from the second power line PL2 and electrically connected to the second power line PL2 via at least one contact hole and / or at least one circuit element. Therefore, the second power to be supplied to the second power line PL2 may be transmitted to the second electrode ELT2.

[0112] In an embodiment, a first power source (eg, Figure 5a to Figure 5c VDD) and a second power supply (e.g., Figure 5a to Figure 5c The first power supply VDD and the second power supply VSS may have different potentials. For example, the potential difference between the first power supply VDD and the second power supply VSS may be equal to or greater than the threshold voltage of the light emitting diode LD. In an embodiment, the first power supply VDD and the second power supply VSS may have a potential that enables at least one light emitting diode LD to be connected between the first electrode ELT1 and the second electrode ELT2 in a forward direction. In other words, the voltage between the first power supply VDD and the second power supply VSS may have a value that enables at least one light emitting diode LD included in the pixel PXL (or the light emitting device) to emit light.

[0113] In an embodiment, the first partition wall PW1 may be disposed under the first electrode ELT1 so that the first partition wall PW1 overlaps with an area of ​​the first electrode ELT1. The second partition wall PW2 may be disposed under the second electrode ELT2 so that the second partition wall PW2 overlaps with an area of ​​the second electrode ELT2. The first partition wall PW1 and the second partition wall PW2 may be disposed in a predetermined emission region at positions spaced apart from each other, and may cause an area of ​​the first electrode ELT1 and an area of ​​the second electrode ELT2 to protrude upward, respectively. For example, the first electrode ELT1 may be disposed on the first partition wall PW1 and protrude in a height direction through the first partition wall PW1. The second electrode ELT2 may be disposed on the second partition wall PW2 and protrude in a height direction through the second partition wall PW2.

[0114] In an embodiment, the light emitting diodes LD may be connected in parallel to each other between the first electrode ELT1 and the second electrode ELT2. For example, each light emitting diode LD may be a rod-shaped light emitting diode arranged between the first electrode ELT1 and the second electrode ELT2 in a first direction DR1 (e.g., in a horizontal direction) in an area where the first electrode ELT1 and the second electrode ELT2 are arranged to face each other.

[0115] although Figure 6 It is shown that the light emitting diodes LD are uniformly arranged in any one direction (eg, in the first direction DR1), but the present disclosure is not limited thereto. For example, at least one of the light emitting diodes LD may be arranged between the first electrode ELT1 and the second electrode ELT2 in a diagonal direction.

[0116] In an embodiment, each light emitting diode LD may be a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size, for example, in the range of nanometer scale to micrometer scale. Figures 1a to 3b As shown in , each light emitting diode LD may be an ultra-small rod-shaped light emitting diode having a diameter D and / or a length L in the range of nanometer to micrometer. However, the size of the light emitting diode LD may be changed in various ways according to the design conditions of each light emitting device (e.g., pixel PXL), etc.

[0117] In an embodiment, the first end EP1 of the light emitting diode LD may be electrically connected to the first electrode ELT1 via the first contact electrode CNE1. The second end EP2 of the light emitting diode LD may be electrically connected to the second electrode ELT2 via the second contact electrode CNE2. In an embodiment, at least one of the first end EP1 and the second end EP2 of each light emitting diode LD may be in direct contact with the first electrode ELT1 and / or the second electrode ELT2 and electrically connected to the first electrode ELT1 and / or the second electrode ELT2.

[0118] In an embodiment, the light emitting diode LD may be prepared in a diffused form in a predetermined solution, and then provided to a predetermined emission area (e.g., the emission area of ​​each pixel PXL) defined in the light emitting device by an inkjet printing scheme or the like. For example, the light emitting diode LD may be mixed with a volatile solvent and provided to each emission area. Here, if the voltages of the first power supply VDD and the second power supply VSS are applied to the first electrode ELT1 and the second electrode ELT2 through the first power line PL1 and the second power line PL2, respectively, an electric field is formed between the first electrode ELT1 and the second electrode ELT2, whereby the light emitting diode LD is aligned between the first electrode ELT1 and the second electrode ELT2. After the light emitting diode LD has been aligned, the solvent may be removed by a volatilization method or other methods. In this way, the light emitting diode LD may be reliably arranged between the first electrode ELT1 and the second electrode ELT2. In addition, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed on the opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting diode LD, respectively. Therefore, the light emitting diode LD may be more reliably connected between the first electrode ELT1 and the second electrode ELT2.

[0119] In an embodiment, the first contact electrode CNE1 may be formed to cover both the first end EP1 of the light emitting diode LD and at least one region of the first electrode ELT1, whereby the first end EP1 of the light emitting diode LD may be physically and / or electrically connected to the first electrode ELT1. Similarly, the second contact electrode CNE2 may be formed to cover both the second end EP2 of the light emitting diode LD and at least one region of the second electrode ELT2, whereby the second end EP2 of the light emitting diode LD may be physically and / or electrically connected to the second electrode ELT2.

[0120] When the voltage of the first power source VDD (or a predetermined first control signal, such as a scan signal or a data signal) is applied to the first end EP1 of the light emitting diode LD via the first power line PL1 and the first electrode ELT1, and the voltage of the second power source VSS (or a predetermined second control signal, such as a scan signal or a data signal) is applied to the second end EP2 of the light emitting diode LD via the second power line PL2 and the second electrode ELT2, at least one light emitting diode LD connected between the first electrode ELT1 and the second electrode ELT2 in the forward direction may emit light. Therefore, the pixel PXL may emit light.

[0121] In an embodiment of the present disclosure, the first electrode ELT1 and the second electrode ELT2 may be disposed on different layers of the substrate that are separated from each other, and at least one insulating layer is interposed between the first electrode ELT1 and the second electrode ELT2. In this way, if the first electrode ELT1 and the second electrode ELT2 are disposed on different layers, respectively, a short circuit defect between the first electrode ELT1 and the second electrode ELT2 may be effectively prevented from occurring during the process of manufacturing the pixel PXL. The stacked structure of the light emitting device including the first electrode ELT1 and the second electrode ELT2 will be described in detail below.

[0122] In an embodiment of the present disclosure, the first electrode ELT1 and the second electrode ELT2 may be spaced apart from each other by a predetermined distance so as not to overlap each other in a plan view (i.e., when viewed from the top). For example, the first electrode ELT1 and the second electrode ELT2 may be arranged in a predetermined emission region at positions spaced apart from each other by a predetermined distance along the first direction DR1. In an embodiment, the spacing and / or distance between the first electrode ELT1 and the second electrode ELT2 may remain constant, or may be changed for a segment or region. By adjusting the position and / or spacing of the first electrode ELT1 and the second electrode ELT2, the light emitting diode LD may be easily arranged in a desired region.

[0123] Figure 7a and Figure 7b Each is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a cross-sectional view corresponding to Figure 6 Different embodiments of the cross section of line II'. In an embodiment, Figure 7a and Figure 7b Each of the light emitting devices may correspond to a passive pixel PXL, and Figure 7a and Figure 7b Various embodiments related to the shapes of the first partition wall PW1 and the second partition wall PW2 are shown. However, the light emitting device according to the present disclosure is not limited to the pixel PXL.

[0124] Reference Figure 6 , Figure 7a and Figure 7b, the pixel PXL (or light emitting device) according to the embodiment of the present disclosure may include a substrate SUB and a buffer layer BFL, a first partition wall PW1 and a second partition wall PW2, a first electrode ELT1, a first insulating layer INS1, a second electrode ELT2, at least one light emitting diode LD (for example, a plurality of light emitting diodes LD), a second contact electrode CNE2, a second insulating layer INS2, a first contact electrode CNE1, and an encapsulation layer ENC, which are sequentially disposed on one surface of the substrate SUB. For example, in the embodiment of the present disclosure, based on one surface of the substrate SUB, the buffer layer BFL may be disposed on the first layer, the first partition wall PW1 and the second partition wall PW2 may be disposed on the second layer, the first electrode ELT1 may be disposed on the third layer, the first insulating layer INS1 may be disposed on the fourth layer, the second electrode ELT2 may be disposed on the fifth layer, the light emitting diode LD may be disposed on the sixth layer, the second contact electrode CNE2 may be disposed on the seventh layer, the second insulating layer INS2 may be disposed on the eighth layer, the first contact electrode CNE1 may be disposed on the ninth layer, and the encapsulation layer ENC may be disposed on the tenth layer. Here, the above-defined corresponding positions of the components on the layer may be based on the mutual arrangement relationship between the components disposed on the substrate SUB and / or the order in which the components are formed, and may not be based on the distance, height, etc. from the substrate SUB. In addition, in some embodiments, at least one of the aforementioned components may be omitted, or its position may be changed. For example, the positions of the first electrode ELT1 and the second electrode ELT2 on the layer may be swapped with each other. Similarly, the positions of the first contact electrode CNE1 and the second contact electrode CNE2 on the layer may be swapped with each other. In addition, in an embodiment, the first electrode ELT1 and the second electrode ELT2 may be selectively omitted. Figure 7a and Figure 7b At least one of the components shown in FIG. 1 , or other additional components may be provided in each pixel PXL.

[0125] The substrate SUB may form a display panel (eg, Figure 4 The substrate SUB may be a substrate of a PNL and may be a rigid substrate or a flexible substrate. In addition, the substrate SUB may be a transparent substrate, but is not limited thereto. In other words, in the present disclosure, the material or properties of the substrate SUB are not particularly limited. The buffer layer BFL may be disposed on one surface of the substrate SUB.

[0126] The buffer layer BFL may prevent impurities from diffusing into electrodes, wires, and / or circuit elements disposed on the buffer layer BFL. In an embodiment, the buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having two or more layers. In the case where the buffer layer BFL has a multilayer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted. The buffer layer BFL may be selectively formed on one surface of the substrate SUB. The first partition wall PW1 and the second partition wall PW2 may be disposed on one surface of the substrate SUB on which the buffer layer BFL is formed.

[0127] The first partition wall PW1 and the second partition wall PW2 may be disposed on one surface of the substrate SUB at positions spaced apart from each other. For example, the first partition wall PW1 and the second partition wall PW2 may be disposed on the same layer on the substrate SUB at positions spaced apart from each other by a predetermined distance. However, the present disclosure is not limited thereto, and the positions of the first partition wall PW1 and the second partition wall PW2 on the layer may be changed.

[0128] In an embodiment, the first partition wall PW1 may be disposed between the substrate SUB and a region of the first electrode ELT1. The second partition wall PW2 may be disposed between the substrate SUB and a region of the second electrode ELT2. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same structure, shape and / or height, but the present disclosure is not limited thereto.

[0129] Each of the first partition wall PW1 and the second partition wall PW2 may have various shapes. Figure 7a As shown in , each of the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-sectional shape whose width decreases from the bottom to the top thereof. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side thereof. In an embodiment, as Figure 7b As shown in , each of the first partition wall PW1 and the second partition wall PW2 may have a semicircular or semi-elliptical cross-section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side thereof. In other words, the shape of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited. In an embodiment, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted or the position of at least one of the first partition wall PW1 and the second partition wall PW2 may be changed.

[0130] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material having an inorganic material or an organic material. In addition, each of the first partition wall PW1 and the second partition wall PW2 may have a single-layer structure or a multi-layer structure. In other words, the material and / or stacking structure of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited.

[0131] In an embodiment of the present disclosure, each of the first partition wall PW1 and the second partition wall PW2 may also be used as a reflective member. For example, the first partition wall PW1 and the second partition wall PW2 together with the first electrode ELT1 and the second electrode ELT2 disposed on the first partition wall PW1 and the second partition wall PW2 may be used as a reflective member for enhancing the efficiency of light emitted from each light emitting diode LD.

[0132] The first electrode ELT1 and the first contact electrode CNE1 may be disposed on the first partition wall PW1. The second electrode ELT2 and the second contact electrode CNE2 may be disposed on the second partition wall PW2. In an embodiment of the present disclosure, at least one insulating layer may be interposed between the first partition wall PW1 and the first electrode ELT1 and / or between the second partition wall PW2 and the second electrode ELT2. For example, the first insulating layer INS1 may be interposed between the second partition wall PW2 and the second electrode ELT2. In an embodiment, at least one electrode and / or insulating layer disposed on each of the first partition wall PW1 and the second partition wall PW2 may have a shape corresponding to the shape of a corresponding one of the first partition wall PW1 and the second partition wall PW2.

[0133] In detail, the first electrode ELT1 may be disposed on one surface of the substrate SUB on which the first partition wall PW1 and the second partition wall PW2 are formed. In an implementation, the first electrode ELT1 may be any one pixel electrode, for example, one of an anode electrode and a cathode electrode.

[0134] In an implementation, the first electrode ELT1 may be disposed on at least one region of the first partition wall PW1. For example, the first electrode ELT1 may be disposed on the first partition wall PW1 to completely cover the first partition wall PW1.

[0135] The first electrode ELT1 may have a shape corresponding to that of the first partition wall PW1. For example, the first electrode ELT1 may have an inclined surface or a curved surface corresponding to the shape of the first partition wall PW1. In an embodiment, the first partition wall PW1 may not be provided in the pixel PXL. In this case, the first electrode ELT1 may have a substantially flat shape.

[0136] In an embodiment, the first electrode ELT1 may include various conductive materials. For example, the first electrode ELT1 may have at least one reflective electrode layer, but the present disclosure is not limited thereto.

[0137] For example, the first electrode ELT1 may include a conductive material having a predetermined reflectivity. For example, the first electrode ELT1 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or an alloy thereof), a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)), and a conductive polymer (such as PEDOT), but the present disclosure is not limited thereto. In other words, the material used to form the first electrode ELT1 is not particularly limited, and the first electrode ELT1 may include various well-known electrode materials.

[0138] In addition, the first electrode ELT1 can be configured by a single layer or multiple layers, and its stacking structure is not limited. For example, the first electrode ELT1 can have a multilayer structure including at least one reflective electrode layer and at least one conductive capping layer. In addition, the first electrode ELT1 can also selectively include at least one transparent electrode layer.

[0139] For example, the first electrode ELT1 may include at least one reflective electrode layer, at least one transparent electrode layer disposed above and / or below the reflective electrode layer, and at least one conductive capping layer configured to cover the upper portion of the reflective electrode layer and / or the transparent electrode layer. In an embodiment, the reflective electrode layer may be formed of various conductive materials (e.g., Ag) having reflectivity, and its constituent materials are not particularly limited. In the case where the first electrode ELT1 includes a reflective electrode layer, the first electrode ELT1 may enable light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting diodes LD to travel in the direction of displaying an image (e.g., the front direction). Specifically, if the first electrode ELT1 has an inclination corresponding to the shape of the first partition wall PW1, the light emitted from the first end EP1 of each light emitting diode LD may be reflected by the first electrode ELT1 and travel more efficiently in the front direction. Therefore, the efficiency of the light emitted from the light emitting diode LD may be improved.

[0140] In addition, if the first electrode ELT1 has a multilayer structure including at least one transparent electrode layer disposed above and / or below the reflective electrode layer, the voltage drop caused by the signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light emitting diode LD. In an embodiment, the transparent electrode layer can be formed of various transparent conductive materials including ITO, and its constituent materials are not particularly limited.

[0141] In addition, if the first electrode ELT1 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first electrode ELT1 can be prevented from being damaged due to defects caused during the process of manufacturing the pixel PXL. However, the conductive capping layer may be selectively included in the first electrode ELT1, and the conductive capping layer may be omitted in some embodiments. In addition, the conductive capping layer may be considered as a component of the first electrode ELT1 or a separate component disposed on the first electrode ELT1.

[0142] The first insulating layer INS1 may be disposed on the substrate SUB on which the first electrode ELT1 is formed. For example, the first insulating layer INS1 may be disposed on the substrate SUB to cover at least one region of the first electrode ELT1. In an embodiment, the first insulating layer INS1 may be disposed on the second partition wall PW2 such that a region of the first insulating layer INS1 is interposed between the second partition wall PW2 and the second electrode ELT2, but the present disclosure is not limited thereto. For example, in an embodiment, the first insulating layer INS1 may be disposed under the second partition wall PW2 such that the first insulating layer INS1 is interposed between the substrate SUB and the second partition wall PW2.

[0143] The first insulating layer INS1 may have a single-layer structure or a multi-layer structure including at least one organic layer and / or inorganic layer, and may be formed of various known insulating materials. For example, the first insulating layer INS1 may include SiN x At least one inorganic layer is formed, but the present disclosure is not limited thereto. In other words, the first insulating layer INS1 may include various known insulating materials.

[0144] In an implementation, the first insulating layer INS1 may include an opening exposing one region of the first electrode ELT1. For example, the first insulating layer INS1 may have an opening corresponding to the predetermined first contact portion CNT1.

[0145] The second electrode ELT2 may be disposed on a substrate SUB on which a first insulating layer INS1 is formed. In an embodiment, the second electrode ELT2 may be any one pixel electrode, for example, one of an anode electrode and a cathode electrode. For example, if the first electrode ELT1 may be an anode electrode, the second electrode ELT2 may be a cathode electrode. Conversely, if the first electrode ELT1 may be a cathode electrode, the second electrode ELT2 may be an anode electrode.

[0146] The second electrode ELT2 may be disposed on the first insulating layer INS1 at a position spaced apart from the first electrode ELT1. In other words, the second electrode ELT2 may be disposed on a layer different from that of the first electrode ELT1 with the first insulating layer INS1 interposed therebetween.

[0147] In addition, the second electrode ELT2 may be disposed on at least one region of the second partition wall PW2. For example, the second electrode ELT2 may be disposed on the second partition wall PW2 to completely cover the second partition wall PW2.

[0148] The second electrode ELT2 may have a shape corresponding to the shape of the second partition wall PW2. For example, the second electrode ELT2 may have an inclined surface or a curved surface corresponding to the shape of the second partition wall PW2. In an embodiment, the second partition wall PW2 may not be provided in the pixel PXL. In this case, the second electrode ELT2 may have a substantially flat shape.

[0149] In an embodiment, the second electrode ELT2 may have various conductive materials. For example, the second electrode ELT2 may have at least one reflective electrode layer, but the present disclosure is not limited thereto.

[0150] For example, the second electrode ELT2 may include a conductive material having a predetermined reflectivity. For example, the second electrode ELT2 may include at least one of a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or an alloy thereof), a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO)) and a conductive polymer (such as PEDOT), but the present disclosure is not limited thereto. In other words, the material used to form the second electrode ELT2 is not particularly limited, and the second electrode ELT2 may have various well-known electrode materials. In addition, the second electrode ELT2 may include the same conductive material as the conductive material of the first electrode ELT1, or include a conductive material different from the conductive material of the first electrode ELT1.

[0151] In addition, the second electrode ELT2 can be configured by a single layer or multiple layers, and its stacking structure is not limited. For example, the second electrode ELT2 can have a multilayer structure including at least one reflective electrode layer and at least one conductive capping layer. In addition, the second electrode ELT2 can also selectively include at least one transparent electrode layer.

[0152] For example, the second electrode ELT2 may include at least one reflective electrode layer, at least one transparent electrode layer disposed above and / or below the reflective electrode layer, and at least one conductive capping layer configured to cover the upper portion of the reflective electrode layer and / or the transparent electrode layer. In an embodiment, the reflective electrode layer may be formed of various conductive materials (e.g., Ag) having reflectivity, and its constituent materials are not particularly limited.

[0153] In the case where the second electrode ELT2 includes a reflective electrode layer, the second electrode ELT2 can enable light emitted from opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting diodes LD to travel in a direction (e.g., a front direction) in which an image is displayed. Specifically, if the second electrode ELT2 has an inclination corresponding to the shape of the second partition wall PW2, light emitted from the second end EP2 of each light emitting diode LD can be reflected by the second electrode ELT2 and travel more efficiently in the front direction. Therefore, the efficiency of light emitted from the light emitting diode LD can be improved.

[0154] In addition, if the second electrode ELT2 has a multilayer structure including at least one transparent electrode layer disposed above and / or below the reflective electrode layer, the voltage drop caused by the signal delay (RC delay) can be minimized. Therefore, the desired voltage can be effectively transmitted to the light emitting diode LD. In an embodiment, the transparent electrode layer can be formed of various transparent conductive materials including ITO, and its constituent materials are not particularly limited.

[0155] In addition, if the second electrode ELT2 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the second electrode ELT2 can be prevented from being damaged due to defects caused during the process of manufacturing the pixel PXL. However, the conductive capping layer may be selectively included in the second electrode ELT2, and the conductive capping layer may be omitted in some embodiments. In addition, the conductive capping layer may be considered as a component of the second electrode ELT2 or a separate component disposed on the second electrode ELT2.

[0156] At least one light emitting diode LD may be disposed on the substrate SUB on which the second electrode ELT2 is formed. For example, a plurality of light emitting diodes LD may be disposed in each pixel region in which each pixel PXL is formed.

[0157] In an embodiment, the light emitting diode LD may be arranged between the first electrode ELT1 and the second electrode ELT2 in a horizontal direction in a plan view (e.g., when viewed from above the substrate SUB). For example, each light emitting diode LD may have a first end EP1 and a second end EP2 on opposite sides relative to a longitudinal direction thereof. The first end EP1 of the light emitting diode LD may be disposed to face the first electrode ELT1, and the second end EP2 of the light emitting diode LD may be disposed to face the second electrode ELT2.

[0158] The second contact electrode CNE2 may be disposed on the substrate SUB on which the light emitting diode LD is disposed. For example, the second contact electrode CNE2 may be disposed to cover the second end EP2 of the light emitting diode LD and at least one region of the second electrode ELT2.

[0159] For example, the second contact electrode CNE2 may be disposed on the light emitting diode LD and the second electrode ELT2 so that the second contact electrode CNE2 is in direct contact with the second end EP2 of the light emitting diode LD and at least one region of the second electrode ELT2. For example, one region of the second contact electrode CNE2 may be disposed on the second end EP2 of the light emitting diode LD and thus in contact with the second end EP2. Another region of the second contact electrode CNE2 may be disposed on the second electrode ELT2 in the second contact portion CNT2 and thus in direct contact with the second electrode ELT2. The second contact electrode CNE2 may stably support the second end EP2 of the light emitting diode LD and electrically connect the second end EP2 to the second electrode ELT2.

[0160] In an embodiment, the second contact electrode CNE2 may be substantially transparent or translucent. For example, the second contact electrode CNE2 may be formed of a transparent conductive material including ITO or IZO, and may also be made of various known transparent conductive materials. Therefore, light generated from each light emitting diode LD may be emitted from the light emitting diode LD through the second contact electrode CNE2.

[0161] The second insulating layer INS2 may be disposed on the substrate SUB on which the second contact electrode CNE2 is formed. For example, the second insulating layer INS2 may be disposed on the second contact electrode CNE2 to at least cover the second contact electrode CNE2. One end of the second insulating layer INS2 may be interposed between the first contact electrode CNE1 and the second contact electrode CNE2. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 may be reliably separated from each other, so that the electrical stability between the first contact electrode CNE1 and the second contact electrode CNE2 may be ensured. In other words, a short circuit defect between the first contact electrode CNE1 and the second contact electrode CNE2 may be prevented by the second insulating layer INS2.

[0162] In an embodiment, the second insulating layer INS2 may have a single-layer structure or a multi-layer structure including at least one organic layer and / or inorganic layer, and may be formed of various known insulating materials. For example, the second insulating layer INS2 may include SiN x At least one inorganic layer is formed, but the present disclosure is not limited thereto. In other words, the second insulating layer INS2 may include various known insulating materials. In addition, the second insulating layer INS2 may include the same insulating material as the insulating material of the first insulating layer INS1, or may include an insulating material different from the insulating material of the first insulating layer INS1.

[0163] In the case where there is a space between the first insulating layer INS1 and the light emitting diode LD, the space may be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the light emitting diode LD may be supported more stably. In addition, in the case where the first insulating layer INS1 and the second insulating layer INS2 are formed of the same material, the first insulating layer INS1 and the second insulating layer INS2 may form an integral insulating layer instead of being divided into separate insulating layers under the light emitting diode LD.

[0164] The first contact electrode CNE1 may be disposed on the substrate SUB on which the second insulating layer INS2 is formed. For example, the first contact electrode CNE1 may be disposed to cover the first end EP1 of the light emitting diode LD and at least one region of the first electrode ELT1.

[0165] For example, the first contact electrode CNE1 may be disposed on the light emitting diode LD and the first electrode ELT1 so that the first contact electrode CNE1 is in direct contact with the first end EP1 of the light emitting diode LD and at least one region of the first electrode ELT1. For example, one region of the first contact electrode CNE1 may be disposed on the first end EP1 of the light emitting diode LD and in contact with the first end EP1. Another region of the first contact electrode CNE1 may be disposed on the first electrode ELT1 exposed through the opening of the first insulating layer INS1 and in direct contact with the first electrode ELT1. The first contact electrode CNE1 may stably support the first end EP1 of the light emitting diode LD and electrically connect the first end EP1 to the first electrode ELT1.

[0166] In an embodiment, the first contact electrode CNE1 may be substantially transparent or translucent. For example, the first contact electrode CNE1 may be formed of a transparent conductive material including ITO or IZO, and may also be made of various known transparent conductive materials. Thus, light generated from each light emitting diode LD may be emitted from the light emitting diode LD through the first contact electrode CNE1. In addition, the first contact electrode CNE1 may include a conductive material that is the same as that of the second contact electrode CNE2, or include a conductive material that is different from that of the second contact electrode CNE2.

[0167] At least one insulating layer may be disposed on the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed. For example, one surface of the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed may be covered with at least one insulating layer. In an embodiment, the at least one insulating layer may include an encapsulation layer ENC (or an overcoat layer).

[0168] The encapsulation layer ENC may be formed of a single layer or multiple layers. For example, the encapsulation layer ENC may be a thin film encapsulation layer including a plurality of inorganic insulating layers overlapping each other and at least one organic insulating layer interposed between the inorganic insulating layers. However, the constituent material and / or cross-sectional structure of the encapsulation layer ENC are not particularly limited and may be changed in various ways. In an embodiment, the encapsulation layer ENC may be formed to cover at least the display area (e.g., Figure 4 In an embodiment, not only an encapsulation layer ENC but also at least one passivation layer, an optical layer, etc. may be disposed on one surface of the substrate SUB on which the light emitting diode LD, etc. is disposed.

[0169] As described above, in the embodiment of the present disclosure, the first electrode ELT1 and the second electrode ELT2 are respectively disposed on different layers separated from each other on the substrate SUB, and the first insulating layer INS1 is interposed between the first electrode ELT1 and the second electrode ELT2. In this way, if the first electrode ELT1 and the second electrode ELT2 are respectively disposed on different layers, a short circuit defect between the first electrode ELT1 and the second electrode ELT2 can be effectively prevented from occurring in the process of manufacturing the pixel PXL (or the light emitting device).

[0170] In addition, as described in the aforementioned embodiment, if the first electrode ELT1 and the second electrode ELT2 are respectively disposed on different layers, the distance between the first electrode ELT1 and the second electrode ELT2 can be further reduced compared to the distance between the first electrode ELT1 and the second electrode ELT2 of the pixel of other embodiments (or the light-emitting device of other embodiments) in which the first electrode ELT1 and the second electrode ELT2 are formed on the same layer, and the distance between the first electrode ELT1 and the second electrode ELT2 can be set in consideration of process margin, etc. If the distance between the first electrode ELT1 and the second electrode ELT2 is reduced, a stronger electric field can be formed between the first electrode ELT1 and the second electrode ELT2 even when the voltage applied to the first electrode ELT1 and the second electrode ELT2 is the same as that of the aforementioned embodiment. Therefore, the light-emitting diode LD can be effectively aligned between the first electrode ELT1 and the second electrode ELT2, and the quality of the alignment can be improved.

[0171] In other words, according to the aforementioned embodiment, at least one light emitting diode LD may be reliably disposed between the first electrode ELT1 and the second electrode ELT2 , and a short circuit defect between the first electrode ELT1 and the second electrode ELT2 may be effectively prevented or mitigated.

[0172] Figure 8is a plan view showing a light emitting device according to an embodiment of the present disclosure, and shows, for example, an example of a pixel PXL including the light emitting device. Figure 9a and Figure 9b Each is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a cross-sectional view corresponding to Figure 8 Different embodiments of the cross section along line II-II'.

[0173] In an embodiment, Figures 8 to 9b A light-emitting device (e.g., a pixel PXL of an active light-emitting display device) is shown in which the first electrode ELT1 and / or the second electrode ELT2 are connected to the first power line PL1 and the second power line PL2 respectively through at least one contact hole, or the first electrode ELT1 and / or the second electrode ELT2 are connected to the first power line PL1 or the second power line PL2 via at least one circuit element (including at least one transistor in the pixel circuit PXC).

[0174] In an embodiment, Figure 8 The light source unit LSU shown in FIG. 1 may have the same configuration as that according to the above-mentioned embodiments (eg, Figure 6 The configuration of the light emitting device (or pixel PXL) of the embodiment shown in FIG. 1 is substantially similar or identical to that of the embodiment shown in FIG. Figure 9a and Figure 9b The display element layer LDL shown in FIG. 1 may have a Figure 7a and Figure 7b The cross-section of the light emitting device (or pixel PXL) of the embodiment shown in FIG. is substantially similar or identical to the cross-section of FIG. Figures 8 to 9b In the following description of the embodiments of the present invention, the same reference numerals are used to represent Figure 6 to Figure 7b The components of the embodiments are the same or similar components, and their detailed description will be omitted.

[0175] Reference Figures 4 to 9b Each pixel PXL may include a display element layer LDL including a first electrode ELT1, a second electrode ELT2, at least one light emitting diode LD, etc., and a circuit element layer PCL disposed under the display element layer LDL. For example, the circuit element layer PCL may be disposed between the substrate SUB and the display element layer LDL.

[0176] In an embodiment, the circuit element layer PCL may include a plurality of circuit elements disposed in the display area DA. For example, the circuit element layer PCL may include a plurality of circuit elements disposed in each pixel region to form each pixel circuit PXC. In other words, in an embodiment, the circuit element layer PCL may be a pixel circuit layer.

[0177] For example, the circuit element layer PCL may include a plurality of transistors (eg, Figure 5a and Figure 5b a first transistor T1 and a second transistor T2) and at least one capacitor (eg, Figure 5a and Figure 5b In addition, the circuit element layer PCL may further include at least one scan line Si, a data line Dj, a first power line PL1 and / or a second power line PL2.

[0178] In an embodiment, a plurality of transistors (e.g., a first transistor T1 and a second transistor T2) provided in each pixel circuit PXC may have substantially the same or similar cross-sectional structures. However, the present disclosure is not limited thereto. In an embodiment, at least some of the plurality of transistors may have different types and / or structures.

[0179] In addition, the circuit element layer PCL may include a plurality of insulating layers. For example, the circuit element layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the substrate SUB.

[0180] In an embodiment, the buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having two or more layers. In the case where the buffer layer BFL has a multilayer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0181] In an embodiment, each of the first transistor T1 and the second transistor T2 may include a semiconductor layer SCL, a gate electrode GE, a first transistor electrode ET1, and a second transistor electrode ET2. Figure 9a and Figure 9b An embodiment in which each of the first transistor T1 and the second transistor T2 includes a first transistor electrode ET1 and a second transistor electrode ET2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, the first transistor electrode ET1 and / or the second transistor electrode ET2 provided in at least one transistor forming each pixel circuit PXC may be formed integrally with the corresponding semiconductor layer SCL.

[0182] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the substrate SUB on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with the first transistor electrode ET1, a second region in contact with the second transistor electrode ET2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0183] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor of an undoped semiconductor pattern. Each of the first and second regions of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0184] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one region of the semiconductor layer SCL.

[0185] The first transistor electrode ET1 and the second transistor electrode ET2 may be disposed on the semiconductor layer SCL and the gate electrode GE with at least one interlayer insulating layer ILD interposed therebetween. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be disposed between the interlayer insulating layer ILD and the passivation layer PSV. The first transistor electrode ET1 and the second transistor electrode ET2 may be electrically connected to the semiconductor layer SCL. For example, the first transistor electrode ET1 and the second transistor electrode ET2 may be connected to the first region and the second region of the semiconductor layer SCL respectively through corresponding contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0186] In an embodiment, at least one transistor (eg, Figure 5a and Figure 5b Any one of the first transistor electrode ET1 and the second transistor electrode ET2 of the first transistor T1 of the passivation layer may be electrically connected to the first electrode ELT1 of the light source unit LSU disposed on the passivation layer PSV through the first contact hole CH1 passing through the passivation layer PSV.

[0187] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be disposed on the same layer as the layer of one electrode of each of the circuit elements forming the pixel circuit PXC. For example, a second power line PL2 for providing a second power source VSS may be disposed on the same layer as the layer of the gate electrode GE of the first transistor T1 and the second transistor T2, and may be electrically connected to the second electrode ELT2 of the light source unit LSU disposed on the passivation layer PSV through both a bridge pattern BRP disposed on the same layer as the first transistor electrode ET1 and the second transistor electrode ET2 and through at least one second contact hole CH2 passing through the passivation layer PSV. However, the structure and / or position of the second power line PL2 may be changed in various ways.

[0188] The display element layer LDL may be a layer on which the light source unit LSU of each pixel PXL is disposed, and may be, for example, disposed in the same manner as the reference Figure 6 to Figure 7b The light emitting device of the pixel PXL described above is configured in the same manner. For example, the display element layer LDL may include at least one pair of first electrodes ELT1 and second electrodes ELT2 arranged in each pixel region above the circuit element layer PCL and at least one light emitting diode LD electrically connected between the first electrode ELT1 and the second electrode ELT2. For example, the display element layer LDL may include a plurality of light emitting diodes LD, which are arranged above the circuit element layer PCL in each pixel region and configure each light source unit LSU. In addition, the display element layer LDL may further include, for example, at least one insulating layer (or insulating pattern) and / or electrode. For example, the display element layer LDL may also include reference Figure 6 to Figure 7b At least one of the first and second partition walls PW1 and PW2 , the first and second insulating layers INS1 and INS2 , the first and second contact electrodes CNE1 and CNE2 , and the encapsulation layer ENC is described.

[0189] In the above embodiment, the light source unit LSU of each pixel PXL may be configured by a light emitting device including at least one light emitting diode LD. Since the light emitting device according to the embodiment of the present disclosure has been described above, a detailed description of each light source unit LSU corresponding to the light emitting device and a display element layer LDL for configuring the light source unit LSU will be omitted.

[0190] In an embodiment, at least one first circuit element and / or line provided in the circuit element layer PCL may overlap with the first electrode ELT1 and / or the second electrode ELT2 of the display element layer LDL. For example, the first transistor T1 may overlap with a region of the first electrode ELT1 (or the first connection electrode CNL1) and be electrically connected to the first electrode ELT1 through the first contact hole CH1. Alternatively, in an embodiment, in the case where the first electrode ELT1 is directly connected to the first power line PL1, a region of the first power line PL1 may overlap with the first electrode ELT1 and may be electrically connected to the first electrode ELT1 through at least one contact hole.

[0191] In an embodiment, the second power line PL2 may overlap with a region of the second electrode ELT2 (or the second connection electrode CNL2) and may be electrically connected to the second electrode ELT2 through a second contact hole CH2. In an embodiment, the second electrode ELT2 may be connected to the second power line PL2 via at least one second circuit element. In this case, the second circuit element may overlap with a region of the second electrode ELT2 (or the second connection electrode CNL2) and may be electrically connected to the second electrode ELT2 through at least one contact hole.

[0192] In an embodiment, a first circuit element electrically connected to the first electrode ELT1 or a region of the first power line PL1 may overlap with the second electrode ELT2. Here, the first circuit element or the first power line PL1 may be physically separated and / or electrically disconnected from the second electrode ELT2 by at least one insulating layer (e.g., at least the passivation layer PSV). Similarly, a second circuit element electrically connected to the second electrode ELT2 or a region of the second power line PL2 may overlap with the first electrode ELT1. Here, the second circuit element or the second power line PL2 may be physically separated and / or electrically disconnected from the first electrode ELT1 by at least one insulating layer. In this way, if the circuit element layer PCL and the display element layer LDL are arranged to overlap each other, the limited pixel area can be used more effectively.

[0193] Figures 10a to 10k is a cross-sectional view showing a method of manufacturing a light emitting device according to an embodiment of the present disclosure, and for example shows a method of manufacturing a light emitting device according to Figure 9a A method for a light emitting device of an embodiment of the present invention.

[0194] Reference Fig.10a as well as Figure 9a, a circuit element layer PCL is formed on one surface of the substrate SUB, and a first partition wall PW1 and a second partition wall PW2 are formed at positions spaced apart from each other on the substrate SUB on which the circuit element layer PCL is formed. In addition, a first contact hole CH1 is formed to connect a first circuit element (e.g., a first transistor T1) of the circuit element layer PCL with any one electrode (e.g., a first electrode ELT1) of the display element layer LDL. In some embodiments, in the case where the circuit element layer PCL is omitted, the first partition wall PW1 and the second partition wall PW2 may be formed directly on one surface of the substrate SUB (or a substrate SUB on which a buffer layer BFL is formed).

[0195] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be formed by a process of forming an insulating layer including an inorganic material and / or an organic material and / or a patterning process (e.g., a photolithography process), and may be formed by various types of known processes. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be simultaneously formed on the same layer (or the same plane) on the substrate SUB using the same material, but the present disclosure is not limited thereto.

[0196] Reference Fig.10b Here, in some embodiments, the first electrode ELT1 may be directly formed on one surface of the substrate SUB (or the substrate SUB having the buffer layer BFL formed thereon) without omitting the circuit element layer PCL and / or the first partition wall PW1.

[0197] In an embodiment, the first electrode ELT1 may be formed by a process and / or a patterning process of forming a conductive layer including at least one conductive material, and may be formed by various types of known processes. In an embodiment, the first electrode ELT1 may be formed of a single layer or multiple layers. For example, the first electrode ELT1 may be formed of a conductive pattern having a single-layer structure, or may be formed of a conductive pattern having a multi-layer structure including a first reflective electrode and a first conductive capping layer.

[0198] Reference Fig.10c , a first insulating layer INS1 is formed on the substrate SUB including the first electrode ELT1. In an embodiment, the first insulating layer INS1 may be formed on one surface of the substrate SUB to cover at least the first electrode ELT1. For example, the first insulating layer INS1 may be formed in the entire region of each pixel region.

[0199] In an embodiment, the first insulating layer INS1 may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. In an embodiment, the first insulating layer INS1 may be formed of a single layer or multiple layers.

[0200] refer to Fig.10d A second contact hole CH2 is formed on the substrate SUB having the first insulating layer INS1 formed thereon. For example, the second contact hole CH2 may be formed to expose the second power line PL2 or a bridge pattern BRP connected to the second power line PL2.

[0201] Reference Fig.10e , a second electrode ELT2 is formed on the first insulating layer INS1 including an opening corresponding to the second contact hole CH2. In an embodiment, the second electrode ELT2 may be formed on the second partition wall PW2 and the second contact hole CH2. In addition, the second electrode ELT2 may be formed at a position spaced apart from the first electrode ELT1 by a predetermined distance so as not to overlap with the first electrode ELT1.

[0202] In an embodiment, the second electrode ELT2 may be formed by a process and / or a patterning process of forming a conductive layer including at least one conductive material, and may be formed by various types of known processes. In an embodiment, the second electrode ELT2 may be formed of a single layer or multiple layers. For example, the second electrode ELT2 may be formed of a conductive pattern having a single-layer structure, or may be formed of a conductive pattern having a multi-layer structure including a second reflective electrode and a second conductive capping layer.

[0203] refer to Fig.10f , at least one light emitting diode LD is provided on a substrate SUB including a first electrode ELT1, a second electrode ELT2, etc., and the light emitting diode LD is aligned between the first electrode ELT1 and the second electrode ELT2. For example, a plurality of light emitting diodes LD are provided to each pixel region including the first electrode ELT1 and the second electrode ELT2, and the light emitting diodes LD can be aligned by applying a predetermined voltage (e.g., an AC voltage) to the first electrode ELT1 and the second electrode ELT2.

[0204] In an embodiment, the light emitting diode LD may be provided to a predetermined emission region (e.g., an emission region of each pixel PXL) by applying a solution in which a plurality of light emitting diodes LD are dispersed to the substrate SUB using an inkjet printing method, a slit coating method, or the like. However, the method of providing the light emitting diode LD is not limited to the above method, and the light emitting diode LD may be provided to an area of ​​the substrate SUB in various other ways. In an embodiment, an electric field may be formed by applying an AC voltage between the first electrode ELT1 and the second electrode ELT2, but the type of voltage or signal applied between the first electrode ELT1 and the second electrode ELT2 is not limited thereto.

[0205] In an embodiment, each light emitting diode LD may be aligned between the first electrode ELT1 and the second electrode ELT2 in the horizontal direction. For example, the first end EP1 of each of the light emitting diodes LD may be disposed to face the first electrode ELT1. The second end EP2 of each of the light emitting diodes LD may be disposed to face the second electrode ELT2.

[0206] Reference Figure 10g , a second contact electrode CNE2 is formed on a substrate SUB on which at least one light emitting diode LD is disposed. For example, in order to cover the second end EP2 of the light emitting diode LD and a region of the second electrode ELT2 (e.g., a predetermined second contact portion CNT2), the second contact electrode CNE2 may be formed on the second end EP2 of the light emitting diode LD and at least one region of the second electrode ELT2. The second end EP2 of the light emitting diode LD may be electrically connected to the second electrode ELT2 through the second contact electrode CNE2.

[0207] In an embodiment, the second contact electrode CNE2 may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes. In an embodiment, the second contact electrode CNE2 may be formed to be substantially transparent using at least one transparent electrode material.

[0208] Reference Fig.10h , a second insulating layer INS2 is formed on the substrate SUB including the second contact electrode CNE2. For example, the second insulating layer INS2 may be formed on one surface of the substrate SUB to cover at least the second contact electrode CNE2. In an embodiment, in the case where there is a space between the first insulating layer INS1 and the light emitting diode LD in the previous process steps, an insulating material for forming the second insulating layer INS2 may be introduced into the space during the process of forming the second insulating layer INS2, so that the space may be filled with the insulating material.

[0209] In an implementation, the second insulating layer INS2 may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. The second insulating layer INS2 may be formed of a single layer or multiple layers.

[0210] Reference Fig.10i , an opening OPN may be formed in the first insulating layer INS1 and the second insulating layer INS2 by etching the first insulating layer INS1 and the second insulating layer INS2 so that a region of the first electrode ELT1 (e.g., a predetermined first contact portion CNT1) and the first end EP1 of the light emitting diode LD are exposed. The first contact portion CNT1 is formed on the first electrode ELT1. In an embodiment, the first contact portion CNT1 may be formed by a photolithography process or the like, but the present disclosure is not limited thereto.

[0211] Reference Fig.10j A first contact electrode CNE1 is formed on both at least one region of the first electrode ELT1 including the first contact portion CNT1 and the first end EP1 of the light emitting diode LD. The first end EP1 of the light emitting diode LD may be electrically connected to the first electrode ELT1 through the first contact electrode CNE1.

[0212] In an embodiment, the first contact electrode CNE1 may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes. In an embodiment, the first contact electrode CNE1 may be formed to be substantially transparent using at least one transparent electrode material.

[0213] Reference Figure 10k An encapsulation layer ENC (or an overcoat layer, etc.) is formed on one surface of the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed.

[0214] In an embodiment, the encapsulation layer ENC may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. The encapsulation layer ENC may be formed of a single layer or multiple layers. In an embodiment, instead of the encapsulation layer ENC, at least one other passivation layer and / or an encapsulation substrate may be formed on one surface of the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed.

[0215] Through the above process, a light emitting device according to an embodiment of the present disclosure can be manufactured. For example, a light emitting device including Figure 8 and Figure 9a The pixel PXL is shown in the display panel PNL.

[0216] Fig.11 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a light emitting device corresponding to Figure 8 In an embodiment, Fig.11 The diagram shows the positions of the first electrode ELT1 and the second electrode ELT2 on the layer and the positions of the first contact electrode CNE1 and the second contact electrode CNE2 on the layer. Figure 9a In different implementations. Fig.11 In the description of the embodiments of the present invention, the same reference numerals are used to represent the same embodiments as those described above (for example, Figure 9a ) are similar or equivalent to the components of the embodiment, and their detailed description will be omitted.

[0217] Reference Figure 8 and Figure 9a as well as Fig.11 According to an embodiment, the positions (stack order) of the first electrode ELT1 and the second electrode ELT2 on the layer may be changed. For example, the second electrode ELT2 may be directly disposed on the second partition wall PW2, and the first insulating layer INS1 may be disposed to cover at least one region of the second electrode ELT2. The first electrode ELT1 may be disposed on the first insulating layer INS1 to overlap with the first partition wall PW1.

[0218] In an embodiment, the positions of the first electrode ELT1 and the second electrode ELT2 on the layer may be determined by considering the surface area where the first electrode ELT1 and the second electrode ELT2 overlap with the circuit elements and / or lines disposed thereunder. Figure 8 As shown in , in a case where the first electrode ELT1 overlaps a first surface area with a second power line PL2 (or at least one second circuit element) provided with a signal different from that of the first electrode ELT1, and the second electrode ELT2 overlaps a second surface area with a first power line PL1 (or a first circuit element, such as at least one transistor forming a pixel circuit PXC) provided with a signal different from that of the second electrode ELT2, the positions of the first electrode ELT1 and the second electrode ELT2 on the layer can be determined by comparing the size of the first surface area and the size of the second surface area.

[0219] For example, if the second surface area is greater than the first surface area, then Figure 9a As shown in , the second electrode ELT2 can be provided on a layer higher than the layer of the first electrode ELT1. On the contrary, if the first surface area is larger than the second surface area, then Fig.11As shown in , the first electrode ELT1 may be disposed on a higher layer than the second electrode ELT2. When the first surface area is substantially the same as the second surface area, the positions of the first electrode ELT1 and the second electrode ELT2 on the layer may be determined according to a predetermined order, process conditions, etc.

[0220] In other words, in the embodiment of the present disclosure, one of the first electrode ELT1 and the second electrode ELT2 can be arranged at a position farther from the circuit element layer PCL than the other electrode, and one of the first electrode ELT1 and the second electrode ELT2 is larger in overlapping area than the other electrode of the first electrode ELT1 and the second electrode ELT2, and the surface area is the area where the electrode overlaps with at least one circuit element or line arranged thereunder, arranged on the circuit element layer PCL and configured to be provided with different types of signals or power. Therefore, interlayer short circuit defects caused by penetration of foreign matter, etc. in the process steps can be effectively prevented.

[0221] In an embodiment, the positions (or stacking order) of the first contact electrode CNE1 and the second contact electrode CNE2 on the layer may be changed according to the embodiment. Figure 9a As shown in the embodiment of FIG. 1 , the second contact electrode CNE2 may be formed on the second electrode ELT2, and the second contact electrode CNE2 may be covered by the second insulating layer INS2, and then the first contact electrode CNE1 may be formed on the second insulating layer INS2. Alternatively, as Fig.11 As shown in the embodiment of the present invention, the first contact electrode CNE1 may be formed on the first electrode ELT1, and the first contact electrode CNE1 may be covered by the second insulating layer INS2, and then the second contact electrode CNE2 may be formed on the second insulating layer INS2. As a further alternative, in the embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed at the same time. In other words, in the present disclosure, the relative position between the first contact electrode CNE1 and the second contact electrode CNE2 and / or the order of formation thereof are not particularly limited and may be changed in various ways.

[0222] Fig.12 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a light emitting device corresponding to Figure 8 Embodiment of the cross section of line II-II'. Fig.12 In the description of the embodiments of the present invention, the same reference numerals are used to indicate at least one embodiment described above (for example, Figure 9a and Fig.11 ) are similar or equivalent to the components of the embodiment, and their detailed description will be omitted.

[0223] Reference Figure 9a and Fig.11 as well as Fig.12 , at least one additional insulating layer may be disposed on any one of the first electrode ELT1 and the second electrode ELT2 disposed at an upper position. For example, in the case where the second electrode ELT2 is disposed on a layer higher than that of the first electrode ELT1, a third insulating layer INS3 may be additionally disposed on the second electrode ELT2.

[0224] In an embodiment, the third insulating layer INS3 may include an opening corresponding to the second contact portion CNT2. In other words, the third insulating layer INS3 may be disposed on a region of the second electrode ELT2. For example, the third insulating layer INS3 may be disposed on a region of the second electrode ELT2 other than the second contact portion CNT2. A region of the third insulating layer INS3 may be disposed between the second end EP2 of the light emitting diode LD and an end of the second electrode ELT2 adjacent to the second end EP2. The third insulating layer INS3 may protect the second electrode ELT2 during subsequent processes. In an embodiment, the third insulating layer INS3 may prevent or reduce the electric field from being concentrated on any one of the first electrode ELT1 and the second electrode ELT2.

[0225] In an embodiment, after aligning at least one light emitting diode LD on the substrate SUB including the third insulating layer INS3, at least one insulating layer for stably supporting the light emitting diode LD may be further formed. For example, a fourth insulating layer INS4 may be further formed on the first and second electrodes ELT1 and ELT2 and a region of the light emitting diode LD.

[0226] In an embodiment, in the case where the first contact electrode CNE1 and the second contact electrode CNE2 are disposed on different layers, at least one insulating layer may be disposed between the first contact electrode CNE1 and the second contact electrode CNE2 so that electrical stability can be ensured. For example, in the case where the first contact electrode CNE1 is disposed on a layer lower than the second contact electrode CNE2, the fifth insulating layer INS5 may be formed to cover the first contact electrode CNE1. In an embodiment, one end of the fifth insulating layer INS5 may be interposed between the first contact electrode CNE1 and the second contact electrode CNE2.

[0227] Figures 13a to 13i is a cross-sectional view showing a method of manufacturing a light emitting device according to an embodiment of the present disclosure, and for example shows a method of manufacturing a light emitting device according to Fig.12 In the manufacturing method of the light emitting device according to the embodiment of the present invention, Fig.12 In the following description of the method of the light emitting device of the embodiment of the present invention, the mechanical and / or method configurations of the manufacturing method of the above-mentioned embodiment (for example, the configurations of the light emitting device of the embodiment of the present invention) will be omitted. Figures 10a to 10k Description Figure 9a A detailed description of mechanical and / or method configurations similar or equivalent to those of the method for manufacturing a light-emitting device.

[0228] refer to Fig.13a , a third insulating layer INS3 is formed on one surface of the substrate SUB on which the first electrode ELT1, the first insulating layer INS1, and the second electrode ELT2 are sequentially formed. In the embodiment, although the first electrode ELT1, the first insulating layer INS1, the second electrode ELT2, etc. are Figures 10a to 10e The manufacturing process described is formed, but the present disclosure is not limited thereto.

[0229] In an embodiment, a third insulating layer INS3 may be formed on one surface of the substrate SUB including the second electrode ELT2 to cover at least the second electrode ELT2. For example, the third insulating layer INS3 may be formed on the second electrode ELT2 by a photolithography process using a mask or the like.

[0230] In an embodiment, the third insulating layer INS3 may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. In an embodiment, the third insulating layer INS3 may be formed of a single layer or multiple layers.

[0231] refer to Fig.13b , at least one light emitting diode LD is provided on a substrate SUB including a first electrode ELT1 covered with a first insulating layer INS1, a second electrode ELT2 covered with a third insulating layer INS3, etc., and the light emitting diode LD is aligned between the first electrode ELT1 and the second electrode ELT2. For example, a plurality of light emitting diodes LD are provided to each pixel region including the first electrode ELT1 and the second electrode ELT2, and the light emitting diodes LD can be aligned by applying a predetermined voltage to the first electrode ELT1 and the second electrode ELT2.

[0232] refer to Fig.13c , a fourth insulating layer INS4 is formed on the substrate SUB on which at least one light emitting diode LD is disposed. In an embodiment, the fourth insulating layer INS4 may be formed in the entire region of each pixel region. In an embodiment, in the case where there is a space between the first insulating layer INS1 and the light emitting diode LD in the previous process steps, an insulating material for forming the fourth insulating layer INS4 may be introduced into the space during the process of forming the fourth insulating layer INS4, so that the space may be filled with the insulating material.

[0233] In an embodiment, the fourth insulating layer INS4 may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. In an embodiment, the fourth insulating layer INS4 may be formed of a single layer or multiple layers.

[0234] Reference Fig.13d A first opening OPN1 may be formed in the first insulating layer INS1 and the fourth insulating layer INS4 by etching the first insulating layer INS1 and the fourth insulating layer INS4 so that a region of the first electrode ELT1 and the first end EP1 of the light emitting diode LD are exposed. A first contact portion CNT1 may be formed on the first electrode ELT1.

[0235] Reference Fig.13e A first contact electrode CNE1 is formed on both at least one region of the first electrode ELT1 including the first contact portion CNT1 and the first end EP1 of the light emitting diode LD. The first end EP1 of the light emitting diode LD may be electrically connected to the first electrode ELT1 through the first contact electrode CNE1.

[0236] refer to Fig.13f , a fifth insulating layer INS5 is formed on the substrate SUB including the first contact electrode CNE1. In an implementation, the fifth insulating layer INS5 may be formed to cover the first contact electrode CNE1. For example, the fifth insulating layer INS5 may be formed in the entire region of each pixel region.

[0237] In an implementation, the fifth insulating layer INS5 may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. The fifth insulating layer INS5 may be formed of a single layer or multiple layers.

[0238] Reference Figure 13g A second opening OPN2 is formed in the third insulating layer INS3, the fourth insulating layer INS4, and the fifth insulating layer INS5 by etching the third insulating layer INS3, the fourth insulating layer INS4, and the fifth insulating layer INS5 so that a region of the second electrode ELT2 and the second end EP2 of the light emitting diode LD are exposed. A second contact portion CNT2 may be formed on the second electrode ELT2.

[0239] Reference Fig.13h A second contact electrode CNE2 is formed on both at least one region of the second electrode ELT2 including the second contact portion CNT2 and the second end EP2 of the light emitting diode LD. The second end EP2 of the light emitting diode LD may be electrically connected to the second electrode ELT2 through the second contact electrode CNE2.

[0240] Reference Fig.13i An encapsulation layer ENC (or an outer coating layer, etc.) is formed on one surface of the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed. In this way, the Fig.12 A light emitting device (or pixel PXL) of an embodiment.

[0241] Fig.14 is a cross-sectional view showing a light emitting device according to an embodiment of the present disclosure, and for example shows a light emitting device corresponding to Figure 8 An embodiment of a cross section of line II-II'. Figures 15a to 15e is a cross-sectional view showing a method of manufacturing a light emitting device according to an embodiment of the present disclosure, and for example shows a method of manufacturing a light emitting device according to Fig.14 A method for a light emitting device according to an embodiment of the present invention. Figure 14 to Figure 15e In the following description of the embodiments of the present invention, the descriptions related to at least one of the above embodiments (for example, Figures 9a to 10k Detailed description of mechanical and / or method configurations that are similar or equivalent to the mechanical and / or method configurations of the embodiments of the present invention.

[0242] Reference Figure 14 to Figure 15e In the embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed simultaneously by the same process. For example, the light emitting device according to the embodiment of the present disclosure may include a first partition wall PW1 and a second partition wall PW2, a first electrode ELT1, a first insulating layer INS1, a second electrode ELT2, at least one light emitting diode LD (for example, a plurality of light emitting diodes LD), a sixth insulating layer INS6, a first contact electrode CNE1 and a second contact electrode CNE2, and an encapsulation layer ENC sequentially disposed on a surface of a substrate SUB on which a buffer layer BFL and / or a circuit element layer PCL, etc. are formed.

[0243] In an embodiment, the sixth insulating layer INS6 may be partially disposed on the first electrode ELT1 / the second electrode ELT2 and one region of each light emitting diode LD. For example, the sixth insulating layer INS6 may be partially disposed on the first electrode ELT1 and the second electrode ELT2 to expose the first contact portion CNT1 and the second contact portion CNT2, respectively. In addition, the sixth insulating layer INS6 may be partially disposed on the light emitting diode LD to expose the first end EP1 and the second end EP2 of the light emitting diode LD. In an embodiment, in the case where there is a space between the first insulating layer INS1 and the light emitting diode LD, the space may be filled by the sixth insulating layer INS6 during the process of forming the sixth insulating layer INS6. Therefore, one region of the sixth insulating layer INS6 may also be disposed under the light emitting diode LD. In the case where the first insulating layer INS1 and the sixth insulating layer INS6 are formed of the same material, the first insulating layer INS1 and the sixth insulating layer INS6 may form an integral insulating layer, rather than being divided into separate insulating layers under the light emitting diode LD.

[0244] In an embodiment, one end of the first contact electrode CNE1 may be disposed on a region of the sixth insulating layer INS6 disposed on the light emitting diode LD. In addition, one end of the second contact electrode CNE2 may be disposed on a region of the sixth insulating layer INS6 located on the light emitting diode LD and may be disposed to face the first contact electrode CNE1.

[0245] In the following, reference will be made to Figures 15a to 15e Describe in more detail the manufacturing basis Fig.14 A method for a light emitting device of an embodiment of the present invention.

[0246] refer to Fig.15a , at least one light emitting diode LD is provided on one surface of the substrate SUB on which the first electrode ELT1, the first insulating layer INS1, the second electrode ELT2, etc. are sequentially formed, and the light emitting diode LD is aligned between the first electrode ELT1 and the second electrode ELT2. For example, a plurality of light emitting diodes LD are provided to each pixel region including the first electrode ELT1 and the second electrode ELT2, and the light emitting diodes LD can be aligned by applying a predetermined voltage to the first electrode ELT1 and the second electrode ELT2.

[0247] Reference Fig.15b, a sixth insulating layer INS6 is formed on the substrate SUB on which at least one light emitting diode LD is disposed. In an embodiment, the sixth insulating layer INS6 may be formed in the entire region of each pixel region. In an embodiment, in the case where there is a space between the first insulating layer INS1 and the light emitting diode LD in the previous process steps, during the process of forming the sixth insulating layer INS6, an insulating material for forming the sixth insulating layer INS6 may be introduced into the space so that the space may be filled with the insulating material.

[0248] In an embodiment, the sixth insulating layer INS6 may be formed by a deposition process of an insulating layer including an inorganic material and / or an organic material, and may be formed by various types of known processes. In an embodiment, the sixth insulating layer INS6 may be formed of a single layer or multiple layers.

[0249] Reference Fig.15c , a first opening OPN1 and a second opening OPN2 are formed in the first insulating layer INS1 and the sixth insulating layer INS6 by etching the first insulating layer INS1 and the sixth insulating layer INS6 so that one region of each of the first electrode ELT1 and the second electrode ELT2 and the first end EP1 and the second end EP2 of the light emitting diode LD are exposed. Therefore, a first contact portion CNT1 may be formed on the first electrode ELT1, and a second contact portion CNT2 may be formed on the second electrode ELT2.

[0250] Reference Fig.15d , a first contact electrode CNE1 is formed on at least one region of the first electrode ELT1 including the first contact portion CNT1 and the first end EP1 of the light emitting diode LD. A second contact electrode CNE2 is formed on at least one region of the second electrode ELT2 including the second contact portion CNT2 and the second end EP2 of the light emitting diode LD. In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed simultaneously.

[0251] Reference Fig.15e An encapsulation layer ENC (or an outer coating layer, etc.) is formed on one surface of the substrate SUB on which the first contact electrode CNE1 and the second contact electrode CNE2 are formed. In this way, the Fig.14 A light emitting device (or pixel PXL) of an embodiment.

[0252] In a light emitting device (e.g., a pixel PXL configured by or including the light emitting device), a method of manufacturing the light emitting device, and a display device including the light emitting device, a first electrode ELT1 and a second electrode ELT2 are formed on different layers separated from each other, and a first insulating layer INS1 is interposed between the first electrode ELT1 and the second electrode ELT2. In an embodiment of the present disclosure, one of the first electrode ELT1 and the second electrode ELT2 may be disposed on an upper layer, and one of the first electrode ELT1 and the second electrode ELT2 may be larger in overlapping area than the other of the first electrode ELT1 and the second electrode ELT2, and the surface area is an area where the electrode overlaps with at least one circuit element or line disposed thereunder and configured to be provided with different types of signals or power.

[0253] In the embodiment of the present disclosure, a short circuit defect between the first electrode ELT1 and the second electrode ELT2 can be effectively prevented. In addition, the process margin between the first electrode ELT1 and the second electrode ELT2 can be reduced so that the first electrode ELT1 and the second electrode ELT2 can be arranged closer to each other. Therefore, the light emitting diode LD can be more stably arranged between the first electrode ELT1 and the second electrode ELT2.

[0254] In the light emitting device according to the embodiment in which the first electrode ELT1 and the second electrode ELT2 are provided on the same layer, a short circuit defect between the first electrode ELT1 and the second electrode ELT2 may be caused by various factors. For example, if the distance between the first electrode ELT1 and the second electrode ELT2 is insufficient, or penetration of foreign matter occurs in the step of forming the first electrode ELT1 and the second electrode ELT2 and / or in subsequent processes, a short circuit defect may occur between the first electrode ELT1 and the second electrode ELT2.

[0255] Although the scope of the present disclosure is described by detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions and replacements may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0256] The scope of the present disclosure is not limited by the detailed description of this specification, and should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. A light emitting device, comprising: substrate; A first electrode is disposed on the substrate; a first insulating layer disposed on the substrate and configured to cover at least one region of the first electrode; a second electrode disposed on the first insulating layer and spaced apart from the first electrode; as well as at least one light emitting diode electrically connected between the first electrode and the second electrode, wherein the first electrode and the second electrode are disposed on different layers on the substrate, and the first electrode and the second electrode are spaced apart from each other by a predetermined distance so as not to overlap each other in a plan view, and Part of the first insulating layer is disposed between the at least one light emitting diode and the substrate, and the part of the first insulating layer is interposed between the first electrode and the second electrode.

2. The light emitting device according to claim 1, further comprising: a first partition wall disposed between the substrate and a region of the first electrode; as well as A second partition wall is provided between the substrate and a region of the second electrode.

3. The light emitting device according to claim 2, in, The first partition wall and the second partition wall are provided on the same layer on the substrate, and A region of the first insulating layer is interposed between the second partition wall and the second electrode.

4. The light emitting device according to claim 1, further comprising a display element layer and a circuit element layer, wherein the display element layer comprises the first electrode, the second electrode and the light emitting diode, and the circuit element layer is disposed between the display element layer and the substrate. in, The circuit element layer comprises: a first circuit element or a first power line electrically connected to the first electrode and including a region overlapping the second electrode; and A second circuit element or a second power line is electrically connected to the second electrode and includes a region overlapping the first electrode.

5. The light emitting device according to claim 4, wherein: An overlapping surface area between the first circuit element or the first power line and the second electrode is greater than an overlapping surface area between the second circuit element or the second power line and the first electrode.

6. The light emitting device according to claim 1, further comprising: a first contact electrode disposed on at least one region of the first electrode and a first end of the light emitting diode and configured to electrically connect the first end to the first electrode; as well as A second contact electrode is disposed on at least one region of the second electrode and a second end of the light emitting diode and is configured to electrically connect the second end to the second electrode.

7. The light emitting device according to claim 6, in, The first insulating layer includes an opening, a region of the first electrode is exposed in the opening, and The first contact electrode contacts the exposed one region of the first electrode and the first end of the light emitting diode.

8. The light emitting device according to claim 6, further comprising a second insulating layer, the second insulating layer being disposed on the second contact electrode and configured to cover the second contact electrode, in, One end of the second insulating layer is interposed between the first contact electrode and the second contact electrode. 9 . The light emitting device according to claim 6 , further comprising a third insulating layer disposed on a region of the second electrode.

10. The light emitting device according to claim 6, further comprising at least one of the following: a fourth insulating layer disposed on the first electrode, the second electrode and a region of the light emitting diode; and A fifth insulating layer is configured to cover the first contact electrode and includes one end interposed between the first contact electrode and the second contact electrode.

11. The light-emitting device according to claim 6, further comprising a sixth insulating layer, which is partially disposed on the first electrode, the second electrode and a region of the light-emitting diode, and is configured to expose a region of each of the first electrode and the second electrode and the first end and the second end of the light-emitting diode.

12. The light emitting device according to claim 11, in, One end of the first contact electrode is disposed on a region of the sixth insulating layer disposed on the light emitting diode, and One end of the second contact electrode is disposed on the region of the sixth insulating layer disposed on the light emitting diode to face the first contact electrode. 13 . The light emitting device according to claim 6 , further comprising at least one encapsulation layer configured to cover one surface of the substrate on which the first contact electrode and the second contact electrode are disposed.

14. The light emitting device according to claim 1, wherein: The light emitting diode includes a rod-type light emitting diode oriented in a horizontal direction between the first electrode and the second electrode.

15. A method for manufacturing a light emitting device, comprising: forming a first electrode on a substrate having a circuit element layer disposed thereon, wherein the first electrode is electrically connected to a first circuit element or a first power line in the circuit element layer; forming a first insulating layer on the substrate to at least cover the first electrode; forming a second electrode on the first insulating layer at a position spaced apart from the first electrode by a predetermined distance, wherein the second electrode is electrically connected to a second circuit element or a second power line in the circuit element layer, and the first electrode and the second electrode are disposed on different layers on the substrate; providing a light emitting diode on the substrate including the first electrode and the second electrode, and aligning the light emitting diode between the first electrode and the second electrode; and A first contact electrode and a second contact electrode are formed, the first contact electrode electrically connecting the first end of the light emitting diode to the first electrode, and the second contact electrode electrically connecting the second end of the light emitting diode to the second electrode.

16. The method according to claim 15, wherein: Forming the first contact electrode includes: forming a first contact portion by etching the first insulating layer so that a region of the first electrode is exposed; and The first contact electrode is formed on at least the one region of the first electrode including the first contact portion and on the first end of the light emitting diode.

17. The method according to claim 15, wherein: Forming the second contact electrode includes forming the second contact electrode on at least one region of the second electrode and the second end of the light emitting diode.

18. The method according to claim 15, wherein: The first contact electrode and the second contact electrode are sequentially formed on the substrate, or the first contact electrode and the second contact electrode are simultaneously formed on the substrate.

19. The method according to claim 15, further comprising, after forming the second electrode, forming a third insulating layer configured to cover the second electrode, in, The light emitting diode is provided on the substrate on which the third insulating layer is formed.

20. Display equipment, including: a substrate including a display area; as well as pixels, arranged in the display area, Wherein, the pixels include: A first electrode is disposed on the substrate; a first insulating layer disposed on the substrate and configured to cover at least one region of the first electrode; a second electrode disposed on the first insulating layer and spaced apart from the first electrode by a predetermined distance in a plan view; and at least one light emitting diode electrically connected between the first electrode and the second electrode, Part of the first insulating layer is disposed between the at least one light emitting diode and the substrate, and the part of the first insulating layer is interposed between the first electrode and the second electrode.

Images