Display panel

Abstract

The display panel may include a display area in which a plurality of pixels are arranged, a non-display area outside the display area, a plurality of protrusions protruding from the non-display area and formed along edges of the non-display area, and a first driving unit arranged in the non-display area and including a plurality of first stages. The plurality of first stages may be arranged to correspond to the plurality of protrusions, respectively.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a display panel applied to a curved display device. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become increasingly prominent. The use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0003] Flexible display devices, which are easy to carry and can be applied to electronic devices of various shapes, have attracted much attention as next-generation display devices. Specifically, curved display devices can realize images not only from the front surface but also from the side surfaces by bending the edges of the display panel.

[0004] Recently, with the diversification of user design requirements, display panels can be bent along multiple bending axes. However, when the display panel is bent along the bending axes to manufacture a curved display device, cracks may be generated due to stress concentration at the intersections of the bending axes. Summary of the Invention

[0005] An object of the present invention is to provide a display panel having reduced stress at the region where bending axes intersect.

[0006] In order to achieve the above-described purposes of the present invention, a display panel according to an embodiment may include a display area in which a plurality of pixels are arranged, a non-display area located outside the display area, a plurality of protrusions protruding from the non-display area and formed along the edge of the non-display area, and a first driver arranged in the non-display area and including a plurality of first levels arranged to correspond to the plurality of protrusions, respectively.

[0007] In an embodiment, the display panel may further include a first driver control signal line provided in the non-display area and supplying the first driver control signal to the first driver.

[0008] In an embodiment, the first driver control signal line may be located between the first driver and an edge of the non-display area, and may extend along the plurality of protrusions.

[0009] In an embodiment, the first driver control signal line may be spaced apart from an edge of the non-display area by a predetermined distance.

[0010] In an embodiment, the display panel may further include a second driver disposed in the non-display area, between the first driver and the display area, and including a plurality of second stages disposed to respectively correspond to the plurality of protrusions.

[0011] In an embodiment, the display panel may further include a second driver control signal line provided in the non-display area and supplying the second driver control signal to the second driver.

[0012] In an embodiment, the second driver control signal line may be located between the first driver and the second driver.

[0013] In an embodiment, the second driver control signal line may extend in a meandering manner along the plurality of protrusions.

[0014] In an embodiment, one of the first driver and the second driver may be a scan driver, and the other of the first driver and the second driver may be an emission driver.

[0015] In an embodiment, the display panel may further include a voltage line provided in the non-display area, between the first driver and the display area, and supplying a voltage to the plurality of pixels.

[0016] In an embodiment, the voltage line may extend straight along a boundary between the non-display area and the display area.

[0017] In an embodiment, the display panel may further include a thin film encapsulation layer covering the plurality of pixels.

[0018] In an embodiment, an edge of the thin film encapsulation layer may be located on an edge of the non-display area.

[0019] In an embodiment, an edge of the thin film encapsulation layer may be located in the non-display area between the first driver and the display area.

[0020] In order to achieve the above-described purposes of the present invention, the display panel according to the embodiment may include a flat area in which an image is displayed, a first curved area adjacent to the side of the flat area, a second curved area adjacent to the corner of the flat area and the first curved area, and a plurality of protrusions protruding from the second curved area and formed along the edge of the second curved area.

[0021] In an embodiment, the display panel may further include a driver disposed in the second bending region and including a plurality of stages disposed to respectively correspond to the plurality of protrusions.

[0022] In an embodiment, the display panel may further include a driver control signal line provided in the second bending area and supplying a driver control signal to the driver. The driver control signal line may be located between the driver and an edge of the second bending area and may extend along the plurality of protrusions.

[0023] In an embodiment, the first bending region may be bent along a first bending axis extending in a first direction, and the second bending region may be bent along the first bending axis and a second bending axis extending in a second direction intersecting the first direction.

[0024] In an embodiment, the corners of the flat areas may be rounded.

[0025] In an embodiment, the first bending area may be a display area, and the second bending area may be a non-display area.

[0026] In the display panel according to the embodiment, a plurality of protrusions may be formed along the edge of the second bending region bent along intersecting bending axes, so that stress applied to the second bending region may be dispersed and the second bending region may not be cracked.

[0027] In the display panel according to the embodiment, the respective stages of the driver may be disposed to correspond to the plurality of protrusions, respectively, so that the range of the non-display area may be reduced and the dead zone may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0029] Figure 2 It shows Figure 1 A circuit diagram of a pixel in a display device.

[0030] Figure 3 It shows Figure 1 Block diagram of a scan driver for a display device in FIG.

[0031] Figure 4 It shows Figure 1 A block diagram of an emission driver of a display device in FIG.

[0032] Figure 5 is a plan view showing a display panel according to an embodiment.

[0033] Figure 6 It shows Figure 5 A plan view of the display panel in a bent state.

[0034] Figure 7 It shows Figure 5 A perspective view of the display panel in a bent state.

[0035] Figure 8 is a plan view showing a portion of a display panel according to an embodiment.

[0036] Figure 9 is a cross-sectional view showing a portion of a display panel according to an embodiment.

[0037] Figure 10 is a cross-sectional view showing a portion of a display panel according to an embodiment.

[0038] Figure 11 is a plan view showing a portion of a display panel according to an embodiment. DETAILED DESCRIPTION

[0039] Hereinafter, a display panel and a display device including the same according to embodiments of the present invention will be explained in detail with reference to the accompanying drawings.

[0040] In the following, reference will be made to Figures 1 to 4 Each element of the display device according to the embodiment is described in detail.

[0041] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0042] refer to Figure 1 , the display device according to the embodiment may include a display unit 105 , a scan driver 110 , an emission driver 120 , a data driver 130 , and a timing controller 160 .

[0043] The display unit 105 may include a plurality of pixels PX. The pixels PX may be connected to scan lines S1 to Sn, emission lines E1 to En, and data lines D1 to Dm. Further, the pixels PX may be connected to a first power source ELVDD, a second power source ELVSS, and a third power source VINT.

[0044] The pixels PX may receive scan signals from the scan lines S1 to Sn and may receive data signals synchronized with the scan signals from the data lines D1 to Dm. The pixels PX receiving the data signals may control the amount of driving current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode (not shown), and the organic light emitting diode may generate light having a brightness corresponding to the amount of driving current.

[0045] The scan driver 110 may supply scan signals to the scan lines S1 to Sn in response to the scan driver control signal SCS from the timing controller 160. For example, the scan driver 110 may supply scan signals to the scan lines S1 to Sn in sequence. When the scan signals are sequentially supplied to the scan lines S1 to Sn, the pixels PX may be sequentially selected in units of horizontal lines.

[0046] The emission driver 120 may supply the emission signals to the emission lines E1 to En in response to the emission driver control signal ECS from the timing controller 160. For example, the emission driver 120 may sequentially supply the emission signals to the emission lines E1 to En.

[0047] The data driver 130 may supply data signals to the data lines D1 to Dm in response to the data driver control signal DCS. The data signals supplied to the data lines D1 to Dm may be supplied to the pixels PX selected by each scan signal. Therefore, the data driver 130 may supply data signals to the data lines D1 to Dm in synchronization with the scan signals.

[0048] The timing controller 160 may generate a scan driver control signal SCS, an emission driver control signal ECS, and a data driver control signal DCS in response to a control signal supplied from the outside. The scan driver control signal SCS may be supplied to the scan driver 110, the emission driver control signal ECS may be supplied to the emission driver 120, and the data driver control signal DCS may be supplied to the data driver 130. Furthermore, the timing controller 160 may convert image data input from the outside into image data DATA that meets the specifications of the data driver 130, and may supply the converted image data DATA to the data driver 130.

[0049] The scan driver control signal SCS may include a scan start signal and a clock signal. The scan start signal may control the supply timing of the scan signal, and the clock signal may be used to shift the scan start signal.

[0050] The emission driver control signal ECS may include an emission start signal and a clock signal. The emission start signal may control the supply timing of the emission signal, and the clock signal may be used to shift the emission start signal.

[0051] The data driver control signal DCS may include a source start signal, a source output enable signal, or a source sampling clock. The source start signal may control the data sampling start time point of the data driver 130. The source output enable signal may control the output timing of the data driver 130. The source sampling clock may control the sampling operation of the data driver 130 based on a rising edge or a falling edge.

[0052] Figure 2 It shows Figure 1 1. Circuit diagram of a pixel PX of a display device in FIG.

[0053] For ease of description, Figure 2 Pixel PX located in the i-th pixel row and the j-th pixel column is shown. Here, i is a natural number greater than or equal to 1 and less than or equal to n, and j is a natural number greater than or equal to 1 and less than or equal to m.

[0054] refer to Figure 2 , the pixel PX may include a pixel circuit PC and an organic light emitting diode OLED.

[0055] The pixel circuit PC can control the amount of driving current flowing from the first power source ELVDD through the organic light emitting diode OLED to the second power source ELVSS in response to the data signal. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

[0056] A first electrode of the first transistor T1 (driving transistor) may be connected to a first node N1, and a second electrode of the first transistor T1 may be connected to a first electrode of the sixth transistor T6. A gate electrode of the first transistor T1 may be connected to a second node N2. The first transistor T1 may control the amount of driving current flowing from the first power source ELVDD through the organic light emitting diode OLED to the second power source ELVSS in response to a data signal supplied to the j-th data line Dj.

[0057] The second transistor T2 may be connected between the j-th data line Dj and the first node N1. In other words, the second transistor T2 may be connected between the first electrode of the first transistor T1 and the j-th data line Dj. A gate electrode of the second transistor T2 may be connected to the i-th scan line Si. The second transistor T2 may be turned on when a scan signal is supplied to the i-th scan line Si to electrically connect the j-th data line Dj and the first node N1.

[0058] The third transistor T3 may be connected between the second electrode of the first transistor T1 and the second node N2. In other words, the third transistor T3 may be connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 may be turned on when a scan signal is supplied to the i-th scan line Si to diode-connect the first transistor T1.

[0059] The fourth transistor T4 may be connected between the second node N2 and the third power supply VINT. In other words, the fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the third power supply VINT. The gate electrode of the fourth transistor T4 may be connected to the (i-1)th scan line Si-1. The fourth transistor T4 may be turned on when a scan signal is supplied to the (i-1)th scan line Si-1 to supply the voltage of the third power supply VINT to the second node N2.

[0060] The fifth transistor T5 can be connected between the anode electrode of the organic light emitting diode OLED and the third power supply VINT. The gate electrode of the fifth transistor T5 can be connected to the i+1th scan line Si+1. The fifth transistor T5 can be turned on when a scan signal is supplied to the i+1th scan line Si+1 to supply the voltage of the third power supply VINT to the anode electrode of the organic light emitting diode OLED. In another embodiment, the gate electrode of the fifth transistor T5 can be connected to the i-1th scan line Si-1 or the i-th scan line Si. The voltage of the third power supply VINT can be set to a voltage lower than the voltage of the data signal.

[0061] The sixth transistor T6 and the seventh transistor T7 may be located in a path of a driving current and may allow the driving current to flow in response to an emission signal supplied to an i-th emission line Ei.

[0062] The sixth transistor T6 may be connected between the second electrode of the first transistor T1 and the anode electrode of the organic light emitting diode OLED. A gate electrode of the sixth transistor T6 may be connected to the i-th emission line Ei. The sixth transistor T6 may be turned on when an emission signal is supplied to the i-th emission line Ei.

[0063] The seventh transistor T7 may be connected between the first power supply ELVDD and the first node N1. In other words, the seventh transistor T7 may be connected between the first power supply ELVDD and the first electrode of the first transistor T1. The gate electrode of the seventh transistor T7 may be connected to the i-th emission line Ei. The seventh transistor T7 may be turned on when an emission signal is supplied to the i-th emission line Ei.

[0064] The storage capacitor CST may be connected between the first power source ELVDD and the second node N2. In other words, the storage capacitor CST may be connected between the first power source ELVDD and the gate electrode of the first transistor T1. The storage capacitor CST may store a data signal and a voltage corresponding to the threshold voltage of the first transistor T1.

[0065] An anode electrode of the organic light emitting diode OLED may be connected to the pixel circuit PC, and a cathode electrode of the organic light emitting diode OLED may be connected to a second power source ELVSS. The organic light emitting diode OLED may generate light having a predetermined brightness in response to a driving current supplied from the pixel circuit PC. The voltage of the first power source ELVDD may be set to a voltage higher than the voltage of the second power source ELVSS so that current can flow through the organic light emitting diode OLED.

[0066] Figure 3 It shows Figure 1 1 is a block diagram of a scan driver 110 of a display device in FIG.

[0067] refer to Figure 3 , the scan driver 110 may include a plurality of scan stages SST1 to SSTn.

[0068] The scanning stages SST1 to SSTn may be connected to ends of the scan lines S1 to Sn, respectively, and may supply scan signals SS1 to SSn to the scan lines S1 to Sn. The scanning stages SST1 to SSTn may operate in response to clock signals CLK1 and CLK2 supplied from the timing controller 160. The scanning stages SST1 to SSTn may be implemented using the same circuit.

[0069] Scanning stages SST1 to SSTn may receive an output signal (ie, a scan signal) of a previous scanning stage or a scan start signal FLM1. For example, the first scanning stage SST1 may receive the scan start signal FLM1, and the remaining scanning stages SST2 to SSTn may receive an output signal of the previous scanning stage.

[0070] Figure 4 It shows Figure 1 1 is a block diagram of an emission driver 120 of a display device in FIG.

[0071] refer to Figure 4 , the emission driver 120 may include a plurality of emission stages EST1 to ESTn.

[0072] Transmitting stages EST1 to ESTn may be connected to ends of transmission lines E1 to En, respectively, and may supply transmission signals ES1 to ESn to the transmission lines E1 to En. Transmitting stages EST1 to ESTn may operate in response to clock signals CLK3 and CLK4 supplied from the timing controller 160. Transmitting stages EST1 to ESTn may be implemented using the same circuit.

[0073] The transmitting stages EST1 to ESTn may receive the output signal (ie, the transmission signal) of the previous transmitting stage or the transmission start signal FLM2. For example, the first transmitting stage EST1 may receive the transmission start signal FLM2, and the remaining transmitting stages EST2 to ESTn may receive the output signal of the previous transmitting stage.

[0074] In the following, reference will be made to Figures 5 to 7 Each region of the display panel included in the display device according to the embodiment is described in detail.

[0075] Figure 5 is a plan view showing a display panel according to an embodiment. Figure 6 It shows Figure 5 A plan view of the display panel in a bent state. Figure 7 It shows Figure 5 A perspective view of the display panel in a bent state.

[0076] refer to Figure 5 、 Figure 6 and Figure 7 , the display panel 100 according to the embodiment may include a flat area FA, a first curved area CA1, and a second curved area CA2. Figures 1 to 4 The display device of the described embodiment may include the display panel 100 according to the present embodiment.

[0077] In a plan view, the flat area FA may have a rectangular shape. The flat area FA may have four sides SFA and four corners CFA. In an embodiment, the corners CFA of the flat area FA may be rounded.

[0078] When the display panel 100 is bent, the flat area FA may not be bent. Therefore, even when the display panel 100 is bent, the flat area FA may have a flat shape.

[0079] The first curved area CA1 may be adjacent to the side SFA of the flat area FA. For example, the display panel 100 may include four first curved areas CA1, each adjacent to the four side SFA of the flat area FA. The first curved area CA1 may be located in a first direction D1 of the flat area FA or in a second direction D2 intersecting the first direction D1. In a plan view, the first curved area CA1 may have a rectangular shape.

[0080] When the display panel 100 is bent, the first bending area CA1 may be bent. The first bending area CA1 may be bent along a bending axis extending in the first direction D1 or the second direction D2. For example, the first bending area CA1 located in the first direction D1 of the flat area FA may be bent along a bending axis extending in the second direction D2, and the first bending area CA1 located in the second direction D2 of the flat area FA may be bent along a bending axis extending in the first direction D1. Therefore, the first bending area CA1 may have a two-dimensional curved shape. Here, a two-dimensional curved shape may refer to a shape in which a plane is bent in one direction.

[0081] The second curved area CA2 may be adjacent to the corner CFA of the flat area FA and the first curved area CA1. The second curved area CA2 may be located between the first curved area CA1 located in the first direction D1 of the flat area FA and the first curved area CA1 located in the second direction D2 of the flat area FA. For example, the display panel 100 may include four second curved areas CA2 adjacent to the four corners CFA of the flat area FA. In plan view, the second curved areas CA2 adjacent to the rounded corners CFA of the flat area FA may have a fan-shaped shape.

[0082] When the display panel 100 is bent, the second bending area CA2 may be bent. The second bending area CA2 may be bent along a first bending axis extending in the first direction D1 and a second bending axis extending in the second direction D2. Thus, the second bending area CA2 may have a three-dimensional curved shape. Here, a three-dimensional curved shape may refer to a shape in which a plane is bent in two or more directions.

[0083] The display unit 105 described above can be provided in the flat area FA and the first curved area CA1. Specifically, the display unit 105 can be provided in the entire flat area FA and can be provided in a portion of the first curved area CA1 adjacent to the flat area FA. Therefore, the display area DA can be defined in the entire flat area FA and a portion of the first curved area CA1 adjacent to the flat area FA (in the Figure 5 and Figure 7 A plurality of pixels PX may be provided in the display area DA. Thus, an image may be displayed in the flat area FA and the first curved area CA1.

[0084] The scan driver 110 and the emission driver 120 described above may be disposed in the first bending area CA1 and the second bending area CA2. Specifically, the scan driver 110 and the emission driver 120 may be disposed in a portion of the first bending area CA1 spaced apart from the flat area FA and in the entire second bending area CA2. Therefore, the non-display area NDA may be defined in a portion of the first bending area CA1 spaced apart from the flat area FA and in the entire second bending area CA2 (in the first bending area CA1). Figure 5 and Figure 7 Therefore, an image may not be displayed in the second bending area CA2. Further, the non-display area NDA may be located outside the display area DA.

[0085] In the following, reference will be made to Figures 8 to 11 The flat area FA and the second curved area CA2 of the display panel 100 are described in detail.

[0086] Figure 8 is a plan view showing a portion of a display panel according to an embodiment. Figure 9 is a cross-sectional view showing a portion of a display panel according to an embodiment. For example, Figure 8 It may be a plan view showing the second bending area CA2 which is the non-display area NDA and a portion of the flat area FA which is the display area DA adjacent to the second bending area CA2. Figure 9 Can be shown along Figure 8 FIG. 1 is a cross-sectional view of an example of the display panel 100 taken along line AA′ in FIG.

[0087] refer to Figure 8 and Figure 9 The display panel 100 according to the embodiment may include a substrate SUB, a display unit 105, a scan driver 110, a scan driver control signal line 115, an emission driver 120, an emission driver control signal line 125, a voltage line 145, and a thin film encapsulation layer TFE.

[0088] The display unit 105 may be disposed in the flat area FA on the substrate SUB. In an embodiment, the substrate SUB may include a flexible plastic material. For example, the substrate SUB may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), or cellulose acetate propionate (CAP).

[0089] A plurality of protrusions PP protruding from the second bending area CA2 may be formed in the second bending area CA2. The protrusions PP may be formed along the edge of the second bending area CA2. The protrusions PP may be spaced apart from each other with a constant interval therebetween. Thus, the edge of the second bending area CA2 may have an uneven shape.

[0090] As described above, when the second bending area CA2 is bent, the second bending area CA2 may be bent along the intersecting bending axes, and accordingly, stress may be applied to the second bending area CA2. When the edge of the second bending area CA2 has a linear shape, stress may be concentrated on the edge of the second bending area CA2, and cracks may occur in the second bending area CA2. However, in an embodiment of the present invention, the protrusion PP may be formed in the second bending area CA2, and accordingly, the edge of the second bending area CA2 may have an uneven shape. Therefore, when the second bending area CA2 is bent along the intersecting bending axes, the stress applied to the second bending area CA2 can be dispersed, and cracks may not occur in the second bending area CA2.

[0091] The emission driver 120 may be disposed in the second bending area CA2 on the substrate SUB. As described above, the emission driver 120 may include a plurality of emission stages EST.

[0092] The emission stages EST may be provided to correspond to the protrusions PP, respectively. For example, each of the emission stages EST may be provided in each of the protrusions PP. Thus, the emission stages EST may be spaced apart from each other with a constant interval therebetween. In an embodiment, one emission stage EST may be provided to correspond to each of the protrusions PP.

[0093] The emission driver control signal line 125 may be provided in the second bending area CA2 on the substrate SUB and may supply an emission driver control signal ECS to the emission driver 120. Furthermore, the emission driver control signal line 125 may electrically connect the emission stages EST spaced apart from each other.

[0094] In an embodiment, the emission driver control signal line 125 may be located between the emission driver 120 and the edge of the second bending area CA2 and may extend along the protrusion PP. For example, the emission driver control signal line 125 may extend along the uneven shape of the edge of the second bending area CA2. Thus, the emission driver control signal line 125 may extend in a zigzag manner along the edge of the second bending area CA2.

[0095] In an embodiment, the emission driver control signal line 125 may be spaced a predetermined distance from the edge of the second bending area CA2. In such an embodiment, the emission driver control signal line 125 may have substantially the same shape as the edge of the second bending area CA2. When the emission driver control signal line 125 is spaced a predetermined distance from the edge of the second bending area CA2, a free space for cutting the substrate SUB may be ensured during the manufacturing process.

[0096] The scan driver 110 may be disposed in the second bending area CA2 on the substrate SUB. The scan driver 110 may be located between the emission driver 120 and the flat area FA. As described above, the scan driver 110 may include a plurality of scan stages SST.

[0097] The scanning stages SST may be disposed to correspond to the protrusions PP, respectively. For example, at least a portion of each of the scanning stages SST may be disposed within each of the protrusions PP. Thus, the scanning stages SST may be spaced apart from each other with a constant interval therebetween. In an embodiment, one scanning stage SST may be disposed to correspond to each of the protrusions PP.

[0098] The scan driver control signal line 115 may be disposed in the second bending area CA2 on the substrate SUB and may supply a scan driver control signal SCS to the scan driver 110. Furthermore, the scan driver control signal line 115 may electrically connect the scan stages SST spaced apart from each other.

[0099] In an embodiment, the scan driver control signal line 115 may be located between the emission driver 120 and the scan driver 110. For example, the scan driver control signal line 115 may be located between the emission driver control signal line 125 and the flat area FA. The scan driver control signal line 115 may extend in a zigzag manner along the protrusion PP. For example, the scan driver control signal line 115 may extend in a zigzag manner around the side of the scan stage SST.

[0100] In an embodiment, Figure 8 , the emission driver 120 may be disposed closer to the edge of the second bending area CA2 than the scan driver 110. However, the present invention is not limited thereto, and in another embodiment, the scan driver 110 may be disposed closer to the edge of the second bending area CA2 than the emission driver 120. In such another embodiment, the scan driver control signal line 115 may be disposed closer to the edge of the second bending area CA2 than the emission driver control signal line 125.

[0101] When the scan stages SST of the scan driver 110 and the emission stages EST of the emission driver 120 are adjacent to each other and disposed outside the protrusion PP, and the scan driver control signal lines 115 and the emission driver control signal lines 125 extend in a linear shape and are disposed outside the protrusion PP, the range of the non-display area NDA may increase because a free space must be ensured for disposing the scan driver 110, the scan driver control signal lines 115, the emission driver 120, and the emission driver control signal lines 125. However, in an embodiment of the present invention, the scan stages SST of the scan driver 110 and the emission stages EST of the emission driver 120 may be spaced apart from each other and disposed inside the protrusion PP, and the scan driver control signal lines 115 and the emission driver control signal lines 125 may extend in a zigzag manner along the protrusion PP, so that the range of the non-display area NDA can be reduced, and accordingly, the dead zone can be reduced.

[0102] The voltage line 145 may be disposed in the second curved area CA2 on the substrate SUB. The voltage line 145 may be located between the emission driver 120 and the flat area FA. For example, the voltage line 145 may be located adjacent to the flat area FA and between the scan driver 110 and the flat area FA. The voltage line 145 may supply voltage to the pixels PX located in the flat area FA. For example, the voltage line 145 may be connected to the first power supply ELVDD described above to supply the voltage of the first power supply ELVDD to the pixels PX, or connected to the third power supply VINT described above to supply the voltage of the third power supply VINT to the pixels PX.

[0103] In an embodiment, the voltage line 145 may extend straight along the boundary between the second curved area CA2 and the flat area FA. The voltage line 145 located adjacent to the flat area FA may be spaced apart from the protrusion PP. Therefore, the voltage line 145 may extend straight regardless of the uneven shape of the edge of the second curved area CA2.

[0104] A thin film encapsulation layer (TFE) may be provided on the display unit 105 to cover the pixels PX. The thin film encapsulation layer (TFE) may protect the organic light emitting diodes (OLEDs) included in the pixels PX from impurities such as oxygen and moisture. The thin film encapsulation layer (TFE) may include at least one inorganic layer and at least one organic layer. For example, the thin film encapsulation layer (TFE) may include a first inorganic layer, a second inorganic layer formed on the first inorganic layer, and an organic layer formed between the first and second inorganic layers.

[0105] The thin film encapsulation layer TFE may extend from the flat area FA to the second bending area CA2. In this case, an edge ETFE of the thin film encapsulation layer TFE may be located in the second bending area CA2.

[0106] In an embodiment, the edge ETFE of the thin film encapsulation layer TFE may be located on the edge of the second bending area CA2. For example, the edge ETFE of the thin film encapsulation layer TFE may be positioned parallel to the edge of the second bending area CA2. In such an embodiment, the thin film encapsulation layer TFE may cover the drivers 110 and 120 and the wires 115, 125, and 145 located in the second bending area CA2. Therefore, the thin film encapsulation layer TFE may protect the drivers 110 and 120 and the wires 115, 125, and 145 from impurities such as oxygen and moisture.

[0107] Figure 10 is a cross-sectional view showing a portion of a display panel according to an embodiment. For example, Figure 10 Can be shown along Figure 8 FIG. 1 is a cross-sectional view of another example of a display panel taken along line AA′ in FIG.

[0108] In another embodiment, the edge ETFE of the thin film encapsulation layer TFE may be located between the emission driver 120 and the flat area FA. For example, the edge ETFE of the thin film encapsulation layer TFE may be located between the voltage line 145 adjacent to the flat area FA and the flat area FA. In such another embodiment, the thin film encapsulation layer TFE may not cover the drivers 110 and 120 and the lines 115, 125, and 145 located in the second bending area CA2. However, an encapsulation member (not shown) covering the drivers 110 and 120 and the lines 115, 125, and 145 may be provided in the second bending area CA2 on the substrate SUB to protect the drivers 110 and 120 and the lines 115, 125, and 145 from impurities such as oxygen and moisture.

[0109] Figure 11 is a plan view showing a portion of a display panel according to an embodiment.

[0110] refer to Figure 11 In another embodiment, a plurality of emission stages EST and a plurality of scanning stages SST may be provided to correspond to each of the protrusions PP. Figure 11 As shown in FIG, two emission stages EST and two scanning stages SST may be provided to correspond to each of the protrusions PP. However, the present invention is not limited thereto, and three or more emission stages EST and three or more scanning stages SST may be provided to correspond to each of the protrusions PP.

[0111] [Industrial Applicability]

[0112] The display device according to the embodiment of the present invention may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like.

[0113] Although the display panel according to the embodiment of the present invention and the display device including the display panel have been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and changed by ordinary technicians in the relevant technical field without departing from the technical spirit of the present invention described in the claims.

[0114] Description of Reference Signs

[0115] 100: Display panel

[0116] 110: Scan driver

[0117] 115: Scan driver control signal line

[0118] 120: Transmitter Driver

[0119] 125: Transmitter driver control signal line

[0120] 145: Voltage line

[0121] CA1: first flexural area

[0122] CA2: Second flexure area

[0123] DA: Display Area

[0124] FA: Flat Area

[0125] NDA: Non-display area

[0126] PP: protrusion

[0127] TFE: Thin film encapsulation layer

Claims

1. A display panel, comprising: A display area, wherein a plurality of pixels are arranged in the display area; a non-display area located outside the display area and comprising a bending area located at a corner of the display panel, the bending area being bent along a first bending axis extending along a first direction and a second bending axis extending along a second direction intersecting the first direction; a plurality of protrusions protruding from the bending region and formed along an edge of the bending region; as well as The first driver is provided in the bending region and includes a plurality of first stages provided to correspond to the plurality of protrusions, respectively.

2. The display panel according to claim 1, further comprising: A first driver control signal line is provided in the bending region and supplies a first driver control signal to the first driver. 3 . The display panel according to claim 2 , wherein the first driver control signal line is located between the first driver and the edge of the bending area, and extends along the plurality of protrusions. 4 . The display panel of claim 2 , wherein the first driver control signal line is spaced apart from the edge of the bending area by a predetermined distance.

5. The display panel according to claim 1, further comprising: A second driver is provided in the bending area, is located between the first driver and the display area, and includes a plurality of second stages provided to correspond to the plurality of protrusions, respectively.

6. The display panel according to claim 5, further comprising: The second driver control signal line is provided in the bending region and supplies a second driver control signal to the second driver. 7 . The display panel according to claim 6 , wherein the second driver control signal line is located between the first driver and the second driver. 8 . The display panel according to claim 6 , wherein the second driver control signal line extends in a meandering manner along the plurality of protrusions. 9 . The display panel of claim 5 , wherein one of the first driver and the second driver is a scan driver, and the other of the first driver and the second driver is an emission driver.

10. The display panel according to claim 1, further comprising: A voltage line is provided in the bending area, is located between the first driver and the display area, and supplies a voltage to the plurality of pixels. 11 . The display panel according to claim 10 , wherein the voltage line extends straight along a boundary between the bending area and the display area.

12. The display panel according to claim 1, further comprising: A thin film encapsulation layer covers the plurality of pixels. 13 . The display panel according to claim 12 , wherein an edge of the thin film encapsulation layer is located on the edge of the bending area. 14 . The display panel according to claim 12 , wherein an edge of the thin film encapsulation layer is located in the bending area between the first driver and the display area.

15. A display panel comprising: a flat area in which the image is displayed; a first curved region adjacent to a side of the flat region and bent along a first bending axis extending in a first direction; a second bending region adjacent to a corner of the flat region and the first bending region and bent along the first bending axis and a second bending axis extending in a second direction intersecting the first direction; as well as A plurality of protrusions protrude from the second bending region and are formed along an edge of the second bending region.

16. The display panel according to claim 15, further comprising: A driver is provided in the second bending region and includes a plurality of stages provided to correspond to the plurality of protrusions, respectively.

17. The display panel according to claim 16, further comprising: a driver control signal line provided in the second bending region and supplying a driver control signal to the driver, The driver control signal line is located between the driver and the edge of the second bending area and extends along the plurality of protrusions. The display panel according to claim 15 , wherein the corners of the flat area are rounded corners.

19. The display panel according to claim 15, wherein the first curved area is a display area, and The second curved area is a non-display area.

Images