Detection devices, semiconductor devices

Abstract

Reduce power consumption in semiconductor devices. The semiconductor device includes a latch circuit composed of dynamic circuitry. The latch circuit includes a first circuit with decoding functionality, multiple capacitors, multiple clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. During a first clock signal of "H", the potential of the first capacitor is refreshed according to the decoding result of the first circuit. During a second clock signal of "H", the potential of the second capacitor is refreshed according to the potential of the first capacitor, and the first output terminal receives the potential of the second capacitor as a first output signal. During a third clock signal of "H", the potential of the third capacitor is refreshed according to the potential of the second capacitor, and the second output terminal receives the potential of the third capacitor as a second output signal.

Description

Technical Field

[0001] One aspect of the present invention relates to a latching circuit, a counting circuit, a detection device, a battery monitoring device, and a semiconductor device.

[0002] One aspect of the present invention relates to an article, method, or manufacturing method, and also to a process, machine, manufacture, or composition of matter. Another aspect of the present invention relates to a semiconductor device, display device, light-emitting device, energy storage device, lighting device, or electronic device. Furthermore, one aspect of the present invention relates to a charging control method for an energy storage device, a state inference method for an energy storage device, and a detection device for detecting anomalies in an energy storage device, particularly to a charging system for an energy storage device, a state inference system for an energy storage device, and an anomaly detection system for an energy storage device. Additionally, electronic devices incorporating the detection device of one aspect of the present invention include medical devices for detecting bodily states.

[0003] Furthermore, in this specification and the like, a semiconductor device refers to a component, circuit, or device that can operate by utilizing the characteristics of semiconductors. As an example, semiconductor elements such as transistors and diodes are semiconductor devices. Furthermore, as another example, a circuit containing semiconductor elements is a semiconductor device. Furthermore, as yet another example, a device having a circuit containing semiconductor elements is a semiconductor device. Background Technology

[0004] In recent years, various energy storage devices, such as lithium-ion rechargeable batteries, lithium-ion capacitors, and air batteries, have been actively developed. In particular, with the development of the semiconductor industry for portable information terminals such as mobile phones, smartphones, tablets or laptops, gaming devices, portable music players, digital cameras, medical equipment, hybrid electric vehicles (HEVs), electric vehicles (EVs) or plug-in hybrid electric vehicles (PHEVs), and electric motorcycles, the demand for high-output, high-energy-density lithium-ion rechargeable batteries has increased dramatically. As a rechargeable energy source, they have become a necessity in modern information society.

[0005] Secondary batteries (including lithium-ion secondary batteries) do not use the ratio of the remaining capacity (RC) of the battery to its full charge capacity (FCC). Instead, the state of charge (SOC) is set from 0% to 100% of the design capacity (DC), and to prevent over-discharge, the SOC is not set to 0%, but rather has a margin of approximately 5% (or 10%). Similarly, to prevent overcharging, the SOC is not set to 100%, but rather has a margin of approximately 5% (or 10%). As a result, lithium-ion secondary batteries are considered to be used within a range of 5% to 95% (or 10% to 90%) of their design capacity. In practice, the upper limit voltage V is set using a BMS (Battery Management System) connected to the secondary battery. max and lower limit voltage V min The voltage range is used to operate within 5% to 95% (or 10% to 90%) of the design capacity.

[0006] Secondary batteries degrade due to charging and discharging, changes over time, and temperature variations. Therefore, accurately monitoring the internal state of a secondary battery, especially its state of charge (SOC), allows for battery management. Accurate SOC monitoring can extend the upper limit voltage (V). max and lower limit voltage V min The voltage range. To manage secondary batteries, a device is needed to accurately determine their internal state, particularly the state of charge (SOC). Furthermore, the power consumption of this detection device needs to be reduced.

[0007] Patent document 1 discloses an example of a semiconductor integrated circuit used to reduce power consumption.

[0008] [Preliminary Technology Documents]

[0009] [Patent Literature]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2006-66938 Summary of the Invention

[0011] The technical problem that the invention aims to solve

[0012] In view of the above problems, one objective of this invention is to provide a semiconductor device with a novel structure. Furthermore, one objective of this invention is to provide a semiconductor device with reduced power consumption. Additionally, one objective of this invention is to provide a detection device with reduced power consumption.

[0013] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Furthermore, objectives other than those described above are readily apparent from the description, drawings, claims, etc., and can be extracted from these descriptions.

[0014] means of solving technical problems

[0015] One aspect of the present invention is a semiconductor device comprising a latching circuit composed of dynamic circuitry. The latching circuit includes a first circuit, first to third capacitors, first to third clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. The first circuit has a decoding function. The first to third clock input terminals sequentially receive first to third clock signals. During the period when the first clock signal is an "H" signal, the first circuit receives multiple input signals through the signal input terminal, and the potential of the first capacitor is refreshed according to the decoding result of the first circuit. During the period when the second clock signal is an "H" signal, the potential of the second capacitor is refreshed according to the potential of the first capacitor, and the first output terminal receives the potential of the second capacitor as a first output signal. When the third clock signal is an "H" signal, the potential of the third capacitor is refreshed according to the potential of the second capacitor, and the second output terminal receives the potential of the third capacitor as a second output signal.

[0016] In the above structure, the latch circuit includes fourth to sixth clock input terminals. The fourth to sixth clock input terminals sequentially receive fourth to sixth clock signals. During the period when the fourth clock signal is an "H" signal, the first capacitor is pre-charged. During the period when the fifth clock signal is an "H" signal, the second capacitor is pre-charged. During the period when the sixth clock signal is an "H" signal, the third capacitor is pre-charged.

[0017] In the above structure, the latch circuit includes a second circuit. The second circuit generates a seventh clock signal and an eighth clock signal based on the second clock signal received from the second clock input terminal. During the period when the seventh clock signal is an "H" signal, the latch circuit has the function of latching the decoding result of the input signal and outputting the latched result as a first output signal. During the period when the eighth clock signal is an "H" signal, the fifth clock input terminal receives the fifth clock signal, causing the second capacitor to precharge. When the first output signal is an "H" signal, the potential of the precharged second capacitor is output as the first output signal, i.e., the "H" signal. When the first output signal is an "L" signal, the potential of the second capacitor is released according to the second output signal, and the potential of the second capacitor is output as the first output signal, i.e., the "L" signal.

[0018] In the above structure, multiple cascaded latch circuits can be used as counting circuits.

[0019] Each latching circuit in the above structures includes a first to a fifth transistor. A fourth clock input terminal is electrically connected to the gate of the first transistor. A fifth clock input terminal is electrically connected to the gate of the second transistor. A sixth clock input terminal is electrically connected to the gate of the third transistor. One electrode of the second capacitor is electrically connected to the gate of the fourth transistor. One electrode of the third capacitor is electrically connected to the gate of the fifth transistor. The first to fifth transistors contain metal oxide in a semiconductor layer. The first to fifth transistors include a back gate. The back gates of the first to third transistors receive a potential different from the back gates of the fourth and fifth transistors.

[0020] One embodiment of the present invention is a detection device comprising the semiconductor device, detection circuit, and battery described above. The output signal of the semiconductor device is received by the detection circuit. The detection circuit uses the output signal as a monitoring cycle to monitor the output potential of the battery.

[0021] Invention Effects

[0022] One aspect of the present invention can provide a semiconductor device with a novel structure. Furthermore, one aspect of the present invention can provide a semiconductor device with reduced power consumption. Additionally, one aspect of the present invention can provide a detection device for reducing power consumption.

[0023] Note that the effects of one aspect of the present invention are not limited to those described above. The effects listed above do not preclude the existence of other effects. Furthermore, other effects are those not mentioned in this section but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned in this section from the description, drawings, etc. Moreover, one aspect of the present invention achieves at least one of the above-described effects and / or other effects. Therefore, one aspect of the present invention may sometimes not have the effects listed above.

[0024] Brief description of the attached figures

[0025] Figure 1A It is a block diagram illustrating a semiconductor device. Figure 1B It is a circuit diagram illustrating a semiconductor device.

[0026] Figure 2A It is a block diagram illustrating a semiconductor device. Figure 2B1 Figure 2B2 and Figure 2C It is a circuit diagram illustrating a semiconductor device.

[0027] Figure 3 It is a block diagram illustrating a semiconductor device.

[0028] Figures 4A1 to 4A3 , Figure 4BIt is a circuit diagram illustrating a semiconductor device.

[0029] Figure 5 It is a block diagram illustrating a semiconductor device.

[0030] Figures 6A1 to 6A4 It is a circuit diagram illustrating a semiconductor device.

[0031] Figure 7 It is a circuit diagram illustrating a semiconductor device.

[0032] Figure 8A It is a block diagram illustrating a semiconductor device. Figure 8B It is a circuit diagram illustrating a semiconductor device.

[0033] Figure 9A It is a circuit diagram illustrating a semiconductor device. Figure 9B It is a timing diagram illustrating a semiconductor device.

[0034] Figure 10A It is a circuit diagram illustrating a semiconductor device. Figure 10B It is a timing diagram illustrating a semiconductor device.

[0035] Figure 11 It is a circuit diagram illustrating a semiconductor device.

[0036] Figure 12 It is a circuit diagram illustrating a semiconductor device.

[0037] Figure 13A This is a top view showing an example of a transistor. Figure 13B and Figure 13C This is a cross-sectional view showing an example of a transistor.

[0038] Figure 14A This is a top view showing an example of a transistor. Figure 14B and Figure 14C This is a cross-sectional view showing an example of a transistor.

[0039] Figure 15 It is a block diagram illustrating a semiconductor device.

[0040] Figure 16A This is a block diagram of a battery protection IC. Figure 16B This is a 3D diagram of a battery protection IC.

[0041] Figure 17A and Figure 17B It is a diagram illustrating an electronic device.

[0042] Figures 18A to 18C It is a diagram illustrating an electronic device.

[0043] Figure 19A1 , Figure 19A2 , Figures 19B1 to 19B4 It is a diagram illustrating an electronic device.

[0044] Figure 20 This is a block diagram illustrating the prototype device.

[0045] Figure 21A These are photos of prototype devices. Figure 21B It is a diagram illustrating the cross-section of a transistor.

[0046] Figure 22 It is a graph illustrating the measurement data of the pilot-produced device.

[0047] Figure 23A These are simulation data from pilot-produced devices. Figure 23B These are measurement data from pilot-produced devices.

[0048] Methods of implementing the invention

[0049] The embodiments will now be described with reference to the accompanying drawings. It should be noted that those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0050] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings illustrate ideal examples schematically, and the invention is not limited to the shapes or values ​​shown in the drawings.

[0051] Furthermore, the ordinal numbers such as "first," "second," and "third" used in this specification are for the convenience of identifying the constituent elements, and are not intended to limit the quantity.

[0052] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate the positional relationship of the constituent elements with reference to the accompanying drawings. Furthermore, the positional relationship of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0053] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel-forming region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through this channel region between the source and the drain. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0054] Furthermore, in cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0055] In this specification, "electrical connection" includes connections made via "elements having a certain electrical function." Here, "elements having a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements having a certain electrical function" include not only electrodes and wiring formed from different conductive layers, but also switching elements such as transistors, resistive elements, inductors, capacitors, and other elements with various functions.

[0056] In this specification, "parallel" refers to a state where the angle formed by two straight lines is between -10° and 10°. Therefore, it also includes states where the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is between 80° and 100°. Therefore, it also includes states where the angle is between 85° and 95°.

[0057] In this specification and other materials, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0058] Furthermore, in this specification and other documents, unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the state where the gate-source voltage Vgs is lower than the threshold voltage Vth; in a p-channel transistor, the off state refers to the state where the gate-source voltage Vgs is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to the drain current when the gate-source voltage Vgs is lower than the threshold voltage Vth.

[0059] The off-state current of a transistor sometimes depends on Vgs. Therefore, "the off-state current of a transistor is less than or equal to I" sometimes means that there exists a Vgs value that makes the off-state current of the transistor less than or equal to I.

[0060] As an example, consider an n-channel transistor with a threshold voltage Vth of 0.5V and a drain current of 1 × 10⁻⁶ when Vgs is 0.5V. -9 A, the drain current when Vgs is 0.1V is 1×10 -13 A, the drain current when Vgs is -0.5V is 1×10 -19A, the drain current when Vgs is -0.8V is 1×10 -22 A. When Vgs is -0.5V or in the range of -0.5V to -0.8V, the drain current of this transistor is 1×10⁻⁶. -19 The current is below A, so the off-state current of this transistor is sometimes referred to as 1 × 10⁻⁶. -19 Below A. This is because the drain current of this transistor is 1 × 10⁻⁶. -22 The Vgs is below A, therefore the off-state current of this transistor is sometimes referred to as 1 × 10⁻⁶. -22 Below A.

[0061] In this specification, the off-state current of a transistor having a channel width W is sometimes displayed as a current value per channel width W. Furthermore, the off-state current of a transistor having a channel width is sometimes displayed as a current value per predetermined channel width (e.g., 1 μm). In the latter case, the unit of the off-state current is sometimes displayed in units having a current / length dimension (e.g., A / μm).

[0062] The off-state current of a transistor sometimes depends on temperature. In this specification, unless otherwise specified, the off-state current is sometimes shown as the off-state current at room temperature, 60°C, 85°C, 95°C, or 125°C. Alternatively, it is sometimes shown as the off-state current at a temperature that ensures the reliability of the semiconductor device including the transistor, or at a temperature at which the semiconductor device including the transistor is used (e.g., any temperature from 5°C to 35°C). "The off-state current of the transistor is I or less" sometimes means that there exists a value of Vgs at room temperature, 60°C, 85°C, 95°C, 125°C, a temperature that ensures the reliability of the semiconductor device including the transistor, or at a temperature at which the semiconductor device including the transistor is used (e.g., any temperature from 5°C to 35°C) that makes the off-state current of the transistor I or less.

[0063] The off-state current of a transistor sometimes depends on the drain-source voltage Vds. In this specification, unless otherwise specified, the off-state current is sometimes shown when Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, it may sometimes be shown when Vds is sufficient to ensure the reliability of the semiconductor device including the transistor, or when the semiconductor device including the transistor is used. "The off-state current of the transistor is I or less" sometimes means that a value Vgs exists at Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, sufficient to ensure the reliability of the semiconductor device including the transistor, or when the semiconductor device including the transistor is used, causing the off-state current of the transistor to be I or less.

[0064] In the above explanation of off-state current, the drain can be referred to as the source. That is to say, off-state current sometimes refers to the current flowing through the source when the transistor is in the off state.

[0065] In this specification, the off-state current is sometimes referred to as leakage current. In this specification, the off-state current sometimes refers to the current flowing between the source and drain when the transistor is in the off state.

[0066] Note that voltage refers to the difference between the potentials of two points, while potential refers to the electrostatic energy (potential energy) of a unit charge at a point in an electrostatic field. Generally, the potential difference between a point and a reference potential (e.g., ground potential) is simply referred to as potential or voltage; usually, potential and voltage are synonymous. Therefore, in this specification, unless specifically specified, "potential" may be referred to as "voltage" or "voltage" as "potential".

[0067] (Implementation Method 1)

[0068] In this embodiment, refer to Figures 1A to 12 The semiconductor device described in this embodiment is used as a latch circuit. Furthermore, multiple latch circuits can be cascaded to function as a counting circuit.

[0069] A semiconductor device according to one aspect of the present invention will be described. The semiconductor device is composed of dynamic circuitry.

[0070] First, let's briefly describe the dynamic circuit. The dynamic circuit includes a first transistor, a second transistor, a first circuit, a capacitor, a first wiring, and a second wiring. The first circuit includes a first terminal, a second terminal, and a third terminal.

[0071] One of the source and drain of the first transistor is electrically connected to the first wiring. The other of the source and drain of the first transistor is electrically connected to one of the source and drain of the second transistor and one electrode of the capacitor. The other of the source and drain of the second transistor is electrically connected to the first terminal of the first circuit. The second terminal of the first circuit is electrically connected to the other electrode of the capacitor and the second wiring. One electrode of the capacitor corresponds to the output terminal.

[0072] The power supply voltage of the dynamic circuit is applied to the first wiring, and the standard voltage of the dynamic circuit is applied to the second wiring. The first circuit has a decoding function.

[0073] Next, the operation of the dynamic circuit is briefly explained. The gate of the first transistor receives a first signal, turning the first transistor on. The first signal can pre-charge the capacitor with the power supply voltage applied to the first wiring through the first transistor. After the capacitor is pre-charged, the first transistor turns off. Furthermore, the output terminal can process the state of the capacitor after pre-charging as an "H" signal. Additionally, the output terminal can process the state of the capacitor after discharging as an "L" signal.

[0074] Next, the third terminal of the first circuit receives an input signal. The input signal can be a single signal or multiple signals. Furthermore, by using multiple input signals, more complex conditions can be set. When the conditions set in the first circuit match the conditions of the received input signal, the first and second terminals of the first circuit are connected. The connection between the first and second terminals of the first circuit will be described below as the on state of the first circuit.

[0075] Next, the gate of the second transistor receives the second signal, causing the second transistor to turn on. With the first circuit in the on state, the potential held in the capacitor is released through the second transistor and the first circuit.

[0076] When the conditions set in the first circuit match the conditions of the received input signal, the output terminal outputs an "L" signal.

[0077] The semiconductor device used as a latch circuit shown in this embodiment will be described. The latch circuit includes a first circuit, first to third capacitors, first to sixth clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. The first circuit has a decoding function.

[0078] The first to sixth clock input terminals sequentially receive the first to sixth clock signals. During the period when the "H" signal is supplied as the first clock signal, the first capacitor receives a pre-charge potential. During the period when the second clock signal is the "H" signal, the potential of the first capacitor is refreshed according to the decoding result of the first circuit.

[0079] During the period when the third clock signal is "H", the second capacitor receives a pre-charge potential. During the period when the fourth clock signal is "H", the potential of the second capacitor is refreshed along with the change in the potential of the first capacitor, and the first output terminal receives the potential of the second capacitor as the first output signal.

[0080] During the period when the fifth clock signal is "H", the third capacitor receives a pre-charge potential. During the period when the sixth clock signal is "H", the potential of the third capacitor is refreshed along with the change in the potential of the second capacitor, and the second output terminal receives the potential of the third capacitor as the second output signal.

[0081] The latching circuit also includes a second circuit. The second circuit generates a seventh clock signal and an eighth clock signal based on the third clock signal supplied to the third clock input terminal.

[0082] During the period when the seventh clock signal is "H", the latch circuit has the function of latching the decoding result of the input signal and outputting the latched result as the first output signal.

[0083] During the period when the eighth clock signal is "H", the fifth clock input terminal receives the fifth clock signal, causing the second capacitor to precharge. When the first output signal is "H", the potential of the precharged second capacitor is used as the first output signal, i.e., the "H" signal, and output. When the first output signal is "L", the potential of the second capacitor is released according to the second output signal, and the potential of the second capacitor is used as the first output signal, i.e., the "L" signal, and output.

[0084] The latch circuit is described in detail here. The latch circuit includes transistors one through seven. A first clock input terminal is electrically connected to the gate of the first transistor. A third clock input terminal is electrically connected to the gate of the second transistor. A fourth clock input terminal is electrically connected to the gate of the third transistor. A fifth clock input terminal is electrically connected to the gate of the fifth transistor. A sixth clock input terminal is electrically connected to the gate of the sixth transistor. Furthermore, a second clock input terminal is electrically connected to the first circuit.

[0085] The first wiring is electrically connected to one of the source and drain of the first transistor, one of the source and drain of the third transistor, and one of the source and drain of the fifth transistor. The other of the source and drain of the first transistor is electrically connected to the first terminal of the first circuit, the gate of the fourth transistor, and one electrode of the first capacitor. The other of the source and drain of the second transistor is electrically connected to one of the source and drain of the third transistor, the gate of the seventh transistor, and one electrode of the second capacitor. The other of the source and drain of the third transistor is electrically connected to one of the source and drain of the fourth transistor. The other of the source and drain of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor and one electrode of the third capacitor. The other of the source and drain of the sixth transistor is electrically connected to one of the source and drain of the seventh transistor. The second wiring is electrically connected to the second terminal of the first circuit, the other of the source and drain of the fourth transistor, the other of the source and drain of the seventh transistor, the other electrode of the first capacitor, the other electrode of the second capacitor, and the other electrode of the third capacitor.

[0086] The first to seventh transistors contain metal oxide in the semiconductor layer. Furthermore, the first to seventh transistors include a back gate. However, the potential received by the back gates of the first, third, and fifth transistors differs from the potential received by the back gates of the third, fourth, sixth, and seventh transistors.

[0087] As an example, the potentials received at the back gates of the first, second, and fifth transistors are lower than the potentials received at the back gates of the third, fourth, sixth, and seventh transistors. When the potentials received at the back gates of the first, second, and fifth transistors are low, the on-state currents of the first, second, and fifth transistors can be increased. By increasing the on-state currents of the first, second, and fifth transistors, the first to third capacitors can be charged more quickly.

[0088] Furthermore, one electrode of the second capacitor is connected to the first output terminal, thereby improving the driving capability when outputting the "H" signal to the first output terminal. Similarly, one electrode of the third capacitor is connected to the second output terminal, thereby improving the driving capability when outputting the "H" signal to the second output terminal.

[0089] Furthermore, the potentials received at the back gates of the third, fourth, sixth, and seventh transistors are greater than those received at the back gates of the first, second, and fifth transistors. When the potentials received at the back gates of the third, fourth, sixth, and seventh transistors are greater, the on-state currents of these transistors decrease.

[0090] For example, by reducing the off-state current of the third and fourth transistors, the leakage current flowing through the third and fourth transistors from the second capacitor is reduced. Similarly, by reducing the off-state current of the sixth and seventh transistors, the leakage current flowing through the sixth and seventh transistors from the third capacitor is reduced.

[0091] As an example, multiple cascaded latch circuits can be used as counting circuits. This counting circuit can be used as a ternary, hexadecimal, or decimal counting circuit depending on the number of cascaded latch circuits and the individually set decoding conditions. For example, electronic devices such as clocks can use ternary, hexadecimal, or decimal counting circuits to reduce power consumption.

[0092] Furthermore, as another application example, a battery monitoring device can be implemented by incorporating this counting circuit, detection circuit, and battery. For instance, the output signal of the counting circuit is received by the detection circuit. The detection circuit can then use the output signal of the counting circuit as a monitoring period to monitor the battery's output potential.

[0093] Next, the semiconductor device shown in this embodiment will be described with reference to the accompanying drawings. Figure 1A This is a block diagram illustrating the latch circuit 10. The latch circuit 10 includes circuit 20, circuit 40, signal input terminal 10a, clock input terminal 10b, terminal 10c, terminal 10d, output terminal 10e, and output terminal 10f.

[0094] Signal input terminal 10a receives input signals. Furthermore, the number of input signals can be one or more. Clock input terminal 10b receives clock signals. The number of clock signals is preferably multiple. For example, the latch circuit shown in this embodiment receives clock signals P0 to P5. Terminal 10c receives signal EN, and terminal 10d receives signal ENB. Signal ENB is the inverted signal of signal EN. Output terminal 10e outputs output signal Q, and output terminal 10f outputs output signal QB. Output signal QB is the inverted signal of output signal Q.

[0095] If in Figure 1B As detailed in the description, circuit 20 includes terminals (20a, 20b, 20c). The input signal DA is received by terminal 20c through signal input terminal 10a. Furthermore, circuit 20 has a decoding function.

[0096] In addition, circuit 40 includes terminals (40a, 40b, 40c, 40d, 40e). Signal EN is received by terminal 40a via terminal 10c. Signal ENB is received by terminal 40b via terminal 10d. Clock signal P3 is received by terminal 40c via clock input terminal 10b. Circuit 40 is capable of generating clock signals P3I and P3R from clock signal P3.

[0097] Figure 1B This is a circuit diagram detailing the latch circuit 10. The latch circuit 10 includes transistors 11 to 19, capacitors C1 to C3, circuit 20, and circuit 40. Circuit 20 includes transistor 21 and circuit 30. Circuit 30 includes terminals 30a to 30c. Circuit 40 includes transistors 41 and 42. Furthermore, the latch circuit 10 includes wiring VDD and wiring VSS.

[0098] Clock signal P0 is received by the gate of transistor 11. Clock signal P1 is received by the gate of transistor 21. Clock signal P2 is received by the gate of transistor 12. Clock signal P3I is received by the gate of transistor 13. Clock signal P3R is received by the gate of transistor 15. Clock signal P4 is received by the gate of transistor 17. Clock signal P5 is received by the gate of transistor 18.

[0099] The wiring VDD is electrically connected to one of the source and drain of transistor 11, one of the source and drain of transistor 12, and one of the source and drain of transistor 17. The other source and drain of transistor 11 is electrically connected to terminal 20a of circuit 20, the gate of transistor 14, and one electrode of capacitor C1. One of the source and drain of transistor 14 is electrically connected to one of the source and drain of transistor 13. The other source and drain of transistor 13 is electrically connected to the other source and drain of transistor 12, one of the source and drain of transistor 15, one electrode of capacitor C2, the gate of transistor 19, and output terminal 10e. The other source and drain of transistor 15 is electrically connected to one of the source and drain of transistor 16. The other source and drain of transistor 17 is electrically connected to one of the source and drain of transistor 18, one electrode of capacitor C3, and output terminal 10f. One of the source and drain of transistor 18 is electrically connected to one of the source and drain of transistor 19. Wiring VSS is electrically connected to terminal 20b of circuit 20, one of the source and drain of transistor 14, one of the source and drain of transistor 16, one of the source and drain of transistor 19, another electrode of capacitor C1, another electrode of capacitor C2, and another electrode of capacitor C3. Furthermore, node FN is formed by connecting one of the source and drain of transistor 11, terminal 20a of circuit 20, the gate of transistor 14, and one electrode of capacitor C1.

[0100] Terminal 40a is electrically connected to the gate of transistor 41. Terminal 40b is electrically connected to the gate of transistor 42. Terminal 40c is electrically connected to one of the source and drain of transistor 41 and one of the source and drain of transistor 42. The other of the source and drain of transistor 41 is electrically connected to the gate of transistor 13 via terminal 40d. The other of the source and drain of transistor 42 is electrically connected to the gate of transistor 15 via terminal 40e. Output terminal 10f is electrically connected to the gate of transistor 16.

[0101] Terminal 20a of circuit 20 is electrically connected to one of the source and drain of transistor 21. The other of the source and drain of transistor 21 is electrically connected to terminal 30a of circuit 30.

[0102] Next, the operation of latch circuit 10 will be explained. First, the condition where signal EN is "H" (meaning transistor 41 is on) and signal ENB is "L" (meaning transistor 42 is off) will be explained. Under these conditions, before receiving clock signal P3, clock signals P3I and P3R are "L" (meaning they are off).

[0103] Transistor 11 is turned on according to the clock signal P0. Capacitor C1 is precharged by the first potential received by the wiring VDD through transistor 11, thus becoming the "H" signal.

[0104] Next, during the period when the clock signal P1 is the "H" signal, the circuit 30 receives multiple input signals DA through the signal input terminal, and the potential of the capacitor C1 is refreshed due to the decoding result of the circuit 20.

[0105] More specifically, when the decoding result of the input signal DA is consistent, circuit 30 becomes active, making terminals 30a and 30b conductive. The potential of capacitor C1 is released through transistor 21 and circuit 30. When the decoding result of the input signal DA is inconsistent, circuit 30 becomes inactive, making terminals 30a and 30b non-conductive. Thus, capacitor C1 maintains its first potential.

[0106] Next, transistor 12 is turned on according to clock signal P2. Capacitor C2 is precharged by the potential received by wiring VDD through transistor 12, thus becoming the "H" signal.

[0107] Next, during the period when clock signal P3 is "H", clock signal P3I is "H" and clock signal P3R is "L". The potential of capacitor C2 is refreshed according to the potential of capacitor C1, and the output terminal 10e receives the potential of capacitor C2 as the output signal Q.

[0108] More specifically, when the potential of capacitor C1 is "H", transistor 14 is turned on. Simultaneously, when the clock signal P3I is "H", transistor 13 is turned on. The potential of capacitor C2 is released through transistors 13 and 14. Therefore, output terminal 10e outputs an "L" signal. As another example, when the potential of capacitor C1 is "L", transistor 14 is turned off. Thus, the potential of capacitor C2 remains at "H".

[0109] Next, transistor 17 is turned on according to clock signal P4. Capacitor C3 is precharged by the potential received by wiring VDD through transistor 17, thus becoming the "H" signal.

[0110] Next, during the period when the clock signal P5 is the "H" signal, the potential of capacitor C3 is refreshed according to the potential of capacitor C2. The output terminal 10f receives the potential of capacitor C3 as the output signal QB.

[0111] More specifically, when the potential of capacitor C2 is "H", transistor 19 is turned on. Simultaneously, when the clock signal P5 is "H", transistor 18 is turned on. The potential of capacitor C3 is released through transistors 18 and 19. Therefore, the output terminal 10f outputs an "L" signal. As another example, when the potential of capacitor C2 is "L", transistor 19 is turned off. Thus, the potential of capacitor C3 remains at the first potential.

[0112] Next, the case where clock signal P3R is "H" and clock signal P3I is "L" will be explained. When clock signal P3I is "L", transistor 13 is turned off. Therefore, input signal DA does not affect output signal Q or output signal QB.

[0113] The following will explain the situation after clock signal P3R becomes "H" and clock signal P3I becomes "L" during the period when clock signal P3 is "H". Capacitor C2 is precharged by the potential received by wiring VDD through transistor 12, thereby maintaining the "H" signal.

[0114] When the output signal QB is "L", transistor 16 is turned off. Therefore, the pre-charged capacitor C2 maintains a potential of "H". Consequently, the output signal Q is "H".

[0115] When the output signal QB is "H", transistor 16 is turned on. As a result, the potential of capacitor C2 is released through transistors 15 and 16. The potential of output capacitor C2 serves as the "L" signal, which is the output signal Q.

[0116] As an example, the latch circuit 10 can use different clock signals to control the first transistor that precharges the capacitor and the second transistor that discharges the capacitor. That is, the latch circuit 10 shown in this embodiment can suppress the through current of the first transistor and the second transistor, thereby reducing power consumption. Furthermore, the first transistor corresponds to transistors 11, 12, and 17 of the latch circuit 10, and the second transistor corresponds to transistors 13, 14, 15, 16, 18, and 19 of the latch circuit 10.

[0117] Furthermore, in the latch circuit 10, during the period when the signal ENB is "H" and the signal EN is "L", the output signal Q or output signal QB can be refreshed, which can reduce signal degradation.

[0118] Furthermore, the transistor used in the latching circuit 10 preferably contains metal oxide in the semiconductor layer. Transistors with metal oxide in the semiconductor layer have low off-state current when in the off state, making them suitable for circuits operating at low speeds. In circuits operating at low speeds, the clock frequency is preferably below 50 kHz, more preferably below 1 kHz, and even more preferably below 100 Hz. The transistor with metal oxide in the semiconductor layer is referred to as an OS transistor. OS transistors will be described in detail in Embodiment 4.

[0119] Reference Figure 2A This section describes a counting circuit that uses a latch circuit. The differences from latch circuit 10 will be explained later; sometimes, the differences will not be explained. Figure 1A or Figure 1B The same symbols represent the constituent elements.

[0120] Figure 2A This is a block diagram illustrating a ternary counting circuit 60. The ternary counting circuit 60 includes latch circuit 10A, latch circuit 10B, and circuit 10CA. Latch circuit 10A includes circuit 20A, and latch circuit 10B includes circuit 20B. This is consistent with... Figure 1A and Figure 1B The latch circuit 10 shown is different. Furthermore, latch circuit 10A and latch circuit 10B operate synchronously, so only one circuit 40 needs to be set up for latch circuit 10A and latch circuit 10B.

[0121] Here, the ternary counting circuit 60 is described in detail. The input signal DAa is received by terminal 20c of circuit 20A through signal input terminal 10a of latch circuit 10A. The input signal DAb is received by terminal 20c of circuit 20B through signal input terminal 10a of latch circuit 10B. Furthermore, one or more of output signals Q[1:0] and QB[1:0] are provided for input signals DAa or Dab. Clock signals P0 to P5 are received by clock input terminals 10b of latch circuits 10A and 10B. Circuit 40 can provide clock signal P3I to terminal 10c of latch circuits 10A and 10B. Furthermore, circuit 40 can provide clock signal P3R to terminal 10d of latch circuits 10A and 10B.

[0122] Here, circuit 10CA is described. Circuit 10CA includes terminals 10c1, 10c2, 10c3, and 10c4. Terminal 10c1 of circuit 10CA receives output signals Q[1:0] from latch circuits 10A and 10B. Furthermore, terminal 10c2 of circuit 10CA receives output signals QB[1:0] from latch circuits 10A and 10B. Additionally, circuit 10CA can output a carry signal CA3 from the ternary counter circuit to terminal 10c3 and a carry signal CA3B to terminal 10c4. Furthermore, the carry signal CA3B is the inverted signal of the carry signal CA3.

[0123] Figure 2B1 This is a circuit diagram illustrating circuit 20A. Circuit 20A includes transistor 21 and circuit 30A. Circuit 30A includes transistor 31, transistor 32, terminal 30a, terminal 30b, and terminal 30c. Furthermore, in... Figure 2B1 Terminal 30c is not shown in the diagram, but the structure that provides a uniform condition for decoding the input signal DAa at the gate of the transistor in circuit 30A is shown. The uniform condition for decoding the input signal DAa will be explained later.

[0124] Terminal 20a of circuit 20A is electrically connected to one of the source and drain of transistor 21. The other of the source and drain of transistor 21 is electrically connected to one of the source and drain of transistor 31 via terminal 30a. The other of the source and drain of transistor 31 is electrically connected to one of the source and drain of transistor 32. The other of the source and drain of transistor 32 is electrically connected to terminal 20b via terminal 30b. The gate of transistor 31 receives the output signal QB0. The gate of transistor 32 receives the output signal QB1.

[0125] Figure 2B2 is a circuit diagram illustrating circuit 20B. Circuit 20B includes transistor 21 and circuit 30B. Circuit 30B includes transistor 33, terminal 30a, terminal 30b, and terminal 30c. Furthermore, in Figure 2B2, terminal 30c is not shown; instead, the structure providing the uniformity condition for decoding the input signal DAb at the gate of the transistor in circuit 30B is shown. The uniformity condition for decoding the input signal DAb will be explained later.

[0126] Terminal 20a of circuit 20B is electrically connected to one of the source and drain of transistor 21. The other of the source and drain of transistor 21 is electrically connected to one of the source and drain of transistor 33 via terminal 30a. The other of the source and drain of transistor 33 is electrically connected to terminal 20b via terminal 30b. The gate of transistor 33 receives the output signal Q0.

[0127] Here, the consistency condition of circuit 30A and its decoder is explained. The consistency condition of circuit 30A and its decoder can be easily extracted using a Karnaugh map. When the input signal DAa is represented by a logical product as shown in Expression 1, latch circuit 10A can be used as a ternary counter.

[0128] (Expression 1)

[0129] DAa=QB0·QB1 (1)

[0130] The input signal DAb of the latch circuit 10B can be represented by expression 2.

[0131] (Expression 2)

[0132] DAb=Q0 (2)

[0133] Secondly Figure 2C This describes the circuit 10CA. Circuit 10CA includes transistors 61 to 66, transistor 61a, transistor 62a, capacitor C4, capacitor C5, terminals 10c1, 10c2, 10c3, and 10c4. Furthermore, in... Figure 2C Terminals 10c1 and 10c2 are not shown in the diagram. Instead, the diagram shows a structure that provides a uniform condition for decoding the output signal Q[1:0] or output signal QB[1:0] at the gate of the transistor in circuit 10CA. The uniform condition for decoding the output signal Q[1:0] or output signal QB[1:0] will be explained later.

[0134] Clock signal P0 is received by the gate of transistor 61 and the gate of transistor 61a. Clock signal P1 is received by the gate of transistor 62 and the gate of transistor 62a. Wiring VDD is electrically connected to one of the source and drain of transistor 61 and one of the source and drain of transistor 61a.

[0135] One of the source and drain terminals of transistor 61 is electrically connected to one of the source and drain terminals of transistor 62, one electrode of capacitor C4, and terminal 10c3. The other of the source and drain terminals of transistor 62 is electrically connected to one of the source and drain terminals of transistor 63. The other of the source and drain terminals of transistor 63 is electrically connected to one of the source and drain terminals of transistor 64. The other of the source and drain terminals of transistor 64 is electrically connected to wiring VSS. The other electrode of capacitor C4 is electrically connected to wiring VSS.

[0136] One of the source and drain terminals of transistor 61a is electrically connected to one of the source and drain terminals of transistor 62a, one electrode of capacitor C5, and terminal 10c4. The other of the source and drain terminals of transistor 62a is electrically connected to one of the source and drain terminals of transistor 65 and transistor 66. Wiring VSS is electrically connected to the other of the source and drain terminals of transistor 65 and transistor 66. The other electrode of capacitor C4 is electrically connected to wiring VSS.

[0137] The consistency conditions for the 10CA decoder circuit are explained below. Transistor 63's gate receives the output signal QB0. Transistor 64's gate receives the output signal Q1. Transistor 65's gate receives the output signal Q0. Transistor 66's gate receives the output signal QB1.

[0138] Using circuit 10CA, the consistency conditions for decoding the output signals Q[1:0] and QB[1:0] can be set. The consistency condition for decoding the output signals Q[1:0] is constituted by the logical expression CA3_1. The consistency condition for decoding the output signals QB[1:0] is constituted by the logical expression CA3B_1. When the logical expression CA3_1 can be represented by a logical product as shown in expression 3, the ternary counting circuit 60 operates.

[0139] (Expression 3)

[0140] CA3_1=QB0·Q1 (3)

[0141] Furthermore, the logical expression CA3B_1 can be represented by a logical AND as shown in expression 4.

[0142] (Expression 4)

[0143] CA3B_1=Q0+QB1 (4)

[0144] Figure 3This is a block diagram illustrating a hexadecimal counting circuit 60A. The hexadecimal counting circuit 60A includes latch circuits 10C, 10D, and 10E, as well as circuit 10CAa. Latch circuit 10C includes circuit 20C, latch circuit 10D includes circuit 20D, and latch circuit 10E includes circuit 20E. Latch circuits 10C, 10D, and 10E operate synchronously.

[0145] Here, the hexadecimal counting circuit 60A is described in detail. The input signal DAc is received by terminal 20c of circuit 20C via signal input terminal 10a of latch circuit 10C. The input signal DAd is received by terminal 20c of circuit 20D via signal input terminal 10a of latch circuit 10D. The input signal DAe is received by terminal 20c of circuit 20E via signal input terminal 10a of latch circuit 10E. Furthermore, one or more of output signals Q[2:0] and QB[2:0] are provided for the input signals DAc, DAd, or DAe. Clock signals P0 to P5 are received by clock input terminals 10b of latch circuits 10C, 10D, and 10E. Circuit 40 can provide clock signal P3I to terminals 10c of latch circuits 10C, 10D, and 10E. In addition, circuit 40 can provide a clock signal P3R to terminals 10d of latch circuits 10C, 10D and 10E.

[0146] Here, circuit 10CAa is described. Circuit 10CAa includes terminals 10c1, 10c2, 10c3, and 10c4. Terminal 10c1 of circuit 10CAa receives output signals Q[2:0] from latch circuits 10C, 10D, and 10E. Furthermore, terminal 10c2 of circuit 10CAa receives output signals QB[2:0] from latch circuits 10C, 10D, and 10E. Additionally, circuit 10CAa can output a carry signal CA6 from a hexadecimal counter circuit to terminal 10c3 and a carry signal CA6B to terminal 10c4.

[0147] Secondly Figure 4A1 This is a circuit diagram illustrating circuit 20C. Circuit 20C includes transistor 21 and circuit 30C. Circuit 30C has the same constituent elements as circuit 30B. Therefore, it includes transistor 33, terminal 30a, terminal 30b, and terminal 30c. Furthermore, in... Figure 4A1 Terminal 30c is not shown; instead, a structure is shown that provides a uniform condition for decoding the input signal DAc at the gate of the transistor in circuit 30C. The uniform condition for decoding the input signal DAc is different from that of the input signal DAc. The gate of transistor 33 receives the output signal QB0.

[0148] Secondly Figure 4A2 This is a circuit diagram illustrating circuit 20D. Circuit 20D includes transistor 21 and circuit 30D. Circuit 30D includes transistors 34 to 38, which differs from circuit 30C.

[0149] The consistency conditions for decoding the input signal DAd will be explained. The gate of transistor 34 receives the output signal QB0. The gate of transistor 35 receives the output signal Q1. The gate of transistor 36 receives the output signal Q0. The gate of transistor 37 receives the output signal QB1. The gate of transistor 38 receives the output signal QB2.

[0150] Terminal 30a of circuit 30D is electrically connected to one of the source and drain of transistor 34 and one of the source and drain of transistor 36. The other of the source and drain of transistor 34 is electrically connected to one of the source and drain of transistor 35. The other of the source and drain of transistor 36 is electrically connected to one of the source and drain of transistor 37. The other of the source and drain of transistor 37 is electrically connected to one of the source and drain of transistor 38. Terminal 30b of circuit 30D is electrically connected to the other of the source and drain of transistor 35 and the other of the source and drain of transistor 38.

[0151] Secondly Figure 4A3 This is a circuit diagram illustrating circuit 20E. Circuit 20E includes transistor 21 and circuit 30E. Circuit 30E differs from circuit 30C in that it includes transistor 39 and transistors 3A through 3C.

[0152] The consistency conditions for decoding the input signal DAe will be explained. Transistor 39's gate receives the output signal QB0. Transistor 3A's gate receives the output signal Q2. Transistor 3B's gate receives the output signal Q0. Transistor 3C's gate receives the output signal Q1.

[0153] Terminal 33a of circuit 30E is electrically connected to one of the source and drain of transistor 39 and one of the source and drain of transistor 3B. The other of the source and drain of transistor 39 is electrically connected to one of the source and drain of transistor 3A. The other of the source and drain of transistor 3B is electrically connected to one of the source and drain of transistor 3C. Terminal 30b of circuit 30E is electrically connected to the other of the source and drain of transistor 3A and the other of the source and drain of transistor 3B.

[0154] When the input signal DAc of the latch circuit 10C can be represented by expression 5, the hexadecimal counting circuit 60A operates.

[0155] (Expression 5)

[0156] DAc=QB0 (5)

[0157] The input signal DAd of the latch circuit 10D can be represented by the logical sum of the logical product of the first term and the logical product of the second term as shown in Expression 6.

[0158] (Expression 6)

[0159] DAd=QB0·Q1+Q0·QB1·QB2 (6)

[0160] The input signal DAe of the latch circuit 10E can be represented by the logical sum of the logical product of the first term and the logical product of the second term as shown in Expression 7.

[0161] (Expression 7)

[0162] DAe=QB0·Q2+Q0·Q1 (7)

[0163] Secondly Figure 4B This describes the circuit 10CAa. Circuit 10CAa has the same constituent elements as circuit 10CA. Therefore, it includes transistors 61 to 66, transistor 61a, transistor 62a, capacitor C4, capacitor C5, terminals 10c1, 10c2, 10c3, and 10c4. Furthermore, in... Figure 4B Terminals 10c1 and 10c2 are not shown in the diagram; instead, a structure is shown that provides a consistent condition for decoding the output signal Q[2:0] or the output signal QB[2:0] at the gate of the transistor in circuit 10CAa. Furthermore, a description of the circuitry of circuit 10CAa can be found in [link to relevant documentation]. Figure 2C Description of circuit 10CA.

[0164] Here, the consistency condition for the 10CAa decoding circuit is explained. The gate of transistor 63 receives the output signal Q0. The gate of transistor 64 receives the output signal Q2. The gate of transistor 65 receives the output signal QB0. The gate of transistor 66 receives the output signal QB2.

[0165] Using circuit 10CAa, the consistency conditions for decoding the output signals Q[2:0] and QB[2:0] can be set. The consistency condition for decoding the output signals Q[2:0] is constituted by the logical expression CA6_1. The consistency condition for decoding the output signals QB[2:0] is constituted by the logical expression CA6B_1. When the logical expression CA6_1 can be represented by a logical product as shown in expression 8, the hexadecimal counting circuit 60A operates.

[0166] (Expression 8)

[0167] CA6_1=Q0·Q2 (8)

[0168] Furthermore, the logical expression CA6B_1 can be represented by a logical AND as shown in expression 9.

[0169] (Expression 9)

[0170] CA6B_1=QB0+QB2 (9)

[0171] Figure 5 This is a block diagram illustrating the decimal counting circuit 60B. Figure 5 It includes latch circuits 10F, 10G, 10H, 10J, and 10CAb. Latch circuit 10F includes circuit 20F, latch circuit 10G includes circuit 20G, latch circuit 10H includes circuit 20H, and latch circuit 10J includes circuit 20J. Latch circuits 10F, 10G, 10H, and 10J operate synchronously.

[0172] Here, the decimal counting circuit 60B is described in detail. The input signal DAf is received by terminal 20c of circuit 20F via signal input terminal 10a of latch circuit 10F. The input signal DAg is received by terminal 20c of circuit 20G via signal input terminal 10a of latch circuit 10G. The input signal DAh is received by terminal 20c of circuit 20H via signal input terminal 10a of latch circuit 10H. The input signal DAj is received by terminal 20c of circuit 20J via signal input terminal 10a of latch circuit 10J. Furthermore, output signals Q[3:0] and QB[3:0] are provided for the input signals DAf, DAg, DAh, or DAj. Clock signals P0 to P5 are received via clock input terminals 10b of latch circuits 10F, 10G, 10H, and 10J. Circuit 40 can provide a clock signal P3I to terminal 10c of latch circuits 10F, 10G, 10H, and 10J. Circuit 40 can also provide a clock signal P3R to terminal 10d of latch circuits 10F, 10G, 10H, and 10J.

[0173] Here, circuit 10CAb is described. Circuit 10CAb includes terminals 10c1, 10c2, 10c3, and 10c4. Terminal 10c1 of circuit 10CAb receives output signals Q[3:0] from latch circuits 10F, 10G, 10H, and 10J. Furthermore, terminal 10c2 of circuit 10CAb receives output signals QB[3:0] from latch circuits 10F, 10G, 10H, and 10J. Additionally, circuit 10CAb can output a carry signal CA10 from decimal counter circuit 60B to terminal 10c3 and a carry signal CA10B to terminal 10c4.

[0174] Secondly Figure 6A1 This is a circuit diagram illustrating circuit 20F. Circuit 20F includes transistor 21 and circuit 30F. Circuit 30F has the same constituent elements as circuit 30B. Therefore, it includes transistor 33, terminal 30a, terminal 30b, and terminal 30c. Furthermore, in... Figure 6A1 Terminal 30c is not shown, but a matching condition for decoding the input signal DAf is shown at the gate of the transistor in circuit 30F. The matching condition for decoding the input signal DAf is different from that for the input signal DAb. The gate of transistor 33 receives the output signal QB0.

[0175] Secondly Figure 6A2 This is a circuit diagram illustrating circuit 20G. Circuit 20G includes transistor 21 and circuit 30G. Circuit 30G has the same constituent elements as circuit 30D.

[0176] The consistency conditions for decoding the input signal DAg will be explained. The gate of transistor 34 receives the output signal QB0. The gate of transistor 35 receives the output signal Q1. The gate of transistor 36 receives the output signal Q0. The gate of transistor 37 receives the output signal QB1. The gate of transistor 38 receives the output signal QB3.

[0177] Secondly Figure 6A3 This is a circuit diagram illustrating circuit 20H. Circuit 20H includes transistor 21 and circuit 30H. Circuit 30H includes transistors 3D to 3H, transistor 30J, and transistor 3K.

[0178] The consistency conditions for decoding the input signal DAh will be explained. The gate of transistor 3D receives the output signal QB0. The gate of transistor 3E receives the output signal Q2. The gate of transistor 3F receives the output signal QB1. The gate of transistor 3G receives the output signal Q2. The gate of transistor 3H receives the output signal Q0. The gate of transistor 3J receives the output signal Q1. The gate of transistor 3K receives the output signal QB2.

[0179] Terminal 30a of circuit 30H is electrically connected to one of the source and drain of transistor 3D, one of the source and drain of transistor 3F, and one of the source and drain of transistor 3H. The other of the source and drain of transistor 3D is electrically connected to one of the source and drain of transistor 3E. The other of the source and drain of transistor 3F is electrically connected to one of the source and drain of transistor 3G. The other of the source and drain of transistor 3H is electrically connected to one of the source and drain of transistor 3J. The other of the source and drain of transistor 3J is electrically connected to one of the source and drain of transistor 3K. Terminal 30b of circuit 30H is electrically connected to the other of the source and drain of transistor 3E, the other of the source and drain of transistor 3G, and the other of the source and drain of transistor 3K.

[0180] Secondly Figure 6A4 This is a circuit diagram illustrating circuit 20J. Circuit 20J includes transistor 21 and circuit 30J. Circuit 30J has the same constituent elements as circuit 30D.

[0181] The consistency conditions for decoding the input signal DAj will be explained. The gate of transistor 34 receives the output signal QB1. The gate of transistor 35 receives the output signal Q3. The gate of transistor 36 receives the output signal Q0. The gate of transistor 37 receives the output signal Q1. The gate of transistor 38 receives the output signal Q2.

[0182] When the input signal DAf of the latch circuit 10F is represented by expression 10, the decimal counting circuit 60B operates.

[0183] (Expression 10)

[0184] DAf=QB0 (10)

[0185] The input signal DAg of the latch circuit 10G can be represented by the logical sum of the logical product of the first term and the logical product of the second term as shown in expression 11.

[0186] (Expression 11)

[0187] DAg=QB0·Q1+Q0·QB1·QB3 (11)

[0188] The input signal DAh of the latch circuit 10H can be represented by the logical sum of the logical product of the first term, the logical product of the second term, and the logical product of the third term as shown in expression 12.

[0189] (Expression 12)

[0190] DAh=QB0·Q2+QB1·Q2+Q0·Q1·QB2 (12)

[0191] The input signal DAj of the latch circuit 10J can be represented by the logical sum of the logical product of the first term and the logical product of the second term as shown in expression 13.

[0192] (Expression 13)

[0193] DAj=QB1·Q3+Q0·Q1·Q2 (13)

[0194] Secondly Figure 7 This describes the circuit 10CAb. Circuit 10CAb has the same constituent elements as circuit 10CA. Therefore, it includes transistors 61 to 66, transistor 61a, transistor 62a, capacitor C4, capacitor C5, terminals 10c1, 10c2, 10c3, and 10c4. Furthermore, in... Figure 7 Terminals 10c1 and 10c2 are not shown, but the diagram shows the conditions that provide the gate of the transistor in circuit 10CAb with a uniform condition for decoding the output signal Q[3:0] or the output signal QB[3:0]. Furthermore, a description of the circuit of circuit 10CAb can be found in [link to circuit diagram]. Figure 2C Description of circuit 10CA.

[0195] Here, the consistency conditions for the 10CAb decoding circuit will be explained. The gate of transistor 63 receives the output signal Q0. The gate of transistor 64 receives the output signal Q3. The gate of transistor 65 receives the output signal QB0. The gate of transistor 66 receives the output signal QB3.

[0196] Using circuit 10CAb, the consistency conditions for decoding the output signals Q[3:0] and QB[3:0] can be set. The consistency condition for decoding the output signals Q[3:0] can be constructed by the logical expression CA10_1. The consistency condition for decoding the output signals QB[3:0] can be constructed by the logical expression CA10B_1. When the logical expression CA10_1 can be represented by a logical product as shown in expression 14, the decimal counting circuit 60B operates.

[0197] (Expression 14)

[0198] CA10_1=Q0·Q3 (14)

[0199] Furthermore, the logical expression CA10B_1 can be represented by a logical AND as shown in expression 15.

[0200] (Expression 15)

[0201] CA10B_1=QB0+QB3 (15)

[0202] Figure 8A This is a block diagram illustrating the 10K latch circuit. Figure 8A This circuit 50 differs from latch circuit 10. Circuit 50 includes terminals 50a, 50b, and 50c. Circuit 50 can reset latch circuit 10K. Circuit 50 can reset multiple latch circuits simultaneously. Furthermore, circuit 40 can be included in latch circuit 10K or can drive multiple latch circuits simultaneously.

[0203] Figure 8B This is a circuit diagram detailing the latch circuit 10K. Circuit 50 is described in detail here. Other components of the latch circuit 10K can be found in [reference needed]. Figure 1B The description of the latch circuit 10 is omitted here.

[0204] Circuit 50 includes transistors 51 and 52. The signal Reset is received by the gates of transistors 51 and 52 via terminal 50a. One of the source and drain of transistor 51 is electrically connected to wiring VSS. One of the source and drain of transistor 52 is electrically connected to wiring VDD. The other of the source and drain of transistor 51 is electrically connected to output terminal 10e via terminal 50b. The other of the source and drain of transistor 52 is electrically connected to output terminal 10f via terminal 50c.

[0205] The period during which the signal Reset is received by terminal 50a of circuit 50 will be explained. The output terminal 10e of latch circuit 10K receives the standard potential received by wiring VSS via transistor 51. Furthermore, the output terminal 10f of latch circuit 10K receives the potential received by wiring VDD via transistor 52. The standard potential received by wiring VSS corresponds to the "L" signal, and the potential received by wiring VDD corresponds to the "H" signal.

[0206] During the reset of the latch circuit 10K, the clock signal P2 is preferably an "L" signal. By setting the clock signal P2 to an "L" signal, the through current generated through transistors 12, 15, and 16 when capacitor C2 is discharged can be suppressed. Furthermore, the clock signal P5 is preferably an "L" signal. By setting the clock signal P5 to an "L" signal, the through current generated when capacitor C2 is charged can be suppressed.

[0207] Figure 9A This is a circuit diagram illustrating circuit 20K, which is part of latch circuit 10K. Circuit 20K includes transistor 21 and circuit 30K. Circuit 30K has the same constituent elements as circuit 20B. Furthermore, terminal 30c receives the output signal QB.

[0208] Figure 9B This is a timing diagram illustrating the operation of the 10K latch circuit. Furthermore, in Figure 9BIn the timing diagram shown, the latch circuit 10K has a "H" signal EN and a "L" signal ENB, which enables it to latch the input signal.

[0209] At time T0, the signal Reset is at the "H" potential. The output signal Q changes to the "L" signal. The output signal QB changes to the "H" signal.

[0210] At time T1, clock signal P0 is an "H" signal. Therefore, node FN becomes an "H" signal due to pre-charging of transistor 11. Because node FN becomes an "H" signal, transistor 14 is turned on. However, transistor 13 is turned off, thus the output signal Q at output terminal 10e remains unchanged. Furthermore, as... Figure 9B As shown, the Reset signal is preferably changed to the "L" signal.

[0211] At time T2, clock signal P0 is an "L" signal. Because both clock signals P0 and P1 are "L" signals, the through current flowing through transistor 11 and circuit 20K can be suppressed.

[0212] At time T3, clock signal P1 is an "H" signal. Because the Reset signal is an "H" signal from time T0 to time T1, output terminal QB outputs an "H" signal. As a result, transistors 21 and 33 become active, causing circuit 20K to conduct and become active. Consequently, the potential of node FN becomes an "L" signal, causing transistor 14 to become in the off state.

[0213] At time T4, clock signal P1 is an "L" signal. Because both clock signals P0 and P1 are "L" signals, the signal state of node FN is maintained. Figure 9B This shows the case where node FN maintains the "L" signal.

[0214] At time T5, clock signal P2 is an "H" signal. Consequently, capacitor C2 is pre-charged through transistor 12 and becomes an "H" signal. Therefore, output signal Q becomes an "H" signal. Consequently, the gate potential of transistor 19 becomes "H," turning transistor 19 on. However, transistor 18 remains off, thus output signal QB remains unchanged.

[0215] At time T6, clock signal P2 is an "L" signal. Because both clock signals P2 and P3 are "L" signals, transistors 12 and 13 are turned off, and the state of output signal Q is maintained by capacitor C2. Figure 9B This shows the case where the output signal Q remains the "H" signal.

[0216] At time T7, clock signal P3 is an "H" signal. As described above, wiring EN receives the "H" signal, and wiring ENB receives the "L" signal. Therefore, clock signal P3I becomes an "H" signal, causing transistor 13 to turn on. However, node FN maintains the "L" signal, thus transistor 14 remains off. Consequently, the pre-charged voltage of capacitor C2 is not released, and output signal Q remains an "H" signal.

[0217] At time T8, clock signal P3 is an "L" signal. Because both clock signals P2 and P3 are "L" signals, transistors 12 and 13 are turned off, thereby maintaining the state of output signal Q. Figure 9B This shows the case where the output signal Q remains the "H" signal.

[0218] At time T9, clock signal P4 is an "H" signal. Therefore, wiring VDD and capacitor C3 are turned on through transistor 17, causing capacitor C3 to precharge to an "H" potential. However, in Figure 9B During the time interval from T0 to T1, the Reset signal is "H", causing capacitor C3 to maintain the "H" signal, thus keeping the potential of capacitor C3 unchanged. Consequently, the output signal QB also maintains the "H" signal.

[0219] At time T10, clock signal P4 is an "L" signal. Because both clock signals P4 and P5 are "L" signals, transistors 17 and 18 are turned off, and the state of output signal QB is maintained by capacitor C3. Figure 9B This shows the case where the output signal QB remains the "H" signal.

[0220] At time T11, clock signal P5 is an "H" signal. Therefore, transistor 18 is turned on. Furthermore, capacitor C2 maintains an "H" signal, thus transistor 19 is turned on. As a result, the voltage pre-charged by capacitor C3 is released through transistors 18 and 19, causing the output signal QB to become an "L" signal. Because the output signal QB becomes an "L" signal, the input signal DA also becomes an "L" signal.

[0221] At time T12, clock signal P5 is an "L" signal. Because both clock signals P4 and P5 are "L" signals, transistors 17 and 18 are turned off, and the state of output signal QB is maintained by capacitor C3. Figure 9B This shows the case where the output signal QB remains the "L" signal.

[0222] Figure 10AThis is a circuit diagram illustrating circuit 20K, which is part of latch circuit 10K. The components of circuit 20K are similar to... Figure 9A The same, hence the explanation is omitted.

[0223] Figure 10B This is a timing diagram illustrating the operation of the 10K latch circuit. Furthermore, in Figure 10B In the timing diagram, the latch circuit 10K has a "H" signal ENB and a "L" signal EN. Therefore, the output signal Q or output signal QB is refreshed, reducing signal degradation. Furthermore, the operation from time T0 to T6 is related to... Figure 9B Similarly, therefore, the work done from time T0 to T6 is not described, but the work done after time T7 is described.

[0224] At time T7, clock signal P3 is an "H" signal, wiring EN receives an "L" signal, and wiring ENB also receives an "H" signal. As a result, transistor 42 becomes on, causing clock signal P3R to become an "H" signal, thus turning transistor 15 on. Furthermore, output signal QB remains an "H" signal, thus turning transistor 16 on. Consequently, the pre-charged voltage in capacitor C2 is released. Therefore, output signal Q becomes an "L" signal.

[0225] At time T8, clock signal P3 is an "L" signal. Because both clock signals P2 and P3 are "L" signals, transistors 12 and 15 are turned off, and the state of output signal Q is maintained by capacitor C2. Figure 9B This shows the case where the output signal Q remains the "L" signal.

[0226] At time T9, clock signal P4 is an "H" signal. Therefore, wiring VDD and capacitor C3 are turned on through transistor 17, causing capacitor C3 to precharge and reach an "H" potential. However, in Figure 9B During the time interval from T0 to T1, the Reset signal is "H", causing capacitor C3 to maintain the "H" signal, thus keeping the potential of capacitor C3 unchanged. Consequently, the output signal QB also maintains the "H" signal.

[0227] At time T10, clock signal P4 is an "L" signal. Because both clock signals P4 and P5 are "L" signals, transistors 17 and 18 are turned off, and the state of output signal QB is maintained by capacitor C3. Figure 9B This shows the case where the output signal QB remains the "H" signal.

[0228] At time T11, clock signal P5 is "H". Therefore, transistor 18 is turned on. Furthermore, capacitor C2 maintains an "L" signal, thus transistor 19 is turned off. Consequently, the pre-charged voltage of capacitor C3 is not released. Therefore, output signal QB maintains an "H" signal. The output signal QB maintaining an "H" signal makes input signal DA also an "H" signal.

[0229] At time T12, clock signal P5 is an "L" signal. Because both clock signals P4 and P5 are "L" signals, transistors 17 and 18 are turned off, and the state of output signal QB is maintained by capacitor C3. Figure 9B This shows the case where the output signal QB remains the "H" signal.

[0230] Figure 11 This is a circuit diagram illustrating the 10K latch circuit. Figure 11 The transistors in the latch circuit have a back gate, which is consistent with... Figure 8A The latch circuit shown is different from 10K. By giving the transistor a back gate, the threshold voltage of the transistor can be controlled.

[0231] Wiring BG1 is electrically connected to the back gates of transistors 13a, 14a, 15a, 16a, 18a, 19a, 21a, 41a, 42a, and 51a. Wiring BG2 is electrically connected to the back gates of transistors 11a, 12a, 17a, and 52a.

[0232] Wiring BG1 receives potential VBG1. Wiring BG2 receives potential VBG2. Potential VBG1 is preferably a different potential from potential VBG2.

[0233] As an example, potential VBG2 is greater than potential VBG1. When potential VBG2 is greater than potential VBG1, for example, the threshold voltages of transistors 11a, 12a, and 17a can be made lower than those of transistors 13a or 14a, thereby increasing the on-state current. By increasing the on-state current of transistors 11a, 12a, and 17a, capacitors C1 to C3 can be charged quickly. Furthermore, the charging potentials of capacitors C1 to C3 can be reduced, thereby reducing the power consumption of the latch circuit 10K.

[0234] Furthermore, one electrode of capacitor C2 is connected to output terminal 10e, thereby improving the current supply capability when outputting the "H" signal to output terminal 10e. Similarly, one electrode of capacitor C3 is connected to output terminal 10f, thereby improving the current supply capability when outputting the "H" signal to output terminal 10f.

[0235] Furthermore, the potential VBG1 is less than the potential VBG2. When the potential VBG1 is small, the off-state current of transistors 13a, 14a, 15a, 16a, 18a, and 19a decreases.

[0236] For example, by reducing the off-state current of transistor 13 or transistor 14, the leakage current flowing through transistor 13 and transistor 14 from capacitor C2 is reduced. Similarly, by reducing the off-state current of transistor 18a or transistor 19a, the leakage current flowing through transistor 18a and transistor 19a from capacitor C3 is reduced.

[0237] Figure 12 This is a circuit diagram illustrating the 10K latch circuit. Figure 12 In the latch circuit shown, the back gates of transistors 11a, 12a, and 17a are connected to different wirings, which is consistent with... Figure 11 The latch circuit shown is different from 10K.

[0238] Wiring BG3 is electrically connected to transistor 11a. Wiring BG4 is electrically connected to transistor 12a. Wiring BG5 is electrically connected to transistor 17a.

[0239] Wiring BG3 receives potential VBG3, wiring BG4 receives potential VBG4, wiring BG3 receives potential VBG5.

[0240] When the clock signal P0 is "H", potential VBG3 is preferably greater than potential VBG1. This improves the speed of precharging node FN. Simultaneously, potentials VBG4 and VBG5 are preferably equal to potential VBG1. This reduces the off-state current of transistors 12a and 17a, thus suppressing signal degradation of output signals Q and QB.

[0241] When the clock signal P2 is an "H" signal, the potential VBG4 is preferably greater than the potential VBG1. This increases the speed at which capacitor C2 is precharged and also improves the driving capability of the output signal Q. Furthermore, potentials VBG3 and VBG5 are preferably equal to potential VBG1. This reduces the off-state current of transistors 11a and 17a, thereby suppressing signal degradation at node FN and the output signal QB.

[0242] When the clock signal P4 is an "H" signal, the potential VBG5 is preferably greater than the potential VBG1. This improves the speed of pre-charging capacitor C3 and enhances the driving capability of the output signal QB. Furthermore, potentials VBG3 and VBG4 are preferably equal to potential VBG1. This reduces the off-state current of transistors 11a and 12a, thus suppressing signal degradation at node FN and the output signal Q.

[0243] Figures 1A to 12 The latch circuit shown can be called a dynamic circuit. Furthermore, while ternary, hexadecimal, and decimal counting circuits have been described above, latch circuits constructed using dynamic circuits can be applied to other number systems by combining decoding consistency conditions. Therefore, latch circuits constructed using dynamic circuits can reduce power consumption and are suitable for the required manufacturing cycles.

[0244] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0245] (Implementation Method 2)

[0246] In this embodiment, refer to Figures 13A to 14B An example of the transistor shown in Embodiment 1 is described.

[0247] Figure 13A A top view of transistor 1300 is shown. Furthermore, in Figure 13A For clarity, some constituent elements have been omitted from the accompanying drawings. Figure 13B Show along Figure 13A The cross-sectional view of the dotted-dash line A1-A2. Figure 13B This can be described as a cross-sectional view along the channel length of the transistor 1300. Figure 13C Show along Figure 13A The cross-sectional view of the dotted-dash lines A3-A4. Figure 13C This can be described as a cross-sectional view of the channel width of the transistor 1300.

[0248] Figure 14A A top view of transistor 1300A is shown. Furthermore, in Figure 14A For clarity, some constituent elements have been omitted from the accompanying drawings. Figure 14B Show along Figure 14A The cross-sectional view of the dotted-dash line A1-A2. Figure 14B This can be described as a cross-sectional view along the channel length of the transistor 1300A. Figure 14C Show along Figure 14A The cross-sectional view of the dotted-dash lines A3-A4. Figure 14C This can be described as a cross-sectional view of the channel width of the transistor 1300A.

[0249] also, Figures 14A to 14C The transistor 1300A shown is Figures 13A to 13C The example shown is a variation of transistor 1300. Figures 13A to 13C In the middle, oxide layer 1330c, insulating layer 1354, and insulating layer 1380 all have a single-layer structure, while... Figures 14A to 14C In them, they all have a layered structure. Regarding other structures, Figures 13A to 13C and Figures 14A to 14C The structures are the same.

[0250] Transistor 1300 includes a conductive layer 1305 disposed on a substrate (not shown) with an insulating layer 1314 between it and an insulating layer 1316, an insulating layer 1322 disposed on the insulating layer 1316 and the conductive layer 1305, an insulating layer 1324 disposed on the insulating layer 1322, an oxide layer 1330 (oxide layers 1330a, 1330b, and 1330c) disposed on the insulating layer 1324, and an insulating layer disposed on the oxide layer 1330. 1350, conductive layers 1360 (conductive layers 1360a and 1360b) disposed on insulating layer 1350, conductive layers 1342a and 1342b in contact with a portion of the top surface of oxide layer 1330b, and insulating layer 1354 disposed in contact with a portion of the top surface of insulating layer 1324, the side surface of oxide layer 1330a, the side surface of oxide layer 1330b, the side surface and top surface of conductive layer 1342a, and the side surface and top surface of conductive layer 1342b.

[0251] The transistor 1300 has insulating layers 1380, 1374, and 1381, each serving as an interlayer film. Furthermore, the transistor 1300 is electrically connected to conductive layers 1340 (conductive layers 1340a and 1340b), which serve as a connector. Additionally, insulating layers 1341 (insulating layers 1341a and 1341b) are provided in contact with the sides of the conductive layers 1340.

[0252] The oxide layer 1330 preferably includes an oxide layer 1330a disposed on the insulating layer 1324, an oxide layer 1330b disposed on the oxide layer 1330a, and an oxide layer 1330c disposed on the oxide layer 1330b, at least a portion of which is in contact with the top surface of the oxide layer 1330b. When the oxide layer 1330a is disposed below the oxide layer 1330b, the diffusion of impurities from the structure formed below the oxide layer 1330a to the oxide layer 1330b can be suppressed. When the oxide layer 1330c is disposed on the oxide layer 1330b, the diffusion of impurities from the structure formed above the oxide layer 1330c to the oxide layer 1330b can be suppressed.

[0253] Furthermore, transistor 1300 illustrates an example of an oxide layer 1330 having a three-layer structure of oxide layer 1330a, oxide layer 1330b, and oxide layer 1330c, but the invention is not limited thereto. For example, oxide layer 1330 may also have a single layer of oxide layer 1330b, a two-layer structure of oxide layer 1330a and oxide layer 1330b, a two-layer structure of oxide layer 1330b and oxide layer 1330c, or a stacked structure of four or more layers. Furthermore, oxide layer 1330a, oxide layer 1330b, and oxide layer 1330c may each have a stacked structure.

[0254] A conductive layer 1342 (conductive layer 1342a and conductive layer 1342b) is disposed on the oxide layer 1330b. The thickness of the conductive layer 1342 can be, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0255] The conductive layer 1360 is used as the first gate (also called the top gate) electrode of the transistor 1300, and the conductive layers 1342a and 1342b are both used as the source electrode or drain electrode of the transistor 1300.

[0256] In transistor 1300, a metal oxide (hereinafter also referred to as oxide semiconductor) is preferably used in the oxide layer 1330, which includes the channel formation region. By using oxide semiconductor in the channel formation region of the transistor, a transistor with high field-effect mobility can be realized. Furthermore, a transistor with high reliability can be realized.

[0257] As the aforementioned metal oxide, it is preferable to use a metal oxide with a bandgap of 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap in the oxide layer 1330, the off-state current of the transistor can be reduced. By employing such a transistor, a low-power amplifier circuit can be provided.

[0258] For example, the oxide layer 1330 preferably uses an In-M-Zn oxide (where element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) having indium (In), element M. In particular, aluminum, gallium, yttrium, or tin can be used as element M. Furthermore, In-M oxide, In-Zn oxide, or M-Zn oxide can also be used as the oxide layer 1330.

[0259] It is preferable to use metal oxides with low carrier density in transistor 1300. When it is necessary to reduce the carrier density of a metal oxide, the impurity concentration in the metal oxide can be reduced to decrease the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0260] In particular, oxygen vacancies are sometimes formed in metal oxides because hydrogen contained in the oxide reacts with oxygen bonded to metal atoms to form water. When oxygen vacancies are included in the channel-forming region of a metal oxide, the transistor sometimes exhibits always-on characteristics. Furthermore, defects formed by hydrogen entering oxygen vacancies are sometimes used as donors to generate electrons as charge carriers. In addition, a portion of the hydrogen bonds to oxygen bonded to metal atoms to generate electrons as charge carriers. Therefore, transistors using metal oxides containing a large amount of hydrogen tend to have always-on characteristics.

[0261] Therefore, when using metal oxides for oxide layer 1330, it is preferable to minimize the amount of hydrogen in the metal oxide. Specifically, the hydrogen concentration in the metal oxide, as measured by secondary ion mass spectrometry (SIMS), is less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 By using metal oxides with sufficiently reduced impurities such as hydrogen in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0262] When a metal oxide is used for the oxide layer 1330, when the conductive layer 1342 (conductive layer 1342a and conductive layer 1342b) is brought into contact with the oxide layer 1330, oxygen in the oxide layer 1330 diffuses into the conductive layer 1342, resulting in oxidation of the conductive layer 1342. The conductivity of the conductive layer 1342 is highly likely to decrease due to oxidation. Note that the diffusion of oxygen from the oxide layer 1330 into the conductive layer 1342 can also be referred to as the absorption of oxygen from the oxide layer 1330 by the conductive layer 1342.

[0263] When oxygen diffuses from oxide layer 1330 to conductive layer 1342 (conductive layer 1342a and conductive layer 1342b), layers are formed between conductive layer 1342a and oxide layers 1330b and 1330c, and between conductive layer 1342b and oxide layers 1330b and 1330c. Because these layers contain more oxygen than conductive layer 1342, it is presumed that these layers are insulating. In this case, the three-layer structure of conductive layer 1342, this layer, and oxide layer 1330b or oxide layer 1330c can be considered as a three-layer structure composed of metal-insulator-semiconductor, and is sometimes referred to as a MIS (Metal-Insulator-Semiconductor) structure.

[0264] Therefore, the conductive layer 1342 (conductive layer 1342a and conductive layer 1342b) is preferably made of a conductive material that has the characteristics that hydrogen in the oxide layer 1330 can easily diffuse into the conductive layer 1342 and oxygen in the oxide layer 1330 cannot easily diffuse into the conductive layer 1342. Thus, when hydrogen diffuses from the oxide layer 1330 into the conductive layer 1342, the hydrogen concentration in the oxide layer 1330 is reduced, thereby imparting stable electrical characteristics to the transistor 1300.

[0265] As the aforementioned conductive material, examples include conductors containing tantalum (Ta) and titanium (Ti). In particular, it is preferable to use a tantalum-containing conductor for conductive layer 1342. The tantalum-containing conductor can contain either nitrogen or oxygen. Therefore, the composition of the tantalum-containing conductor preferably satisfies TaN. x O y (x is a real number greater than 0 and less than or equal to 1.67, and y is a real number greater than or equal to 0 and less than or equal to 1.0). Conductors containing tantalum include metallic tantalum, tantalum oxide, tantalum nitride, tantalum oxynitride, tantalum oxynitride, etc. Therefore, in this specification, etc., conductors containing tantalum are sometimes referred to as TaN. x O y .

[0266] In TaN x O y In this process, a high tantalum ratio is preferred. Alternatively, a low nitrogen and oxygen ratio is preferred, and small values ​​for x and y are preferred. By increasing the tantalum ratio, TaN... x O y The resistivity decreases, therefore the TaN can be processed. x O y The transistor 1300 used in the conductive layer 1342 imparts good electrical characteristics.

[0267] In addition, in TaN x O y In the process, a high nitrogen ratio is preferred, and a large x value is preferred. This is achieved by using TaN with a high nitrogen ratio.x O y The conductive layer 1342 can be used to suppress oxidation of the conductive layer 1342. Furthermore, the thickness of the layer formed between the conductive layer 1342 and the oxide layer 1330 can be reduced.

[0268] Furthermore, hydrogen that diffuses into the conductive layer 1342 sometimes remains in the conductive layer 1342. In other words, hydrogen in the oxide layer 1330 is sometimes absorbed by the conductive layer 1342. In addition, hydrogen in the oxide layer 1330 is sometimes released through the conductive layer 1342 to the outside of the structure or transistor 1300 disposed near the conductive layer 1342.

[0269] To reduce the hydrogen concentration in the oxide layer 1330 and suppress the formation of a layer between the conductive layer 1342 and the oxide layer 1330, it is preferable that the conductive layer 1342 is made of a conductive material that allows hydrogen from the oxide layer 1330 to easily diffuse into the conductive layer 1342, and that a layer with the function of suppressing oxidation of the conductive layer 1342 is provided between the conductive layer 1342 and the oxide layer 1330. By providing this layer, a structure is achieved in which the conductive layer 1342 and the oxide layer 1330 do not contact each other, thereby suppressing the absorption of oxygen from the oxide layer 1330 by the conductive layer 1342.

[0270] The detailed structure of transistor 1300 is described below.

[0271] The insulating layer 1314 is preferably used as an insulating barrier film to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 1300. Therefore, the insulating layer 1314 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (making it difficult for the above-mentioned impurities to pass through). In addition, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0272] In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or both of the impurity and the oxygen. Furthermore, a membrane having the function of suppressing the diffusion of hydrogen or oxygen is sometimes referred to as a membrane that does not easily allow hydrogen or oxygen to pass through, a membrane with low hydrogen or oxygen permeability, a membrane that blocks hydrogen or oxygen, or a barrier membrane relative to hydrogen or oxygen, etc. Additionally, when the barrier membrane is conductive, it is sometimes referred to as a conductive barrier membrane.

[0273] For example, it is preferable to use an aluminum oxide film or a silicon nitride film as the insulating layer 1314. This suppresses the diffusion of impurities such as water or hydrogen from the side closer to the substrate than the insulating layer 1314 to the transistor 1300 side. Alternatively, it suppresses the diffusion of oxygen contained in the insulating layer 1324, etc., to the side closer to the substrate than the insulating layer 1314. Furthermore, the insulating layer 1314 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material, but can employ a stacked structure made of different materials. For example, a stack of aluminum oxide film and silicon nitride film can also be used.

[0274] For example, it is preferable to use a silicon nitride film formed by sputtering as the insulating layer 1314. This reduces the hydrogen concentration in the insulating layer 1314, thereby further suppressing the diffusion of impurities such as water or hydrogen from the side closer to the substrate than the insulating layer 1314 to the transistor 1300 side.

[0275] The dielectric constant of the insulating layer 1316, which is used as the interlayer film, is preferably lower than that of the insulating layer 1314. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, silicon oxide film, silicon oxynitride film, silicon oxynitride film, silicon nitride film, fluorine-added silicon oxide film, carbon-added silicon oxide film, carbon and nitrogen-added silicon oxide film, or porous silicon oxide film are suitable as the insulating layer 1316.

[0276] The insulating layer 1316 preferably includes regions with low hydrogen concentration and containing oxygen exceeding the stoichiometric composition (hereinafter also referred to as excess oxygen regions) or oxygen removed by heating (hereinafter also referred to as excess oxygen). For example, a silicon oxide film formed by sputtering is preferably used as the insulating layer 1316. This suppresses hydrogen incorporation into the oxide layer 1330 or supplies oxygen to the oxide layer 1330 to reduce oxygen vacancies. Therefore, a transistor with stable electrical characteristics and improved reliability can be provided by suppressing electrical characteristic variations.

[0277] Furthermore, the insulating layer 1316 may also have a laminated structure. For example, it may be possible to employ a structure in which at least the portion of the insulating layer 1316 in contact with the side of the conductive layer 1305 contains the same insulator as the insulating layer 1314. By employing this structure, oxygen oxidation of the conductive layer 1305 contained within the insulating layer 1316 can be suppressed. Alternatively, the reduction of the oxygen content in the insulating layer 1316 due to the conductive layer 1305 can be suppressed.

[0278] Conductive layer 1305 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage (V) of transistor 1300 can be controlled by individually changing the potential applied to conductive layer 1305 without linking it to the potential applied to conductive layer 1360.th In particular, by applying a negative potential to the conductive layer 1305, the V of the transistor 1300 can be increased. th The voltage is higher, which can reduce the off-state current. Therefore, applying a negative potential to the conductive layer 1305 can reduce the leakage current when the conductive layer 1360 is at a potential of 0V, compared to not applying a negative potential.

[0279] The conductive layer 1305 is configured to include a region overlapping with the oxide layer 1330 and the conductive layer 1360. Furthermore, the conductive layer 1305 is preferably disposed within the insulating layer 1314 or the insulating layer 1316.

[0280] like Figure 13B As shown, the conductive layer 1305 is preferably larger than the channel formation region in the oxide layer 1330. In particular, as Figure 13C As shown, the conductive layer 1305 preferably extends to the region outside the end of the oxide layer 1330 that intersects with the channel width direction. That is, preferably, the conductive layer 1305 and the conductive layer 1360 overlap with an insulating layer on the outer side of the side of the oxide layer 1330 in the channel width direction. With this structure, a region can be formed around the channel of the oxide layer 1330 by the electric field of the conductive layer 1360 used as the first gate electrode and the electric field of the conductive layer 1305 used as the second gate electrode.

[0281] like Figure 13C As shown, the conductive layer 1305 is extended to be used for wiring. However, the invention is not limited to this; a conductive layer used for wiring may also be provided under the conductive layer 1305. Furthermore, it is not necessary to provide a conductive layer 1305 in each transistor. For example, the conductive layer 1305 may be shared in multiple transistors.

[0282] Although an example is shown in which the conductive layer 1305 in transistor 1300 has a two-layer stacked structure (a first conductive layer on insulating layer 1314 and a second conductive layer on the first conductive layer), the present invention is not limited thereto. For example, the conductive layer 1305 may also be a single layer or a stacked structure having three or more layers. In the case of a structure having a stacked structure, ordinal numbers are sometimes assigned according to the order of formation for distinction.

[0283] Here, the first conductive layer 1305 preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0284] When the first conductive layer of conductive layer 1305 uses a conductive material that inhibits oxygen diffusion, the oxidation of the second conductive layer of conductive layer 1305, which would otherwise cause a decrease in conductivity, can be prevented. For example, tantalum, tantalum nitride, ruthenium, and ruthenium oxide are preferably used as conductive materials that inhibit oxygen diffusion. Therefore, the first conductive layer of conductive layer 1305 preferably employs a single-layer structure or a stacked structure using the aforementioned conductive materials. For example, the first conductive layer of conductive layer 1305 may also be a stack of tantalum film, tantalum nitride film, ruthenium film, or ruthenium oxide film and titanium film or titanium nitride film.

[0285] As the second conductive layer of conductive layer 1305, a conductive material with tungsten, copper, or aluminum as its main components is preferably used. Figure 13B In the above, the second conductive layer of conductive layer 1305 is a single layer, but the second conductive layer of conductive layer 1305 can also have a stacked structure, for example, a stack of titanium film or titanium nitride film and film containing the conductive material can be used.

[0286] Insulating layers 1322 and 1324 are used as gate insulating layers.

[0287] The insulating layer 1322 preferably has the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, the insulating layer 1322 preferably has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulating layer 1322 is preferably able to suppress the diffusion of one or both of hydrogen and oxygen compared to the insulating layer 1324.

[0288] As the material for the insulating layer 1322, an insulator containing one or both of aluminum and hafnium as insulating materials is preferably used. Aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate) are preferred as such insulators. When this material is used to form the insulating layer 1322, the insulating layer 1322 serves as a layer to suppress the release of oxygen from the oxide layer 1330 to the substrate side or the diffusion of impurities such as hydrogen from the periphery of the transistor 1300 into the oxide layer 1330. Therefore, by providing the insulating layer 1322, the diffusion of impurities such as hydrogen into the inside of the transistor 1300 can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide layer 1330. Furthermore, the reaction between the conductive layer 1305 and the oxygen contained in the insulating layer 1324 or the oxide layer 1330 can be suppressed.

[0289] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Furthermore, the insulator may be nitrided. Additionally, as insulating layer 1322, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film may be laminated on an insulating film containing the insulator.

[0290] As the insulating layer 1322, insulating materials including so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used, for example, in a single-layer or stacked structure. With the advancement of transistor miniaturization and high integration, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material as the insulating layer used as the gate insulating layer, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0291] In the insulating layer 1324 that contacts the oxide layer 1330, oxygen is preferably removed by heating. For example, a silicon oxide film, a silicon oxynitride film, or the like can be appropriately used as the insulating layer 1324. By providing an insulating layer containing oxygen in contact with the oxide layer 1330, oxygen vacancies in the oxide layer 1330 can be reduced, thereby improving the reliability of the transistor 1300.

[0292] Specifically, as the insulating layer 1324, an oxide material that allows a portion of the oxygen to be removed by heating is preferably used. An oxide layer that allows oxygen to be removed by heating refers to a layer where the amount of oxygen molecules removed, as converted to TDS (Thermal Desorption Spectroscopy) analysis, is 1.0 × 10⁻⁶. 18 molecules / cm 3 The preferred value is 1.0 × 10⁴. 19 molecules / cm 3 The above is further preferred to be 2.0×10 19 molecules / cm 3 The above, or 3.0×10 20 molecules / cm 3 The above-mentioned oxide layer. Furthermore, the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0293] The insulating layer 1324 preferably has a low hydrogen concentration and includes excess oxygen regions or excess oxygen, for example, it may also be made of the same material as the insulating layer 1316.

[0294] Insulating layer 1322 and insulating layer 1324 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material, but may also be a stacked structure made of different materials.

[0295] The oxide layer 1330 preferably has a stacked structure of oxides with different chemical compositions. Specifically, in the metal oxide used for oxide layer 1330a, the atomic ratio of element M to the main component metal element is preferably greater than that of the metal oxide used for oxide layer 1330b. Furthermore, in the metal oxide used for oxide layer 1330a, the atomic ratio of element M to In is preferably greater than that of the metal oxide used for oxide layer 1330b. Additionally, in the metal oxide used for oxide layer 1330b, the atomic ratio of In to element M is preferably greater than that of the metal oxide used for oxide layer 1330a. Furthermore, oxide layer 1330c can use a metal oxide that can be used for oxide layer 1330a or oxide layer 1330b.

[0296] Oxide layers 1330b and 1330c are preferably crystalline. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen defects). Therefore, oxygen extraction from the source or drain electrode from the oxide layer 1330b can be suppressed. Thus, even with heat treatment, oxygen extraction from the oxide layer 1330b can be reduced, and the transistor 1300 is also stable against the high temperatures (so-called thermal budget) in the manufacturing process.

[0297] As oxide layer 1330c, CAAC-OS is preferably used, and the c-axis of the crystals included in oxide layer 1330c is preferably oriented in a direction substantially perpendicular to the formed surface or top surface of oxide layer 1330c. CAAC-OS has the property of readily moving oxygen in a direction perpendicular to the c-axis. Therefore, the oxygen included in oxide layer 1330c can be efficiently supplied to oxide layer 1330b.

[0298] Preferably, the energy levels of the conduction band bottom of oxide layers 1330a and 1330c are higher than the energy levels of the conduction band bottom of oxide layer 1330b. In other words, the electron affinity of oxide layers 1330a and 1330c is preferably lower than that of oxide layer 1330b. In this case, oxide layer 1330c is preferably made of a metal oxide that can be used for oxide layer 1330a. At this time, the main path of charge carriers is oxide layer 1330b.

[0299] Here, at the junction of oxide layers 1330a, 1330b, and 1330c, the energy level at the conduction band bottom changes gradually. In other words, it can also be expressed as the energy level at the conduction band bottom of the junction of oxide layers 1330a, 1330b, and 1330c changing continuously or continuously joining. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide layers 1330a and 1330b, and at the interface between oxide layers 1330b and 1330c.

[0300] Specifically, by including common elements as main components other than oxygen in oxide layers 1330a and 1330b, and in oxide layers 1330b and 1330c, a mixed layer with low defect state density can be formed. For example, when oxide layer 1330b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can be used as oxide layers 1330a and 1330c.

[0301] Specifically, for oxide layer 1330a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or 1:1:0.5 (atomic ratio) can be used. Furthermore, for oxide layer 1330b, a metal oxide with an In:Ga:Zn ratio of 1:1:1 or 4:2:3 (atomic ratio) can be used. Furthermore, for oxide layer 1330c, a metal oxide with an In:Ga:Zn ratio of 1:3:4, 4:2:3, 2:1, or 2:5 (atomic ratio) can be used.

[0302] Furthermore, when forming metal oxides by sputtering, the aforementioned atomic ratio is not limited to the atomic ratio of the metal oxides formed, but can also be the atomic ratio of the sputtering target used for forming the metal oxides.

[0303] By equipping oxide layers 1330a and 1330c with the aforementioned structure, the defect state density at the interfaces between oxide layers 1330a and 1330b, and between oxide layers 1330b and 1330c, can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, resulting in high on-state current and high frequency characteristics for transistor 1300.

[0304] The oxide layer 1330c may also have a stacked structure of two or more layers. For example, the oxide layer 1330c may also have a first oxide layer and a second oxide layer on the first oxide layer.

[0305] The first oxide layer of oxide layer 1330c preferably includes at least one of the metal elements constituting the metal oxide for oxide layer 1330b, and more preferably includes all of these metal elements. For example, an In-Ga-Zn oxide film is preferably used as the first oxide layer of oxide layer 1330c, while an In-Ga-Zn oxide film, a Ga-Zn oxide film, or a gallium oxide film is preferably used as the second oxide layer of oxide layer 1330c. This reduces the defect state density at the interface between oxide layer 1330b and the first oxide layer of oxide layer 1330c. Furthermore, the second oxide layer of oxide layer 1330c preferably suppresses oxygen diffusion or permeation compared to the first oxide layer of oxide layer 1330c. By providing the second oxide layer of oxide layer 1330c between insulating layer 1350 and the first oxide layer of oxide layer 1330c, the diffusion of oxygen contained in insulating layer 1380 to insulating layer 1350 can be suppressed. Therefore, the oxygen can easily pass through the first oxide layer of oxide layer 1330c and be received by oxide layer 1330b.

[0306] Preferably, the energy level of the conduction band bottom of the second oxide layer of oxide layers 1330a and 1330c is higher than the energy level of the conduction band bottom of the first oxide layer of oxide layers 1330b and 1330c. Furthermore, in other words, the electron affinity of the second oxide layer of oxide layers 1330a and 1330c is preferably less than the electron affinity of the first oxide layer of oxide layers 1330b and 1330c. In this case, the second oxide layer of oxide layer 1330c is preferably made of a metal oxide that can be used for oxide layer 1330a, and the first oxide layer of oxide layer 1330c is preferably made of a metal oxide that can be used for oxide layer 1330b. At this time, not only oxide layer 1330b becomes the main path for charge carriers, but the first oxide layer of oxide layer 1330c also becomes the main path for charge carriers.

[0307] As the conductive layer 1342, the above-mentioned TaN is preferably used. x O y In addition, TaN x O y Aluminum may also be included. For example, titanium nitride, nitrides containing titanium and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. These materials are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen, so they are preferred.

[0308] like Figure 13BAs shown, the insulating layer 1354 preferably contacts the top and side surfaces of the conductive layer 1342a, the top and side surfaces of the conductive layer 1342b, the side surfaces of the oxide layers 1330a and 1330b, and a portion of the top surface of the insulating layer 1324. With this structure, the insulating layer 1354 separates the insulating layer 1380 from the insulating layer 1324, the oxide layers 1330a and 1330b.

[0309] Like insulating layer 1322, insulating layer 1354 also has the function of suppressing the diffusion of one or both of hydrogen and oxygen. For example, compared with insulating layers 1324 and 1380, insulating layer 1354 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen. Thus, the diffusion of hydrogen contained in insulating layer 1380 into oxide layers 1330a and 1330b can be suppressed. Furthermore, the surrounding of insulating layers 1322 and 1354 with insulating layers 1324 and oxide layers 1330 can suppress the diffusion of impurities such as water and hydrogen from the outside into insulating layers 1324 and oxide layers 1330. Therefore, transistor 1300 can be endowed with good electrical characteristics and reliability.

[0310] As the insulating layer 1354, an insulating film comprising one or more oxides of aluminum and hafnium can be formed, for example. In this case, the insulating layer 1354 is preferably formed using atomic layer deposition (ALD). Because the ALD method has high coverage, it can prevent the insulating layer 1354 from being broken due to unevenness.

[0311] As the insulating layer 1354, an insulating film containing aluminum nitride can be used, for example. Therefore, a film with high insulation and high thermal conductivity can be formed, thereby improving the heat dissipation generated when driving the transistor 1300. Alternatively, silicon nitride or silicon oxynitride can also be used.

[0312] As the insulating layer 1354, gallium-containing oxides can be used, for example. Gallium-containing oxides sometimes have the function of suppressing the diffusion of one or both of hydrogen and oxygen, so they are preferred. In addition, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, etc., can also be used as gallium-containing oxides. Furthermore, when an indium gallium zinc oxide film is used as the insulating layer 1354, the number of gallium atoms relative to indium is preferably larger. This improves the insulation of the oxide film.

[0313] The insulating layer 1350 is used as the gate insulating layer. The insulating layer 1350 is preferably disposed in contact with the top surface of the oxide layer 1330c. The material of the insulating layer 1350 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, silicon oxide with both carbon and nitrogen, porous silicon oxide, etc. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0314] Like insulating layer 1324, insulating layer 1350 is preferably formed using an insulating film that releases oxygen upon heating. By providing an insulating film that releases oxygen upon heating as a contact point between insulating layer 1350 and oxide layer 1330c, oxygen can be effectively supplied to the channel formation region of oxide layer 1330b, thereby reducing oxygen vacancies in the channel formation region of oxide layer 1330b. Therefore, a transistor with stable electrical characteristics and improved reliability can be provided by suppressing electrical characteristic variations. Similar to insulating layer 1324, it is preferable to reduce the concentration of impurities such as water or hydrogen in insulating layer 1350. The thickness of insulating layer 1350 is preferably 1 nm or more and 20 nm or less.

[0315] The conductive layer 1360 preferably includes a conductive layer 1360a and a conductive layer 1360b on the conductive layer 1360a. For example, the conductive layer 1360a is preferably arranged to surround the bottom and side surfaces of the conductive layer 1360b.

[0316] The conductive layer 1360a preferably uses the aforementioned conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0317] When the conductive layer 1360a has the function of inhibiting oxygen diffusion, it can prevent the oxygen contained in the insulating layer 1350 from oxidizing the conductive layer 1360b and causing a decrease in conductivity. As a conductive material with the function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used, for example.

[0318] Since the conductive layer 1360 is also used for wiring, it is preferable to use a conductive material with high conductivity. For example, as the conductive layer 1360b, a conductive material with tungsten, copper, or aluminum as the main components can be used. The conductive layer 1360b can also have a stacked structure, for example, a stacked structure of titanium film, titanium nitride film, and film containing the above-mentioned conductive material can be used.

[0319] exist Figures 13A to 13C In the process, the conductive layer 1360 has a two-layer structure of conductive layer 1360a and conductive layer 1360b, but it can be a single-layer structure or a stacked structure of three or more layers.

[0320] In transistor 1300, a conductive layer 1360, which serves as a gate electrode, is formed in a self-aligned manner by filling the openings formed in the insulating layer 1380, etc. By forming the conductive layer 1360 in this way, the conductive layer 1360 can be reliably disposed in the region between the conductive layers 1342a and 1342b without alignment.

[0321] like Figure 13B As shown, the top surface of the conductive layer 1360 is roughly the same as the top surface of the insulating layer 1350 and the top surface of the oxide layer 1330c.

[0322] like Figure 13C As shown, in the channel width direction of transistor 1300, the height of the bottom surface of the region in conductive layer 1360 that does not overlap with oxide layer 1330b, with the bottom surface of insulating layer 1322 as the standard, is preferably lower than the height of bottom surface of oxide layer 1330b. By adopting a structure in which conductive layer 1360, used as a gate electrode, covers the sides and top surfaces of the channel formation region of oxide layer 1330b through insulating layer 1350, etc., the electric field of conductive layer 1360 can easily act on the entire portion of the channel formation region of oxide layer 1330b. Therefore, the on-state current of transistor 1300 can be increased to improve frequency characteristics.

[0323] An insulating layer 1380 is disposed on an insulating layer 1324, an oxide layer 1330, and a conductive layer 1342, with an insulating layer 1354 in between. Furthermore, the top surface of the insulating layer 1380 can also be planarized.

[0324] The dielectric constant of the insulating layer 1380, used as the interlayer film, is preferably low. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between the wirings can be reduced. The insulating layer 1380 is preferably made of the same material as the insulating layer 1316, for example. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen that has been released by heating.

[0325] The concentration of impurities such as water and hydrogen in the insulating layer 1380 is preferably reduced. Furthermore, the insulating layer 1380 preferably has a low hydrogen concentration and includes regions or areas of excess oxygen; for example, it may be constructed using the same material as the insulating layer 1316. Additionally, the insulating layer 1380 may have a multilayer structure with two or more layers.

[0326] The insulating layer 1374 is preferably used, like the insulating layer 1314, as an insulating barrier film to inhibit the diffusion of impurities such as water and hydrogen from above to the insulating layer 1380. Furthermore, the insulating layer 1374, like the insulating layer 1314, preferably has a low hydrogen concentration and functions to inhibit hydrogen diffusion.

[0327] like Figure 13B As shown, insulating layer 1374 is preferably in contact with the top surface of each of conductive layer 1360, insulating layer 1350, and oxide layer 1330c. This suppresses the incorporation of impurities such as hydrogen contained in insulating layer 1381 into insulating layer 1350. Therefore, negative impacts on the electrical characteristics and reliability of the transistor can be suppressed.

[0328] Preferably, an insulating layer 1381, which serves as an interlayer film, is provided on the insulating layer 1374. The dielectric constant of the insulating layer 1381 is preferably as low as that of the insulating layer 1316, etc. Similar to the insulating layer 1324, it is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 1381 is reduced.

[0329] Conductive layers 1340a and 1340b are disposed in openings formed in insulating layers 1381, 1374, 1380, and 1354. Conductive layers 1340a and 1340b are disposed with a conductive layer 1360 sandwiched between them. Furthermore, the height of the top surface of conductive layers 1340a and 1340b can be the same as the height of the top surface of insulating layer 1381.

[0330] Furthermore, an insulating layer 1341a is provided in contact with the sidewalls of the openings of insulating layers 1381, 1374, 1380, and 1354, and a conductive layer 1340a is formed in contact with its sidewalls. A conductive layer 1342a is located at least a portion of the bottom of the opening, and the conductive layer 1340a is in contact with the conductive layer 1342a. Similarly, an insulating layer 1341b is provided in contact with the sidewalls of the openings of insulating layers 1381, 1374, 1380, and 1354, and a conductive layer 1340b is formed in contact with its sidewalls. A conductive layer 1342b is located at least a portion of the bottom of the opening, and the conductive layer 1340b is in contact with the conductive layer 1342b.

[0331] The conductive layers 1340a and 1340b are preferably made of conductive materials with tungsten, copper or aluminum as the main components.

[0332] Conductive layers 1340a and 1340b may also have a stacked structure. Note that transistor 1300 is shown with conductive layers 1340a and 1340b arranged in a two-layer stacked structure, but the present invention is not limited thereto. For example, conductive layer 1340 may be a single layer or a stacked structure of three or more layers.

[0333] As insulating layers 1341a and 1341b, insulating films suitable for insulating layers 1314, 1354, etc., can be used. Because insulating layers 1341a and 1341b are disposed in contact with insulating layer 1354, the diffusion of impurities such as water or hydrogen contained in insulating layer 1380 through conductive layers 1340a and 1340b to oxide layer 1330 can be suppressed. Furthermore, the absorption of oxygen contained in insulating layer 1380 by conductive layers 1340a and 1340b can be prevented.

[0334] Although not shown, the conductor used for wiring can be configured to contact the top surfaces of conductive layers 1340a and 1340b. The conductive layer used for wiring preferably uses a conductive material with tungsten, copper, or aluminum as its main components. Furthermore, the conductor can have a laminated structure, for example, a laminated structure of a titanium film, a titanium nitride film, and a film containing the aforementioned conductive material. Additionally, the conductive layer can also be formed by embedding it within an opening in an insulating layer.

[0335] Furthermore, although not illustrated, it is preferable to set its resistivity to 1.0 × 10⁻⁶ in such a way that it covers the aforementioned conductive layer. 13 Ωcm or more and 1.0×10 15 Below Ωcm, preferably 5.0 × 10 13 Ωcm or more and 5.0×10 14 An insulating layer with a resistivity of less than Ωcm. By providing an insulating layer with the above resistivity on the conductive layer, the insulating layer can not only maintain insulation, but also disperse the charge accumulated between the transistor 1300 and the wiring of the conductive layer, etc., thereby suppressing the malfunction or electrostatic damage of the transistor or electronic device having the transistor caused by the charge, which is preferred.

[0336] Furthermore, since the size of the transistors shown in this embodiment can be reduced, it is easy to improve precision and apply them to smaller electronic devices.

[0337] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0338] (Implementation Method 3)

[0339] In this embodiment, a semiconductor device incorporating a latching circuit as shown in Embodiment 1 will be described. First, the ternary counting circuit shown in FIG2 will be described. Figure 3 The hexadecimal counting circuit shown Figure 5The example shown illustrates the application of the output of a decimal counting circuit to a clock. Next, examples of applying the outputs of ternary, hexadecimal, and decimal counting circuits to a battery protection IC are explained.

[0340] Figure 15 This is a block diagram illustrating a semiconductor device 80. The semiconductor device 80 includes a control circuit 81, an oscillator 82, a frequency divider 83, circuits 84a, 84b, and 84c, a decoding circuit 86, a selection circuit 87, and display devices 88a to 88f. Furthermore, the semiconductor device 80 includes a battery protection IC 90. Circuit 84a includes a decimal counter circuit 85a and a hexadecimal counter circuit 85b. Circuit 84b includes a decimal counter circuit 85a and a hexadecimal counter circuit 85b. Circuit 84c includes a decimal counter circuit 85a and a ternary counter circuit 85c.

[0341] Oscillator 82 is electrically connected to frequency divider 83. Frequency divider 83 is electrically connected to decimal counting circuit 85a of circuit 84. Furthermore, as... Figure 15 As shown, the frequency divider 83 may also be included in the control circuit 81. The control circuit 81 is electrically connected to circuits 84a, 84b, 84c, the decoding circuit 86, and the selection circuit 87. Circuit 84a is electrically connected to the decoding circuit 86. Circuit 84b is electrically connected to the decoding circuit 86. Circuit 84c is electrically connected to the decoding circuit 86. The decoding circuit 86 is electrically connected to the selection circuit 87. The selection circuit 87 is electrically connected to each of the display devices 88a to 88f.

[0342] The control circuit 81 may also include a frequency divider 83. Because the control circuit 81 includes a frequency divider 83, clock signals P0 to P5 can be easily generated. In addition, signals PRE and EN1, and selection signals sel0 to sel2, which are provided to the decoding circuit 86, can also be easily generated.

[0343] Circuit 84a's decimal counting circuit 85a outputs signal ss1 to decoding circuit 86. Circuit 84a's hexadecimal counting circuit 85b outputs signal ss2 to decoding circuit 86. Circuit 84b's decimal counting circuit 85a outputs signal mm1 to decoding circuit 86. Circuit 84b's hexadecimal counting circuit 85b outputs signal mm2 to decoding circuit 86. Circuit 84c's decimal counting circuit 85a outputs signal hh1 to decoding circuit 86. Circuit 84c's ternary counting circuit 85c outputs signal hh2 to decoding circuit 86.

[0344] Furthermore, the decoding circuit 86 is preferably constructed from a dynamic circuit. The signal PRE provides the timing for pre-charging in the dynamic circuit. The signal EN1 is used to select any output of circuits 84a, 84b, and 84c. Based on the selection signals sel0 to sel2, the content displayed by display devices 88a to 88f can be selected. For example, display devices 88a to 88f include a first to a seventh segment. By activating multiple segments from the first to the seventh segment, the numbers 0 to 9 can be displayed.

[0345] Therefore, display device 88a receives signal s1 to display the first digit of the seconds. Display device 88b receives signal s2 to display the second digit of the seconds. Display device 88c receives signal m1 to display the first digit of the minutes. Display device 88d receives signal m2 to display the second digit of the minutes. Display device 88e receives signal h1 to display the first digit of the hours. Display device 88f receives signal h2 to display the second digit of the hours. Therefore, semiconductor device 80 is used as a clock.

[0346] In addition, the decoding circuit 86 can output signal mn1 to the battery protection IC90.

[0347] Next, the battery protection IC90 will be explained. The battery protection IC90 includes a battery and detection circuitry. Furthermore, the battery protection IC90 can also be referred to as a detection device. The battery protection IC90 includes detection circuitry that is used to detect battery fault modes, not to manage the power supply voltage. For example, in lithium-ion batteries, a fault known as a micro-short circuit (also called an internal short circuit or soft short circuit) occurs. A micro-short circuit is a fault mode in which a short circuit occurs between the positive and negative electrodes due to lithium metal deposited at the negative electrode growing to the positive electrode, causing a slight drop in battery voltage. The signal mn1 output from the decoder circuit 86 to the battery protection IC90 can be used as a monitoring cycle for this fault mode.

[0348] In this specification, the battery protection IC90 using the above-described latch circuit or counting circuit will be referred to as BTOS (Battery operating system or Battery oxide semiconductor). BTOS includes an OS transistor.

[0349] Furthermore, in this embodiment, reference is made to Figure 16A and Figure 16B This section describes the battery protection IC90. The micro short-circuit detection circuit (micro short-circuit detector) of the battery protection IC90 is formed using an N-type transistor. Alternatively, the micro short-circuit detection circuit can use transistors containing metal oxide in the semiconductor layer.

[0350] Figure 16AThis is a block diagram showing a battery protection IC 90, a charger (battery charger), and a control unit (mobile device). As an example, the battery protection IC 90 may also include a charger and a control unit as components. The battery protection IC includes circuitry formed using CMOS technology (CMOS layer), and circuitry for detecting micro-short circuits formed by transistors containing metal-oxide-semiconductor layers in the semiconductor layer. It also includes a micro-short circuit detection circuit (micro-short circuit detector), an overcharge detection circuit (overcharge detector) for managing the power supply voltage, an over-discharge detection circuit (over-discharge detector), an overcurrent detection circuit (charging overcurrent detector and discharging overcurrent detector), or a delay circuit, etc. The signal mn1 is received by the micro-short circuit detection circuit or the delay circuit.

[0351] Figure 16B This is a perspective view of a circuit (logic circuit) formed using CMOS technology and a circuit (analog memory and analog circuit) formed by transistors containing metal oxides in a semiconductor layer, stacked together for detecting micro-short circuits. It shows examples of overcharge detection circuits, over-discharge detection circuits, overcurrent detection circuits, or delay circuits formed using CMOS technology to manage power supply voltage. The micro-short circuit is formed by overlapping the circuit formed using CMOS technology to manage power supply voltage. The micro-short circuit can be formed using only N-type transistors, thereby reducing the layout area. Furthermore, by stacking the micro-short circuit with other circuits, wiring can be shortened. Moreover, CMOS technology preferably uses monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, etc. In particular, polycrystalline silicon can be formed at lower temperatures compared to monocrystalline silicon and has higher field-effect mobility and reliability compared to amorphous silicon.

[0352] The clock and micro-short-circuit detection circuit, including the counting circuit using the dynamic circuit shown in Embodiment 1, can be formed using only the same N-type transistors, thereby simplifying the manufacturing process. Furthermore, by using OS transistors, off-state current can be reduced, thereby lowering power consumption.

[0353] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0354] (Implementation Method 4)

[0355] In this embodiment, a metal oxide that can be applied to the channel formation region of a transistor is described.

[0356] As semiconductor materials for transistors, metal oxides with a bandgap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typically, metal oxides containing indium, such as CAC-OS described later, can be used.

[0357] Furthermore, transistors using metal oxides, which have a wider bandgap than silicon and a lower carrier density, are able to retain the charge stored in a capacitor connected in series with the transistor for extended periods due to their low off-state current.

[0358] For example, a film containing indium, zinc, and M (metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be used as a semiconductor layer, as shown in "In-M-Zn type oxide".

[0359] When the metal oxide constituting the semiconductor layer is an In-M-Zn type oxide, it is preferable that the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film satisfies In≥M and Zn≥M. Preferred atomic ratios of the metal elements in this sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, and In:M:Zn = 5:1:8. Note that the atomic ratio of the formed semiconductor layer can vary within ±40% of the atomic ratio of the metal elements in the sputtering target described above.

[0360] Metal oxide films with low carrier density can be used as semiconductor layers. For example, a semiconductor layer with a carrier density of 1 × 10⁻⁶ can be used. 17 / cm 3 The following is preferred: 1×10 15 / cm 3 Hereinafter, 1×10 is more preferred. 13 / cm 3 Hereinafter, 1×10 is further preferred. 11 / cm 3 The following is a further preferred option: less than 1×10 10 / cm 3 1×10 9 / cm 3 The above-mentioned metal oxides are referred to as high-purity intrinsic or substantially high-purity intrinsic metal oxides. These metal oxides have a low defect state density and can be considered to possess stable properties.

[0361] Note that the present invention is not limited to the above description, and an oxide semiconductor with an appropriate composition can be used according to the desired semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier density, impurity concentration, defect density, ratio of metal elements to oxygen atoms, interatomic distance, density, etc., of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0362] When the metal oxide constituting the semiconductor layer contains silicon or carbon, one of Group 14 elements, the oxygen defects in the semiconductor layer increase, causing the semiconductor layer to become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0363] Furthermore, sometimes when alkali metals and alkaline earth metals bond with metal oxides, charge carriers are generated, increasing the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer, measured by secondary ion mass spectrometry, was set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0364] Furthermore, when the metal oxide constituting the semiconductor layer contains nitrogen, electrons are generated as charge carriers, increasing the charge carrier density and facilitating n-type conversion. As a result, transistors using nitrogen-containing metal oxides tend to exhibit always-on characteristics. Therefore, the nitrogen concentration of the semiconductor layer, as measured by secondary ion mass spectrometry, is preferably 5 × 10⁻⁶. 18 atoms / cm 3 the following.

[0365] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0366] The semiconductor layer of the transistor disclosed as one aspect of the present invention can also be CAC-OS (Cloud-Aligned Composite oxide semiconductor).

[0367] The semiconductor layer of the transistor disclosed in one embodiment of the present invention can use the aforementioned non-single-crystal oxide semiconductor or CAC-OS. Furthermore, nc-OS or CAAC-OS is preferred as the non-single-crystal oxide semiconductor.

[0368] In one embodiment of the invention, CAC-OS is preferably used as the semiconductor layer of the transistor. By using CAC-OS, the transistor can be endowed with high electrical characteristics or high reliability.

[0369] The semiconductor layer can also be a hybrid film comprising two or more of the following regions: CAAC-OS, polycrystalline oxide semiconductor, nc-OS, a-like OS, and amorphous oxide semiconductor. Hybrid films sometimes have, for example, a single-layer structure or a stacked structure comprising two or more of the aforementioned regions.

[0370] The following describes the configuration of a CAC (Cloud-Aligned Composite)-OS in a transistor that can be used in one aspect of the present invention.

[0371] CAC-OS, for example, refers to a composition in which elements are disproportionately distributed within a metal oxide, wherein the size of the material containing the disproportionately distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately. Note that the state in which one or more metal elements are disproportionately distributed within a metal oxide and the regions containing those metal elements are mixed is also referred to below as mosaic or patch-like, wherein the size of such regions is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately.

[0372] The metal oxide preferably contains at least indium. In particular, it preferably contains both indium and zinc. In addition, it may also contain one or more of the following: aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0373] For example, CAC-OS in In-Ga-Zn oxides (in particular, In-Ga-Zn oxides can be referred to as CAC-IGZO) refers to materials that are indium oxides (hereinafter referred to as InO). X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) and gallium oxide (hereinafter referred to as GaO) X3 (X3 is a real number greater than 0) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) etc., thus forming a mosaic pattern, and the mosaic-shaped InO X1or In X2 Zn Y2 O Z2 The composition (hereinafter also referred to as cloud-like) is uniformly distributed in the membrane.

[0374] In other words, CAC-OS is a system with GaO X3 The region with In as the main component and X2 Zn Y2 O Z2 or InO X1 A composite metal oxide consisting of regions that are the main components mixed together. In this specification, for example, when the atomic ratio of In to element M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0375] Note that IGZO is a general term, sometimes referring to compounds containing In, Ga, Zn, and O. A typical example is InGaO3 (ZnO). m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is any number) shows crystalline compounds.

[0376] The aforementioned crystalline compounds have single-crystal, polycrystalline, or CAAC structures. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0377] On the other hand, CAC-OS is related to the material composition of metal oxides. CAC-OS refers to a material composition containing In, Ga, Zn, and O, in one part of which nanoparticle-like regions with Ga as the main component are observed, and in another part, nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0378] CAC-OS does not contain stacked structures consisting of two or more different membranes. For example, it does not contain a structure consisting of two layers: one with In as the main component and the other with Ga as the main component.

[0379] Note that sometimes GaO cannot be observed. X3 Regions with In as the main component X2 Zn Y2 O Z2 or InO X1 Clear boundaries between regions that are the main components.

[0380] In the case where CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium to replace gallium, CAC-OS refers to a composition in which nanoparticle-like regions with the metal element as the main component are observed in one part, and nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern in another part.

[0381] CAC-OS can be formed, for example, by sputtering without heating the substrate. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gases, and nitrogen gases can be used as the film-forming gas. Furthermore, the lower the proportion of oxygen gas in the total flow rate of the film-forming gas during film formation, the better; for example, it is preferable to set the oxygen gas flow rate to 0% or more and less than 30%, and more preferably 0% or more and less than 10%.

[0382] CAC-OS has the following characteristics: when measured using the out-of-plane method (XRD), one of the X-ray diffraction measurement methods, with θ / 2θ scanning, no clear peak is observed. In other words, according to X-ray diffraction measurements, there is no orientation in the ab plane direction or the c-axis direction within the measurement region.

[0383] Furthermore, in the electron diffraction pattern of CAC-OS obtained by irradiating it with an electron beam with a diameter of 1 nm (also known as a nanobeam), a ring-shaped region of high brightness (ring region) and multiple bright spots within the ring region were observed. Therefore, based on the electron diffraction pattern, it can be concluded that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is unoriented in both the planar and cross-sectional directions.

[0384] Furthermore, for example, in CAC-OS of In-Ga-Zn oxides, based on EDX surface mapping images obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that: [the structure exhibits characteristics of GaO]. X3 Regions with In as the main component and X2 Zn Y2 O Z2 or InO X1 The composition is a mixture of components with regional deviations in their distribution.

[0385] CAC-OS differs in structure from IGZO compounds, which have a uniform distribution of metallic elements, and thus exhibits different properties. In other words, CAC-OS possesses properties centered around GaO. X3Regions with In as the main component and In X2 Zn Y2 O Z2 or InO X1 The regions that are the main components are separated from each other, and the regions that are the main components of each element are mosaic-like.

[0386] Here, in In X2 Zn Y2 O Z2 or InO X1 The conductivity of regions with GaO as the main component is higher than that of regions with GaO as the main component. X3 The region is dominated by components such as In. In other words, when charge carriers flow through a region dominated by In X2 Zn Y2 O Z2 or InO X1 When In is the main component, it exhibits the conductivity of metal oxides. Therefore, when In... X2 Zn Y2 O Z2 or InO X1 When the region that is the main component is distributed in a cloud-like manner in a metal oxide, a high field-effect mobility (μ) can be achieved.

[0387] On the other hand, with GaO X3 The insulation of regions with In as the main component is higher than that of regions with In as the main component. X2 Zn Y2 O Z2 or InO X1 The region where GaO is the main component. In other words, when GaO is used... X3 When regions with these as the main components are distributed in metal oxides, leakage current can be suppressed, thus achieving good switching operation.

[0388] Therefore, when CAC-OS is used in semiconductor devices, it is due to GaO X3 The insulation properties of etc. and their causes in In X2 Zn Y2 O Z2 or InO X1 The complementary effect of conductivity can achieve high on-state current (I) on ) and high field-effect mobility (μ).

[0389] Furthermore, semiconductor components using CAC-OS exhibit high reliability. Therefore, CAC-OS is best suited for use in various semiconductor devices such as displays.

[0390] Because transistors with CAC-OS in the semiconductor layer have high field-effect mobility and high driving capability, using these transistors in driving circuits, typically scan line driving circuits for generating gate signals, can provide display devices with narrow bezel widths. Furthermore, by using these transistors in signal line driving circuits included in the display device (especially demultiplexers connected to the output terminals of shift registers included in the signal line driving circuits), display devices with fewer wiring connections to the display device can be provided.

[0391] Furthermore, unlike transistors using low-temperature polycrystalline silicon, transistors with CAC-OS in the semiconductor layer do not require a laser crystallization process. This reduces manufacturing costs even for display devices using large-area substrates. Moreover, in large-scale display devices with high resolutions, such as those referred to as "4K resolution," "4K2K," or "4K" Ultra High-Definition, and those referred to as "8K resolution," "8K4K," or "8K" Super High-Definition, using transistors with CAC-OS in the semiconductor layer for the drive circuitry and display section allows for faster writing and reduces display defects, making it a preferred option.

[0392] Alternatively, silicon can be used in semiconductors to form channels for transistors. Amorphous silicon can be used as the silicon, but crystalline silicon is particularly preferred. For example, microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon are preferred. In particular, polycrystalline silicon can be formed at lower temperatures compared to monocrystalline silicon, and it has higher field-effect mobility and higher reliability compared to amorphous silicon.

[0393] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0394] (Implementation Method 5)

[0395] In this embodiment, an example of an electronic device capable of using a semiconductor device according to one aspect of the present invention will be described.

[0396] exist Figure 17A In this document, an electronic device 500 using the semiconductor device described in Embodiment 1 or Embodiment 3 will be described.

[0397] Electronic device 500 includes semiconductor device 80 (not shown), battery protection IC 90 (not shown), processor (not shown), memory (not shown), battery (not shown), image processing circuit (not shown), communication module (not shown) or sensing device, etc.

[0398] Electronic device 500 includes a portable terminal 502. The portable terminal includes a watch 502a, email sending and receiving 502b, communication functions 502c, battery management 502d, calendar 502e, and call function, etc. The portable terminal is disposed on the outside of electronic device 500, and the sensing device is disposed on the inside of electronic device 500.

[0399] The sensing device includes light-emitting regions (531a, 531b) and sensing regions (541a, 541b, 541c). The light-emitting regions (531a, 531b) can emit light with different peak wavelengths. Since the sensing regions (541a, 541b, 541c) encompass the peak wavelengths of the light emitted from each light-emitting region within their detection range, light with different peak wavelengths can be detected simultaneously.

[0400] As an example Figure 17B This diagram shows an electronic device 500 mounted on the wrist. By arranging the sensing device inwards, it can be used as a biomonitor. For example, by detecting the amount of glucose in the blood, blood glucose levels can be managed. The signal mn1 generated by the semiconductor device 80 can set the monitoring cycle for detecting blood glucose levels. The detected glucose level is stored as data in the mobile terminal's memory, allowing management of daily changes in blood glucose levels. Furthermore, by managing changes in blood glucose levels, the electronic device 500 can notify diabetic patients of insulin dosing schedules via vibration, display content, or lighting. This data can also be sent to a server via the communication function 502c. Moreover, the managed object is not limited to glucose. For example, hemoglobin levels can also be detected. As another example, changes in body temperature can be detected. Furthermore, the semiconductor device 80, being constructed with dynamic circuitry, can reduce power consumption to acquire long-term data.

[0401] Figure 18A This is a biometric device, including a thin frame 911, operation buttons 912, and a sensing device 913. The shape of veins can be identified by placing a hand or finger on or in close contact with the sensing device 913. The signal mn1 generated by the semiconductor device 80 can be set to monitor how the vein shape changes over time. Individuals can be identified by sending the acquired data to a server via a wireless communication unit 914 and comparing it with a database. Alternatively, a password can be entered using the operation buttons. In one embodiment of the invention, the sensing device 913 can be formed into a thin authentication device with a light-emitting area and a sensing area. Because it is thin, it is easy to install in various devices. Furthermore, portability is improved.

[0402] Figure 18BThis is a non-destructive testing device, including a housing 921, an operation panel 922, a conveying mechanism 923, a display 924, and a testing unit 925. The testing unit 925 has a sensing device. The component 926 to be tested is conveyed to the bottom of the testing unit 925 by the conveying mechanism 923. The sensing device 927, according to one embodiment of the invention, located within the testing unit 925, captures an image of the component 926, and the display 924 shows the captured image. Furthermore, the conveying mechanism 923 and the sensing device 927 preferably operate synchronously with a signal mn1 generated by the semiconductor device 80. The component 926 is then conveyed to the exit of the housing 921, where defective products are sorted and recycled. By using near-infrared light for imaging, defects or foreign objects in non-tested components can be detected non-destructively and at high speed. The sensing device 927, according to one embodiment of the invention, may include a light-emitting area and a sensing area, thus allowing the testing unit 925 to be formed inexpensively.

[0403] Figure 18C This is a food sorting device, including a frame 931, operation buttons 932, a display unit 933, and a light-shielding cover 934. By closely contacting the light-shielding cover 934, which is located around the light-receiving part, with the food being tested, such as fruit, and taking pictures, foreign objects, insects, and internal cavities or spoilage can be detected in the food. Furthermore, the sugar content or water content of the food can be detected based on the intensity of the detected infrared light. The food sorting device can classify defective products or grades, or determine the harvest period. Furthermore, since the near-infrared light suitable for detecting sugar content is different from the near-infrared light suitable for detecting water content, the near-infrared light preferably has multiple wavelengths. The signal mn1 generated by the semiconductor device 80 preferably manages the irradiation time of the multiple near-infrared lights. Since the sensing device 935 of one embodiment of the present invention, located in the light-receiving part, has a light-emitting area and a sensing area, a thin, lightweight, and highly portable food sorting device can be inexpensively formed. Furthermore, it is also possible to... Figure 18B The structure shown is used as a food sorting device. Alternatively, it can also be used... Figure 18C The structure shown is used as a non-destructive testing device.

[0404] Figure 19A1 An example is shown where multiple sensor modules are mounted on the body. The sensor module includes at least one of an infrared sensor, a near-infrared sensor, a temperature sensor, and an accelerometer, and also includes a secondary battery, a detection device, or a communication module. This sensor module has functions such as sampling inductive waveforms used in electrocardiograms, detecting body temperature, detecting pulse, detecting blood glucose levels, and detecting the workload of limbs.

[0405] Figure 19A1An example is shown where sensor modules LA, RA, LL, and RL are mounted on the limbs. By using multiple sensor modules, [the following can be achieved]... Figure 19B1 The electrocardiogram shown is used to check for abnormalities such as arrhythmias. For example, sensor module LA is installed in the left arm, sensor module RA in the right arm, sensor module LL in the left leg, and sensor module RL in the right leg. The arms mentioned above include the upper arm, wrist, palm, fingers, etc., and the legs mentioned above include the thigh, fibula, shin, ankle, instep, sole, toes, etc.

[0406] Generally, the electrocardiogram (ECG) is determined by comparing the first induced waveform (waveform 1), the second induced waveform (waveform 2), and the third induced waveform (waveform 3). That is, sensor module LA obtains the change in waveform 1 based on RA. Sensor module LL obtains the change in waveform 2 based on RA. Sensor module LL obtains the change in waveform 3 based on LA. Furthermore, sensor modules LA, RA, LL, and RL preferably operate synchronously according to the signal mn1 generated by semiconductor device 80. Because semiconductor device 80 is constructed with dynamic circuitry, it can acquire long-term data with reduced power consumption.

[0407] Data can also be shared between sensor modules. Furthermore, data can be transmitted wirelessly or via wired connections. Figure 19A2 A portable data terminal is used to detect waveforms 1 to 3. The portable data terminal can detect problems such as arrhythmia from the data acquired by each sensor module. When data acquired by the sensor modules is transmitted to the portable data terminal via a wired connection, it is preferable to simultaneously forward previously acquired data via the wired connection. Furthermore, the detected data can be automatically dated and stored in the portable data terminal for personal management. It can also be transmitted to hospitals, etc., via a network (including the Internet). This data can be managed by the hospital's data server and used as examination data during treatment. In addition, the portable data terminal can use... Figure 17A The structure shown.

[0408] When the aforementioned sensor module also includes multiple microneedles, it can measure the current or resistance value flowing between the microneedles. In other words, the sensor module can detect blood glucose levels in the blood by measuring the conductivity between the microneedles. Figure 19B2 )wait.

[0409] The aforementioned sensor module can detect the amount of movement (mobility) of the limbs by incorporating an accelerometer. By individually managing the movement of the limbs, it is possible to detect whether there is an imbalance in the body's overall movement.

[0410] As described above, by installing multiple sensor modules on the body, a portable data terminal can be used to determine the conditions under which arrhythmias occur during daily life. This can be achieved by utilizing body temperature (when an arrhythmia occurs) Figure 19B3 ),pulse( Figure 19B4 Information such as blood sugar levels can help manage one's health or make a diagnosis in a hospital.

[0411] The aforementioned sensor modules can be directly attached to the body using patches or embedded in the body, or they can be used in wearable electronic devices such as watches. Furthermore, the sensor module can possess all, several, or any of the aforementioned functions.

[0412] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0413] [Example 1]

[0414] In this embodiment, a wearable watch device using the dynamic circuit shown in Embodiment 1 is described. Figure 20 This is a block diagram showing a prototype wearable watch device. The wearable watch device (hereinafter referred to as device 1400) includes an oscillator (OSC) 1410, a frequency divider (15-bit frequency divider) 1401, a counting circuit (counter) 1402, a control circuit (controller) 1403, a decoding circuit (7-segment decoder) 1404, and a display device (7-segment display) 1420. The counting circuit 1402 includes a second counter (second counter) 1402a for counting "seconds," a minute counter (minute counter) 1402b for counting "minutes," and an hour counter (hour counter) 1402c for counting "hours." Counting circuits 1402a and 1402b are composed of a decimal counter and a hexadecimal counter, respectively. Counting circuit 1402c is composed of a decimal counter and a ternary counter. The decoding circuit 1404 has the function of easily displaying the time by controlling the seven segments that can display numbers. Furthermore, the frequency divider 1401, the counting circuit 1402, the control circuit 1403, and the decoding circuit 1404 can be latched by a dynamic circuit as shown in Embodiment 1.

[0415] Frequency divider 1401 divides the 32.768kHz output from oscillator 1410 by 15 to generate a clock signal. This 1Hz clock signal is received by counting circuit 1402a and control circuit 1403. Counting circuit 1402a counts seconds based on the 1Hz clock signal. Furthermore, counting circuit 1402a can provide a carry signal to counting circuit 1402b. Additionally, counting circuit 1402b can provide a carry signal to counting circuit 1402c.

[0416] Control circuit 1403 generates a 6-phase clock signal P[5:0] from the clock signal. This clock signal P[5:0] can be received by counting circuits 1402a, 1402b, and 1402c. In addition, control circuit 1403 can provide control signals to decoding circuit 1404.

[0417] The counting circuit 1402a provides the counting value of "seconds" to the decoding circuit 1404, the counting circuit 1402b provides the counting value of "minutes" to the decoding circuit 1404, and the counting circuit 1402c provides the counting value of "hours" to the decoding circuit 1404.

[0418] The decoding circuit 1404 converts the count value of "seconds" received from the counting circuit 1402a into 7-segment data and provides it to the display device 1420, converts the count value of "minutes" received from the counting circuit 1402b into 7-segment data and provides it to the display device 1420, and converts the count value of "hours" received from the counting circuit 1402c into 7-segment data and provides it to the display device 1420.

[0419] Figure 21A This is a photograph of the prototype device 1400. Device 1400 is fabricated using a technique that stacks a 350nm top-gate self-aligned CAAC-IGZO FET on a Si wafer. Device 1400, namely... Figure 20 The frequency divider 1401, counting circuit 1402, control circuit 1403 and decoding circuit 1404 shown are formed on a Si wafer.

[0420] The chip size of Device 1400 is 0.9mm × 1.92mm. Device 1400 uses approximately 12,000 transistors.

[0421] Figure 21B This is a cross-sectional schematic diagram of a transistor used in wearable watches. A back gate is formed on a Si wafer (substrate), and a semiconductor layer (OS) and a top gate, also formed of a conductive layer, are sequentially disposed on the back gate. The transistor is formed by overlapping the top gate with the semiconductor layer and the back gate. Furthermore, a transistor containing metal oxide in the semiconductor layer is called an OS transistor. A portion of the back gate and the top gate are used as wiring. The conductive layers (metal 1, metal 2) are used as wiring layers. Input / output pads for signals are provided on the conductive layers.

[0422] Figure 22The waveforms measured during device 1400's operation are shown. It is confirmed that device 1400 operates normally within a positive power supply voltage range of 3.3V to 4V. Furthermore, clock signals P0 to P5 are shown as clock signals Ф1 to Ф6. Additionally, control signals (signal PRE, signal EVA) are provided from control circuit 1403 to decoding circuit 1404. Furthermore, signals PRE and EVA are equivalent to... Figure 15 The signals PRE and EN1 are shown. Output signals Z0 to Z6 are provided from the decoding circuit 1404 to the display device 1420, which displays numbers by activating any one of the seven segments according to the output signals Z0 to Z6.

[0423] Figure 23A This shows the simulation results of the power consumption when device 1400 is operating in a simulated manner. When the positive supply voltage is 3.3V, the power consumption of device 1400 is 55.6uW. Specifically, the power consumption of device 1400 is as follows: frequency divider 1401 is 12.6uW, counting circuit 1402 is 3.6uW, control circuit 1403 is 11.6uW, and others are 27.8uW.

[0424] Figure 23B The measured power consumption of the prototype device 1400 during operation is shown. As described above, device 1400 is composed of dynamic circuitry (dynamic logic circuitry). The positive supply voltage is 3.3V. The power consumption of device 1400 is 90uA. Therefore, the power consumption is calculated to be 297uW. Furthermore, the gate insulating film settings in the simulation differ from those of the gate insulating film in the prototype device 1400, therefore... Figure 23A The simulation results shown are consistent with Figure 23B The power consumption of the device 1400 shown varies.

[0425] By using OS transistors with low off-state current in functional circuits, wearable watch devices that operate as low-speed circuits are manufactured. The result is a dynamic approach to realizing logic circuits with low on-state current composed solely of OS transistors, thereby achieving extremely low-power wearable systems.

[0426] [Symbol Explanation]

[0427] BG1: Wiring, BG2: Wiring, BG3: Wiring, BG4: Wiring, BG5: Wiring, C1: Capacitor, C2: Capacitor, C3: Capacitor, C4: Capacitor, C5: Capacitor, 3A: Transistor, 3B: Transistor, 3C: Transistor, 3D: Transistor, 3E: Transistor, 3F: Transistor, 3G: Transistor, 3H: Transistor, 3J: Transistor, 3K: Transistor, 10: Latch circuit, 10A: Latch circuit, 10B: Latch circuit, 10C: Latch circuit, 10CA: Circuit, 10CAa: Circuit, 10CAb: Circuit, 10D: Latch circuit, 10E: Latch circuit, 10F: Latch circuit, 10G: Latch circuit, 10H: Latch circuit, 10J : Latch circuit, 10K: Latch circuit, 11: Transistor, 11a: Transistor, 12: Transistor, 12a: Transistor, 13: Transistor, 13a: Transistor, 14: Transistor, 14a: Transistor, 15: Transistor, 15a: Transistor, 16: Transistor, 16a: Transistor, 17: Transistor, 17a: Transistor, 18: Transistor, 18a: Transistor, 19: Transistor, 19a: Transistor, 20: Circuit, 20A: Circuit, 20B: Circuit, 20C: Circuit, 20D: Circuit, 20E: Circuit, 20F: Circuit, 20G: Circuit, 20H: Circuit, 20J: Circuit, 20K: Circuit, 21: Transistor, 21a: Transistor, 30: Circuit, 30A : Circuit, 30B: Circuit, 30C: Circuit, 30D: Circuit, 30E: Circuit, 30F: Circuit, 30G: Circuit, 30H: Circuit, 30J: Circuit, 30K: Circuit, 31: Transistor, 32: Transistor, 33: Transistor, 34: Transistor, 35: Transistor, 36: Transistor, 37: Transistor, 38: Transistor, 39: Transistor, 40: Circuit, 41: Transistor, 41a: Transistor, 42: Transistor, 42a: Transistor, 50: Circuit, 51: Transistor, 51a: Transistor, 52: Transistor, 52a: Transistor, 61: Transistor, 61a: Transistor, 62: Transistor, 62a: Transistor, 63: Transistor, 64: Transistor, 65: Crystal 66: Transistor; 80: Semiconductor device; 81: Control circuit; 82: Oscillator; 83: Frequency divider; 84: Circuit; 84a: Circuit; 84b: Circuit; 84c: Circuit; 86: Decoding circuit; 87: Selection circuit; 88a: Display device; 88b: Display device; 88c: Display device; 88d: Display device; 88e: Display device; 88f: Display device; 90: Battery protection IC; 300: Transistor; 314: Insulating layer; 322: Insulating layer; 324: Insulating layer; 330: Oxide layer; 500: Electronic device; 911: Housing; 912: Operation button; 913: Sensing device; 914: Wireless communication unit; 921: Housing; 922: Operation panel.923: Conveying mechanism; 924: Display; 925: Detection unit; 926: Detected component; 927: Sensing device; 931: Frame; 932: Operation button; 933: Display unit; 934: Light shield; 935: Sensing device; 1300: Transistor; 1300A: Transistor; 1305: Conductive layer; 1314: Insulating layer; 1316: Insulating layer; 1322: Insulating layer; 1324: Insulating layer; 1330: Oxide layer; 1330a: Oxide layer; 1330b: Oxide layer; 1330c: Oxide layer; 1340: Conductive layer; 1340a: Conductive layer; 1340b: Conductive layer; 1341 1341a: Insulating layer; 1341b: Insulating layer; 1342: Conductive layer; 1342a: Conductive layer; 1342b: Conductive layer; 1350: Insulating layer; 1354: Insulating layer; 1360: Conductive layer; 1360a: Conductive layer; 1360b: Conductive layer; 1374: Insulating layer; 1380: Insulating layer; 1381: Insulating layer; 1400: Device; 1401: Frequency divider; 1402: Counting circuit; 1402a: Counting circuit; 1402b: Counting circuit; 1402c: Counting circuit; 1403: Control circuit; 1404: Decoding circuit; 1410: Oscillator; 1420: Display device.

Claims

1. A semiconductor device, comprising: Latch circuit composed of dynamic circuits The latching circuit includes a first circuit, a second circuit, first and third capacitors, first and third clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. The first circuit has a decoding function. The first to third clock input terminals have the function of receiving the first to third clock signals sequentially. During the period when the first clock signal is the "H" signal, The first circuit has the function of receiving multiple input signals through the signal input terminal. The first capacitor has the function of having its potential refreshed according to the decoding result of the first circuit. During the period when the second clock signal is the "H" signal, The second capacitor has the function of refreshing its potential based on the potential of the first capacitor. The first output terminal has the function of receiving the potential of the second capacitor as a first output signal. During the period when the third clock signal is the "H" signal, The third capacitor has the function of refreshing its potential based on the potential of the second capacitor. The second output terminal has the function of receiving the potential of the third capacitor as a second output signal. The second circuit generates a seventh clock signal and an eighth clock signal based on the second clock signal received from the second clock input terminal. During the period when the seventh clock signal is "H", the latch circuit has the function of latching the decoding result of the input signal and outputting the latched result as the first output signal. During the period when the eighth clock signal is the "H" signal, The fifth clock input terminal receives the fifth clock signal, causing the second capacitor to precharge. When the first output signal is an "H" signal, the potential of the pre-charged second capacitor is used as the first output signal, i.e., the "H" signal, and output. When the first output signal is an "L" signal, the potential of the second capacitor is released according to the second output signal. Furthermore, the potential of the second capacitor is used as the first output signal, namely the "L" signal, for output.

2. The semiconductor device according to claim 1, The latch circuit includes the fourth to sixth clock input terminals. The fourth to sixth clock input terminals receive the fourth to sixth clock signals sequentially. During the period when the fourth clock signal is the "H" signal, The first capacitor is precharged. During the period when the fifth clock signal is the "H" signal, The second capacitor is precharged. And during the period when the sixth clock signal is the "H" signal, The third capacitor is precharged.

3. The semiconductor device according to claim 1, It also includes multiple cascaded latch circuits, The plurality of latching circuits are used as counting circuits.

4. The semiconductor device according to claim 1, The latch circuit includes first to fifth transistors. The first clock input terminal is electrically connected to the gate of the first transistor. The third clock input terminal is electrically connected to the gate of the third transistor. The fifth clock input terminal is electrically connected to the gate of the fifth transistor. One electrode of the second capacitor is electrically connected to the gate of the fourth transistor. One electrode of the third capacitor is electrically connected to the gate of the fifth transistor. The first to fifth transistors contain metal oxides in the semiconductor layer. The first to fifth transistors include a back gate. Furthermore, the back gates of the first to third transistors receive a different potential than the back gates of the fourth and fifth transistors.

5. A detection device, comprising: The semiconductor device, detection circuit, and battery as described in claim 3 The output signal of the semiconductor device is received by the detection circuit. Furthermore, the detection circuit uses the output signal as a monitoring cycle to monitor the output potential of the battery.

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