Slope detection and correction of current sensing with power switch on-state resistance

Abstract

Embodiments of the present disclosure relate to slope detection and correction for current sensing with power switch on-state resistance. A current estimation circuit is configured to estimate current within a power switch, e.g., within a switched voltage converter, using a voltage measured across its load terminal and its on-state resistance. By ignoring the measured voltage across the power switch during a blanking interval following a transition, ringing and other transient anomalies associated with the on-transition of the power switch can be ignored. During the remainder of the power switch on-interval, the measured voltage is sampled to provide a first sample and a second sample. Also during this interval, a slope of the measured voltage is estimated and tracked. The estimated slope is combined with the first sample and the second sample to yield a current estimate for the entire on-interval of the power switch, including the blanking interval. The estimated slope is used to correct for inaccuracies resulting from not using the measured voltage during the blanking interval.

Description

TECHNICAL FIELD

[0001] This application relates to techniques for estimating current in an inductor of a switched voltage converter using the on-state resistance of a power switch connected to the inductor, where the current is estimated using a slope determined after a blanking interval following the switch being transitioned to its on-state and a sample taken after the blanking interval. BACKGROUND

[0002] Accurate current sensing is required when powering many electronic loads, such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), and application specific integrated circuits (ASICs), particularly when such loads are used in server and telecommunications applications. Accurate current sensing enables the performance of such processors to be optimized, and allows for precise thermal management of the processor system. For large server farms, this can save significant costs as the power used to cool the servers can be kept to a minimum. Furthermore, the infrastructure required for cooling can be limited to a minimum (i.e. not significantly oversized) such that the cost of the cooling infrastructure can be reduced when accurate current sensing is available.

[0003] Processors and other circuitry used within servers and other applications are typically powered using switched voltage converters. In server applications, a high direct current (DC) voltage (e.g. 48V) is typically distributed widely and stepped down by a point of load (POL) switched voltage converter physically close to each processor or other load. In many applications, the POL converter can reduce the widely distributed high DC voltage to a lower voltage (e.g. 12V, 3.3V, 1.8V, etc.). A frequently used type of POL converter is a buck converter, which in its most common form uses a high-side power switch and a low-side power switch to control the flow of power into an energy storage inductor coupled to the load.

[0004] Estimation of the power consumption of a load can be done by sensing the current in the energy storage inductor of, for example, a buck converter. Although there are many techniques for such current sensing, one of the most popular is to sense the voltage across one (or both) of the power switches connected to the inductor and estimate the current through that switch (or switches) using the on-state resistance of the power switch(s) (e.g. R DSON ). The current in the given power switch (corresponding to the current in the inductor) can then be estimated using the voltage measured across the load terminal of the switch and the characteristic on-state resistance of the switch (e.g. R DSON ). Based on R DSONCurrent sensing based on R DSON does not waste power in the switching converter as other current sensing techniques (e.g., those based on shunt resistors) do. Moreover, current sensing based on R DSON is more accurate than many techniques (e.g., those based on Hall effect sensors or inductor DCR sensing) and does not require expensive or large circuit components.

[0005] When the high-side switch is conducting, the current flowing through the high-side switch and the buck converter inductor increases linearly, while when the low-side switch is conducting, the current flowing through the low-side switch and the inductor decreases linearly. While ideally the voltage (e.g., drain-to-source voltage V DS ) across the conducting power switch follows the linear increase and decrease of the inductor current, in practice, the waveform of the power switch voltage V DS exhibits anomalies during a time interval immediately following the transition of the power switch between its off and on states. In particular, for the on transition of the low-side switch in a buck converter, this voltage waveform, following such a transition, rings due to ground bounce and other undesirable signals (noise). This means that, at least without certain mitigation measures to deal with such noise, current sensing based on R DSON based on the power switch voltage V DS will not provide a very accurate current estimate.

[0006] One technique to mitigate the noise in the power switch voltage V DS immediately following an on transition is to filter out the ringing / noise portion of the voltage waveform, i.e., to treat the voltage waveform as unusable for a blanking time interval following the on transition, and to use the remaining portion of the voltage waveform following the blanking interval to estimate the current. Such blanking avoids inaccuracies caused by artifacts at the on transition, but ignoring a portion of the voltage waveform during the blanking interval will cause the current estimate to be biased, generating another type of inaccuracy. In certain situations, e.g., when the blanking interval is a small fraction of the power switch on interval (e.g., occurs at low switching frequencies), this inaccuracy is tolerable. However, generally, the switching frequencies used by switching voltage converters, including buck converters, are on a long-term upward trajectory. Higher switching speeds allow the use of smaller energy storage inductors, providing higher power density for the switching voltage converter. As the switching frequency increases, the inaccuracies associated with such blanking intervals become significant enough that they can no longer be ignored. SUMMARY

[0007] Circuits and techniques are needed to estimate the current of an inductor in a switched voltage converter using the on-state resistance of a power switch, and these circuits and techniques can compensate for estimation inaccuracies due to blanking the sense signal immediately after a turn-on transition of the power switch.

[0008] According to one embodiment of a current estimation circuit, the current estimation circuit is configured to estimate a current in a power switch during a conduction interval of the power switch. The power switch is typically part of a switched power converter, and the estimated current corresponds to and can be equivalent to an output current of the switched power converter. The current estimation circuit includes a slope estimator and a sampler circuit. The slope estimator is configured to estimate a slope representative of the current in the power switch during a portion of a first conduction interval starting at or after a first delay from a turn-on transition of the power switch. The sampler circuit is configured to generate a first sample corresponding to a first sense voltage across the power switch at or after the first delay from the turn-on transition, and to generate a second sample corresponding to a second sense voltage across the power switch after the first sense voltage. The first delay includes a blanking interval to avoid sampling or estimating the slope during a portion of the sense voltage immediately after the turn-on transition of the power switch, during which a ringing or other artifact makes the sense voltage unavailable. The current estimation circuit is configured to estimate the current in the power switch over the conduction interval based on the first sample, the second sample, and the estimated slope.

[0009] According to one embodiment of a power conversion system, the power conversion system includes a switched voltage converter and a current estimation circuit. The switched voltage converter includes a power switch and an inductor. The current estimation circuit of the power conversion system is configured and includes components as described above.

[0010] According to one embodiment of a method for estimating a current in a power switch having a switch voltage between a first load terminal and a second load terminal of the power switch, the method includes turning the power switch on at a turn-on transition, and turning the power switch off at a turn-off transition. The method further includes estimating a slope representative of the current in the power switch between a first time and a second time, the first time being a first delay after the turn-on transition, and the second time being after the first time and at or before the turn-off transition. The method includes sampling the switch voltage at a first sampling time to produce a first sampled voltage, the first sampling time being at or after the first delay after the turn-on transition, and sampling the switch voltage at a second sampling time to produce a second sampled voltage, the second sampling time being after the first sampling time and at or before the turn-off transition. The method additionally includes outputting an estimated current based on the first sampled voltage, the second sampled voltage, and the estimated slope.

[0011] Those skilled in the art will recognize, upon reading the following detailed description and viewing the drawings, additional features and advantages. BRIEF DESCRIPTION OF DRAWINGS

[0012] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding like parts. The features of the various illustrated embodiments can be combined, unless they are mutually exclusive. Embodiments are depicted in the drawings and described in detail in the following description.

[0013] Figure 1 A schematic diagram of a switched voltage converter system is illustrated, including current estimation circuitry using the on-state resistance of a power switch.

[0014] Figure 2 Waveforms corresponding to voltages and currents within a switched voltage converter of Figure 1 are illustrated.

[0015] Figure 3 Waveforms of timing signals in a switched voltage converter system of Figure 1 are illustrated.

[0016] Figure 4A and Figure 4B A schematic diagram of more detailed circuitry for current estimation using the on-state resistance of a power switch is illustrated.

[0017] Figure 5A and Figure 5B A method of estimating current in a switched voltage converter using the on-state resistance of a power switch is illustrated.

[0018] Figure 6 Waveforms corresponding to a voltage across a power switch, and amplified and inverted versions of that voltage, are illustrated.

[0019] Figure 7 Waveforms corresponding to slope error signals over several switching cycles of a voltage converter, and corresponding to convergence of those error signals, are illustrated. DETAILED DESCRIPTION

[0020] Embodiments described herein provide circuitry and methods for estimating current within an inductor of a switched voltage converter. The described embodiments' techniques sense a voltage across a load terminal of a power switch within a switched voltage converter, where the power switch provides current to an inductor. Because this power switch voltage rings or otherwise behaves abnormally after a transition of the power switch, the current estimate blanks (ignores) the sensed voltage for a blanking interval after the transition. Unlike existing current estimation techniques, the techniques herein correct for the portion of the waveform that was blanked. This correction is performed by a circuit arrangement that estimates a slope of the waveform after the blanking interval, and uses this slope to model a version of the waveform during the blanking interval. The slope and / or the modeled waveform are used to correct for the current estimation error caused by the blanking of the waveform.

[0021] Existing power conversion systems typically use a low enough switching frequency that the inaccuracy caused by waveform blanking is not significant. However, using a low switching frequency requires the use of larger energy storage inductors within switched power converters. The accuracy of current estimation is not a limiting factor for increasing the switching frequency, which has the general advantage of reducing the cost and size of switched power converters. Thus, existing current estimation techniques that simply ignore the sensed voltage during the blanking interval provide an undesirable long-term solution because they effectively limit the switching frequency.

[0022] Other existing power conversion systems are simply over-designed so that the lack of accuracy in the estimation of inductor current does not cause significant problems (e.g., overheating). Such over-design has the undesirable effect of using unnecessary levels of cooling and / or providing unnecessarily large cooling infrastructure (e.g., heat sinks, fans, air conditioning).

[0023] Switching voltage converters typically include a controller for generating switching control signals, and the controller can involve current estimation to varying degrees. One option to address the inaccuracy caused by blanking is to have the controller add a coarse compensation term to the estimated current in order to reduce the inaccuracy. The coarse compensation can be a constant and can be based on the blanking interval. For example, compensation based on duty cycle or using more complex sampling more frequently than the switching frequency is typically not feasible, or at least is not desirable, because such complexity would typically limit the possible switching frequency. Instead, it is desirable for the current estimation to be performed by a dedicated circuitry that provides an accurate current estimate to the controller so that the controller does not need to perform complex calculations within the switching period. Although not so limiting the claimed invention, the examples described herein use a current estimation circuitry that provides an accurate current estimate sample for each switching period of the voltage converter so that there is minimal intervention of the controller required for the current estimation. When the current estimation circuitry ignores the voltage waveform detected during the blanking interval, the blanking is compensated for by the current estimation circuitry. This compensation can be effective over a wide range of duty cycles and does not place any significant limit on the switching frequency because other components (e.g., power switches or the controller) typically set the upper limit on the switching frequency.

[0024] For clarity of description, embodiments are described below in the context of specific examples based on a non-isolated switching voltage conversion system using a buck converter. However, it can be inferred that the techniques are used with other non-isolated switching voltage converters (e.g., a boost converter or a buck-boost converter) and even isolated voltage converters where the current through the power switch is estimated. Various techniques are described using examples in which the current estimation is based on a voltage sensed across the load terminal of the power switch. However, other current estimation techniques that also use blanking to filter out a noisy portion of the sensed waveform (e.g., a technique that measures the voltage across a shunt resistor in series with the power switch) can also benefit from the current estimation circuitry and techniques described above.

[0025] The described embodiments provide specific examples for purposes of explanation and are not meant to be limiting. Individual features and aspects of the example embodiments can be combined or rearranged unless the context otherwise dictates. Below, a description starts with a description of a voltage conversion system including a buck converter and a current estimator. Next, detailed circuitry for implementing the current estimator is described. Finally, an exemplary method for estimating current in a power switch of a switching voltage converter is described.

[0026] Figure 1A schematic diagram of a voltage conversion system 100 is shown, including a buck converter 110 and a current estimation circuit arrangement 400. The buck converter 110 includes a high-side power switch HS and a low-side power switch LS connected at a switching node SW. An inductor LI couples the switching node SW to an output having a voltage V OUT . The output is used to connect to a load (not shown for ease of illustration), for example a CPU powered by the voltage V OUT . The high-side switch HS is also coupled to an input that provides a voltage V IN , while the low-side switch LS is coupled to ground. The buck converter 110 reduces the supply voltage V IN to provide an output voltage V OUT . For example, the buck converter can reduce an input voltage V IN = 12V to produce an output voltage V OUT = 3.3V.

[0027] Figure 1 The high-side power switch HS and the low-side power switch LS shown in FIG. 1 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), but other switch types can be used. For example, in some applications, p-channel MOSFETs, junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), high-electron-mobility transistors (HEMTs), or other types of power transistors can be preferred. The high-side switch HS has a gate controlled by a pulse-width-modulation (PWM) control signal via a high-side gate driver 112. The low-side power switch LS has a gate controlled by an inverted version LGATE of the PWM signal via a low-side driver 114 and a dead-time insertion circuit arrangement 118. An inverter 116 in combination with the dead-time insertion circuit 118 causes the high-side power switch HS and the low-side power switch LS to conduct alternately, except for a small dead-time inserted between conduction intervals, to avoid a direct current path from the power supply (having voltage V IN ) to ground.

[0028] When the high-side switch HS is conducting, a current I HS flows through it and is passed directly to the inductor LI, so that the high-side current I HS and the inductor current I NID are the same (during such high-side conduction intervals, no appreciable current flows through the low-side switch LS). When the low-side switch LS is conducting, a current I LS flows through it and is passed directly to the inductor LI, so that the low-side current I LS and the inductor current I IND are equivalent (during such low-side conduction intervals, no appreciable current flows through the high-side switch HS). At least during typical operation of the buck converter 110, these currents IIS LS In Figure 1 the direction shown is positive.

[0029] The level of the output current I IND provided by the buck converter 110 is determined by a PWM control signal, which is typically generated by a controller (not shown for ease of illustration) of the buck converter 110. Such a controller and its constituent parts can be implemented using a combination of analog hardware components (e.g., transistors, amplifiers, diodes, and resistors) and processor circuitry that includes primarily digital components. The controller can include one or more of a digital signal processor (DSP), a general purpose processor, and an application specific integrated circuit (ASIC). Memory coupled to the controller can include non-volatile memory such as flash memory in which instructions and / or data can be stored for use by the controller. To provide a regulated output voltage V OUT , the controller senses the output voltage V OUT and adjusts the duty cycle and / or frequency of the PWM signal to produce an appropriate inductor current I IND to keep the output voltage near a target voltage V TGT (e.g., the previously mentioned 3.3V level). The PWM signal is typically generated using closed loop control techniques (e.g., in a proportional-integral-derivative (PID) controller). Because voltage converter controllers and closed loop control techniques are well known in the art, such controllers and techniques are not described further to avoid obscuring the unique aspects of the present invention.

[0030] The current estimation circuitry 400 is coupled to the buck converter 110. As shown, this circuitry 400 senses the voltage V DS_LS across the load terminals (e.g., drain and source terminals) of the low side power switch LS. The current estimator 400 outputs an estimate of the inductor current I IND , or a similar parameter that can be readily converted to a current estimate. The current estimator 400 includes a voltage sensor 410, a timing generator 420, a slope estimator 430, voltage sampler circuits 440, 460, and a combiner and slope-based correction circuit 470. These circuits are described directly in high level below and are further described in detail in connection with the waveforms of Figures 2-3 and the circuit of Figures 4A-4B .

[0031] The voltage sensor 410 is coupled to the load terminals of the low side switch LS to sense the voltage V DS_LS ​Although one of these terminals (e.g., the source terminal) is grounded, the voltage sensor 410 preferably senses this voltage differentially to provide good common-mode rejection (including accounting for any local ground node noise associated with the switching of the low-side power switch LS). The voltage sensor 410 output is related to the voltage V DS_LS The corresponding sensing voltage V SNS As follows about Figure 4A As explained, the sensing voltage V SNS Can be relative to the voltage V DS_LS Amplified, inverted, and / or level-shifted to provide a positive voltage and / or a sufficiently high voltage level to avoid potential adverse effects of noise.

[0032] Sense voltage V SNS is provided to the slope estimator 430 and the voltage samplers 440, 460. These circuits 430, 440, 460 ignore the sensed voltage V during the blanking interval after the low-side switch LS is switched on and during the conduction (on) interval of the high-side power switch HS. SNS The slope estimator 430 estimates the sense voltage V during the interval after the blanking interval and before the low-side switch is turned off. SNS The slope of the sensing voltage V SNS Directly corresponds to the low-side current I LS The blanking interval is set to avoid noise / ringing associated with the turn-on transition of the low-side switch LS and taking into account the sense voltage V SNS Stability. Figure 4A and Figure 4B As explained in the description of , the slope estimator can generate and update the slope estimate during the non-blanking portion of the low-side conduction interval using closed-loop feedback, and can maintain the slope estimate after the low-side conduction interval (e.g., during the high-side conduction interval). By maintaining the slope estimate in this way, a valid slope estimate can be provided to the combiner and slope-based correction circuit 470 even after the low-side switch LS has been turned off. The slope estimate provided by the slope estimator 430 does not have to depend on the switching frequency of the voltage converter 110, the output voltage V OUT Or the inductance of inductor L1.

[0033] The first voltage sampler 440 preferably senses the voltage V at time t2 immediately after the blanking interval. SNS The second voltage sampler 460 preferably samples the sensed voltage V at a time t3 at or near the turn-off transition of the low-side switch LS. SNSA sample is taken to produce a voltage sample V2. Although the following example describes sample V2 taken at a time corresponding to the turn-off transition of low-side switch LS, other implementations can take sample V2 earlier than the turn-off of low-side switch LS, but after the sampling time of VI, and can compensate for such timing differences. Such timing variations are not further described as they facilitate description and provide similar results.

[0034] Timing generator 420 produces timing pulses to control the sampling in slope estimator 430 and sampling circuits 440, 460, and other timing. Timing signals PHI, PH2, PH3, PH4, PH6, and PH7 are generated to ensure that the slope estimate is based on the sensed voltage V SNS within a time window after the blanking interval and before the turn-off transition of low-side switch LS, and that voltage samples VI, V2 are taken within the same window, such that voltage sample V2 is taken after voltage sample VI. Timing generator 420 additionally generates timing signal PH5, which is used to properly latch the signal providing the final output from combiner and slope-based correction circuit 470.

[0035] Timing generator 420 inputs the PWM signal used to control the high-side and low-side switches, as well as an early version of that signal, denoted as PWM ADV. Timing generator 420 also inputs a time delay t BLANK corresponding to the blanking interval, or holds that delay within memory of timing generator 420. Timing generator 420 is illustrated as a circuit within current estimator 400, but can instead be included in a controller that generates the PWM signal.

[0036] Combiner and slope-based correction circuit 470 generates a current estimate, or a signal corresponding to such an estimate, based on the estimated slope and voltage samples VI, V2. In one technique, first voltage sample VI is adjusted based on the estimated slope, such that if the switching transition artifacts (ringing and noise) during the blanking interval do not corrupt that voltage, the adjusted voltage is an extrapolated voltage corresponding to the expected voltage V0 when the low-side switch is first transitioned on. In one embodiment, the adjusted voltage and second voltage sample V2 are averaged to provide a sensed voltage estimate that accurately represents the average current <I IND of the low-side switch over the entire conduction interval of the low-side switch, and that accurately represents the inductor current I INDIn a second technique, the voltage samples V1, V2 are combined, for example, via averaging, to produce a preliminary voltage corresponding to the current estimate. A correction factor (voltage) based on the slope estimate is then applied to the preliminary voltage to produce a corrected average voltage that is proportional to the estimated current. IND_EST Both techniques determine a slope estimate and use it to correct for the voltage V that is sensed during the blanking interval. SNS While the described examples focus on techniques for estimating average current, the estimated slope can also be used to estimate current at specific times in time, such as allowing current to be estimated and reported periodically at a frequency higher than the switching frequency of the voltage converter.

[0037] Figure 2 The diagram shows Figure 1 The first waveform 210 shows the inductor current I in one switching cycle of the buck converter 110. IND Between time t0 and t1, the high-side power switch HS conducts, resulting in the high-side current I shown. HS , high-side current I HS Between time t1 and t3, the low-side power switch LS conducts, resulting in the low-side current I shown. LS , low-side current I LS Decreases linearly during this interval. Inductor (output) current I IND By the high side current I HS and low-side current I LS The combination of the inductor current I IND It increases linearly from time t0 to t1 and decreases linearly from time t1 to t3. For each switching cycle, the inductor current I IND However, for a fixed frequency PWM signal, as the load connected to the buck converter 110 requires more or less current, the PWM duty cycle and corresponding time t1 will change.

[0038] Figure 2 The waveforms shown correspond to operation of the buck converter 100 in continuous conduction mode (CCM), with the inductor current I IND exist Figure 1 The illustrated current direction is always positive as shown. However, the current estimation techniques described herein are also applicable to operation in discontinuous conduction mode (DCM) and operation where the current flows through the inductor L1 in a direction opposite to that shown.

[0039] The high-side switch HS and the low-side switch LS have an on-state resistance R​DS_ON , when these switches are fully on (saturated), the on-state resistance R DS_ON Characterizes the relationship between the voltage across these switches HS, LS and the current flowing through these switches. Figure 1 , V DS_HS =R DS_ON_HS *I HS , and V SD_LS =R DS_ON_LS *I LS Using these relationships, the current H IS , I LS , I NDN The estimation can be made using the voltage measured across the switches HS, LS.

[0040] Figure 2 The second waveform 220 shows the voltage V from the source terminal to the drain terminal of the low-side switch LS. SD_LS , i.e., the voltage drop from ground to the switching node SW. Before time t1, the switching node SW is coupled to the source voltage V IN , so that the voltage at the switching node SW is equal to the source voltage V IN Subtract the small voltage drop across the high-side switch, V DS_HS After time t1, the switching node SW is coupled to ground via the low-side switch LS. However, due to the voltage drop across the low-side switch LS, the voltage at the switching node SW actually becomes slightly negative. The second waveform 220 shows the positive source-drain voltage V during the time interval from t1 to t3. SD_LS After time t2, the voltage V SD_LS is linear and follows (is linearly related to) the current ILS, i.e., V SD_LS =R DS_ON_LS *I LS .

[0041] However, the turn-on transition of the low-side switch LS at time t1 generates a number of artifacts, primarily in the form of high-frequency ringing due to the attempted sharp voltage transitions. These artifacts cause the switch voltage V SD_LS (or V DS_LS ) is not available for current estimation during the interval immediately following the on-transition at time t1. Figure 2 is represented as t BLANK , and covers the delay corresponding to the ringing / noise of the switching voltage and the delay that makes the output V of the voltage sensor 410 SNS As previously mentioned and explained in further detail below, the voltage across the low-side switch LS (V SD_LS or V DS_LS) can be used between times t2 and t3 to estimate the slope of the current (I LS or I IND ) and to estimate the absolute current at a particular sampling time point.

[0042] The voltage sensor 410 senses the differential voltage between the switching node SW and ground, i.e., V DS_LS , which is the negative of the voltage V SD_LS shown in the second waveform 220. The voltage sensor 410 inverts and level shifts the voltage V DS_LS so that it is positive within the time interval of interest, i.e., after the blanking interval. In addition, the amplitude of the voltage V DS_LS is typically relatively small. (For example, the on-state resistance of a low-voltage power MOSFET can be as low as 1 mΩ to 5 mΩ. For an output current of 100 A, the resulting voltage is only 100 mV to 500 mV.) To limit the effect of noise in the current estimator 400, the voltage sensor 410 amplifies the voltage before distributing it to the slope estimator 430 and the voltage samplers 440, 460. The resulting voltage V SNS is shown in the third waveform 230 and the fourth waveform 240. The voltage V SNS is inverted, level shifted, and amplified with respect to the source-drain voltage V SD_LS . The third waveform 230 illustrates a technique such as that in the circuit of Figure 4A , whereby the voltage sample V1 increases for a period of time t BLANK , and the average voltage V AVG is then determined from the updated voltage V1 and the voltage sample V2. The fourth waveform 240 illustrates a technique such as that in the circuit of Figure 4B , whereby the voltage samples V1 and V2 are averaged, and then a correction is applied to arrive at the final voltage V AVG_CORR used to estimate the current.

[0043] Figure 3 The timing signals PH1-PH7 generated by the timing generator 410 or similar and used by the slope estimator 430, the voltage samplers 440, 460, and the combiner and slope-based correction circuit 470 are illustrated. These signals will be described directly below, and their use will be further explained in the description of the circuits 400A, 400B of Figure 4A and Figure 4B .

[0044] The baseline for generating the output timing signal is the PWM signal, which is used to control the high-side power switch HS and the low-side power switch LS and is typically generated by a PWM generator within the buck converter controller. Additionally generated is an early version of the PWM signal, PWM_ADV, which precedes the PWM signal by a time interval t ADV . The low-side control signal LGATE is generated from an inverted version of the PWM signal. The rising edge of this signal LGATE is delayed by a dead time t DT to provide a safety margin to prevent the high-side switch HS and the low-side switch LS from being conductive at the same time. Otherwise, the propagation delay through the low-side driver 114 is considered negligible and not shown.

[0045] The time pulses PH1 and PH4 are generated at time t2, which is the blanking interval t BLANK after the falling edge of the PWM signal. These pulses only need to be long enough to trigger the sample-and-hold circuit. Also at time t2, the timing signal PH3 rises. This signal remains active until the end of the conductive interval for the low-side switch LS, e.g., time t3 coinciding with the rising edge of the PWM signal. The timing signal PH3 indicates the sense voltage V SNS is available. The timing signal PH6 is high for the time interval corresponding to the blanking interval t BLANK and, as shown, rises at the falling edge of the PWM signal.

[0046] The time pulse PH2 is generated just before the end of the available conductive interval to latch the final voltage. This is achieved by using the early PWM signal PWM_ADV so that the pulse PH2 is activated for a time interval t ADV before the end of the low-side conductive interval. Like pulses PH1, PH4, the duration of pulse PH2 is long enough to allow the sample-and-hold circuit to latch the voltage correctly. The time pulse PH5 is generated from time t1.

[0047] Figure 4A and Figure 4B Figures illustrate the detailed circuit arrangements 400A, 400B corresponding to the current estimator 400 of Figure 1 Each of these circuits includes a voltage sensor 410, a slope estimator 430, a voltage sampler circuit 440, 460, and a combiner and slope-based correction 470. The circuit arrangement 400A of Figure 4A is described in detail below. Next is a description of the circuit arrangement 400B of Figure 4B differing from the circuit of Figure 4A .

[0048] The voltage sensor 410 is configured to level-shift the voltage between the switching node SW and the ground and inversely amplify the voltage. The voltage sensor includes a voltage source 414 that level-shifts the input voltage by V OFFSET (For example, 300mV). As determined by R1, R2, R3, and R4, the amplifier 412 is configured to inversely amplify the input differential voltage. In a specific example, R1 = R2 = 15kΩ, and R3 = R4 = 120kΩ, so that the resultant sensed voltage V output by the voltage sensor 410 is SNS is level shifted by 300 mV and amplified by 8. Of course, other amplification levels and voltage offsets may be used, with the specific values ​​chosen depending on the voltage produced by the switching converter and the required input range of the slope estimate 430 and combiner circuit 470.

[0049] Slope estimator 430 includes switches 432, 434, a transconductance amplifier 436, a current setting switch Q1, a capacitor C6, and a resistor R6. These components combine to generate a current that is proportional to the sense voltage V SNS The slope of the inductor current I IND The slope of the current I1 is determined by the current mirror M2a, M2b, and M2c. This current I1 is mirrored using switches M2a, M2b, and M2c for use by other circuits. Another current mirror composed of M1a and M1b can mirror this current to provide a feedback path for slope estimation.

[0050] like Figure 3 As shown, the timing signal PH4 is immediately followed by the blanking interval t BLANK After the pulse, and the sample and hold switch 434 is triggered, so that the voltage V SNS Latched. This voltage, designated as V4, is initialized on holding capacitor C4. Also at time t2, timing signal PH3 closes switch 432, thereby latching voltage V SNS The switch 432 is kept closed until time t3, so that the voltage on the capacitor C3 (denoted as V3) is equal to the voltage V between time t2 and t3 (i.e., during the non-blanking conduction interval of the low-side switch). SNS Note that the voltages on capacitors C3 and C4 are exactly BLANK The same is true afterwards, ie, at time t2, V3 = V4.

[0051] Voltage V3 begins to decrease after time t2, resulting in a positive difference between voltages V4 and V3. These voltages are input to transconductance amplifier 436, which converts the difference between these voltages V DIFF (t)=V4(t)-V3(t) is converted into error current I ERR (t) = Gm *V DIFF (t) Error current I ERR The gate capacitor of current setting switch Q1 is charged. Switch Q1 has a gate capacitor C GS , the gate capacitor C GS is typically not sufficient to sufficiently filter and maintain the gate voltage V GS . As shown, the gate capacitor C GS is supplemented with an additional capacitor C6, e.g., adding a capacitance of about 20 pF to the gate capacitor C GS . The capacitance of C6 mainly determines the slew rate of transconductance amplifier 436, and thus the loop bandwidth of the correction. The additional capacitor C6 can be monolithically integrated with switch Q1, such that switch Q1 and capacitor C6 are in the same semiconductor die. In some embodiments, this capacitor can be omitted, e.g., if the gate capacitor is sufficiently high.

[0052] Once the gate capacitor and capacitor C6 are sufficiently charged, e.g., such that the gate voltage V GS is raised above the threshold voltage of switch Q1, the current setting switch Q1 starts to conduct. The resulting current I1 corresponds to the slope of the sensed voltage V SNS (t), and is scaled by resistor R6. As explained in further detail below, this correspondence is implemented via a feedback loop, in which current I C4 discharges charge from capacitor C4, thereby reducing voltage V4, such that voltage V4 tracks voltage V3. Once steady state operation is achieved, current I C4 should remain stable / constant, corresponding to the slope of the linear decrease of voltage V3 (corresponding to V SNS (t) between t2 and t3).

[0053] Current I1 flows through transistor M2a, and transistors M2b and M2c mirror this current. Current I2 flowing through mirrored transistor M2b is further mirrored using transistors M1a, M1b, thereby providing a feedback path for transconductance amplifier 436. Thus, current I C4 mirrors current I2 (and I1), and discharges charge from capacitor C4, such that voltage V4 tracks voltage V3 (V SNS (t) between t2 and t3). Feedback cutoff switch 438 is controlled by control signal PH7, such that the feedback loop is only enabled during the interval in which the sensed voltage V SNS is available (e.g., during the time interval between time t2a and t3 in Figure 3 . During other intervals, including the conductive interval of high-side switch HS and the blanking interval, switch 438 is open, such that the feedback loop is disabled and the slope estimate provided by the voltage across C6 is not updated.

[0054] Once the feedback loop reaches steady state, voltage V4 decreases at the same rate as voltage V3, and the input voltage to transconductance amplifier 436 is the same. This results in no current being output from transconductance amplifier 436, i.e., I SLOP_ERR =0, and the voltage across C6 and the gate voltage V GS These stable voltages produce a stable current I1 that corresponds exactly to the current I1 for the voltage V SNS (t) and current I LS The slope estimate of .

[0055] If voltage V4 is higher than voltage V3 (e.g., occurring immediately after time t2 when the slope estimate is first initialized), the positive voltage difference V DIFF is applied to the input of transconductance amplifier 436. This generates a positive current I SLOPE_ERR , the positive current I SLOPE_ERR Charges the gate capacitance of Q1 and increases the gate voltage V GS , thereby increasing the current I1 and the mirror image equivalent value of the current I1. The total increased current I C4 The voltage V4 is decreased until the voltage V4 matches and tracks V3.

[0056] Conversely, if voltage V4 is lower than voltage V3 (e.g., as occurs when the feedback loop overcorrects the slope estimate), the negative voltage difference V DIFF is applied to the input of transconductance amplifier 436. This generates a negative current I SLOPE_ERR , the negative current I SLOPE_ERR This discharges the gate capacitance of Q1 and reduces the gate voltage V GS , thereby reducing the current I1 and the mirror image equivalent value of the current I1. The total reduced current I C4 The rate at which voltage V4 is reduced is slowed so that voltage V4 accurately tracks V3.

[0057] As shown, current setting transistor Q1 and mirror transistors M1a, M1b are n-channel MOSFETs, while mirror transistors M2a, M2b, M2c are p-channel MOSFETs, but other switch types may be used. For example, in certain configurations of slope estimation circuit 430, junction field effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), high electron mobility transistors (HEMTs), or other types of power transistors may be preferred.

[0058] The closed-loop feedback configuration using the transconductance amplifier 436 and related components is based on the on-resistance R of the low-side power switch LS. DS_ON , provides a sense voltage V SNSAccurate estimation of the slope, the slope and the inductor current I IND The estimated slope is output from the slope estimation circuit 430 as the current I3.

[0059] During intervals other than the non-blanking conduction intervals during which the slope is estimated, the feedback loop can be disabled so that a valid slope estimate is available at other times. For example, switch 438 can be used to disable the gate of current mirror transistor M1a. Switch 438 is controlled by timing control signal PH7, which is identical to timing signal PH3 except that it is activated after a settling time for the voltage across capacitor C3.

[0060] The combiner and slope-based correction circuit 470A combines the voltage samples provided by the voltage sampler circuits 440, 460 and the slope estimate I3 provided by the slope estimator 430. The voltage sampler circuit 440 senses the voltage V at time t2. SNS The voltage V1 is sampled and the voltage sampler circuit 460 senses the voltage V at time t3. SNS Sampling is performed to provide a voltage sample V2. These voltages V1 and V2 are held by holding capacitors C1 and C2, respectively. Switch 471 enables the slope estimation current I3 to flow to capacitor C1 according to the timing signal PH6. Figure 3 As shown, the timing signal for PH6 starts to activate at time t3 and continues for the blanking interval t BLANK Therefore, if Figure 2 As shown in the waveform 230, the slope of the estimated current I3 in the blanking interval t BLANK The capacitor C1 is charged during the time t3, thereby increasing the voltage V1 across the capacitor C1. If the ringing and related artifacts do not corrupt the sensed voltage, the resultant voltage (e.g., at time t3+t BLANK V1 at time t1) approximates the expected sensed voltage V SNS (exist Figure 2 is marked as V0).

[0061] For the timing described, the capacitances of capacitors C1, C4 are substantially the same. The capacitances of capacitors C3, C2 and C5 are chosen to allow sufficient time to charge them and to enable them to retain their charge for a sufficient time interval.

[0062] At the end of the low-side conduction time, e.g. Figure 2 and Figure 3 At time t3, voltages V1 and V2 can be averaged to provide a sense voltage V SNSAccurate representation over the entire low-side conduction interval. The voltage V1 is effectively corrected using the slope estimated current I3. Voltage followers 472, 474 buffer the voltages V1, V2 and provide them to switches 476, 477. The timing signal PH5 latches these voltages onto capacitor C5 at a time after t3, so that the voltage across capacitor C5 is the average value of the voltages V1, V2 (the latch to C5 should occur after the sampled voltage V2 stabilizes and the voltage V1 reaches its steady state, otherwise the timing is somewhat flexible.). The voltage follower 478 buffers the resultant average value and provides it to an analog-to-digital converter (ADC) 480. In some implementations, the voltage follower 478 can be configured as an amplifier that provides a voltage range customized for the input range of ADC480. The ADC provides a digital signal V SNS_AVG , digital signal V SNS_AVG represents the average voltage V during the low-side conduction interval (e.g., between time t2 and t3). SNS Note that this average voltage for the low-side conduction interval can also be used as a representation of the entire switching period including the high-side conduction interval. SNS_AVG can be modified to compensate for the voltage offset and amplification provided by the voltage sensor 410. After such modification / compensation, the resultant signal can be compared with the on-state resistance R of the low-side power switch LS. DS_ON Used together to estimate the current I IND .

[0063] Note that the above description and Figure 2 and Figure 3 The specific timing shown can be modified and still achieve the same or similar results. For example, timing signal PH6 can be pulsed at any time after time t2 as long as sufficient time is provided for charging capacitor C1 before voltage V1 is latched by timing signal PH5.

[0064] As mentioned above, the sensing voltage V SNS The average value of t after time t3 BLANK The sample V1 is obtained at the time of t3+t BLANK ) is then compensated (corrected) using the slope estimate I3. The compensated version of V1 is averaged with the sample V2 taken at time t3, which corresponds to the end of the low-side conduction interval. The resulting average provides a measure of the sensed voltage V SNS In an alternative technique, the voltage samples V1, V2 obtained at t2 and t3 respectively are first averaged and then the compensation (correction) is applied. Such an alternative technique can be used Figure 4B This is achieved by the circuit device 400B.

[0065] Figure 4B The current estimation circuit arrangement 400B is illustrated, which is very similar to the current estimation circuit arrangement 400A of Figure 4A The following only describes those circuits that are obviously different.

[0066] The combiner and slope-based correction circuit 470B inputs the voltage samples VI, V2 captured by the sampling circuits 440, 460. However, as shown, the voltage across the capacitor CI does not increase due to the slope estimation current II. Instead, the capacitor CI simply holds the voltage sample VI. The voltage followers 472, 474 and the sampling circuits 476, 477 provide the average of the voltages VI, V2 onto the capacitor C5 in much the same way as described above. However, as shown, the voltage sample VI provided at this average has not been compensated (corrected). Figure 4A Figure 4A

[0067] The combiner and slope-based correction circuit 470B includes a summing amplifier 479 that adds a correction factor to the average of the voltages VI and V2. The slope estimation current I3 is fed to the resistor R8 to generate the correction V CORR = I3 * R8. This correction factor compensates for the fact that, if not for the ringing and related artifacts, the voltage sample VI would be less than the expected sensed voltage V SNS at time t2. Once the correction factor V CORR is added to the initial average of VI and V2, the combined voltage (i.e., the output of the amplifier 479) is provided to the ADC 480. Figure 2 The fourth waveform 240 of FIG. 2B shows the combined voltage, where the uncompensated average voltage (VI + V2) / 2 is determined at time t3 (or later) and compensated using the voltage correction V CORR .

[0068] The output of the amplifier 479 provides a voltage similar to the voltage provided by the voltage follower 478 of Figure 4A As described with respect to Figure 4A , the amplifier 479 can be configured to provide an amplified or attenuated voltage having a range that matches the expected input range of the ADC 480.

[0069] Figure 4A Another minor difference between the current estimation circuit arrangements 400A and 400B is that the gating switch 471 is not needed in the circuit arrangement 400B. Figure 4B

[0070] Figure 5A 5B Embodiments of methods 500A, 500B for estimating current in an inductor of a switched voltage converter are illustrated. These methods can be implemented in a current estimation circuit arrangement such as​​​​Figure 4A and Figure 4B implemented within the current estimation circuit shown and / or within a controller of the switched voltage converter. The illustrated method represents an example, and it will be appreciated that the order of steps can be rearranged to achieve the same effect, e.g. steps shown consecutively can be interchanged or performed in parallel where context and data dependencies allow. Furthermore, the illustrated method does not exclude additional steps.

[0071] The method 500A starts with a step of detecting 502 conduction of a low-side switch (e.g. the low-side switch LS of the switched voltage converter 100 of Figure 1 Fig. 1). After waiting 510 for a blanking interval, the voltage V DS across the low-side switch LS is sampled 520 at a time t2, the blanking interval allowing the voltage V DS across the low-side switch to stabilize. Also after the blanking interval, the slope of the voltage V DS or a corresponding sensed voltage is estimated 530. Based on the estimated slope, the voltage sampled at time t2 is updated 540. The updated version of the voltage V DS or its sensed voltage is again sampled 550 at a time t3, where time t3 is after time t2 and preferably aligned with the turn-off of the low-side switch LS. The updated version of the voltage sampled at time t2 is combined 560 with the voltage sample taken at time t3. The combined quantity is then converted 580 to an estimate of the current I LS in the low-side switch LS, which also corresponds to the current output from the switched voltage converter.

[0072] Figure 5B The method 500B is similar to the method 500A of Figure 5A and only the differences are described below. Unlike the method 500A, the voltage sample taken at time t2 520 is not updated. The voltage samples taken at times t2 and t3 are combined 560, but the combined quantity does not use the slope estimate. After the combining 560, the estimated slope is used to correct 570 the combined voltage.

[0073] The above methods describe voltage samples taken at times corresponding to the blanking interval after the turn-on of the low-side switch LS and at the turn-off of such switch. It will be appreciated that these samples need not be taken at these exact times, but can be taken at other locations within the LS conduction interval between the blanking interval and the turn-off. Furthermore, the slope estimate can be performed during all or part of such conduction interval. Although the slope estimate can be performed within this interval, the slope estimate can be saved and used later.

[0074] Figure 6 illustrates the source-drain voltage VSD_LS and the corresponding sensed voltage V SNS The waveforms, as output from the amplifier 412, correspond to the two switching periods of the voltage converter 100.

[0075] Figure 7 The waveforms illustrate the convergence of the slope estimate using the above described circuit arrangement and / or technique. The waveforms correspond to the transient response of the switched voltage converter, and the sum waveform used for the slope estimate. The convergence of the slope estimate requires several switching periods of the voltage converter.

[0076] For the sake of clarity, the above description focuses on an example in which the output current of the switched voltage converter is estimated using measurements taken across the low-side power switch. The described technique can be extrapolated to use measurements taken across the high-side power switch within the switched voltage converter. The output current (e.g., the current through the inductor of the switched voltage converter) can be estimated using measurements taken across the low-side switch LS, measurements taken across the high-side switch HS as described above, or based on measurements taken across both the high-side switch and the low-side switch.

[0077] While the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the present disclosure.

[0078] Example 1. According to one embodiment of a current estimation circuit, the current estimation circuit is configured to estimate a current in a power switch during a conduction interval of the power switch. The power switch is typically part of a switched power converter, and the estimated current corresponds to and can be equivalent to an output current of the switched power converter. The current estimation circuit includes a slope estimator and a sampler circuit. The slope estimator is configured to estimate a slope representative of the current in the power switch during a portion of the conduction interval starting at or after a first delay from a turn-on transition of the power switch. The sampler circuit is configured to generate a first sample corresponding to a first sensed voltage across the power switch at or after the first delay from the turn-on transition, and to generate a second sample corresponding to a second sensed voltage across the power switch, the second sensed voltage being after the first sensed voltage. The current estimation circuit is configured to estimate the current in the power switch over the conduction interval based on the first sample, the second sample, and the estimated slope.

[0079] Example 2. The current estimation circuit of example 1, further comprising an update circuit. The update circuit is coupled to the slope estimator and the sampler circuit, and is configured to generate a third sample based on the first sample and the estimated slope. The current estimation is based on a combination of the second sample and the third sample.

[0080] Example 3. The current estimation circuit of example 2, wherein the first sensed voltage corresponds to a first time and the second sensed voltage corresponds to a second time. The update circuit includes a first voltage node that is initialized with the voltage corresponding to the first sample and the voltage of the first voltage node is increased based on the estimated slope for a time interval that starts after the first time and continues for the delay time.

[0081] Example 4. The current estimation circuit of example 1, wherein the preliminary current estimate is based on a combination of the first sample and the second sample, and the preliminary current estimate is updated based on the slope estimate to produce the current estimate.

[0082] Example 5. The current estimation circuit of example 4, wherein the combination of the first sample and the second sample is generated by latching the first sample and the second sample such that the preliminary estimate is an average of the first sample and the second sample, and wherein the current estimation circuit includes a summing amplifier configured to sum the average with a correction factor, the correction factor sum being based on the estimated slope and the first delay.

[0083] Example 6. The current estimation circuit of example 1, further comprising a voltage sensor configured to sense a voltage across a load terminal of a power switch during a conduction interval, and provide the sensed voltage or a variation of the sensed voltage to the sampler circuit and the slope estimator.

[0084] Example 7. The current estimation circuit of example 1, wherein the slope estimator includes an amplifier, a first input switch, and a second input switch. The amplifier has a first amplifier input, a second amplifier input, and an amplifier output. A current at the amplifier output corresponds to an error in the slope estimate. The first input switch is configured to couple a sensed voltage across the power switch to the first amplifier input during a portion of the conduction interval that starts at or after the first delay from the transition to on. The second input switch is configured to output an initial amplifier sample to the second amplifier input, the initial amplifier sample being based on the sensed voltage sampled at a time that is at or after the first delay from the transition to on of the power switch.

[0085] Example 8. The current estimation circuit of example 7, wherein the slope estimator includes a feedback circuit that couples a signal corresponding to the estimated slope to the second amplifier input.

[0086] Example 9. The current estimation circuit of example 7, wherein the slope estimator includes a current setting transistor having a control terminal coupled to the amplifier output, and wherein a current in the current setting transistor corresponds to the estimated slope.

[0087] Example 10. The current estimation circuit of example 9, wherein the slope estimator comprises a current mirror configured to mirror a current in the current setting transistor, and wherein the mirrored current provides an estimated slope for estimating the current in the power switch.

[0088] Example 11. A power conversion system according to one embodiment, the power conversion system comprising a switched voltage converter and a current estimation circuit. The switched voltage converter comprises a power switch and an inductor. The current estimation circuit of the power conversion system is configured and comprises components as recited in example 1.

[0089] Example 12. The power conversion system of example 11, wherein the current estimation circuit further comprises a voltage sensor configured to sense a voltage across a load terminal of the power switch during a conduction interval, and provide the sensed voltage or a variation of the sensed voltage to the sampler circuit and the slope estimator.

[0090] Example 13. The power conversion system of example 11, wherein the switched voltage converter is a buck converter, the power switch is a low-side switch of the buck converter, and the buck converter further comprises a high-side switch.

[0091] Example 14. The power conversion system of example 13, wherein the estimated current in the inductor is based on the estimated slope, and wherein the estimated slope corresponds to a current in the low-side switch when the low-side switch is conducting.

[0092] Example 15. A method according to one embodiment, the method for estimating a current in a power switch having a switching voltage between a first load terminal and a second load terminal of the power switch. The method comprises turning the power switch on at a turn-on transition, and turning the power switch off at a turn-off transition. The method further comprises estimating a slope representative of a current in the power switch between a first time and a second time, the first time being a first delay after the turn-on transition, and the second time being after the first time and at or before the turn-off transition. The method comprises sampling the switching voltage at a first sampling time to produce a first sampled voltage, the first sampling time being at or after the first delay after the turn-on transition, and sampling the switching voltage at a second sampling time to produce a second sampled voltage, the second sampling time being after the first sampling time and at or before the turn-off transition. The method additionally comprises outputting an estimated current based on the first sampled voltage, the second sampled voltage, and the estimated slope.

[0093] Example 16. The method of example 15, further comprising updating the first sampled voltage based on the estimated slope, and combining the second sampled voltage and the updated first sampled voltage to generate the estimated current.

[0094] Example 17. The method of example 15, further comprising generating a preliminary current estimate based on a combination of the first sampled voltage and the second sampled voltage, and updating the preliminary current estimate based on the slope estimate and the first delay to generate the estimated current.

[0095] As used herein, the terms “have,” “having,” “include,” “including,” “include

[0096] It is to be understood that the features of the various embodiments described herein can be combined with each other, unless specifically noted otherwise.

[0097] While specific embodiments have been illustrated and described herein, it will be appreciated that various alternative and / or equivalent implementations can be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the application be limited only by the claims and the equivalents thereof.

Claims

1. A current estimation circuit for estimating a current in a power switch during a conduction interval of the power switch, the current estimation circuit comprising: a slope estimator configured to estimate a slope representative of the current in the power switch during a portion of the conduction interval beginning at or after a first delay from an on-transition of the power switch; and a sampler circuit configured to: generate a first sample corresponding to a first sensed voltage across the power switch at or after the first delay from the on-transition; and generating a second sample corresponding to a second sensed voltage across the power switch, the second sensed voltage being subsequent to the first sensed voltage, The current estimation circuit is configured to estimate a current in the power switch over the conduction interval based on the first sample, the second sample, and the estimated slope.

2. The current estimation circuit according to claim 1 , further comprising: an update circuit coupled to the slope estimator and the sampler circuit and configured to generate a third sample based on the first sample and the estimated slope, Wherein the current estimate is based on a combination of the second sample and the third sample.

3. The current estimation circuit according to claim 2, wherein the first sensing voltage corresponds to a first moment, and the second sensing voltage corresponds to a second moment; The update circuit includes a first voltage node that is initialized with a voltage corresponding to the first sample, and the voltage of the first voltage node increases based on the estimated slope starting after the first moment and lasting for a time interval of the first delay. 4 . The current estimation circuit of claim 1 , wherein a preliminary current estimate is based on a combination of the first sample and the second sample, and the preliminary current estimate is updated based on the estimated slope to produce the current estimate.

5. The current estimation circuit of claim 4 , wherein the combination of the first sample and the second sample is generated by latching the first sample and the second sample such that the preliminary current estimate is an average of the first sample and the second sample, and wherein the current estimation circuit includes a summing amplifier configured to sum the average with a correction factor based on the estimated slope and the first delay.

6. The current estimation circuit according to claim 1 , further comprising: A voltage sensor is configured to sense a voltage across a load terminal of the power switch during the conduction interval and provide the sensed voltage or a variation of the sensed voltage to the sampler circuit and the slope estimator.

7. The current estimation circuit according to claim 1 , wherein the slope estimator comprises: an amplifier having a first amplifier input, a second amplifier input, and an amplifier output, wherein a current at the amplifier output corresponds to an error in the estimated slope; a first input switch configured to couple a sensed voltage across the power switch to the first amplifier input during a portion of the conduction interval beginning at or after the first delay from the on-transition; as well as A second input switch is configured to output an initial amplifier sample to the second amplifier input, the initial amplifier sample being based on a sense voltage sampled at or after the first delay from the on-transition of the power switch. 8 . The current estimation circuit of claim 7 , wherein the slope estimator comprises a feedback circuit that couples a signal corresponding to the estimated slope to the second amplifier input.

9. The current estimation circuit of claim 7, wherein the slope estimator comprises a current setting transistor having a control terminal coupled to the amplifier output, and wherein a current in the current setting transistor corresponds to the estimated slope.

10. The current estimation circuit of claim 9, wherein the slope estimator comprises a current mirror configured to mirror the current in the current setting transistor, and wherein the mirrored current provides an estimated slope for estimating the current in the power switch.

11. The current estimation circuit of claim 1 , wherein the first delay comprises a blanking interval, wherein in an interval after the blanking interval and before a turn-off transition of the power switch, a slope of a voltage across a load terminal of the power switch is monotonic.

12. A power conversion system comprising: a switch-mode voltage converter having a power switch and an inductor, the power switch including a first load terminal and a second load terminal; a current estimation circuit for estimating a current in the power switch during a conduction interval of the power switch, the current estimation circuit comprising: a slope estimator configured to estimate a slope representative of the current in the power switch during a portion of the conduction interval beginning at or after a first delay from an on-transition of the power switch; and a sampler circuit configured to: generate a first sample corresponding to a first sensed voltage across the power switch at or after the first delay from the on-transition; and generating a second sample corresponding to a second sensed voltage across the power switch, the second sensed voltage being subsequent to the first sensed voltage, The current estimation circuit is configured to estimate a current in the power switch over the conduction interval based on the first sample, the second sample, and the estimated slope.

13. The power conversion system of claim 12 , wherein the current estimation circuit further comprises: A voltage sensor is configured to sense a voltage across the load terminals of the power switch during the conduction interval and provide the sensed voltage or a variation of the sensed voltage to the sampler circuit and the slope estimator.

14. The power conversion system of claim 12, wherein the switching voltage converter is a buck converter, the power switch is a low-side switch of the buck converter, and the buck converter further includes a high-side switch. 15 . The power conversion system of claim 14 , wherein the estimated current in the inductor is based on the estimated slope, and wherein the estimated slope corresponds to the current in the low-side switch when the low-side switch is conductive.

16. A method for estimating a current in a power switch, the power switch having a switching voltage between a first load terminal and a second load terminal of the power switch, the method comprising: During conduction switching, the power switch is turned on; During the shutdown transition, the power switch is turned off; estimating a slope representative of the current in the power switch between a first time instant that is a first delay after the on-transition and a second time instant that is after the first time instant and at or before the off-transition; sampling the switch voltage at a first sampling time to generate a first sampled voltage, the first sampling time being at or after the first delay after the on-transition; At a second sampling time, sampling the switch voltage to generate a second sampled voltage, wherein the second sampling time is after the first sampling time and before or at the time of the turn-off transition; An estimated current is output based on the first sampled voltage, the second sampled voltage, and the estimated slope.

17. The method according to claim 16, further comprising: updating the first sampled voltage based on the estimated slope; as well as The second sampled voltage and the updated first sampled voltage are combined to generate the estimated current.

18. The method according to claim 16, further comprising: generating a preliminary current estimate based on a combination of the first sampled voltage and the second sampled voltage, and The preliminary current estimate is updated based on the estimated slope and the first delay to generate the estimated current.

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