Debugging method of I2C slave device, I2C master device and storage medium

Abstract

The embodiment of the present application relates to the field of communication, and discloses a debugging method of I2C slave equipment, I2C master equipment and storage medium.In the present application, at least one test frequency is selected in the applicable clock frequency range of the pre-acquired I2C slave equipment; the access control timing of the I2C slave equipment is determined according to the test frequency and the pre-acquired timing template; the applicable clock frequency range of each I2C slave equipment on the bus is automatically acquired by the master equipment, and the test frequency is selected in the applicable frequency range; the access control timing of the I2C slave equipment is automatically determined in combination with the acquired timing template; the access control timing of the I2C slave equipment is efficiently and accurately obtained by means of automatic selection and debugging of the master equipment, and the problems of long time consumption and inaccurate control in the debugging process are avoided.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the field of communication, in particular to a debugging method of I2C slave device, I2C master device and storage medium. BACKGROUND

[0002] I2C (Inter-Integrated Circuit) is a kind of bidirectional synchronous serial bus developed by PHILIPS company, which is composed of a serial clock bus (SCK) and a serial data bus (SDA), and is widely used in electronic communication and other fields due to the advantages of few signal lines, simple operation and the like.

[0003] Generally, there are multiple I2C devices on an I2C bus, each of which can operate and access other I2C devices (slave devices) as a master device, and in the access process, the I2C device as the master device needs to provide a clock signal (CLK) and send relevant control signals to the I2C slave device according to a specific timing sequence, and the slave device responds to the control signals sent by the master device according to the clock signal provided by the master device. Generally, the communication between the master and the slave is a series of timing operation processes of organically organizing the clock signal, Start signal, Stop signal and ACK signal, and the method adopted in the prior art is that for each I2C slave device, an access control timing of the I2C slave device needs to be created manually according to different clock frequencies and timing sequences, and the slave device is debugged and verified one by one according to the created access control timing. SUMMARY

[0004] The embodiment of the present application aims to provide a debugging method of I2C slave device, I2C master device and storage medium, the master device selects at least one test frequency according to the pre-acquired applicable clock frequency range of the I2C slave device, and combines the selected test frequency with the pre-acquired timing template to perform a function test on the I2C slave device, so as to determine the control timing of the I2C slave device, that is, the master device can automatically determine the control timing of the I2C slave device, and efficient and accurate debugging of the I2C slave device is realized.

[0005] To solve the above technical problems, the embodiment of the present application provides a debugging method of I2C slave device, which comprises the following steps: selecting at least one test frequency in the pre-acquired applicable clock frequency range of the I2C slave device; and determining the access control timing of the I2C slave device according to the test frequency and the pre-acquired timing template.

[0006] The embodiment of the present application also provides an I2C master device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the debugging method of the I2C slave device.

[0007] The embodiment of the present application also provides a computer readable storage medium storing a computer program, and the computer program is executed by a processor to implement the debugging method of the I2C slave device.

[0008] Compared with the prior art, the embodiment of the present application automatically acquires the applicable clock frequency range of each I2C slave device on the bus, selects a test frequency in the applicable frequency range, and automatically determines the access control timing of the I2C slave device in combination with the acquired timing template, so that the access control timing of the I2C slave device is efficiently and accurately obtained through automatic selection and testing of the master device, and the problems of long time consumption and inaccurate control caused by manual debugging are avoided.

[0009] In addition, the access control timing of the I2C slave device is determined according to the test frequency and the pre-acquired timing template, which comprises: performing read-write testing on the I2C slave device according to the test frequency and the pre-acquired timing template, and determining the test frequency and the timing template used when the read-write testing result is passed as the access control timing of the I2C slave device. By determining the timing template and the test frequency used when the read-write testing result is passed as the access control timing of the I2C slave device, the accuracy of the obtained access control timing is ensured.

[0010] In addition, when the read-write testing on the I2C slave device according to the pre-acquired timing template and the test frequency fails, a new timing template generated by machine learning is acquired, read-write testing on the I2C slave device is performed according to the acquired timing template and the test frequency, and the test frequency and the timing template used when the read-write testing result is passed are determined as the access control timing of the I2C slave device. When the access control timing determined by the pre-acquired timing template and the test frequency fails in the read-write testing on the I2C slave device, a new timing template is generated by machine learning, and the access control timing that can successfully perform read-write testing on the I2C slave device is determined. By generating a new timing template and access control timing by machine learning, it is avoided that the pre-acquired timing template cannot meet the debugging requirements of the I2C slave device, and it is ensured that the access control timing of the I2C slave device can be accurately obtained.

[0011] In addition, when the read-write test of the I2C slave device fails according to the pre-acquired timing template and the test frequency, a new timing template is acquired according to the I2C slave device parameters input by the user, the read-write test of the I2C slave device is performed according to the acquired timing template and the test frequency, and the test frequency and the timing template adopted when the read-write test result is passed are determined as the access control timing of the I2C slave device. When the read-write test of the I2C slave device fails according to the pre-acquired timing template and the test frequency, the I2C slave device parameters input by the user are acquired, a new timing template is generated according to the acquired parameters, and the access control timing that can successfully perform the read-write test of the I2C slave device is determined. The timing template and the access control timing generated by acquiring the parameters input by the user ensure that the access control timing of the I2C slave device can be accurately acquired.

[0012] In addition, the access control timing of the I2C slave device includes that the test frequency and the timing template when the read-write test is passed are used to perform the read-write test of the I2C slave device multiple times, the test frequency and the timing template when the accuracy of the multiple read-write tests exceeds a preset threshold are determined as the access control timing of the I2C slave device, and when the accuracy of the multiple read-write tests does not exceed the preset threshold, the test frequency and the timing template when a new read-write test is passed are acquired, and the multiple read-write tests are performed again. Through the multiple read-write tests and the detection of the accuracy of the read-write tests, it is ensured that the determined access control timing can meet the accuracy required in the access control of the I2C slave device.

[0013] In addition, the at least one test frequency is selected from the applicable clock frequency range of the I2C slave device, which includes that the I2C slave devices on different addresses are detected at different clock frequencies within a preset clock frequency range, the applicable clock frequency range of the I2C slave devices on the different addresses is determined according to the highest frequency and the lowest frequency at which the I2C slave devices respond, and the at least one test frequency is selected from the applicable clock frequency range of the I2C slave device. By sending access test information to the I2C slave devices on different addresses and receiving the responses of the I2C slave devices, the applicable clock frequency range of the I2C slave devices can be accurately determined.

[0014] In addition, before the at least one test frequency is selected from the applicable clock frequency range of the I2C slave device, the address of the I2C slave device is detected according to the address of the I2C slave device when the applicable clock frequency range of the I2C slave device is acquired. By detecting and determining the address of the I2C slave device, it is ensured that the applicable clock frequency range of the I2C slave device on each address can be accurately acquired.

[0015] In addition, selecting at least one test frequency from the applicable clock frequency range of the pre-acquired I2C slave device comprises: dividing the applicable clock frequency range of the I2C slave device into three clock frequency intervals according to a preset ratio, and taking the clock frequency corresponding to the midpoint of each clock frequency interval as a test frequency. By dividing the frequency intervals according to the preset ratio and selecting a test frequency from each interval, it is ensured that the test frequency can cover different frequency bands as much as possible, and it is ensured that the access control timing obtained can meet most use scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example with reference to the figures that form a part of this patent specification. These illustrations are not intended to limit the embodiments to their specific embodiments described in this specification.

[0017] Figure 1 is a flowchart of the debugging method of the I2C slave device according to the first embodiment of the present application;

[0018] Figure 2 is a schematic diagram of address transmission in the debugging method of the I2C slave device according to the first embodiment of the present application;

[0019] Figure 3 is a schematic diagram of timing combination in the debugging method of the I2C slave device according to the first embodiment of the present application;

[0020] Figure 4 is a flowchart of the debugging method of the I2C slave device according to the second embodiment of the present application;

[0021] Figure 5 is a sub-flowchart of the debugging method in the debugging method of the I2C slave device according to the second embodiment of the present application;

[0022] Figure 6 is a flowchart of the debugging method of the I2C slave device according to the third embodiment of the present application;

[0023] Figure 7 is a schematic diagram of the I2C master device structure according to the fourth embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application, and the embodiments can be combined and referenced with each other without contradiction.

[0025] The first embodiment of the present application relates to a debugging method of an I2C slave device, which automatically accesses each I2C slave device by a master device and receives the response of the I2C slave device, acquires the applicable clock frequency range of the I2C slave device and selects a test frequency therefrom, obtains the control timing of the I2C slave device in combination with a pre-acquired timing template, and detects and debugs the I2C slave device by the master device, thereby greatly improving the efficiency of the debugging of the I2C slave device and the accuracy of the obtained access control timing.

[0026] The implementation details of the debugging method of the I2C slave device of the present embodiment will be described in detail below, and the following content is only provided for the implementation details for the convenience of understanding, and is not necessary for implementing the present solution.

[0027] The flowchart of the debugging method of the I2C slave device in the present embodiment is shown in Figure 1 , and specifically includes the following steps:

[0028] Step 101, acquiring the address of the I2C slave device on the I2C bus.

[0029] Specifically, within the preset clock frequency range of the I2C slave device, the master device sends an address request instruction to the specified address or standard address (7-bit address) on the bus at different clock frequencies, determines the address of the I2C slave device on the bus through the acquired response, and prompts the user to input the I2C slave device address when it is known that there is an undetected I2C slave device address on the bus.

[0030] In one example, in the interval of the limit value of the clock frequency applicable to the I2C device (1 ns ~ 1 s), a commonly used clock frequency such as 10 ms is selected, a standard address (1 ~ 255) on the bus is traversed to send a start signal plus a 7-bit address data and a 1-bit read-write flag to form an address request timing, and an ACK signal (information receiving confirmation character) of the I2C slave device is detected and received. According to the received address information, it is determined that the address of the I2C slave device on the bus is 0x51. In the automatic detection process of the master device, after the I2C slave device address request is performed on the traversed clock frequency and all standard addresses, if no I2C slave device is detected, the user is prompted to input the address of the I2C slave device, and the I2C slave device on the bus is determined according to the address input by the user.

[0031] In one example, it is known that the I2C slave device contains an I2C slave device with a nine-bit address. At the same time of sending the address request information to the standard address, the address request instruction is also sent to the remaining nine-bit addresses for detection of the I2C slave device. By traversing the address request instruction to all addresses in the nine-bit address, the address of the I2C slave device is determined by receiving the feedback of the I2C slave device. If the address of the I2C slave device is a 10-bit address, the address request instruction needs to be sent to the addresses (1 ~ 2043) on the bus. When the address request information is sent, the master device will send the complete address in two bytes. The first byte is 11110XX plus a read-write flag bit, XX is the high two bits of the address, and the low eight bits of the address are sent by the second byte. The specific diagram is shown in Figure 2 The I2C slave device at a specific address on the bus will only send an ACK signal to confirm the receipt when it receives a complete message of two bytes corresponding to its own position, so as to confirm that there is an I2C slave device at the address by the master device.

[0032] Step 102, obtaining the applicable clock frequency range of the I2C slave device and selecting a test frequency.

[0033] Specifically, in the preset clock frequency range of the I2C slave device, an access signal is sent to the address of the I2C slave device in a variable step size increasing manner, the I2C slave device is detected for access, and the highest clock frequency and the lowest clock frequency at which the I2C slave device responds to the access signal of the master device are used to determine the applicable clock frequency range of the I2C slave device. For the I2C slave device whose clock frequency has been specified, the address request instruction is directly sent using the set clock frequency. In the determined applicable clock frequency range of the I2C slave device, at least one clock frequency is selected as a test frequency according to the commonly used clock frequency of the I2C slave device or according to the use scene of the I2C slave device.

[0034] In one example, the clock frequency applicable to the I2C slave device contained in 0x51 is preset to 1 microsecond-10 milliseconds, and directly in this applicable clock frequency range, different clock frequencies, 1 microsecond, 10 microseconds, 500 microseconds, 1 millisecond, and 10 milliseconds, are selected according to the variable step method, and access instructions are sent to the I2C slave device at address 0x51 on the bus to detect the slave device. After the master device sends the access signal, the ACK signal given by the response of the slave device to the master device access is detected, and after receiving the ACK signal of the slave device, the relationship between the clock frequencies at which the I2C slave device responds is compared, and the highest frequency and the lowest frequency at which the I2C slave device responds are detected again according to the same principle, and the applicable clock frequency range of the I2C slave device is obtained as accurately as possible. When the I2C slave device receives the instruction of the master device, the highest clock frequency at which the I2C slave device responds to the access instruction of the master device is finally determined to be 2 microseconds, and the lowest clock frequency is 5 milliseconds, so the applicable clock frequency range of this I2C slave device is determined to be 2 microseconds-2 milliseconds. In this range, according to the possible application and working scene of the device, the interval from 2 microseconds to 5 milliseconds is divided into three intervals of 2 microseconds to 100 microseconds, 100 microseconds to 1000 microseconds, and 1000 microseconds to 2000 microseconds, and three clock frequencies of 50 microseconds, 500 microseconds, and 1 millisecond are selected as high, medium, and low test frequencies, so as to ensure that the finally determined access control timing can meet the processing speed of most devices.

[0035] Step 103, obtaining a timing template and determining the access control timing of the I2C slave device.

[0036] Specifically, when determining the applicable clock frequency range of the I2C slave device and selecting the test frequency, the master device also needs to determine the correct timing template corresponding to the I2C slave device for the I2C slave device, and perform read-write testing on the I2C slave device in combination with the test frequency, and the timing template and the test frequency used for read-write testing through the I2C slave device are determined as the access control timing of the I2C slave device.

[0037] In one example, after the applicable frequency of the I2C slave device is determined, the master device directly reads the pre-stored standard timing template and some specific timing templates in the storage space of the master device, combines each timing template with the selected test frequency, generates multiple access control timings, and performs access and read-write testing on the I2C slave device according to the generated multiple access control timings. The timing combination schematic diagram is as follows: Figure 3As shown in the figure, SCL and SD are signals of I2C serial bus, the start signal is that SCL keeps high level, and SDA jumps from high to low, the stop signal is that SCL keeps high level, and SDA jumps from low to high, the ACK signal is that SCL keeps high level, and SDA keeps low level, ADDRES occupying seven bits is the address of I2C slave device, the eighth bit is the read-write flag, R is the read flag, W is the write flag, and the DATA signal after the ACK signal is the read or written information. In the write phase, under the control of the access control timing generated by combining a timing template and a test frequency, a string CBD is written to an I2C slave device, and in the read phase, the read information is CB, at this time, it can be judged that the timing template cannot pass the read-write test, and the timing template and the test frequency used for the read-write test need to be replaced, and the I2C slave device is tested again in the write and read phases, under the control of all test frequencies combined with a timing template, it is detected that the information written and read to the I2C slave device is consistent, so the timing template and the test frequency are directly used as the access control timing of the I2C slave device. When all the timing templates combined with the test frequency cannot successfully complete the information writing and reading in the read-write test, the user is prompted that the access control timing cannot be automatically generated.

[0038] Therefore, the embodiment provides a debugging method of an I2C slave device, which automatically finds the adaptive frequency range of the I2C slave device through a master device, selects a test frequency, and determines a timing template suitable for the I2C slave device by combining the read-write test result of the master device, to automatically generate and accurately determine the access control timing of the I2C slave device, thereby greatly improving the debugging efficiency of the I2C slave device.

[0039] The second embodiment of the application relates to a debugging method of an I2C slave device. The second embodiment is basically the same as the first embodiment, and the main difference is that when all the read pre-stored timing templates combined with the test frequency cannot effectively control the I2C slave device to read and write, a new timing template combined with a test frequency is generated through machine learning to test and determine the access control timing, so as to ensure that the correct access control timing of the I2C slave device is obtained as much as possible, the I2C slave device is read and written for multiple times according to the timing template and the test frequency that can pass the read-write test, and when the read-write accuracy meets the requirement, the timing template and the test frequency are used as the access control timing of the I2C slave device.

[0040] The specific flowchart of the embodiment is shown as Figure 4 The specific steps include the following steps:

[0041] In step 401, the address of the I2C slave device on the I2C bus is acquired.

[0042] Step 402, obtain the applicable clock frequency range of the I2C slave device and select a test frequency.

[0043] Steps 401 and 402 in this embodiment are similar to steps 101 and 102 in the first embodiment, and will not be described again here.

[0044] Step 403, detect whether the pre-stored timing template in combination with the test frequency can complete the read-write test of the I2C slave device. If the read-write test can be completed, step 405 is entered. If the read-write test cannot be completed, step 404 is entered.

[0045] Specifically, the pre-stored timing template is first obtained in combination with the test frequency to perform the read-write test of the I2C slave device. It is detected whether the existing timing template in combination with the test frequency can complete the correct read-write of the I2C slave device. If it is detected that a certain pre-stored timing template and multiple test frequencies can correctly read and write the I2C slave device, the read-write accuracy detection is entered. If it is detected that all pre-stored templates in combination with multiple test frequencies cannot complete the read-write test, a new timing template is generated through self-learning.

[0046] Step 404, generate a new timing template through self-learning and determine the access control timing.

[0047] Specifically, through the obtained I2C slave device address and other parameters, in combination with the pre-stored timing template, the adaptive module in the machine will perform adaptive learning and generate a new timing template corresponding to the I2C slave device. In combination with the selected test frequency, the read-write detection of the I2C slave device is performed, and the read-write accuracy is judged. Finally, the access control timing of the I2C slave device is determined. When the machine learning cannot obtain the access control timing of the I2C slave device, the user is prompted that the access control timing cannot be obtained. The specific flow chart is as shown in Figure 5 The steps include:

[0048] Sub-step 501, generate a new timing template; through self-learning and the obtained I2C slave device parameters, a new timing template corresponding to the I2C slave device is generated.

[0049] Sub-step 502, detect whether the new timing template in combination with the test frequency can correctly read and write the I2C slave device. If the read-write can be correct, sub-step 503 is entered. If the read-write cannot be correct, sub-step 504 is entered.

[0050] Specifically, after obtaining the new timing template, in combination with the test frequency, the read-write test of the I2C slave device is performed. If the I2C slave device can be controlled to correctly read and write, the read-write accuracy test is performed. If the I2C slave device cannot be controlled to correctly read and write, the detection and judgment of the number of times of generating the timing template are performed.

[0051] Sub-step 503, detect whether the accuracy of multiple read-write tests on the slave device using the generated timing template and test frequency exceeds the preset threshold, if it exceeds the preset threshold, proceed to sub-step 506, if it does not exceed the preset threshold, proceed to step 504.

[0052] Specifically, when the accuracy of multiple read-write tests on the I2C slave device according to the new timing template and test frequency can meet the requirement of exceeding the preset threshold, it is determined that the access control timing can better control the I2C slave device, and the timing template and test frequency are taken as the access control timing when the I2C slave device is normally accessed. When the accuracy of multiple read-write tests is lower than the preset threshold, the control accuracy does not meet the requirement, and the number of times of generating a new timing template by machine learning is detected and judged.

[0053] Sub-step 504, judge whether the number of times of generating a timing template exceeds the preset number of times, if it exceeds the preset number of times, proceed to step 505, if it does not exceed the preset number of times, proceed to step 501.

[0054] Specifically, when the combination of the timing template generated by machine learning and the test frequency cannot meet the requirement of read-write test, the number of times of generating a new timing template by machine learning is first detected. When the number of times of generating a timing template exceeds the preset number of times, it is determined that machine learning cannot generate accurate I2C slave device access control timing, and the result of being unable to generate access control timing is output. When the number of times does not exceed the preset number of times, machine learning is performed again to generate a new timing template and combine the test frequency for read-write test.

[0055] Sub-step 505, output that access control timing cannot be generated by machine learning.

[0056] Sub-step 506, proceed to determine the access control timing; determine the timing template and test frequency that meet the read-write requirement as the access control timing and output, or output that the access control timing of the I2C slave device cannot be determined.

[0057] Step 405, perform multiple read-write tests on the I2C slave device according to the timing template and test frequency that pass the read-write test result.

[0058] Specifically, when it is detected that a certain pre-stored timing template and test frequency can correctly perform read-write test on the I2C slave device, the timing template at this time is obtained, combined with the test frequency, multiple repeated read-write tests are performed on the I2C slave device, and the test result of multiple read-write tests is obtained.

[0059] Step 406, judge whether the accuracy of multiple read-write tests exceeds the preset threshold, if it exceeds the preset threshold, proceed to step 407, if it does not exceed the preset threshold, proceed to step 403.

[0060] Specifically, the results of multiple read-write operations on the I2C slave device according to the selected timing template and test frequency are obtained, and the read-write accuracy is counted. When the read-write accuracy is higher than a preset threshold, it is directly determined that the I2C slave device can be accurately accessed and controlled, and the step of directly confirming the access control timing is performed. If the read-write accuracy does not exceed the preset threshold, it is determined that the I2C slave device cannot be accurately controlled, and the timing template needs to be excluded, and a timing template that can successfully read and write the I2C slave device in combination with the test frequency is re-obtained, and the access control timing of the I2C slave device is determined according to multiple read-write tests.

[0061] Step 407, determine the access control timing of the I2C slave device.

[0062] Specifically, when it is detected that the selected timing template and test frequency can correctly control the read-write of the I2C slave device and the read-write accuracy exceeds the preset threshold, the selected timing template and test frequency are used as the access control timing when the I2C slave device is normally accessed. When it is detected that the access control timing cannot be obtained, the user is prompted that the access control timing of the I2C slave device cannot be obtained.

[0063] Therefore, the embodiment provides a debugging method of an I2C slave device. In the process of determining the access control timing of the I2C slave device, the accuracy of the obtained access control timing is ensured through detection of read-write accuracy. When the pre-stored timing template combined with the test frequency cannot meet the requirements of read-write verification, a new timing template is generated through machine learning, and the access control timing of the I2C slave device is determined according to the test, thereby avoiding that the access control timing of the I2C slave device that meets the requirements cannot be obtained according to the pre-stored timing template, and the accuracy of the obtained access control timing is improved.

[0064] The third embodiment of the application relates to a debugging method of an I2C slave device. The main difference between the embodiment and the second embodiment is that when the access control timing that meets the requirements cannot be obtained based on machine learning, the user is prompted to input the parameters of the I2C slave device, and the I2C slave device is accurately debugged according to the input parameters to obtain the access control timing.

[0065] The flowchart of the embodiment is shown in Figure 6 The specific steps include the following steps:

[0066] Step 601, obtain the address of the I2C slave device on the I2C bus.

[0067] Step 602, obtain the applicable clock frequency range of the I2C slave device and select a test frequency.

[0068] Step 603, detecting whether the pre-stored timing template can complete the read-write test of the I2C slave device in combination with the test frequency, if the read-write test can be completed, entering step 605, if the read-write test cannot be completed, entering step 604.

[0069] Steps 601 to 603 in the embodiment are similar to steps 401 to 403 in the second embodiment, and will not be described here.

[0070] Step 604, generating a new timing template according to the I2C slave device parameters obtained from the timing setting interface.

[0071] Specifically, when the read-write test cannot be completed in combination with the pre-stored timing template and the test frequency, the user will be prompted to input the parameters of the I2C slave device, and the user inputs the number of I2C slave devices, clock frequency, address bit number, address, timing combination mode and other I2C slave device parameters in the timing setting interface, and a new timing template is generated according to the obtained I2C slave device parameters and the method of creating a timing template.

[0072] Step 605, performing multiple read-write tests on the I2C slave device according to the timing template and the test frequency that pass the read-write test results.

[0073] Step 606, judging whether the accuracy of multiple read-write tests exceeds a preset threshold, if the accuracy exceeds the preset threshold, entering step 608, if the accuracy does not exceed the preset threshold, entering step 603.

[0074] Steps 605 to 606 in the embodiment are similar to steps 405 to 406 in the second embodiment, and will not be described here.

[0075] Step 607, judging whether the generated timing template meets the read-write test requirements, if the generated timing template meets the requirements, entering step 608, if the generated timing template does not meet the requirements, entering step 604.

[0076] Specifically, after generating a new timing template according to the obtained I2C slave device parameters, performing read-write test on the I2C slave device in combination with the test frequency according to the generated timing template, and judging whether the timing template generated according to the I2C slave device parameters can complete the read-write test in the read-write test and whether the read-write accuracy exceeds the preset threshold, if the generated timing template cannot pass the read-write test or the read-write accuracy is lower than the preset threshold, generating a new timing template according to the I2C slave device parameters input by the user in combination with the timing template creation method, and re-performing detection of the read-write test results, if the generated timing template meets the requirements of the read-write test, entering the determination of the access control timing.

[0077] Step 608, determining the access control timing of the I2C slave device.

[0078] Based on the results of the read / write tests and the accuracy verification, the timing template and test frequency that meet the read / write test requirements will be used as the access control timing for the I2C slave device.

[0079] Therefore, this embodiment provides a debugging method for I2C slave devices. The master device first determines the access control timing of the I2C slave device by combining a pre-stored timing template with a timing template generated by machine self-learning. When the required access control timing cannot be obtained, the I2C slave device is precisely debugged by obtaining the I2C slave device parameters input by the user, thereby determining the access control timing of the I2C slave device and ensuring that the I2C slave device access control timing can be obtained accurately.

[0080] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0081] The fourth embodiment of the present invention relates to an I2C master device, the structural schematic diagram of which is shown below. Figure 7 As shown, it includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the debugging method for the I2C slave device as described above.

[0082] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0083] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0084] The fifth embodiment of the present application relates to a computer readable storage medium storing a computer program. The computer program is executed by a processor to implement the above method embodiments.

[0085] That is, those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by instructing the relevant hardware through a program stored in a storage medium, including a plurality of instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0086] Those skilled in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application.

Claims

1. A debugging method of an I2C slave device, characterized by, The method comprises: selecting at least one test frequency from the applicable clock frequency range of the pre-acquired I2C slave device; performing read-write test on the I2C slave device according to the test frequency and the pre-acquired timing template; performing multiple read-write tests on the I2C slave device based on the test frequency and timing template that pass the read-write test; determining the test frequency and timing template that pass the read-write test as the access control timing of the I2C slave device when the accuracy of the multiple read-write tests exceeds a preset threshold; when the accuracy of the multiple read-write tests does not exceed the preset threshold, acquiring a new test frequency and timing template that pass the read-write test, and re-performing the multiple read-write tests.

2. The method of claim 1, wherein, The read-write test on the I2C slave device according to the test frequency and the pre-acquired timing template comprises: performing read-write test on the I2C slave device according to the test frequency and the pre-existing local timing template, and generating a new timing template based on a preset machine learning model when the read-write test result does not pass; performing read-write test on the I2C slave device according to the test frequency and the new timing template; wherein the pre-acquired timing template comprises the pre-existing local timing template or the new timing template generated based on the preset machine learning model.

3. The method of claim 1, wherein, The read-write test on the I2C slave device according to the test frequency and the pre-acquired timing template further comprises: performing read-write test on the I2C slave device according to the test frequency and the pre-existing local timing template, and providing a timing template setting interface when the read-write test result does not pass; acquiring a new timing template generated according to the setting parameters of the timing template input by the user through the timing template setting interface; performing read-write test on the I2C slave device according to the test frequency and the new timing template.

4. The method of claim 1, wherein, Before selecting at least one test frequency from the applicable clock frequency range of the pre-acquired I2C slave device, the method further comprises: detecting the I2C slave device at different clock frequencies within a preset clock frequency range, and taking the highest frequency and the lowest frequency at which the I2C slave device responds as the upper limit value and the lower limit value of the pre-acquired applicable clock frequency range of the I2C slave device, respectively.

5. The method of debugging an I2C slave device according to claim 4, wherein, Before detecting the I2C slave device at different clock frequencies within a preset clock frequency range, the method further comprises: sending address request instructions to all addresses on the I2C bus at different clock frequencies within a preset clock frequency range, determining the address of the I2C slave device according to the received response, and detecting the I2C slave device according to the address of the I2C slave device when acquiring the applicable clock frequency range of the I2C slave device.

6. The method of claim 1, wherein, The method of selecting at least one test frequency from the applicable clock frequency range of the pre-acquired I2C slave device comprises: dividing the applicable clock frequency range of the I2C slave device into three consecutive clock frequency intervals, and taking the middle value of each clock frequency interval as a test frequency.

7. An I2C master device, characterized in that, The method comprises: at least one processor; and a memory in communication connection with the at least one processor; wherein The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of debugging an I2C slave device as claimed in any one of claims 1 to 6.

8. A computer readable storage medium storing a computer program, characterized in that, The computer program, when executed by a processor, implements the method of debugging an I2C slave device as claimed in any one of claims 1 to 6.

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