CAN frame double-edge resynchronization decoding method and device, equipment and storage medium

Abstract

The application discloses a CAN frame double-edge resynchronization decoding method and device, equipment and a storage medium, and relates to the field of signal processing. The scheme obtains the CAN frame signal of the sending end through the CAN simulation circuit, converts the digital waveform, and performs edge detection; based on the clock frequencies of the receiving end and the sending end, the rising edge delay and the falling edge delay of the sending end edge signal relative to the receiving end when the receiving end captures the edge signal are determined; the delay correction configuration is performed based on the rising edge delay and the falling edge delay, and the level timing and signal sampling are performed based on the edge signal after the delay correction; and the CAN frame information is decoded and output based on the bit value output by the signal sampling. The technology accurately calculates and corrects the edge delay difference caused by the clock deviation through the double-edge resynchronization mechanism, effectively corrects the timing deviation in combination with the dynamically adjusted sampling point position, has the advantages of effectively coping with the risk of synchronization failure and improving the decoding stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal processing, in particular to a CAN frame double-edge resynchronization decoding method and device, equipment and storage medium. BACKGROUND

[0002] Since the controller area network (CAN) protocol was developed by Bosch in 1986, it has become the core standard for communication between electronic control units in vehicles, and is widely used in key scenarios such as engine management, transmission control, and anti-lock braking systems. The protocol uses a multi-master structure and a non-destructive arbitration mechanism to ensure high real-time data transmission through message identifier priority, while combining differential signal transmission, cyclic redundancy check, and automatic retransmission mechanisms to significantly improve anti-interference capability and communication reliability. However, the CAN bus uses non-return-to-zero encoding, which has high efficiency but is prone to clock synchronization failure between the sending and receiving parties due to continuous multiple same-level signals. Specifically, when there is a clock frequency deviation between the sending and receiving ends, if the bus maintains a high or low level state for a long time, the receiving end may misjudge the bit boundary, for example, the sending end outputs five bits of signal, but the receiving end recognizes four or six bits, causing the sampling timing to be misaligned.

[0003] To alleviate this problem, the CAN protocol introduces bit stuffing rules, which force the insertion of reverse stuffing bits after five consecutive same-value bits to artificially generate level transition edges for the receiving end to resynchronize. The industry currently generally only uses falling edges as the resynchronization trigger condition, mainly because the CAN bus is normally high, and the falling edge is generated by active pull-down, so the signal edge is clearer and more stable. However, this single-edge resynchronization mechanism has inherent limitations: when the clock deviation is significant or the continuous same-value bits are long, relying solely on falling edges cannot fully correct the timing deviation, which can easily cause the sampling point to deviate from the ideal position, leading to decoding errors. Especially when the rising edge is blurred due to passive pull-up characteristics, the current solution cannot effectively utilize its potential synchronization value, resulting in decreased reliability of the system in complex electromagnetic environments or large clock drift scenarios.

[0004] Therefore, it is urgent to explore a more robust resynchronization strategy to address the risk of synchronization failure and improve decoding stability. SUMMARY

[0005] The present application provides a CAN frame double-edge resynchronization decoding method, device, equipment and storage medium, which has the advantages of effectively addressing the risk of synchronization failure and improving decoding stability.

[0006] In one aspect, the present application provides a CAN frame double-edge resynchronization decoding method, which comprises:

[0007] Obtain the CAN frame signal of the sending end through the CAN analog circuit, and convert the digital waveform and perform edge detection;

[0008] determining, based on clock frequencies of the receiving end and the sending end, a rising edge delay and a falling edge delay of the receiving end relative to a rising edge and a falling edge of the sending end when the receiving end captures the edge signal;

[0009] configuring a delay correction based on the rising edge delay and the falling edge delay, and performing level timing and signal sampling based on the edge signal after the delay correction; the delay correction specifically calculates the falling edge delay d1 T and the rising edge delay d2 T, and calculates a delay difference d between the two; the delay difference d is expressed as d = |d1 T-d2 T|; wherein T represents a length of time that the receiving end maintains each single-bit data signal, and d1 and d2 are electrical parameters;

[0010] Based on the delay difference d, a delay is applied to the side with a smaller delay value, and the delay target is to reduce the delay difference d to a target threshold, and the ideal condition is that the delay target is delay difference d = 0;

[0011] The bit value decoded from the signal sampling output is used to output CAN frame information.

[0012] Specifically, the length of time that the sending end maintains each bit data signal is f T, and is not fixed; the receiving end signal lags behind the sending end signal, and a CAN frame contains 1-5 bit values of the same level signal;

[0013] The falling edge delay d1 T: represents the time difference between the falling edge of the sending end and the falling edge of the receiving end;

[0014] The rising edge delay d2 T: represents the time difference between the rising edge of the sending end and the rising edge of the receiving end;

[0015] The receiving end falling edge is the resynchronization starting point of the continuous same level signal, and the receiving end rising edge is the resynchronization end point of the continuous same level signal;

[0016] The interval length between the resynchronization starting point and the next sampling point is s T; s is a proportional coefficient, and f is the deviation amplitude of the sending end clock relative to the receiving end clock.

[0017] Specifically, the level timing and signal sampling based on the edge signal after the delay correction comprises:

[0018] The receiving end and the sending end negotiate the length of the single-bit data signal, and configure the baud rate of the single-bit length;

[0019] Two resynchronization mechanisms are defined, one of which is triggered by the arrival of an edge signal, and the other of which is triggered based on the same level duration reaching a single-bit length; the single-bit length is determined by the configured baud rate;

[0020] Each bit period is timed by a counter, and a signal sample is taken whenever the single-bit length is reached.

[0021] Specifically, the edge signal of each CAN frame signal is taken as the resynchronization starting point, and the interval length s The first sampling point is determined at T, and the next sampling point is determined according to the single-bit length recorded by the counter, and so on, until the next edge signal is detected as the resynchronization end point.

[0022] Specifically, each sampling point is set at the middle position of each single-bit data signal at the receiving end, i.e., s T=T 1 / 2; the delay difference d between the falling edge delay and the rising edge delay is controlled to be 0.

[0023] Specifically, the corresponding bit value is output based on each determined sampling point position, and then the padding bit processing is performed according to the CAN protocol; except for the ACK stage, after each time the padding bit condition is met, the next bit value is skipped, and only the part that has not been skipped is sent to the CAN frame field state machine;

[0024] The CAN frame field state machine follows the CAN protocol to perform frame analysis work on the bit value information after padding processing according to the field length and conditions.

[0025] Specifically, the CAN frame signal of the sending end is obtained through the CAN analog circuit, and the digital waveform is converted and the edge is detected, including:

[0026] The information of the CAN differential line is converted into a CAN bus digital waveform of 1 and 0 binary through the CAN analog circuit; the CAN bus digital waveform is an asynchronous waveform;

[0027] The CAN bus digital waveform output by the analog circuit is tapped into a synchronous signal;

[0028] All rising edges from 0 to 1 and falling edges from 1 to 0 are detected and extracted from the synchronous digital waveform.

[0029] Specifically, when only a single-edge resynchronization is used, the level timing and signal sampling process is performed, and each sampling point is set at the middle position of each single-bit data signal at the receiving end, i.e., s=1 / 2; the delay difference between the falling edge delay d1 T and the rising edge delay d2 The delay difference range of the falling edge delay d1 T and the rising edge delay d2 T is (-0.25T, +0.25T).

[0030] In another aspect, the application provides a CAN frame double-edge resynchronization decoding device, which comprises:

[0031] a detection module, configured to acquire a CAN frame signal of a sending end through a CAN analog circuit, and convert a digital waveform and perform edge detection;

[0032] a determination module, configured to determine, based on clock frequencies of the receiving end and the sending end, a rising edge delay and a falling edge delay of the sending end edge signal when the receiving end captures the edge signal;

[0033] a sampling module, configured to perform delay correction configuration based on the rising edge delay and the falling edge delay, and perform level timing and signal sampling based on the delay-corrected edge signal; the delay correction configuration specifically calculates the falling edge delay d1 T and the rising edge delay d2 T, and calculates a delay difference d; the delay difference d is expressed as d=|d1 T-d2 T|; wherein T represents a length of time maintained by each single-bit data signal of the receiving end, and d1 and d2 are electrical parameters;

[0034] Based on the delay difference d, a delay is applied to the side with a smaller delay value, and the delay target is to reduce the delay difference d to a target threshold, and the ideal condition is that the delay target is delay difference d=0;

[0035] an output module, configured to decode and output CAN frame information based on a bit value output by the signal sampling.

[0036] In yet another aspect, the application provides a computer device, which comprises a processor and a memory, and the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the CAN frame double-edge resynchronization decoding method in the above aspect.

[0037] In yet another aspect, the application provides a computer-readable storage medium, which stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the CAN frame double-edge resynchronization decoding method in the above aspect.

[0038] The technical scheme provided by the embodiment of the application has at least the following beneficial effects: breaking through the limitation of traditional CAN decoding which only relies on a single falling edge for resynchronization, and dynamically compensating by using double information of rising edge and falling edge, effectively dealing with the problems of clock frequency deviation and synchronization failure in the case of continuous same level, thereby improving the stability of the decoding process. The double-edge resynchronization mechanism avoids the synchronization blind area caused by long same level, enables the receiving end to adaptively adjust based on the double-edge delay difference, ensures that the sampling point position is maintained in the effective area of the bit period, and finally realizes reliable decoding of CAN frame information. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A typical CAN2.0 frame format field content diagram in the related art is shown;

[0040] Figure 2 A most pessimistic example diagram of CAN frame decoding single-edge resynchronization is shown;

[0041] Figure 3 A most pessimistic example diagram of CAN frame decoding double-edge resynchronization is shown;

[0042] Figure 4 A flowchart of a CAN frame double-edge resynchronization decoding method provided by the embodiment of the application is shown;

[0043] Figure 5 An algorithm flowchart of a CAN frame double-edge resynchronization decoding method is shown;

[0044] Figure 6 An output sampling value diagram of a sampling point detection level signal is shown;

[0045] Figure 7 A structure block diagram of a CAN frame double-edge resynchronization decoding device provided by the embodiment of the application is shown;

[0046] Figure 8 A structure block diagram of a computer device provided by an example embodiment of the application is shown. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical scheme and advantages of the application clearer, the embodiments of the application will be further described in detail below with reference to the drawings.

[0048] In this paper, "a plurality of" refers to two or more. The association relationship of "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after it are in an "or" relationship.

[0049] In the traditional CAN bus communication, the synchronization failure phenomenon is caused in the sampling process of the receiving end due to the clock frequency deviation between the sending end and the receiving end and the occurrence of continuous same level signals. Among them, when a long string of same level bits is transmitted on the bus, the absence of level transition edges makes it impossible to perform resynchronization, causing the deviation between the local clock of the receiving end and the clock of the sending end to be accumulated. Further, the offset of the bit sampling position is caused, the accurate parsing of the data frame is affected, bit errors or frame errors are generated, and the reliability of the communication is reduced.

[0050] For example, in the specific application scenario of the automobile powertrain system, when the engine control unit sends a CAN frame to the gearbox control unit, the transmission of more than six consecutive high-level bits in the data field occurs. Since the bus is normally high, and the receiving end only relies on the falling edge for resynchronization, the absence of falling edges during continuous high-levels causes the synchronization mechanism to fail. Specifically, although the bit stuffing rule inserts a stuffing bit after five consecutive same-level bits, the clock deviation may cause misjudgment of the stuffing bit position, and thus the frame parsing fails. In this scenario, the receiving end cannot accurately identify the level transition edge, causing subsequent bit sampling errors and destroying the integrity of the control command.

[0051] If the above problems are not solved, the inevitable increase in bit errors is expected, and the integrity of the CAN frame is damaged. In critical control systems such as the anti-lock braking system, transmission anomalies of control commands are caused, the cooperative control function of the system is affected, and the safe operation of the vehicle is endangered. Therefore, the synchronization stability in the communication process is weakened, and the decoding reliability is continuously reduced, and a synchronization mechanism that can effectively cope with clock deviation and continuous same level challenges is urgently needed.

[0052] For the convenience of understanding, the following explains the terms involved in the embodiments of the present application:

[0053] CAN: Controller Area Network, Controller Area Network;

[0054] ECU: Electronic Control Unit, Electronic Control Unit;

[0055] ISO: International Organization for Standardization, International Organization for Standardization;

[0056] CRC: Cyclic Redundancy Check, Cyclic Redundancy Check;

[0057] ACK: Acknowledgement, the receiving side sends the sending side the receiving state of the data, here also refers to a field of CAN2.0 protocol frame; Figure 1

[0058] NRZ: Not Return Zero, here refers to non-return-to-zero encoding;

[0059] SOF / ID / RTR / IDE / R0 / DLC / DATA / CRC / CRCL / ACK / ACKL / EOF: the format content in Figure 1 , is the frame of each field of CAN2.0 protocol specification.

[0060] Figure 2 The most pessimistic example of single edge resynchronization of CAN frame decoding is shown. That is, the sending end sends a continuous 5-bit same level signal, and the receiving end loses synchronization due to the difference in clock frequency, that is, the receiving end detects the delay of the falling edge and the delay of the rising edge to different degrees. As to why synchronization is lost, the main reason is:

[0061] The clock of the sending end and the receiving end has a relative deviation;

[0062] If a large number of consecutive bits are the same value, the waveform will maintain the same level unchanged;

[0063] There may be a situation that the sending end sends 5 bits, and the receiving end thinks that it receives 4 or 6 bits.

[0064] The current CAN frame decoding usually only uses the falling edge as the resynchronization condition, which is also the recommended behavior of CAN protocol and the mainstream implementation scheme in the industry. Because the normal state of CAN bus is high level, the receiving and transmitting sides have the ability to actively pull down the bus to low level, and when released, it is passively pulled up to high level. Therefore, the falling edge is a more explicit behavior, and its edge is relatively sharper and clearer, and more reliable. But this does not mean that the rising edge cannot be used. If used properly, through double-edge resynchronization mechanism, better ability to resist synchronization failure can be obtained, and the decoding success rate can be improved.

[0065] Figure 2 The horizontal axis on the above is the time axis, and the time when the receiving end receives the falling edge is taken as the 0 time origin.

[0066] Set the length of a bit that the receiving end thinks as T, and other lengths are converted based on this length,

[0067] Receiving end: each green square represents a defined single-bit data signal, and the signal time length is T;

[0068] ​Transmitter: purple grid represents defined single-bit data signal, signal length is f T;

[0069] Red dotted line (sampling point): is the position of each green grid deviating from left to right by s T length;

[0070] Falling edge delay d1 T: time difference between falling edge of transmitter and falling edge of receiver;

[0071] Rising edge delay d2 T: time difference between rising edge of transmitter and rising edge of receiver;

[0072] Let delay difference d = |d1 T-d2 T|.

[0073] Wherein d1 and d2 are determined by electrical parameters of bus and chip simulation circuit, and often d1≠d2. However, because electrical parameters are not easily changed after being determined, it can be considered that the delay of any falling edge is stable d1 T. The delay of any rising edge is stable d2 T. s is a proportional coefficient, and f is the deviation amplitude of transmitter clock relative to receiver clock, for example, f=1.03 corresponds to 3% slower transmitter clock.

[0074] Each green grid represents that the receiver considers that one bit has passed,

[0075] The first bit is represented by n=0;

[0076] The second bit is represented by n=1;

[0077] By analogy, the (n+1)th bit is referred to as bit n.

[0078] Red dotted line (sampling point) is when the receiver considers to obtain the current value from the CAN bus.

[0079] Each green grid corresponds to a red dotted line, and the distance relative to the left end of the green grid is s T.

[0080] There are:

[0081] The sampling point time ts0 of bit 0 is (0+s) T;

[0082] The sampling point time ts1 of bit 1 is (1+s) T;

[0083] Similarly, the sampling point time tsnof bit n is (n + s) T.

[0084] According to the rule, the low level lasts for 5 bits at most, so the rising edge can occur at n = 0, 1, 2, 3, 4, corresponding to the low level lasting for 1, 2, 3, 4, 5 bits.

[0085] The bit is output by the sending end, and the sending end considers the length of one bit to be f T, and the length of n bits is n f T.

[0086] Considering the edge delay, the accurate time tpof the rising edge is (n f - d1 + d2) T.

[0087] For each possible rising edge, its time must be between the two sampling points before and after the bit to be correctly decoded.

[0088] The two sampling points before and after the bit are referred to as t1and t2, and t1< tp< t2, n = 0, 1, 2, 3, 4.

[0089] The high level lasts for 5 bits at most after the low level, so the falling edge can occur at the shortest n = 1 (1 bit of high and low level) and the longest n = 9 (5 bits of high and low level).

[0090] The delay of the two falling edges before and after the bit is offset, and the accurate time tnof the falling edge is n f T.

[0091] For each possible falling edge, the two sampling points before and after the bit are also required to be between the two sampling points to be correctly decoded.

[0092] The two sampling points before and after the bit are referred to as t3and t4, and t3< tn< t4, n = 1 ~ 9.

[0093] Let d = d1 T - d2 T, tp= (n f - d) T.

[0094] Considering the reasonableness of the values, 0 < f < 2, -1 < d < 1, 0 < s < 1, and n is an integer can be constrained.

[0095] t1< tp< t2can be expressed as: (n + s) < (n + 1) f - d < (n + 1 + s), which is true when 0 <= n <= 4.

[0096] t3 < tn < t4 can be expressed as: (n + s) < (n + 1) f < (n + 1 + s), which holds for 1 <= n <= 9

[0097] Whenever a set of d and s is selected, a range of f values fmin < f < fmax will be determined

[0098] This range of values represents the maximum allowable clock deviation range of the transmitter relative to the receiver

[0099] Let r = min(|fmax - 1|, |1 - fmin|), which represents the maximum allowable clock deviation. r = 0.03 indicates an allowable deviation of ±3%

[0100] Now it is necessary to make r reach the maximum value

[0101] Through program Monte Carlo simulation, the function graph of r(d, s) can be returned, and the conclusion is obtained that

[0102] During single-edge resynchronization, when d is within the range (-0.25, +0.25) and s = 0.5, the maximum value r = 0.05 is obtained

[0103] Continue to analyze the situation during double-edge resynchronization. Refer to Figure 3 The most pessimistic example diagram showing double-edge resynchronization of CAN frame decoding

[0104] All the prerequisite information is the same as that of single-edge resynchronization and will not be elaborated. The difference lies in the falling-edge sampling constraint of double-edge resynchronization. Let d = d1 T - d2 T, then tp = (n f - d) T, tn = (n f + d) T

[0105] t1 < tp < t2 can be expressed as: (n + s) < (n + 1) f - d < (n + 1 + s), which holds for 0 <= n <= 4

[0106] t3 < tn < t4 can be expressed as: (n + s) < (n + 1) f + d < (n + 1 + s), which holds for 0 <= n <= 4

[0107] The conclusion is obtained that during double-edge resynchronization, when d = 0 and s = 0.5, the maximum value r = 0.1 is obtained

[0108] By comparing the conclusions of single-edge resynchronization and double-edge resynchronization, it can be obtained that

[0109] Single edge resynchronization r upper limit low, d value wide.

[0110] Double edge resynchronization r upper limit high, d value strict.

[0111] This conclusion provides a theoretical basis for the conclusion that "double edge resynchronization has better decoding ability than single edge resynchronization under certain conditions."

[0112] Based on the above inference, the application provides a CAN frame double edge resynchronization decoding method, as shown in Figure 4 The method comprises the following steps:

[0113] S1, obtaining the CAN frame signal of the sending end through the CAN simulation circuit, and converting the digital waveform and performing edge detection;

[0114] The process mainly uses physical circuits and chips to receive and detect, such as using CAN differential signals, converting through analog circuits, and using Schmidt trigger and other devices to process and perform edge detection.

[0115] S2, based on the clock frequency of the receiving end and the sending end, determining the rising edge delay and falling edge delay of the receiving end relative to the rising edge signal of the sending end when the receiving end captures the edge signal;

[0116] This process is to assume that the time when the receiving end detects the edge signal is compared with the time when the sending end generates the edge signal, and the time sequence offset is generated. Specifically, a high-precision timer can be used to record the arrival time of the edge and compare it with the expected time, or a phase detection circuit can be used to measure the clock phase difference. For example, the first falling edge signal and the second rising edge signal both produce a certain delay. Figure 2

[0117] S3, based on the rising edge delay and the falling edge delay, performing delay correction configuration, and based on the edge signal after delay correction, performing level timing and signal sampling;

[0118] Delay correction configuration refers to adjusting the sampling time according to the double edge delay information to compensate for the clock deviation, which can use software algorithm to dynamically calculate the compensation value and update the counter threshold, or use adjustable delay line hardware circuit to apply fixed compensation amount. For example, based on historical delay data to fit the compensation curve, or using an adaptive filter to correct the sampling window in real time, which is mainly to realize the accuracy of level timing. Therefore, based on the edge signal after delay correction, level timing and signal sampling can be performed by using a programmable counter to count each bit period, and when the preset length is reached, the sampling operation is triggered.

[0119] ​To overcome the possible disadvantages of double-edge resynchronization (i.e., the delays of the rising edge and the falling edge to the receiving end may be different, resulting in inaccurate resynchronization points), the scheme introduces a double-edge delay difference correction mechanism. The mechanism analyzes the delay d1 of the falling edge and the delay d2 of the rising edge from the sending end to the receiving end, and according to the preset "delay correction configuration value", intentionally increases the delay of the side with smaller delay, so that the delay difference tends to be as close to zero as possible, thereby balancing the delays of the rising edge and the falling edge. In this way, the accuracy and reliability of double-edge resynchronization are ensured, and the decoding adaptability of the system in the presence of clock bias is significantly improved.

[0120] S4, the bit value decoding output based on the signal sampling output outputs CAN frame information.

[0121] The bit value decoding output based on the signal sampling output outputs CAN frame information refers to parsing the sampling results into data frames conforming to the CAN protocol. It can use a finite state machine to parse according to the field length, or process the bit sequence by table lookup method. The main purpose is to realize the correct recovery of CAN frame information.

[0122] The core innovation of the embodiment is to break through the limitation of traditional CAN decoding which only relies on a single falling edge for resynchronization, and to effectively cope with the synchronization failure problem under the condition of clock frequency deviation and continuous same level by using the double information of rising edge and falling edge for dynamic compensation, thereby improving the stability of the decoding process. The double-edge resynchronization mechanism avoids the synchronization blind area caused by long strings of the same level, so that the receiving end can adaptively adjust based on the delay difference of the double edges, ensure that the sampling point position is maintained in the effective area of the bit period, and finally realize reliable decoding of the CAN frame information.

[0123] For example Figure 2 and Figure 3 The design sets the length of each single-bit data signal maintained by the receiving end as T; the length of each bit data signal maintained by the sending end as f T, and is not fixed (i.e., the length of the single-bit level signal of the sending end is not fixed); the receiving end signal lags behind the sending end signal, and the analysis is usually performed on a CAN frame (period) of five bit lengths (maximum value);

[0124] The falling edge delay d1 T represents the time difference between the falling edge of the sending end and the falling edge of the receiving end;

[0125] The rising edge delay d2 T represents the time difference between the rising edge of the sending end and the rising edge of the receiving end;

[0126] The receiving end falling edge is the starting point of resynchronization of the continuous same level signal (i.e., the t0 position in Figure 3 ), and the receiving end rising edge (i.e.,Figure 3 The tp position is the resynchronization endpoint of consecutive signals with the same level;

[0127] The interval length between the resynchronization start point and the next sampling point is s. T; where d1 and d2 are electrical parameters, s is the proportionality coefficient, and f is the deviation of the transmitting clock from the receiving clock.

[0128] Before configuring delay compensation, calculate the following parameters:

[0129] Falling edge delay d1 T and rising edge delay d2 Determine the delay magnitude of T and calculate the delay difference d between the two; the delay difference d is expressed as d = |d1| T-d2 T|;

[0130] The delay configuration process is based on the delay difference d, applying a delay to the one with the smaller delay value. The delay goal is to reduce the delay difference d to a target threshold. Ideally, the delay goal is delay difference d = 0.

[0131] Figure 3 The diagram above illustrates the level delay for two possible scenarios, with the falling edge delay d1 in the figure above. T is less than the rising edge d2 At time T, the exact time of the rising edge is tp = ((n+1)). f-d1+d2)) T represents the delay applied to the falling edge; in the diagram below, the rising edge delay is d1. T is greater than the falling edge delay d2 At time T, a delay is applied to the falling edge.

[0132] Figure 5 The flowchart of the CAN frame dual-edge resynchronization decoding method is shown. The process of acquiring the CAN frame signal from the transmitting end through the CAN analog circuit, converting it into a digital waveform, and performing edge detection can be implemented through the following steps:

[0133] The CAN bus analog circuit converts the information of the CAN differential line into a binary CAN bus digital waveform of 1s and 0s. This CAN bus digital waveform is an asynchronous waveform.

[0134] The digital waveform of the CAN bus output from the analog circuit is stamped into a synchronization signal;

[0135] Detect and extract all rising edges from 0 to 1 and falling edges from 1 to 0 from the synchronized digital waveform.

[0136] Among them, the CAN bus digital waveform refers to the signal processing process of converting the analog signal on the CAN differential line into a binary logic level signal, which can be realized by a comparator circuit or a special CAN transceiver chip, and the purpose is to convert the physical layer differential signal into a discrete logic state convenient for digital system processing; The beat into a synchronous signal refers to the operation of sampling the asynchronous waveform by the local clock of the receiving end to eliminate the influence of clock deviation, which can be realized by using D flip-flop or register chain structure, and the purpose is to stabilize the signal level and avoid the risk of metastability, and ensure that the waveform remains deterministic at the sampling time; Edge detection refers to the technical implementation of identifying the level jump point, which can be realized by using XOR gate combination logic or finite state machine, and the purpose is to accurately capture the time reference point of signal change and provide reliable basis for subsequent delay calculation.

[0137] Specifically, the scheme of the present application first converts the CAN differential signal into an asynchronous digital waveform to complete the mapping of physical signal to digital signal, then synchronizes the waveform using the receiving end clock to eliminate the signal drift caused by clock frequency deviation, and finally performs edge detection operation on the basis of the synchronous signal, thereby forming a complete technical chain from signal acquisition to edge positioning. In this chain, the synchronization of the asynchronous waveform as a key link effectively isolates the influence of the clock difference between the sending end and the receiving end on the integrity of the signal, ensures the time stability of the waveform relied on by the subsequent edge detection, and further provides accurate edge position information for delay correction configuration.

[0138] After applying delay correction, further level timing and signal sampling are performed on the corrected signal, that is, the level value is obtained by referring to the dotted line position in Figure 3 The specific process includes:

[0139] 1. The receiving end and the sending end negotiate the length of the single-bit data signal, and configure the baud rate of the single-bit length;

[0140] 2. Two kinds of resynchronization timing mechanisms are defined, one of which is triggered by the arrival of the edge signal, and the other is triggered based on the same level duration reaching the single-bit length; The single-bit length is determined by the configured baud rate;

[0141] 3. The counter is used to time each bit period, and signal sampling is performed whenever the single-bit length is reached.

[0142] Among them, the length of the single-bit data signal is negotiated in advance by the receiving end and the sending end, which is used to accurately define the length of 1-bit signal and realize accurate acquisition.

[0143] bit period timing, taking the green grid in Figure 3 as an example, there are two starting conditions:

[0144] Edge detected (falling edge, both edges for double-edge resynchronization, rising edge as well)

[0145] Grid length is one bit

[0146] Two reset conditions of the counter in bit period timing:

[0147] Edge signal sent after double-edge delay difference correction

[0148] Internal counter counts one bit length.

[0149] In practical applications, the counter can be a hardware timer or a software counting logic module for accurately tracking the bit period, and the purpose is to provide a stable timing reference to ensure accurate sampling timing.

[0150] In the embodiments of the present application, the edge signal of each CAN frame signal is taken as the resynchronization starting point, and the interval length s The first sampling point is determined at T, and the next sampling point is determined according to the single-bit length recorded by the counter, and so on, until the next edge signal is detected as the resynchronization end point. For example, Figure 3 The falling edge in the upper diagram in FIG. 1 is taken as the resynchronization starting point, and the next edge signal is taken as the resynchronization end point (which is also the edge signal of the starting phase of the next CAN frame).

[0151] Sampling output process: the counter in bit period timing is incremented with the green grid, and when the value of the counter is equal to the sampling time configuration value, the sampling point is given. This behavior corresponds to the red dashed line in FIG. 1, and the distance from the start of the green grid is s Figure 3 T.

[0152] As can be seen from the foregoing conclusion, double-edge resynchronization requires s to be as close to 0.5 as possible to obtain the maximum r value. Figure 6 A schematic diagram of the sampling point detection level signal output sampling value is shown, and the sampling time configuration value is configured according to the actual situation to control the sampling when the counter counts exactly half of one bit length.

[0153] It should be noted that when only single-edge resynchronization is used, the present application can still be improved based on the foregoing inference content, and the level timing and signal sampling process are performed, and each sampling point is set at the middle position of each single-bit data signal received at the receiving end, that is, s = 1 / 2; the delay difference range of the falling edge delay d1 T and the rising edge delay d2 T is (-0.25T, +0.25T), which can also achieve a certain decoding improvement effect.

[0154] ​Further, bit filling processing is performed, which outputs corresponding bit values based on each determined sampling point position, and then performs bit filling processing according to the CAN protocol. Except for the ACK stage, after detecting that the bit filling condition is met, the next bit value is skipped, and only the part that is not skipped is sent to the CAN frame field state machine.

[0155] The CAN frame field state machine complies with the CAN protocol, and performs frame parsing on the bit value information after the bit filling processing according to the field length and conditions.

[0156] The bit filling condition refers to the detection of five consecutive same level bits, which can be achieved by using a bit counter to count the consecutive same level bits, and the purpose is to identify the bit filling position that needs to be processed. The next bit value is skipped, which means that after detecting that the bit filling condition is met, the subsequent bit value is ignored, and this can be achieved by skipping the transmission or processing of the bit in the data stream, and the purpose is to prevent the bit filling from being misinterpreted as valid data. The CAN frame field state machine refers to a finite state machine used to parse the CAN frame structure, which can be implemented by using a hardware logic circuit or a software state machine, and the purpose is to divide and parse the bit value stream according to the protocol specification. This step is already at the frame protocol level, and is not related to the decoding logic of the physical layer itself, so it will not be described in detail here.

[0157] Through the above scheme, the method effectively solves the synchronization failure problem caused by clock frequency deviation and continuous same level through the cooperative use of double-edge information. Specifically, the traditional single-edge resynchronization mechanism is prone to sampling drift due to the absence of the jump edge in the long string of same level scenarios. However, the present scheme achieves targeted compensation for clock deviation by simultaneously analyzing the delay characteristics of the rising edge and the falling edge. The delay correction configuration process dynamically corrects the timing reference based on the difference between the double-edge delays, so that the sampling point always remains in a reliable region of the bit period, thereby avoiding synchronization loss caused by continuous same level. Thus, under the condition of the jump edge absence triggered by the bit filling rule, signal sampling can still maintain high precision, ensuring accurate decoding of the CAN frame information, and significantly improving the synchronization stability and decoding reliability of the communication process.

[0158] Figure 7 FIG. 1 is a structural block diagram of a CAN frame double-edge resynchronization decoding device provided by an embodiment of the present application. The device includes:

[0159] The detection module 710 is configured to obtain the CAN frame signal of the sending end through the CAN simulation circuit, and convert the digital waveform and perform edge detection.

[0160] The determination module 720 is configured to determine the rising edge delay and the falling edge delay of the edge signal of the receiving end relative to the edge signal of the sending end based on the clock frequencies of the receiving end and the sending end.

[0161] a sampling module 730, configured to perform delay correction configuration based on the rising edge delay and the falling edge delay, and perform level timing and signal sampling based on the delay-corrected edge signal;

[0162] an output module 740, configured to decode and output CAN frame information based on bit values output by the signal sampling.

[0163] It should be noted that the CAN frame double-edge resynchronization decoding apparatus provided in the embodiments of the present application is only exemplified by the division of the above functional modules / functional units, and in actual application, the above functions can be completed by different functional modules / functional units according to needs, that is, the internal structure of the CAN frame double-edge resynchronization decoding apparatus is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation of the CAN frame double-edge resynchronization decoding method provided in the method embodiments belongs to the same concept as the implementation of the CAN frame double-edge resynchronization decoding apparatus provided in the embodiments, and the specific implementation process of the CAN frame double-edge resynchronization decoding apparatus provided in the embodiments is described above in the method embodiments, which will not be repeated here.

[0164] Figure 8 A structural block diagram of a computer device provided by an example embodiment of the present application is shown. The computer device can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The computer device can include, but is not limited to, a memory and a processor (hereinafter referred to as a processor). The memory stores at least one instruction, at least one program, a code set or an instruction set. The at least one instruction, at least one program, code set or instruction set is loaded and executed by the processor to implement the GPU scheduling strategy execution method described in the above aspects. The processor and the memory can be connected by a bus or other means. The processor can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, graphics processing units (GPUs), embedded neural network processing units (NPUs) or other dedicated deep learning coprocessors, discrete gate or transistor logic devices, discrete hardware components, and the like chips, or combinations of the above chips.

[0165] The processor can include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor can also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a CPU (Central Processing Unit), and the coprocessor being a low-power processor for processing data in a standby state. In some embodiments, the processor can be integrated with a GPU (Graphics Processing Unit) for rendering and drawing content required to be displayed by the display screen. In some embodiments, the processor can further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

[0166] In some embodiments, the computer device can further optionally include a peripheral device interface and at least one peripheral device. The processor, the memory, and the peripheral device interface can be connected through a bus or a signal line. Each peripheral device can be connected to the peripheral device interface through a bus, a signal line, or a circuit board. Specifically, the peripheral device includes a physical network card, and at least one of a radio frequency circuit, a display screen, and a keyboard.

[0167] The embodiments of the present application further disclose a computer readable storage medium. Specifically, the computer readable storage medium is used to store a computer program, and the computer program is executed by a processor to implement the method in the above method embodiments. Those skilled in the art can understand that all or part of the processes in the above method embodiments of the present application can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above embodiments. The storage medium can be a magnetic disc, an optical disc, a ROM (Read-Only Memory), a RAM (Random Access Memory), a flash memory, a hard disk (HDD) or a solid-state disk (SSD), etc. The storage medium can also include a combination of the above types of memories.

[0168] The specific embodiments are only illustrative of the present application, and are not intended to limit the present application. Those skilled in the art can make modifications to the embodiments without creative contribution after reading the specification, and the modifications are protected by the patent law as long as they are within the scope of the claims of the present application.

Claims

1. A method of CAN frame double-edge resynchronization decoding, characterized in that, The method comprises: The CAN frame signal of the sending end is acquired by the CAN simulation circuit, and a digital waveform is converted and edge detection is performed; Based on the clock frequencies of the receiving end and the sending end, the rising edge delay and the falling edge delay of the receiving end relative to the rising edge and the falling edge of the sending end are determined when the receiving end captures the edge signal; Based on the rising edge delay and the falling edge delay, delay correction configuration is performed, and level timing and signal sampling are performed based on the edge signal after delay correction; the delay correction configuration specifically calculates the delay size of the falling edge delay and the rising edge delay d2*T, and calculates the delay difference d between the two; the delay difference d is represented as d=|d1*T-d2*T|; wherein T represents the length of time that each single-bit data signal of the receiving end is maintained, d1 and d2 are electrical parameters; the falling edge delay d1*T represents the time difference between the falling edge of the sending end and the falling edge of the receiving end, and the rising edge delay d2*T represents the time difference between the rising edge of the sending end and the rising edge of the receiving end; the level timing and signal sampling specifically negotiate the length of time of the single-bit data signal between the receiving end and the sending end, and configure the baud rate of the single-bit length; Two resynchronization timing mechanisms are defined, one of which is triggered by the arrival of the edge signal, and the other of which is triggered based on the same level duration reaching the single-bit length; the single-bit length is determined by the configured baud rate; the counter is used to time each bit period, and signal sampling is performed whenever the single-bit length is reached; Based on the delay difference d, the party with the smaller delay value is subjected to delay, and the delay target is to reduce the delay difference d to a target threshold, and the ideal condition is that the delay target is delay difference d=0; The bit value decoded based on the signal sampling output is used to output the CAN frame information.

2. The method of claim 1, wherein, The length of time that each bit data signal of the sending end is maintained is f*T, and is not fixed; the receiving end signal lags behind the sending end signal, and one CAN frame contains 1-5 bit values of the same level signal; The receiving end falling edge is the resynchronization starting point of the continuous same level signal, and the receiving end rising edge is the resynchronization ending point of the continuous same level signal; The interval length between the resynchronization starting point and the next sampling point is s*T; s is a proportionality coefficient, and f is the deviation amplitude of the sending end clock relative to the receiving end clock.

3. The method according to claim 1 or 2, characterized in that, The edge signal of each CAN frame signal is used as the resynchronization starting point, the first sampling point is determined at the interval length s*T, the single-bit length recorded by the counter is used as the next sampling point, and so on, until the next edge signal is detected as the resynchronization ending point.

4. The method of claim 1, wherein, Each sampling point is arranged at the middle position of each single-bit data signal of the receiving end, i.e. s*T=T*1 / 2; the delay difference d between the falling edge delay and the rising edge delay is controlled to be 0.

5. The method of claim 4, wherein, The corresponding bit value is output based on each determined sampling point position, and then the padding bit processing is performed according to the CAN protocol; except for the ACK stage, the next bit value is skipped after detecting that the padding bit condition is met, and only the part that has not been skipped is sent to the CAN frame field state machine; The CAN frame field state machine follows the CAN protocol to perform frame analysis work on the bit value information after the padding processing according to the field length and the condition.

6. The method of claim 1, wherein, The CAN frame signal of the sending end is acquired through the CAN analog circuit, and a digital waveform is converted and edge detection is performed, including: The information of the CAN differential line is converted into a CAN bus digital waveform of 1 and 0 binary through the CAN analog circuit, and the CAN bus digital waveform is an asynchronous waveform; The CAN bus digital waveform output by the analog circuit is punched into a synchronous signal; All rising edges of 0 to 1 and falling edges of 1 to 0 are detected and extracted from the synchronous digital waveform.

7. The method of claim 1, wherein, When only a single edge resynchronization is used, level timing and signal sampling processes are performed, each sampling point is set at the middle position of each single-bit data signal of the receiving end, that is, s=1 / 2; the delay difference range of the falling edge delay d1*T and the rising edge delay d2*T is (-0.25T, +0.25T).

8. A CAN frame double-slope resynchronization decoding apparatus, characterized by comprising: The device comprises: A detection module for acquiring the CAN frame signal of the sending end through the CAN analog circuit, converting a digital waveform, and performing edge detection; A determination module for determining, based on the clock frequencies of the receiving end and the sending end, the rising edge delay and the falling edge delay of the receiving end relative to the edge signal of the sending end when the receiving end captures the edge signal; A sampling module for performing delay correction configuration based on the rising edge delay and the falling edge delay, and performing level timing and signal sampling based on the edge signal after delay correction; the delay correction configuration specifically calculates the delay sizes of the falling edge delay d1*T and the rising edge delay d2*T, and calculates the delay difference d between the two; the delay difference d is represented as d=|d1*T-d2*T|; wherein T represents the length of time that each single-bit data signal of the receiving end is maintained, and d1 and d2 are electrical parameters; the level timing and signal sampling specifically negotiate the length of the single-bit data signal between the receiving end and the sending end, and configure the baud rate of the single-bit length; Two resynchronization timing mechanisms are defined, one of which is triggered by the arrival of the edge signal, and the other of which is triggered based on the same level duration reaching the single-bit length; the single-bit length is determined by the configured baud rate; a counter is used to time each bit period, and signal sampling is performed whenever the single-bit length is reached; Based on the delay difference d, the smaller one of the delay values is delayed, and the delay target is to reduce the delay difference d to a target threshold, and the ideal condition is that the delay target is delay difference d=0; An output module for decoding and outputting CAN frame information based on the bit value output by signal sampling.

9. A computer device, comprising: The computer device comprises a processor and a memory, and the memory stores at least one instruction, at least one program, a code set or an instruction set, which is loaded and executed by the processor to implement the CAN frame double-edge resynchronization decoding method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, which is loaded and executed by the processor to implement the CAN frame double-edge resynchronization decoding method according to any one of claims 1 to 7.

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