A data processing method and a data processing apparatus

Abstract

This application discloses a data processing method and a data processing apparatus. First data processing is performed on multiple first data streams encoded with a first FEC to obtain m second data streams. Each second data stream undergoes second FEC encoding, and each codeword after second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, and S represents the number of parity bits. Second data processing is performed on each of the m second data streams to obtain m third data streams. Each third data stream includes at least one bit sequence, each bit sequence including P + W bits, where P bits in each bit sequence come from the second data streams, and W bits in each bit sequence are added alignment markers, where P = N × b. Third data processing is performed on the m third data streams to obtain Y modulation symbol streams, each modulation symbol stream being modulated, and the baud rate value of each modulation symbol stream being an integer multiple of the typical Ethernet reference clock frequency value.

Description

[0001] This application is a divisional application of the original application, application number 202480001044.8, filed on July 21, 2023, the entire contents of which are incorporated herein by reference. This application claims priority to Chinese Patent Application No. 202211307290.5, filed on October 24, 2022, entitled "A Data Processing Method and Data Processing Apparatus"; Chinese Patent Application No. 202211559068.4, filed on December 6, 2022, entitled "A Data Processing Method and Data Processing Apparatus"; and Chinese Patent Application No. 202310631032.0, filed on May 30, 2023, entitled "A Data Processing Method and Data Processing Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and more particularly to a data processing method and a data processing apparatus. Background Technology

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, Ethernet networks are evolving towards greater capacity, higher speeds, and lower latency. Using forward error correction (FEC) to correct transmitted data can resolve transmission errors and recover the original data sent by the transmitter from the received data.

[0004] A cascaded FEC transmission scheme is currently proposed, where the transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, modulates the bit sequence of the second FEC-encoded data to generate a corresponding modulation symbol sequence, and finally transmits the generated modulation symbol sequence to the receiving end via optical fiber. The data stream received at the receiving end is asynchronous and noisy. Typically, clock and data recovery (CDR) based on a phase-locked loop (PLL) is used. This involves extracting the clock from the data, retiming the data to remove jitter during transmission, and then demodulating and decoding to recover the original data sent by the transmitting end. However, the PLL circuit implementation used in existing schemes for CDR at the receiving end is complex, and the PLL jitter is relatively high. Summary of the Invention

[0005] This application provides a data processing method and a data processing device. On the one hand, it simplifies the way the receiving end extracts and synchronizes the clock, enabling fast phase locking, low PLL complexity and low jitter. On the other hand, it simplifies the receiving end's frame synchronization, internal code word synchronization and other operations, resulting in lower implementation complexity.

[0006] In a first aspect, embodiments of this application provide a data processing method applied to a sending end, comprising the following steps: First, multiple first data streams encoded by a first FEC are processed to obtain m second data streams. Here, m is an integer greater than 1, each second data stream is encoded by a second FEC, and each codeword after the second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, S represents the number of parity bits, K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. Next, the m second data streams are processed by a second data processing method to obtain m third data streams. Each third data stream includes at least one bit sequence, each bit sequence includes P + W bits, where P bits in each bit sequence come from the second data streams, and W bits in each bit sequence are added alignment identifiers, where P = N × b, and b is an integer greater than or equal to 1. Then, the m third data streams are processed to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1. Each modulated symbol stream is modulated, and the baud rate of each modulated symbol stream is an integer multiple of the reference clock frequency.

[0007] In this implementation, P bits are periodically extracted from the concatenated FEC-encoded data stream, and an alignment identifier of length W bits is inserted, ensuring that every P+W bits in the data stream contains an alignment identifier of length W bits. By selecting positive integers P and W, the baud rate of the modulation symbol data stream can be made an integer multiple of the Ethernet common reference clock frequency, simplifying the clock extraction and synchronization at the receiver, enabling fast phase locking, and resulting in low PLL complexity and low jitter. Furthermore, P is required to be a multiple of the inner code length N, i.e. After the receiving end performs frame synchronization (i.e., frame synchronization of P+W bits, also known as identifier locking operation) on the received data, the internal code word synchronization can be guaranteed, which simplifies the frame synchronization and internal code word synchronization operations at the receiving end and reduces the complexity of implementation.

[0008] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0009] In some possible implementations, each second data stream undergoes convolutional interleaving before being encoded by the second FEC. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their numbers. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r... The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0010] In some possible implementations, after convolutional interleaving, every f bits output, the input and output switches corresponding to the convolutional interleaving are located on the 0th delay line, and K×b is divisible by f. It should be ensured that the start position of each frame (W+P bits) corresponds to the start position of the input and output switches of the convolutional deinterleaving unit, typically at the topmost positions. More specifically, every output of the convolutional interleaving unit and the convolutional deinterleaving unit... Each bit has its input / output switch position at the top, ensuring that the convolutional deinterleaver is synchronized during frame synchronization.

[0011] In some possible implementations, r × d × c = K × b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and convolutional deinterleaver can output [a value] per c polling iterations. With 1 bit, its input and output switch positions are at the starting position of the switch, so that the convolution deinterleaver can be synchronized during frame synchronization.

[0012] In some possible implementations, the rate of the first data stream is 850 Gbps. , where a is an integer greater than or equal to 1, and G represents M represents .

[0013] In some possible implementations, N=128, K=120, .

[0014] In some possible implementations, W=48, P=13056, a=728, b=102, and baud rate=113.75Gbaud;

[0015] Alternatively, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud;

[0016] Alternatively, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud;

[0017] Alternatively, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud;

[0018] Alternatively, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud;

[0019] Alternatively, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud;

[0020] Alternatively, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud;

[0021] Alternatively, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud;

[0022] Alternatively, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud;

[0023] Alternatively, W=128, P=34816, a=728, b=272, baud rate=113.75Gbaud;

[0024] Alternatively, W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0025] In some possible implementations, N=170, K=160, .

[0026] In some possible implementations, W=48, P=23120, a=724, b=136, and baud rate=113.125Gbaud;

[0027] Alternatively, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud;

[0028] Alternatively, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud;

[0029] Alternatively, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud;

[0030] Alternatively, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud;

[0031] Alternatively, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud;

[0032] Alternatively, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud;

[0033] Alternatively, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud;

[0034] Alternatively, W=170, P=49130, a=725, b=289, baud rate=113.2813Gbaud;

[0035] Alternatively, W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0036] In some possible implementations, N=144, K=136. .

[0037] In some possible implementations, W=48, P=5760, a=726, b=40, and baud rate=113.4375Gbaud;

[0038] Alternatively, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud;

[0039] Alternatively, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud;

[0040] Alternatively, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud;

[0041] Alternatively, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud;

[0042] Alternatively, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud;

[0043] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0044] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud;

[0045] Alternatively, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud;

[0046] Alternatively, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud;

[0047] Alternatively, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud;

[0048] Alternatively, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud;

[0049] Alternatively, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud;

[0050] Alternatively, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud;

[0051] Alternatively, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud;

[0052] Alternatively, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud;

[0053] Alternatively, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud;

[0054] Alternatively, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud;

[0055] Alternatively, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud;

[0056] Alternatively, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud;

[0057] Alternatively, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud;

[0058] Alternatively, W=144, P=51840, a=723, b=360, baud rate=112.8125Gbaud;

[0059] Alternatively, W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0060] In some possible implementations, W=56, P=5040, a=728, b=35, and baud rate=113.75Gbaud;

[0061] Alternatively, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud;

[0062] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0063] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0064] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0065] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0066] In some possible implementations, .

[0067] In some possible implementations, the alignment identifier includes at least one frame synchronization sequence of length 48 bits.

[0068] In some possible implementations, the 48 bits of the frame synchronization sequence are consecutive in the alignment identifier.

[0069] In some possible implementations, the 48 bits of the frame synchronization sequence may take values ​​of 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0070] In some possible implementations, the frame synchronization sequence includes two frame synchronization sub-sequences, each with a bit length of 24 bits, and the two frame synchronization sub-sequences are spaced 8 bits apart in the alignment identifier.

[0071] In some possible implementations, the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other frame synchronization subsequence include 0x65, 0xB5, and 0xD9.

[0072] In some possible implementations, the alignment identifier includes padding bits and / or a status field.

[0073] In some possible implementations, W is divisible by N.

[0074] In some possible implementations, each second data stream undergoes at least one of the following operations before being encoded by the second FEC: identifier locking, channel skew correction, and channel reordering. And / or, each second data stream undergoes at least one of the following operations after being encoded by the second FEC: channel interleaving and scrambling.

[0075] In some possible implementations, performing first data processing on multiple first data streams to obtain m second data streams includes: performing second FEC coding on each group of 8 first data streams to obtain 8 coded data streams in each group; and performing channel interleaving on each group of 8 coded data streams to obtain 1 second data stream, thus obtaining m second data streams.

[0076] In some possible implementations, N=128, K=120, channel interleaving of each group of 8 coded data streams to obtain a second data stream includes: obtaining one 128-bit inner codeword from each of the coded data streams in each group of 8 coded data streams to obtain a total of 8 inner codewords. Polling then extracts 2 bits from each of the 8 inner codewords to obtain 1024 consecutive bits in the second data stream.

[0077] In some possible implementations, each second data stream undergoes a cyclic shift before being encoded by the second FEC.

[0078] In some possible implementations, performing first data processing on multiple first data streams includes: processing 8 The m first data streams are convolutionally interleaved. The resulting 8... The m data streams are cyclically shifted. The 8 data streams after the cyclic shift are then processed. Each of the m first data streams is then subjected to second FEC encoding.

[0079] In some possible implementations, performing first data processing on multiple first data streams includes: processing 2 The m first data streams are convolutionally interleaved. Each convolutionally interleaved first data stream is then distributed into four distributed first data streams, resulting in a total of 8... The first data stream after m distributions. For the 8 distributed data streams... The m data streams are cyclically shifted. The 8 data streams after the cyclic shift are then processed. Each of the m first data streams is then subjected to second FEC encoding.

[0080] In some possible implementations, the first data processing of multiple first data streams includes: performing convolutional interleaving on each of the m first data streams. Each of the convolutionally interleaved first data streams is then distributed to obtain 8 distributed first data streams, resulting in a total of 8... The first data stream after m distributions. For the 8 distributed data streams... The m data streams are cyclically shifted. The 8 data streams after the cyclic shift are then processed. Each of the m first data streams is then subjected to second FEC encoding.

[0081] In some possible implementations, to achieve lower latency, lower complexity, and lower power consumption, the cyclic shift operation and / or channel interleaving operation may be skipped. Specifically, processing multiple first data streams to obtain m second data streams includes: firstly, distributing each of the m first data streams to obtain 8 distributed first data streams, resulting in a total of 8... The first data stream after distribution of m data points. Then, for the 8 distributed data points... Each of the m first data streams is encoded using the second FEC encoding to obtain 8. m encoded data streams. Furthermore, for 8... In m encoded data streams, every 8 encoded data streams are merged into one second data stream, resulting in a total of m second data streams. It should be understood that merging the 8 encoded data streams into codewords is equivalent to performing one-way Hamming codeword interleaving on the 8 encoded data streams.

[0082] In some possible implementations, the alignment identifier includes at least one target codeword, which comprises N bits.

[0083] In some possible implementations, the target codeword is obtained by encoding K bits of alignment identifier information using a second FEC. It should be understood that the target codeword can also be called the inner codeword, and selecting one or more inner codewords as the specific pattern of the alignment identifier is beneficial for the receiver to achieve low-complexity frame synchronization and codeword synchronization.

[0084] In some possible implementations, the alignment identifier is obtained by interleaving multiple target codewords. For example, each alignment identifier is obtained by interleaving 8 target codewords through 8-way codeword interleaving; this codeword interleaving can also be referred to as channel interleaving. It should be understood that the alignment identifier obtained by interleaving multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment identifier is obtained by combining multiple target codewords; for example, each alignment identifier is obtained by combining 8 target codewords; this codeword combining can also be referred to as 1-way codeword interleaving.

[0085] Secondly, embodiments of this application provide a data processing method applied at a receiving end, comprising the following steps: First, the received Y modulated symbol streams are subjected to fourth data processing to obtain m fourth data streams. Each fourth data stream is demodulated; the Y modulated symbol streams are obtained by third data processing of m third data streams, each modulated symbol stream is modulated; the m third data streams are obtained by second data processing of m second data streams respectively; and the m second data streams are obtained by first data processing of multiple first data streams encoded with first FEC. Y is an integer greater than or equal to 1, and m is an integer greater than 1. Each second data stream is encoded with second FEC, and each codeword after second FEC encoding includes N bits, N = K + S, where K represents the number of information bits, S represents the number of parity bits, and K and S are integers greater than or equal to 1. Each third data stream includes at least one bit sequence, each bit sequence including P + W bits, where P bits in each bit sequence come from the second data streams, and W bits in each bit sequence are added alignment markers. P = N × b, where b is an integer greater than or equal to 1, and the baud rate of each modulation symbol stream is an integer multiple of the reference clock frequency. Furthermore, each fourth data stream is frame-synchronized according to the alignment flag in each fourth data stream.

[0086] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0087] In some possible implementations, each second data stream undergoes convolutional interleaving before being encoded by the second FEC. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their numbers. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r... The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0088] In some possible implementations, after convolutional interleaving, every f bits output, the input and output switches corresponding to the convolutional interleaving are located on the 0th delay line, and K×b is divisible by f. It should be ensured that the start position of each frame (W+P bits) corresponds to the start position of the input and output switches of the convolutional deinterleaving unit, typically at the topmost positions. More specifically, every output of the convolutional interleaving unit and the convolutional deinterleaving unit... Each bit has its input / output switch position at the top, ensuring that the convolutional deinterleaver is synchronized during frame synchronization.

[0089] In some possible implementations, r × d × c = K × b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and convolutional deinterleaver can output [a value] per c polling iterations. With 1 bit, its input and output switch positions are at the starting position of the switch, so that the convolution deinterleaver can be synchronized during frame synchronization.

[0090] In some possible implementations, the rate of the first data stream is 850 Gbps. , where a is an integer greater than or equal to 1, and G represents M represents .

[0091] In some possible implementations, N=128, K=120, .

[0092] In some possible implementations, W=48, P=13056, a=728, b=102, and baud rate=113.75Gbaud;

[0093] Alternatively, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud;

[0094] Alternatively, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud;

[0095] Alternatively, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud;

[0096] Alternatively, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud;

[0097] Alternatively, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud;

[0098] Alternatively, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud;

[0099] Alternatively, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud;

[0100] Alternatively, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud;

[0101] Alternatively, W=128, P=34816, a=728, b=272, baud rate=113.75Gbaud;

[0102] Alternatively, W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0103] In some possible implementations, N=170, K=160, .

[0104] In some possible implementations, W=48, P=23120, a=724, b=136, and baud rate=113.125Gbaud;

[0105] Alternatively, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud;

[0106] Alternatively, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud;

[0107] Alternatively, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud;

[0108] Alternatively, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud;

[0109] Alternatively, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud;

[0110] Alternatively, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud;

[0111] Alternatively, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud;

[0112] Alternatively, W=170, P=49130, a=725, b=289, baud rate=113.2813Gbaud;

[0113] Alternatively, W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0114] In some possible implementations, N=144, K=136. .

[0115] In some possible implementations, W=48, P=5760, a=726, b=40, and baud rate=113.4375Gbaud;

[0116] Alternatively, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud;

[0117] Alternatively, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud;

[0118] Alternatively, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud;

[0119] Alternatively, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud;

[0120] Alternatively, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud;

[0121] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0122] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud;

[0123] Alternatively, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud;

[0124] Alternatively, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud;

[0125] Alternatively, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud;

[0126] Alternatively, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud;

[0127] Alternatively, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud;

[0128] Alternatively, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud;

[0129] Alternatively, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud;

[0130] Alternatively, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud;

[0131] Alternatively, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud;

[0132] Alternatively, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud;

[0133] Alternatively, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud;

[0134] Alternatively, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud;

[0135] Alternatively, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud;

[0136] Alternatively, W=144, P=51840, a=723, b=360, baud rate=112.8125Gbaud;

[0137] Alternatively, W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0138] In some possible implementations, W=56, P=5040, a=728, b=35, and baud rate=113.75Gbaud;

[0139] Alternatively, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud;

[0140] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0141] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0142] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0143] In some possible implementations, the alignment identifier includes padding bits and / or a status field.

[0144] In some possible implementations, W is divisible by N.

[0145] In some possible implementations, the alignment identifier includes at least one target codeword, which comprises N bits.

[0146] In some possible implementations, the target codeword is obtained by encoding K bits of alignment identifier information using a second FEC. It should be understood that the target codeword can also be called the inner codeword, and selecting one or more inner codewords as the specific pattern of the alignment identifier is beneficial for the receiver to achieve low-complexity frame synchronization and codeword synchronization.

[0147] In some possible implementations, the alignment identifier is obtained by interleaving multiple target codewords. For example, each alignment identifier is obtained by interleaving 8 target codewords through 8-way codeword interleaving; this codeword interleaving can also be referred to as channel interleaving. It should be understood that the alignment identifier obtained by interleaving multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment identifier is obtained by combining multiple target codewords; for example, each alignment identifier is obtained by combining 8 target codewords; this codeword combining can also be referred to as 1-way codeword interleaving.

[0148] Thirdly, embodiments of this application provide a data processing apparatus applied at a transmitting end. The data processing apparatus includes a first data processing unit, a second data processing unit, and a third data processing unit. The first data processing unit is configured to: perform first data processing on multiple first data streams encoded with first forward error correction (FEC) to obtain m second data streams, where m is an integer greater than 1. Each second data stream undergoes second FEC encoding, and each codeword after second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, S represents the number of parity bits, and K and S are integers greater than or equal to 1. The second data processing unit is configured to: perform second data processing on the m second data streams respectively to obtain m third data streams. Each third data stream includes at least one bit sequence, each bit sequence including P + W bits, where P bits in each bit sequence come from the second data streams, and W bits in each bit sequence are added alignment identifiers, where P = N × b, and b is an integer greater than or equal to 1. The third data processing unit is used to: perform third data processing on m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1, each modulated symbol stream is modulated, and the baud rate value of each modulated symbol stream is an integer multiple of the reference clock frequency value.

[0149] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0150] In some possible implementations, each second data stream undergoes convolutional interleaving before being encoded by the second FEC. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their numbers. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r... The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0151] In some possible implementations, after convolutional interleaving, every f bits output, the input and output switches corresponding to the convolutional interleaving are located on the 0th delay line, and K×b is divisible by f. It should be ensured that the start position of each frame (W+P bits) corresponds to the start position of the input and output switches of the convolutional deinterleaving unit, typically at the topmost positions. More specifically, every output of the convolutional interleaving unit and the convolutional deinterleaving unit... Each bit has its input / output switch position at the top, ensuring that the convolutional deinterleaver is synchronized during frame synchronization.

[0152] In some possible implementations, r × d × c = K × b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and convolutional deinterleaver can output [a value] per c polling iterations. With 1 bit, its input and output switch positions are at the starting position of the switch, so that the convolution deinterleaver can be synchronized during frame synchronization.

[0153] In some possible implementations, the rate of the first data stream is 850 Gbps. , where a is an integer greater than or equal to 1, and G represents M represents .

[0154] In some possible implementations, N=128, K=120, .

[0155] In some possible implementations, W=48, P=13056, a=728, b=102, and baud rate=113.75Gbaud;

[0156] Alternatively, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud;

[0157] Alternatively, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud;

[0158] Alternatively, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud;

[0159] Alternatively, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud;

[0160] Alternatively, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud;

[0161] Alternatively, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud;

[0162] Alternatively, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud;

[0163] Alternatively, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud;

[0164] Alternatively, W=128, P=34816, a=728, b=272, baud rate=113.75Gbaud;

[0165] Alternatively, W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0166] In some possible implementations, N=170, K=160, .

[0167] In some possible implementations, W=48, P=23120, a=724, b=136, and baud rate=113.125Gbaud;

[0168] Alternatively, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud;

[0169] Alternatively, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud;

[0170] Alternatively, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud;

[0171] Alternatively, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud;

[0172] Alternatively, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud;

[0173] Alternatively, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud;

[0174] Alternatively, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud;

[0175] Alternatively, W=170, P=49130, a=725, b=289, baud rate=113.2813Gbaud;

[0176] Alternatively, W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0177] In some possible implementations, N=144, K=136. .

[0178] In some possible implementations, W=48, P=5760, a=726, b=40, and baud rate=113.4375Gbaud;

[0179] Alternatively, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud;

[0180] Alternatively, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud;

[0181] Alternatively, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud;

[0182] Alternatively, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud;

[0183] Alternatively, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud;

[0184] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0185] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud;

[0186] Alternatively, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud;

[0187] Alternatively, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud;

[0188] Alternatively, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud;

[0189] Alternatively, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud;

[0190] Alternatively, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud;

[0191] Alternatively, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud;

[0192] Alternatively, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud;

[0193] Alternatively, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud;

[0194] Alternatively, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud;

[0195] Alternatively, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud;

[0196] Alternatively, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud;

[0197] Alternatively, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud;

[0198] Alternatively, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud;

[0199] Alternatively, W=144, P=51840, a=723, b=360, baud rate=112.8125Gbaud;

[0200] Alternatively, W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0201] In some possible implementations, W=56, P=5040, a=728, b=35, and baud rate=113.75Gbaud;

[0202] Alternatively, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud;

[0203] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0204] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0205] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0206] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0207] In some possible implementations, .

[0208] In some possible implementations, the alignment identifier includes at least one frame synchronization sequence of length 48 bits.

[0209] In some possible implementations, the 48 bits of the frame synchronization sequence are consecutive in the alignment identifier.

[0210] In some possible implementations, the 48 bits of the frame synchronization sequence may take values ​​of 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0211] In some possible implementations, the frame synchronization sequence includes two frame synchronization sub-sequences, each with a bit length of 24 bits, and the two frame synchronization sub-sequences are spaced 8 bits apart in the alignment identifier.

[0212] In some possible implementations, the 24-bit values ​​of one of the two frame synchronization subsequences include 0x9A, 0x4A, and 0x26, and the 24-bit values ​​of the other frame synchronization subsequence include 0x65, 0xB5, and 0xD9.

[0213] In some possible implementations, the alignment identifier includes padding bits and / or a status field.

[0214] In some possible implementations, W is divisible by N. In some possible implementations, each second data stream undergoes at least one of the following operations before being encoded by the second FEC: identifier locking, channel skew correction, and channel reordering. And / or, each second data stream undergoes at least one of the following operations after being encoded by the second FEC: channel interleaving and scrambling.

[0215] In some possible implementations, the first data processing unit is specifically used to: perform second FEC coding on each group of 8 first data streams in multiple first data streams to obtain 8 coded data streams in each group; and perform channel interleaving on each group of 8 coded data streams to obtain 1 second data stream, so as to obtain m second data streams.

[0216] In some possible implementations, N=128, K=120, and the first data processing unit is specifically used to: obtain one 128-bit internal codeword from each of the eight coded data streams in each group to obtain a total of eight internal codewords. Then, it polls to obtain two bits from each of the eight internal codewords to obtain 1024 consecutive bits in the second data stream.

[0217] In some possible implementations, each second data stream undergoes a cyclic shift before being encoded by the second FEC.

[0218] In some possible implementations, the first data processing unit is specifically used for: processing 8 The m first data streams are convolutionally interleaved. The resulting 8... The m data streams are cyclically shifted. The 8 data streams after the cyclic shift are then processed. Each of the m first data streams is then subjected to second FEC encoding.

[0219] In some possible implementations, the first data processing unit is specifically used for: processing 2 The m first data streams are convolutionally interleaved. Each convolutionally interleaved first data stream is then distributed into four distributed first data streams, resulting in a total of 8... The first data stream after m distributions. For the 8 distributed data streams... The m data streams are cyclically shifted. The 8 data streams after the cyclic shift are then processed. Each of the m first data streams is then subjected to second FEC encoding.

[0220] In some possible implementations, the first data processing unit is specifically used to: perform convolutional interleaving on m first data streams respectively. Each of the convolutionally interleaved first data streams is then distributed to obtain 8 distributed first data streams, resulting in a total of 8... The first data stream after m distributions. For the 8 distributed data streams... The m data streams are cyclically shifted. The 8 data streams after the cyclic shift are then processed. Each of the m first data streams is then subjected to second FEC encoding.

[0221] In some possible implementations, the first data processing unit is specifically used to: distribute each of the m first data streams to obtain 8 distributed first data streams, so as to obtain a total of 8 The first data stream after m distributions. For the 8 distributed data streams... Each of the m first data streams is encoded using the second FEC encoding to obtain 8. m encoded data streams. For 8 In m encoded data streams, every 8 encoded data streams are merged into one second data stream, resulting in a total of m second data streams. It should be understood that merging the 8 encoded data streams into codewords is equivalent to performing one-way Hamming codeword interleaving on the 8 encoded data streams.

[0222] In some possible implementations, the alignment identifier includes at least one target codeword, which comprises N bits.

[0223] In some possible implementations, the target codeword is obtained by encoding K bits of alignment identifier information using a second FEC. It should be understood that the target codeword can also be called the inner codeword, and selecting one or more inner codewords as the specific pattern of the alignment identifier is beneficial for the receiver to achieve low-complexity frame synchronization and codeword synchronization.

[0224] In some possible implementations, the alignment identifier is obtained by interleaving multiple target codewords. For example, each alignment identifier is obtained by interleaving 8 target codewords through 8-way codeword interleaving; this codeword interleaving can also be referred to as channel interleaving. It should be understood that the alignment identifier obtained by interleaving multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment identifier is obtained by combining multiple target codewords; for example, each alignment identifier is obtained by combining 8 target codewords; this codeword combining can also be referred to as 1-way codeword interleaving.

[0225] Fourthly, embodiments of this application provide a data processing apparatus applied at a receiving end. The data processing apparatus includes a data processing unit and a synchronization unit. The data processing unit is used to perform fourth data processing on Y received modulated symbol streams to obtain m fourth data streams. Each fourth data stream is demodulated. The Y modulated symbol streams are obtained by third data processing on m third data streams. Each modulated symbol stream is modulated. The m third data streams are obtained by second data processing on m second data streams respectively. The m second data streams are obtained by first data processing on multiple first data streams encoded with first forward error correction (FEC). Y is an integer greater than or equal to 1, and m is an integer greater than 1. Each second data stream undergoes second FEC encoding. Each codeword after second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, S represents the number of parity bits, and K and S are integers greater than or equal to 1. Each third data stream includes at least one bit sequence, each bit sequence consisting of P+W bits. P bits in each bit sequence come from the second data stream, and W bits in each bit sequence are added alignment identifiers. P = N × b, where b is an integer greater than or equal to 1. The baud rate of each modulation symbol stream is an integer multiple of the reference clock frequency. The synchronization unit is used to perform frame synchronization of each fourth data stream based on the alignment identifiers in each fourth data stream.

[0226] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0227] In some possible implementations, each second data stream undergoes convolutional interleaving before being encoded by the second FEC. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line has a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their numbers. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r... The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0228] In some possible implementations, after convolutional interleaving, every f bits output, the input and output switches corresponding to the convolutional interleaving are located on the 0th delay line, and K×b is divisible by f. It should be ensured that the start position of each frame (W+P bits) corresponds to the start position of the input and output switches of the convolutional deinterleaving unit, typically at the topmost positions. More specifically, every output of the convolutional interleaving unit and the convolutional deinterleaving unit... Each bit has its input / output switch position at the top, ensuring that the convolutional deinterleaver is synchronized during frame synchronization.

[0229] In some possible implementations, r × d × c = K × b, where c is an integer greater than or equal to 1. That is, the convolutional interleaver and convolutional deinterleaver can output [a value] per c polling iterations. With 1 bit, its input and output switch positions are at the starting position of the switch, so that the convolution deinterleaver can be synchronized during frame synchronization.

[0230] In some possible implementations, the rate of the first data stream is 850 Gbps. , where a is an integer greater than or equal to 1, and G represents M represents .

[0231] In some possible implementations, N=128, K=120, .

[0232] In some possible implementations, W=48, P=13056, a=728, b=102, and baud rate=113.75Gbaud;

[0233] Alternatively, W=48, P=52224, a=726, b=408, baud rate=113.4375Gbaud;

[0234] Alternatively, W=56, P=15232, a=728, b=119, baud rate=113.75Gbaud;

[0235] Alternatively, W=56, P=60928, a=726, b=476, baud rate=113.4375Gbaud;

[0236] Alternatively, W=64, P=13056, a=728, b=102, baud rate=113.75Gbaud;

[0237] Alternatively, W=64, P=69632, a=726, b=544, baud rate=113.4375Gbaud;

[0238] Alternatively, W=120, P=32640, a=728, b=255, baud rate=113.75Gbaud;

[0239] Alternatively, W=120, P=52224, a=727, b=408, baud rate=113.5938Gbaud;

[0240] Alternatively, W=120, P=130560, a=726, b=1020, baud rate=113.4375Gbaud;

[0241] Alternatively, W=128, P=34816, a=728, b=272, baud rate=113.75Gbaud;

[0242] Alternatively, W=128, P=139264, a=726, b=1088, baud rate=113.4375Gbaud.

[0243] In some possible implementations, N=170, K=160, .

[0244] In some possible implementations, W=48, P=23120, a=724, b=136, and baud rate=113.125Gbaud;

[0245] Alternatively, W=48, P=69360, a=723, b=408, baud rate=112.9688Gbaud;

[0246] Alternatively, W=56, P=11560, a=726, b=68, baud rate=113.4375Gbaud;

[0247] Alternatively, W=56, P=80920, a=723, b=476, baud rate=112.9688Gbaud;

[0248] Alternatively, W=64, P=92480, a=723, b=544, baud rate=112.9688Gbaud;

[0249] Alternatively, W=120, P=34680, a=725, b=204, baud rate=113.2813Gbaud;

[0250] Alternatively, W=120, P=57800, a=724, b=340, baud rate=113.125Gbaud;

[0251] Alternatively, W=120, P=173400, a=723, b=1020, baud rate=112.9688Gbaud;

[0252] Alternatively, W=170, P=49130, a=725, b=289, baud rate=113.2813Gbaud;

[0253] Alternatively, W=170, P=245650, a=723, b=1445, baud rate=112.9688Gbaud.

[0254] In some possible implementations, N=144, K=136. .

[0255] In some possible implementations, W=48, P=5760, a=726, b=40, and baud rate=113.4375Gbaud;

[0256] Alternatively, W=48, P=8640, a=724, b=60, baud rate=113.125Gbaud;

[0257] Alternatively, W=48, P=11520, a=723, b=80, baud rate=112.9688Gbaud;

[0258] Alternatively, W=48, P=17280, a=722, b=120, baud rate=112.8125Gbaud;

[0259] Alternatively, W=48, P=34560, a=721, b=240, baud rate=112.6563Gbaud;

[0260] Alternatively, W=56, P=5760, a=727, b=40, baud rate=113.5938Gbaud;

[0261] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0262] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud;

[0263] Alternatively, W=64, P=5760, a=728, b=40, baud rate=113.75Gbaud;

[0264] Alternatively, W=64, P=11520, a=724, b=80, baud rate=113.125Gbaud;

[0265] Alternatively, W=64, P=23040, a=722, b=160, baud rate=112.8125Gbaud;

[0266] Alternatively, W=64, P=46080, a=721, b=320, baud rate=112.6563Gbaud;

[0267] Alternatively, W=120, P=14400, a=726, b=100, baud rate=113.4375Gbaud;

[0268] Alternatively, W=120, P=17280, a=725, b=120, baud rate=113.2813Gbaud;

[0269] Alternatively, W=120, P=28800, a=723, b=200, baud rate=112.9688Gbaud;

[0270] Alternatively, W=120, P=43200, a=722, b=300, baud rate=112.8125Gbaud;

[0271] Alternatively, W=120, P=86400, a=721, b=600, baud rate=112.6563Gbaud;

[0272] Alternatively, W=144, P=11520, a=729, b=80, baud rate=113.9063Gbaud;

[0273] Alternatively, W=144, P=17280, a=726, b=120, baud rate=113.4375Gbaud;

[0274] Alternatively, W=144, P=25920, a=724, b=180, baud rate=113.125Gbaud;

[0275] Alternatively, W=144, P=34560, a=723, b=240, baud rate=112.9688Gbaud;

[0276] Alternatively, W=144, P=51840, a=723, b=360, baud rate=112.8125Gbaud;

[0277] Alternatively, W=144, P=103680, a=721, b=720, baud rate=112.6563Gbaud.

[0278] In some possible implementations, W=56, P=5040, a=728, b=35, and baud rate=113.75Gbaud;

[0279] Alternatively, W=56, P=10080, a=724, b=70, baud rate=113.125Gbaud;

[0280] Alternatively, W=56, P=20160, a=722, b=140, baud rate=112.8125Gbaud;

[0281] Alternatively, W=56, P=40320, a=721, b=280, baud rate=112.6563Gbaud.

[0282] In some possible implementations, N=148, K=140, W is a multiple of 4, and b is a multiple of 17.

[0283] In some possible implementations, the alignment identifier includes padding bits and / or a status field.

[0284] In some possible implementations, W is divisible by N.

[0285] In some possible implementations, the alignment identifier includes at least one target codeword, which comprises N bits.

[0286] In some possible implementations, the target codeword is obtained by encoding K bits of alignment identifier information using a second FEC. It should be understood that the target codeword can also be called the inner codeword, and selecting one or more inner codewords as the specific pattern of the alignment identifier is beneficial for the receiver to achieve low-complexity frame synchronization and codeword synchronization.

[0287] In some possible implementations, the alignment identifier is obtained by interleaving multiple target codewords. For example, each alignment identifier is obtained by interleaving 8 target codewords through 8-way codeword interleaving; this codeword interleaving can also be referred to as channel interleaving. It should be understood that the alignment identifier obtained by interleaving multiple target codewords should also be considered to include multiple target codewords. Alternatively, each alignment identifier is obtained by combining multiple target codewords; for example, each alignment identifier is obtained by combining 8 target codewords; this codeword combining can also be referred to as 1-way codeword interleaving.

[0288] Fifthly, embodiments of this application provide a data processing method applied at a sending end. The method includes the following steps: First, m first data streams encoded with first forward error correction (FEC) are subjected to first data processing to obtain m second data streams. Wherein, m is an integer greater than 1, and each second data stream includes at least one first bit sequence, each first bit sequence including... Each of the first bit sequences contains bits, and each bit sequence contains bits. Each bit comes from the first data stream, and each first bit sequence contains... Each bit is the first identifier to be added. Next, the m second data streams undergo second data processing to obtain m third data streams. The second data processing includes second FEC encoding. Each codeword after second FEC encoding consists of N bits, where N = K + S, K represents the number of information bits, and S represents the number of check bits. K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. =K×b, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. Then, the m third data streams are processed to obtain Y modulated symbol streams. Here, Y is an integer greater than or equal to 1, each modulated symbol stream is modulated, and the baud rate of each modulated symbol stream is an integer multiple of the reference clock frequency.

[0289] In this embodiment, the data stream encoded with the external code is periodically inserted with the first identifier before internal code encoding. Specifically, the data stream encoded with the external code is periodically obtained... 1 bit, and insert 1 bit A first identifier of length 1 bit makes each bit in the data stream... There are bits in The first identifier is of length 1 bit. This application selects a positive integer. and This allows the baud rate of the modulated symbol data stream to be an integer multiple of the reference clock frequency, simplifying clock extraction and synchronization at the receiver, enabling fast phase locking, and resulting in low PLL complexity and minimal jitter. Furthermore, selecting a positive integer... All values ​​are divisible by the length K of the internal code information, resulting in low hardware complexity for the receiving end processing module's frame synchronization and codeword synchronization operations. Furthermore, selecting positive integers... This allows the synchronization of internal codewords to guarantee the synchronization of concatenated deinterleaving. In other words, the data processing method provided in this application reduces the complexity of frame synchronization, internal codeword synchronization, and concatenated deinterleaving synchronization in the receiving end processing module.

[0290] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence comprising P+W bits, wherein the P bits in each second bit sequence are composed of... The first bit is obtained by encoding the first bit using the second FEC. The W bits in each second bit sequence are the second identifier, which is obtained by encoding the first identifier using the second FEC. P = N × b, W = N × e.

[0291] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0292] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0293] In some possible implementations, each first data stream is further subjected to convolutional interleaving. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their indices. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r bits. The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0294] In some possible implementations, after convolutional interleaving, every f bits are output, and the input / output switch corresponding to the convolutional interleaving is located on the 0th delay line, and K×b is divisible by f.

[0295] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0296] In some possible implementations, .

[0297] In some possible implementations, N=148, K=140, It is divisible by b, and It is divisible by 7.

[0298] In some possible implementations, .

[0299] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(148,140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=140 information bits to obtain 70 bits, and then performs Hamming(78,70) encoding on these 70 bits to obtain S=8 parity bits. The resulting 148-bit codeword after the second FEC encoding contains K=140 information bits and S=8 parity bits.

[0300] In some possible implementations, N=127, K=120, It is divisible by b, and It is divisible by 3.

[0301] In some possible implementations, .

[0302] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(127,120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=120 information bits to obtain 60 bits, and then performs Hamming(67,60) encoding on these 60 bits to obtain S=7 parity bits. The resulting 127-bit codeword after the second FEC encoding contains K=120 information bits and S=7 parity bits.

[0303] In some possible implementations, the first data processing also includes scrambling.

[0304] In some possible implementations, the third data processing further includes codeword interleaving, where t codewords are interleaved to obtain a result including... A sequence of interleaved bits, where the i-th codeword is one of the t codewords. A sequence of K bits of information and a check sequence of S bits , The interleaved sequence contains continuous The first subsequence of bits and consecutive bits The second subsequence of bits, the first subsequence contains … There are a total of t information sequences, and the second subsequence contains … There are a total of t verification sequences.

[0305] In some possible implementations, the baud rate of the modulated symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, and G represents... M represents .

[0306] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0307] In some possible implementations, .

[0308] In some possible implementations, processing m third data streams to obtain Y modulated symbol streams includes: channel interleaving each group of eight third data streams from the m third data streams to obtain one fourth data stream, resulting in a total of Y fourth data streams. Modulating each of the Y fourth data streams yields Y modulated symbol streams.

[0309] In some possible implementations, the first identifier in each second data stream includes a length of A synchronization subsequence of bits, wherein the synchronization subsequence is located in a continuous sequence starting from the start position in the first identifier. 1 bit.

[0310] In some possible implementations, A set of 8 third data streams from m third data streams is obtained by second FEC coding of a set of 8 second data streams from m second data streams. A fourth data stream obtained by channel interleaving of a set of 8 third data streams includes a synchronization sequence of 48 bits in length. The 48-bit synchronization sequence is continuous in the fourth data stream. The 48-bit synchronization sequence includes a synchronization subsequence from each of the 8 second data streams, for a total of 8 synchronization subsequences.

[0311] In some possible implementations, the 48 bits of the synchronization sequence may take values ​​of 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0312] In some possible implementations, the synchronization subsequence 0 of the 0th second data stream in a set of 8 second data streams is 010110;

[0313] The synchronization subsequence 1 of the first of a set of 8 second data streams is 011010;

[0314] The second second data stream in a set of eight second data streams includes a synchronization subsequence 2 of 100111;

[0315] The synchronization subsequence 3 of the third second data stream in a set of eight second data streams is 010001;

[0316] The synchronization subsequence 4 of the 4th second data stream in a set of 8 second data streams is 011010;

[0317] The synchronization subsequence 5 of the 5th second data stream in a set of 8 second data streams is 011001;

[0318] The synchronization subsequence 6 in the 6th second data stream of a set of 8 second data streams is 000110;

[0319] The synchronization subsequence 7 of the 7th second data stream in a set of 8 second data streams is 101011.

[0320] In some possible implementations, a set of 8 third data streams from the m third data streams is obtained by second FEC encoding of a set of 8 second data streams from the m second data streams. The 0th, 1st, 2nd, and 3rd second data streams in the set of 8 each include a synchronization subsequence of length 8 bits. The 4th, 5th, 6th, and 7th second data streams in the set of 8 each include a synchronization subsequence of length 4 bits, wherein the first two bits of the 4-bit synchronization subsequence are spaced 2 bits apart from the last two bits.

[0321] In some possible implementations, a fourth data stream obtained by channel interleaving of a set of eight third data streams includes a synchronization sequence of 48 bits in length. The synchronization sequence of 48 bits in length includes a synchronization subsequence of each of the eight second data streams, for a total of eight synchronization subsequences. The first 24 bits and the last 24 bits of the synchronization sequence of 48 bits in length are spaced 8 bits apart.

[0322] In some possible implementations, the first 24 bits of a 48-bit synchronization sequence may have values ​​of 0x9A, 0x4A, and 0x26, and the last 24 bits may have values ​​of 0x65, 0xB5, and 0xD9.

[0323] In some possible implementations, the synchronization subsequence 0 of the 0th second data stream in a set of 8 second data streams is 01011010;

[0324] The synchronization subsequence 1 of the first of a set of 8 second data streams is 01101001;

[0325] The second second data stream in a set of eight second data streams includes a synchronization subsequence 2 of 10010110;

[0326] The synchronization subsequence 3 of the third second data stream in a set of eight second data streams is 01001011;

[0327] The synchronization subsequence 4 of the 8 second data streams is 0110;

[0328] The synchronization subsequence 5 of the 5th second data stream in a set of 8 second data streams is 0110;

[0329] The synchronization subsequence 6 in the 6th second data stream of a set of 8 second data streams is 0011;

[0330] The synchronization subsequence 7 of the 7th second data stream in a set of 8 second data streams is 1001.

[0331] In some possible implementations, the first identifier in each second data stream includes a synchronization subsequence of 48 bits, wherein the first 24 bits of the synchronization subsequence are spaced 8 bits apart from the last 24 bits.

[0332] In some possible implementations, the first 24 bits of the 48-bit synchronization subsequence may have values ​​of 0x9A, 0x4A, and 0x26, and the last 24 bits may have values ​​of 0x65, 0xB5, and 0xD9.

[0333] In some possible implementations, N=128, K=120, channel interleaving of each group of 8 third data streams to obtain one fourth data stream includes: obtaining one 128-bit internal codeword from each of the 8 third data streams to obtain a total of 8 internal codewords. Polling then extracts 2 bits from each of the 8 internal codewords to obtain 1024 consecutive bits in the fourth data stream.

[0334] In some possible implementations, performing first data processing on m first data streams includes: cyclically shifting each of the m first data streams.

[0335] In some possible implementations, the first data processing of the m first data streams before performing cyclic shifts on the m first data streams includes performing convolutional interleaving on the m first data streams respectively.

[0336] In some possible implementations, before cyclically shifting the m first data streams, the method further includes: performing convolutional interleaving on the m / 4 input data streams respectively. Each of the convolutionally interleaved input data streams is then distributed to obtain 4 first data streams, resulting in a total of m first data streams.

[0337] In some possible implementations, before cyclically shifting the m first data streams, the method further includes: performing convolutional interleaving on the m / 8 input data streams respectively. Each of the convolutionally interleaved input data streams is then distributed to obtain 8 first data streams, resulting in a total of m first data streams.

[0338] Sixthly, embodiments of this application provide a data processing method applied at a receiving end, comprising the following steps: First, the received Y modulated symbol streams are subjected to fourth data processing to obtain m fourth data streams. Wherein, Y is an integer greater than or equal to 1, each fourth data stream is demodulated, and the baud rate value of each modulated symbol stream is an integer multiple of the reference clock frequency value. The Y modulated symbol streams are obtained by third data processing of m third data streams, each modulated symbol stream being modulated. The m third data streams are obtained by second data processing of m second data streams, and the m second data streams are obtained by first data processing of m first data streams encoded with first forward error correction (FEC). m is an integer greater than 1, each second data stream includes at least one first bit sequence, and each first bit sequence includes... Each of the first bit sequences contains bits, and each bit sequence contains bits. Each bit comes from the first data stream, and each first bit sequence contains... The first identifier is added using 1 bit. The second data processing includes the second FEC encoding. Each codeword after the second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, and S represents the number of parity bits. K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. =K×b, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. Furthermore, codeword synchronization and / or frame synchronization are performed on each fourth data stream.

[0339] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence comprising P+W bits, wherein the P bits in each second bit sequence are composed of... The first bit is obtained by encoding the first bit using the second FEC. The W bits in each second bit sequence are the second identifier, which is obtained by encoding the first identifier using the second FEC. P = N × b, W = N × e.

[0340] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0341] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0342] In some possible implementations, each first data stream is further subjected to convolutional interleaving. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their indices. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r bits. The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0343] In some possible implementations, after convolutional interleaving, every f bits are output, and the input / output switch corresponding to the convolutional interleaving is located on the 0th delay line, and K×b is divisible by f.

[0344] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0345] In some possible implementations, .

[0346] In some possible implementations, N=148, K=140, It is divisible by b, and It is divisible by 7.

[0347] In some possible implementations, .

[0348] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(148,140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=140 information bits to obtain 70 bits, and then performs Hamming(78,70) encoding on these 70 bits to obtain S=8 parity bits. The resulting 148-bit codeword after the second FEC encoding contains K=140 information bits and S=8 parity bits.

[0349] In some possible implementations, N=127, K=120, It is divisible by b, and It is divisible by 3.

[0350] In some possible implementations, .

[0351] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(127,120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=120 information bits to obtain 60 bits, and then performs Hamming(67,60) encoding on these 60 bits to obtain S=7 parity bits. The resulting 127-bit codeword after the second FEC encoding contains K=120 information bits and S=7 parity bits.

[0352] In some possible implementations, the first data processing also includes scrambling.

[0353] In some possible implementations, the third data processing further includes codeword interleaving, where t codewords are interleaved to obtain a result including... A sequence of interleaved bits, where the i-th codeword is one of the t codewords. A sequence of K bits of information and a check sequence of S bits , The interleaved sequence contains continuous The first subsequence of bits and consecutive bits The second subsequence of bits, the first subsequence contains … There are a total of t information sequences, and the second subsequence contains … There are a total of t verification sequences.

[0354] In a seventh aspect, embodiments of this application provide a data processing apparatus. The data processing apparatus includes: a first data processing unit, a second data processing unit, and a third data processing unit. The first data processing unit is configured to: perform first data processing on m first data streams encoded with first forward error correction (FEC) to obtain m second data streams, where m is an integer greater than 1, and each second data stream includes at least one first bit sequence, each first bit sequence including... Each of the first bit sequences contains bits, and each bit sequence contains bits. Each bit comes from the first data stream, and each first bit sequence contains... Each bit is the first identifier to be added. The second data processing unit is used to: perform second data processing on m second data streams to obtain m third data streams. The second data processing includes second FEC encoding. Each codeword after second FEC encoding includes N bits, N=K+S, where K represents the number of information bits, S represents the number of check bits, and K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. =K×b, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. The third data processing unit is used to: perform third data processing on m third data streams to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1. Each modulated symbol stream has been modulated, and the baud rate of each modulated symbol stream is an integer multiple of the reference clock frequency.

[0355] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence comprising P+W bits, wherein the P bits in each second bit sequence are composed of... The first bit is obtained by encoding the first bit using the second FEC. The W bits in each second bit sequence are the second identifier, which is obtained by encoding the first identifier using the second FEC. P = N × b, W = N × e.

[0356] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0357] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0358] In some possible implementations, each first data stream is further subjected to convolutional interleaving. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their indices. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r bits. The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0359] In some possible implementations, after convolutional interleaving, every f bits are output, and the input / output switch corresponding to the convolutional interleaving is located on the 0th delay line, and K×b is divisible by f.

[0360] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0361] In some possible implementations, .

[0362] In some possible implementations, N=148, K=140, It is divisible by b, and It is divisible by 7.

[0363] In some possible implementations, .

[0364] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(148,140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=140 information bits to obtain 70 bits, and then performs Hamming(78,70) encoding on these 70 bits to obtain S=8 parity bits. The resulting 148-bit codeword after the second FEC encoding contains K=140 information bits and S=8 parity bits.

[0365] In some possible implementations, N=127, K=120, It is divisible by b, and It is divisible by 3.

[0366] In some possible implementations, .

[0367] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(127,120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=120 information bits to obtain 60 bits, and then performs Hamming(67,60) encoding on these 60 bits to obtain S=7 parity bits. The resulting 127-bit codeword after the second FEC encoding contains K=120 information bits and S=7 parity bits.

[0368] In some possible implementations, the first data processing also includes scrambling.

[0369] In some possible implementations, the third data processing further includes codeword interleaving, where t codewords are interleaved to obtain a result including... A sequence of interleaved bits, where the i-th codeword is one of the t codewords. A sequence of K bits of information and a check sequence of S bits , The interleaved sequence contains continuous The first subsequence of bits and consecutive bits The second subsequence of bits, the first subsequence contains … There are a total of t information sequences, and the second subsequence contains … There are a total of t verification sequences.

[0370] In some possible implementations, the baud rate of the modulated symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, and G represents... M represents .

[0371] In some possible implementations, N=128, K=120, and the baud rate of the modulated symbol stream is 113.4375 Gbaud.

[0372] In some possible implementations, .

[0373] In some possible implementations, the third data processing unit is specifically used to: perform channel interleaving on each group of 8 third data streams from the m third data streams to obtain 1 fourth data stream, resulting in a total of Y fourth data streams. The Y fourth data streams are then modulated to obtain Y modulated symbol streams.

[0374] In some possible implementations, the first identifier in each second data stream includes a length of A synchronization subsequence of bits, wherein the synchronization subsequence is located in a continuous sequence starting from the start position in the first identifier. 1 bit.

[0375] In some possible implementations, A set of 8 third data streams from m third data streams is obtained by second FEC coding of a set of 8 second data streams from m second data streams. A fourth data stream obtained by channel interleaving of a set of 8 third data streams includes a synchronization sequence of 48 bits in length. The 48-bit synchronization sequence is continuous in the fourth data stream. The 48-bit synchronization sequence includes a synchronization subsequence from each of the 8 second data streams, for a total of 8 synchronization subsequences.

[0376] In some possible implementations, the 48 bits of the synchronization sequence may take values ​​of 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0377] In some possible implementations, the synchronization subsequence 0 of the 0th second data stream in a set of 8 second data streams is 010110;

[0378] The synchronization subsequence 1 of the first of a set of 8 second data streams is 011010;

[0379] The second second data stream in a set of eight second data streams includes a synchronization subsequence 2 of 100111;

[0380] The synchronization subsequence 3 of the third second data stream in a set of eight second data streams is 010001;

[0381] The synchronization subsequence 4 of the 4th second data stream in a set of 8 second data streams is 011010;

[0382] The synchronization subsequence 5 of the 5th second data stream in a set of 8 second data streams is 011001;

[0383] The synchronization subsequence 6 in the 6th second data stream of a set of 8 second data streams is 000110;

[0384] The synchronization subsequence 7 of the 7th second data stream in a set of 8 second data streams is 101011.

[0385] In some possible implementations, a set of 8 third data streams from the m third data streams is obtained by second FEC encoding of a set of 8 second data streams from the m second data streams. The 0th, 1st, 2nd, and 3rd second data streams in the set of 8 each include a synchronization subsequence of length 8 bits. The 4th, 5th, 6th, and 7th second data streams in the set of 8 each include a synchronization subsequence of length 4 bits, wherein the first two bits of the 4-bit synchronization subsequence are spaced 2 bits apart from the last two bits.

[0386] In some possible implementations, a fourth data stream obtained by channel interleaving of a set of eight third data streams includes a synchronization sequence of 48 bits in length. The synchronization sequence of 48 bits in length includes a synchronization subsequence of each of the eight second data streams, for a total of eight synchronization subsequences. The first 24 bits and the last 24 bits of the synchronization sequence of 48 bits in length are spaced 8 bits apart.

[0387] In some possible implementations, the first 24 bits of a 48-bit synchronization sequence may have values ​​of 0x9A, 0x4A, and 0x26, and the last 24 bits may have values ​​of 0x65, 0xB5, and 0xD9.

[0388] In some possible implementations, the synchronization subsequence 0 of the 0th second data stream in a set of 8 second data streams is 01011010;

[0389] The synchronization subsequence 1 of the first of a set of 8 second data streams is 01101001;

[0390] The second second data stream in a set of eight second data streams includes a synchronization subsequence 2 of 10010110;

[0391] The synchronization subsequence 3 of the third second data stream in a set of eight second data streams is 01001011;

[0392] The synchronization subsequence 4 of the 8 second data streams is 0110;

[0393] The synchronization subsequence 5 of the 5th second data stream in a set of 8 second data streams is 0110;

[0394] The synchronization subsequence 6 in the 6th second data stream of a set of 8 second data streams is 0011;

[0395] The synchronization subsequence 7 of the 7th second data stream in a set of 8 second data streams is 1001.

[0396] In some possible implementations, the first identifier in each second data stream includes a synchronization subsequence of 48 bits, wherein the first 24 bits of the synchronization subsequence are spaced 8 bits apart from the last 24 bits.

[0397] In some possible implementations, the first 24 bits of the 48-bit synchronization subsequence may have values ​​of 0x9A, 0x4A, and 0x26, and the last 24 bits may have values ​​of 0x65, 0xB5, and 0xD9.

[0398] In some possible implementations, N=128, K=120, and the third data processing unit is specifically used to: obtain one 128-bit internal codeword from each of the eight third data streams in each group to obtain a total of eight internal codewords. Then, it polls to obtain two bits from each of the eight internal codewords to obtain 1024 consecutive bits in the fourth data stream.

[0399] In some possible implementations, the first data processing unit is specifically used to: perform cyclic shifting on each of the m first data streams.

[0400] In some possible implementations, before performing cyclic shifting on each of the m first data streams, the first data processing unit is specifically used to: perform convolutional interleaving on each of the m first data streams.

[0401] In some possible implementations, the data processing apparatus further includes a convolutional interleaving unit and a distribution unit. Before cyclically shifting the m first data streams, the convolutional interleaving unit performs convolutional interleaving on the m / 4 input data streams respectively. The distribution unit distributes each of the convolutionally interleaved input data streams to obtain 4 first data streams, resulting in a total of m first data streams.

[0402] In some possible implementations, the data processing apparatus further includes a convolutional interleaving unit and a distribution unit. Before cyclically shifting the m first data streams, the convolutional interleaving unit performs convolutional interleaving on the m / 8 input data streams respectively. The distribution unit distributes each of the convolutionally interleaved input data streams to obtain 8 first data streams, resulting in a total of m first data streams.

[0403] Eighthly, embodiments of this application provide a data processing apparatus. The data processing apparatus includes: a data processing unit and a synchronization unit;

[0404] The data processing unit is used to: perform fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams, where Y is an integer greater than or equal to 1. Each fourth data stream is demodulated, and the baud rate of each modulated symbol stream is an integer multiple of the reference clock frequency. The Y modulated symbol streams are obtained by performing third data processing on m third data streams, where each modulated symbol stream is modulated. The m third data streams are obtained by performing second data processing on m second data streams. The m second data streams are obtained by performing first data processing on m first data streams encoded with first forward error correction (FEC), where m is an integer greater than 1. Each second data stream includes at least one first bit sequence, and each first bit sequence includes... Each of the first bit sequences contains bits, and each bit sequence contains bits. Each bit comes from the first data stream, and each first bit sequence contains... The first identifier is added using 1 bit. The second data processing includes the second FEC encoding. Each codeword after the second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, and S represents the number of parity bits. K is an integer greater than or equal to 1, and S is an integer greater than or equal to 1. =K×b, b is an integer greater than or equal to 1, and e is an integer greater than or equal to 1. The synchronization unit is used for: codeword synchronization and / or frame synchronization for each fourth data stream.

[0405] In some possible implementations, each third data stream includes at least one second bit sequence, each second bit sequence comprising P+W bits, wherein the P bits in each second bit sequence are composed of... The first bit is obtained by encoding the first bit using the second FEC. The W bits in each second bit sequence are the second identifier, which is obtained by encoding the first identifier using the second FEC. P = N × b, W = N × e.

[0406] In some possible implementations, the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz.

[0407] In some possible implementations, the first identifier includes padding bits and / or a status field.

[0408] In some possible implementations, each first data stream is further subjected to convolutional interleaving. Convolutional interleaving involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits from the input data stream are sequentially input to the r delay lines according to their indices. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r bits. The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

[0409] In some possible implementations, after convolutional interleaving, every f bits are output, and the input / output switch corresponding to the convolutional interleaving is located on the 0th delay line, and K×b is divisible by f.

[0410] In some possible implementations, r×d×c=K×b, where c is an integer greater than or equal to 1.

[0411] In some possible implementations, .

[0412] In some possible implementations, N=148, K=140, It is divisible by b, and It is divisible by 7.

[0413] In some possible implementations, .

[0414] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(148,140). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=140 information bits to obtain 70 bits, and then performs Hamming(78,70) encoding on these 70 bits to obtain S=8 parity bits. The resulting 148-bit codeword after the second FEC encoding contains K=140 information bits and S=8 parity bits.

[0415] In some possible implementations, N=127, K=120, It is divisible by b, and It is divisible by 3.

[0416] In some possible implementations, .

[0417] In some possible implementations, the first FEC encoding uses KP4 encoding, and the second FEC encoding uses Hamming(127,120). Alternatively, the first FEC encoding uses KP4 encoding, and the second FEC encoding performs a bitwise XOR operation on every two consecutive information bits in the K=120 information bits to obtain 60 bits, and then performs Hamming(67,60) encoding on these 60 bits to obtain S=7 parity bits. The resulting 127-bit codeword after the second FEC encoding contains K=120 information bits and S=7 parity bits.

[0418] In some possible implementations, the first data processing also includes scrambling.

[0419] In some possible implementations, the third data processing further includes codeword interleaving, where t codewords are interleaved to obtain a result including... A sequence of interleaved bits, where the i-th codeword is one of the t codewords. A sequence of K bits of information and a check sequence of S bits , The interleaved sequence contains continuous The first subsequence of bits and consecutive bits The second subsequence of bits, the first subsequence contains … There are a total of t information sequences, and the second subsequence contains … There are a total of t verification sequences.

[0420] In this embodiment, alignment markers are periodically inserted into the data stream after concatenated FEC encoding. Specifically, P bits are periodically extracted from the concatenated FEC encoded data stream, and an alignment marker of length W bits is inserted, so that there are W bit-length alignment markers in every P+W bits of the data stream. By selecting positive integers P and W, the baud rate of the modulation symbol data stream can be made an integer multiple of the Ethernet common reference clock frequency, simplifying the clock extraction and synchronization method at the receiver, enabling fast phase locking, and resulting in low PLL complexity and low jitter. Furthermore, P is required to be a multiple of the inner code length N, i.e. After the receiving end performs frame synchronization (i.e., frame synchronization of P+W bits, also known as identifier locking operation) on the received data, the internal codeword synchronization can be guaranteed, simplifying the frame synchronization and internal codeword synchronization operations at the receiving end and reducing implementation complexity. Furthermore, the convolutional interleaver and convolutional deinterleaver output each... K×b has 1 bit, and its input / output switch position is at the top. K×b is divisible by f, which ensures that the convolutional deinterleaver is synchronized during frame synchronization.

[0421] This application also provides another embodiment, in which the data stream encoded with the external code is periodically inserted after the first identifier is encoden with the internal code. Specifically, the data stream is periodically obtained from the data stream encoded with the external code. 1 bit, and insert 1 bit A first identifier of length 1 bit makes each bit in the data stream... There are bits in The first identifier is of length 1 bit. This application selects a positive integer. and This allows the baud rate of the modulated symbol data stream to be an integer multiple of the reference clock frequency, simplifying clock extraction and synchronization at the receiver, enabling fast phase locking, and resulting in low PLL complexity and minimal jitter. Furthermore, selecting a positive integer... All values ​​are divisible by the length K of the internal code information, resulting in low hardware complexity for the receiving end processing module's frame synchronization and codeword synchronization operations. Furthermore, selecting positive integers... This allows the synchronization of internal codewords to guarantee the synchronization of concatenated deinterleaving. In other words, the data processing method provided in this application reduces the complexity of frame synchronization, internal codeword synchronization, and concatenated deinterleaving synchronization in the receiving end processing module. Attached Figure Description

[0422] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application;

[0423] Figure 2(a) is Figure 1 A schematic diagram of a data transmission process in the communication system shown.

[0424] Figure 2(b) is a schematic diagram of another communication system applied in the embodiments of this application;

[0425] Figure 3 A schematic flowchart of a data processing method provided in an embodiment of this application;

[0426] Figure 4(a) is a schematic diagram of the first structure of the convolutional interleaver in the embodiments of this application;

[0427] Figure 4(b) is a schematic diagram of the second structure of the convolutional interleaver in an embodiment of this application;

[0428] Figure 5(a) is a schematic diagram of a third data stream structure in an embodiment of this application;

[0429] Figure 5(b) is a schematic diagram of another structure of the third data stream in an embodiment of this application;

[0430] Figure 6 Another flowchart illustrating the data processing method provided in this application embodiment;

[0431] Figure 7 Another flowchart illustrating the data processing method provided in this application embodiment;

[0432] Figure 8 This is a schematic diagram of the structure of the second data stream in an embodiment of this application;

[0433] Figure 9 This is a schematic diagram of the structure of the third data stream in an embodiment of this application;

[0434] Figure 10 This is a schematic diagram illustrating one implementation of the internal code encoding in the embodiments of this application;

[0435] Figure 11 This is a schematic diagram illustrating another implementation of the internal code encoding in the embodiments of this application;

[0436] Figure 12 This is a schematic diagram of the structure of a code character;

[0437] Figure 13 This is a schematic diagram of another type of codeword structure;

[0438] Figure 14 This is a schematic diagram illustrating one implementation method of data processing in this application.

[0439] Figure 15 This is a schematic diagram of one structure of the alignment mark in an embodiment of this application;

[0440] Figure 16 A schematic diagram of the calculator architecture used for synchronization;

[0441] Figure 17 This is a schematic diagram of another structure of the alignment mark in an embodiment of this application;

[0442] Figure 18 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0443] Figure 19 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0444] Figure 20 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0445] Figure 21 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0446] Figure 22(a) is a schematic diagram of another implementation of data processing in the embodiments of this application;

[0447] Figure 22(b) is a schematic diagram of another implementation of data processing in the embodiments of this application;

[0448] Figure 22(c) is a schematic diagram of another implementation of data processing in the embodiments of this application;

[0449] Figure 22(d) is a schematic diagram of an embodiment of generating alignment identifiers in this application;

[0450] Figure 23 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0451] Figure 24 This is a schematic diagram of one structure of the first identifier in an embodiment of this application;

[0452] Figure 25 This is a schematic diagram of a synchronization sequence after channel interleaving in an embodiment of this application;

[0453] Figure 26 This is a schematic diagram of another structure of the first identifier in the embodiments of this application;

[0454] Figure 27 This is a schematic diagram of another structure of the synchronization sequence after channel interleaving in an embodiment of this application;

[0455] Figure 28This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0456] Figure 29 This is a schematic diagram of another structure of the first identifier in the embodiments of this application;

[0457] Figure 30 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0458] Figure 31 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0459] Figure 32 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0460] Figure 33 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application;

[0461] Figure 34 This is a schematic diagram of a data processing device applied to the sending end in an embodiment of this application;

[0462] Figure 35 This is a schematic diagram of a data processing device applied at the receiving end in an embodiment of this application;

[0463] Figure 36 This is a schematic diagram of another structure of the data processing device in the embodiments of this application. Detailed Implementation

[0464] This application provides a data processing method and apparatus, which simplifies the clock extraction and synchronization process at the receiving end, enabling fast phase locking, low PLL complexity, and low jitter. It also simplifies frame synchronization and internal codeword synchronization at the receiving end, resulting in lower implementation complexity. It should be noted that the terms "first," "second," etc., in this application specification, claims, and accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be interchanged where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0465] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application. Figure 1As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers. The transmitting device 01 is also called a host chip located at the transmitting end, and the receiving device 05 is also called a host chip located at the receiving end. The channel transmission medium 03 can be optical fiber. The host chip is sometimes also called a host device. The transmitting device 01 and the transmitting processing module 02 can be connected via an attachment unit interface (AUI), and the receiving device 05 and the receiving processing module 04 can be connected via an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an 800LR module (an 800LR module, a coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission, and the specifics are not limited here.

[0466] Figure 2(a) is Figure 1 The diagram illustrates a data transmission process in the communication system shown. As shown in Figure 2(a), during data transmission from transmitting device 01 to receiving device 05, transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to transmitting processing module 02. Transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits the externally and internally encoded data to channel transmission medium 03. Channel transmission medium 03 transmits the externally and internally encoded data to receiving processing module 04. Receiving processing module 04 performs internal code decoding on the externally and internally encoded data and transmits the internally decoded data to receiving device 05. Receiving device 05 performs external code decoding on the internally decoded data.

[0467] It should be understood that the distinction between "internal" in internal code and "external" in external code is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with external code, the data encoded by the transmitting processing module 02 is called data encoded with internal code, the data decoded by the receiving device 05 is called data decoded with external code, and the data decoded by the receiving processing module 04 is called data decoded with internal code. In one possible implementation, both the internal and external code encoding described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Hamming code for internal code encoding. Alternatively, the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal code encoding. A BCH code correcting a single error is equivalent to a Hamming code. Another example: the transmitting device 01 can use RS code for external code encoding, and the transmitting processing module 02 can use Polar code for internal code encoding.

[0468] Figure 2(b) is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 2(b), the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data, and the encoded data is sent to the transmission medium 03. The receiving device 05 decodes the internal code and external code of the data received from the transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches or routers. The transmitting device 01 is also called a host chip located at the transmitting end, and the receiving device 05 is also called a host chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The host chip is sometimes also called a host device. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission, which is not limited here.

[0469] It should be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0470] Figure 3 This is a schematic flowchart of a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied to the sending end, and for example, it can be implemented by the sending end processing module 02 shown in Figure 2(a) above.

[0471] 301. Perform first data processing on multiple first data streams to obtain m second data streams.

[0472] In this embodiment, multiple first data streams are all data streams encoded by the first FEC, which is the data stream encoded by the external code as described above. The external code encoding can use RS code, and the data stream after external code encoding can include multiple RS codewords. In practical applications, other encoding methods can also be used for external code encoding. For ease of description, RS codewords are used to represent the codewords generated after external code encoding in the following text. It should be noted that the external code length value in this application is counted in units of external code symbols, where an external code symbol can include one or more bits. For example, the external code uses KP4 RS(544,514) code, with a code length of 544 symbols, and one external code RS symbol contains 10 bits.

[0473] It should be understood that the first data processing operations include, but are not limited to, performing a second FEC encoding on each first data stream. This second FEC encoding can be understood as the internal code encoding described above. That is, all m second data streams have undergone second FEC encoding, where m is an integer greater than 1. Typically, m takes values ​​of 4, 8, 16, 32, or 64. As an example, an internal code encoder is used to encode every K information bits in each first data stream using internal code encoding, i.e., adding S check bits to obtain a total of N bits of internal codeword, i.e., N = K + S, where K ≥ 1 and S ≥ 1. In some scenarios, K is a multiple of 10, and these K bits correspond to K / 10 external code symbols, and the corresponding K / 10 external code symbols come from K / 10 different external codewords.

[0474] In some possible implementations, the first data processing operation described above may further include at least one of the following operations: alignment lock, lane de-skew, lane reordering, concatenated interleaving, channel interleave, and scrambling. For example, each second data stream undergoes at least one of the following operations before being encoded by the second FEC: alignment lock, lane de-skew, lane reordering, and concatenated interleaving. As another example, each second data stream undergoes at least one of the following operations after being encoded by the second FEC: channel interleave and scrambling.

[0475] It should be noted that each second data stream undergoes channel interleaving after the second FEC encoding. This channel interleaving originates from the input... After the second FEC encoding (internal code encoding), the data stream obtains a total of one internal codeword of length N bits. The internal codewords include Each bit is used to generate two bits from each inner codeword in a round-robin fashion, which are then used as bits in the second data stream to obtain consecutive bits in the second data stream. Each bit. That is, the channel interleaving will... The second FEC-encoded (internal code encoded) data stream is processed to obtain a second data stream. This channel interleaving is also called... -Interweaving of internal code characters ( -wayinnercodewordinterleaver), also known as inner codeword interleaving.

[0476] It should be noted that, considering AWGN channels, the error bits of the inner code decoding input follow a random distribution, while the error bits of the decoding output no longer follow a random distribution. Adding a concatenated interleaver between the inner and outer codes can improve the performance of the entire concatenated FEC scheme. The concatenated interleaver operation typically includes convolutional interleavering to achieve lower latency. One specific implementation of concatenated interleavering includes channel permutation and convolutional interleavering. Channel permutation permutes the input g data streams to obtain g permuted data streams, which are then convolved and interleaved to obtain g convolutionally interleaved data streams. Another specific implementation of concatenated interleavering includes channel multiplexing and convolutional interleavering. Channel multiplexing permutes symbolically multiplexes the input g data streams to obtain g1 symbolically multiplexed data streams, where g is divisible by g1. These g1 data streams are then convolved and interleaved to obtain g1 convolutionally interleaved data streams, where g1 is not equal to g. In other words, the number of the first data stream and the second data stream obtained after the first data processing may be the same or different, depending on the actual application scenario, and is not limited here.

[0477] The following section introduces the possible implementation methods of the above convolutional interleaving.

[0478] The convolutional interleaver consists of r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1. Each storage unit stores d bits. Bits from each channel's data stream are sequentially input to the r delay lines according to their indices. Each delay line inputs d bits and outputs d bits at a time. After convolutional interleaverization, the output data stream contains consecutive r... The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, r delay lines may each include 0 storage units, Q storage units, 2Q storage units, ..., (r-1)Q storage units, with each storage unit storing d bits. Therefore, the r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits included in the delay values ​​of a delay line, the longer the delay (also called latency) of that delay line to the data stream. It should be understood that when a delay line does not contain any storage units, the delay of the delay line is 0 bits, which is called zero-latency pass-through.

[0479] The specific structure of the convolutional interleaver is described below with reference to the accompanying drawings. Figure 4(a) is a schematic diagram of the first structure of the convolutional interleaver in this embodiment. As shown in Figure 4(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 4(b) is a schematic diagram of the second structure of the convolutional interleaver in this embodiment. As shown in Figure 4(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units.

[0480] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is then switched to the next delay line. This ensures that the bits in each channel's data stream are sequentially input to the r delay lines according to their sequence numbers, and that consecutive r bits in the first data stream are... The d bits include the d bits output from each delay line. The specific data read / write operations are as follows: Read d bits from the memory cell closest to the output port of the current delay line. Transfer the d bits stored in each memory cell of the current delay line to the next memory cell. Then write d bits to the memory cell closest to the input port of the current delay line. Afterward, switch to the next delay line and repeat the above operations, and so on.

[0481] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving process in Figure 4(a) and the convolutional interleaving process in Figure 4(b) are the inverse operations of each other. That is, when the sending-end processing module adopts the convolutional interleaving structure shown in Figure 4(a), the convolutional deinterleaving structure corresponding to its receiving-end processing module adopts the structure shown in Figure 4(b). Similarly, when the sending-end processing module adopts the convolutional interleaving structure shown in Figure 4(b), the convolutional deinterleaving structure corresponding to its receiving-end processing module adopts the structure shown in Figure 4(a).

[0482] It should be noted that in some specific applications, before the internal code encoder encodes every K information bits in each first data stream, it also performs a cyclic shift operation. The cyclic shift operation shifts every K information bits to the left or to the right to improve the overall concatenated code's anti-burst performance.

[0483] 302. Perform second data processing on each of the m second data streams to obtain m third data streams.

[0484] In this embodiment, an alignment marker is periodically inserted into each second data stream to obtain the third data stream. Specifically, P bits are periodically obtained from each second data stream, and an alignment marker of length W bits is inserted, such that each third data stream contains an alignment marker of length W bits for every P+W bits. It should be understood that this application does not limit the specific form of the alignment marker. For example, the alignment marker added here can be the same as the alignment marker used in the aforementioned alignment lock, or, for example, the alignment marker added here can be a part of the alignment marker used in the aforementioned alignment lock. It should be noted that if the alignment marker added here contains a part of the alignment marker used in the aforementioned alignment lock, the first data processing operation typically includes scrambling.

[0485] Figure 5(a) is a schematic diagram of a third data stream in an embodiment of this application. As shown in Figure 5(a), the third data stream includes at least one bit sequence, each bit sequence including P+W bits, where P bits in each bit sequence come from the second data stream, and W bits in each bit sequence are added alignment identifiers. It should be noted that each P+W bit sequence can be called a frame, and the W-bit alignment identifier is usually located in the first W consecutive bits of the frame. In some specific application scenarios, the W-bit alignment identifier is also called a frame header, a frame alignment signal (FAS), or other names. It should be noted that the alignment identifier can contain bits with multiple functions, that is, only some of the W bits are used for receiver synchronization.

[0486] It should be noted that, in the P+W bits of each frame, the alignment identifier of the W bits can be located in the first W consecutive bits of the frame, or the alignment identifier of the W bits can be located in the last W consecutive bits of the frame.

[0487] Figure 5(b) is a schematic diagram of another structure of the third data stream in an embodiment of this application. As shown in Figure 5(b), the alignment identifier includes pad bits and / or a status field. For example, in W bits... One bit is used for receiver synchronization. Each bit is a padding bit, which can be a preset bit, such as... All bits are 0, or Each bit is a random bit, where, For example, in W bits... One bit is used for receiver synchronization. One bit is reserved as a pad bit for future development or innovative use. Each bit is a status field used to indicate the status of the FEC, where, .

[0488] In other scenarios, the aforementioned W-bit alignment identifier may not be arranged consecutively. For example, the alignment identifier can be split into multiple sub-identifier blocks distributed across P+W bits. Specifically, the W-bit alignment identifier is divided into h sub-identifier blocks distributed across P+W bits, with the lengths of the h sub-identifier blocks respectively represented by... The position of the W-bit alignment identifier within a frame of P+W bits is not specifically constrained here.

[0489] 303. Perform third data processing on m third data streams to obtain Y modulated symbol streams.

[0490] In this embodiment, m third data streams are processed with modulation to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1.

[0491] It should be noted that by selecting positive integers P and W, this application allows the baud rate of the modulated symbol data stream to be an integer multiple of the reference clock frequency. This simplifies clock extraction and synchronization at the receiver, enables fast phase locking, and results in low PLL complexity and low jitter. It should be understood that this application does not limit the specific value of the reference clock frequency; for example, it could be the Ethernet common reference clock frequency. As an example, the baud rate of the modulated symbol data stream is an integer multiple of 156.25 MHz. It should also be understood that a certain error range is acceptable in practical applications; for example, the baud rate of the modulated symbol data stream can be ±V (ppm) of an integer multiple of 156.25 MHz, where V can be 20, 50, or 100.

[0492] Furthermore, selecting a positive integer P enables the receiving end processing module to perform frame synchronization of received data (i.e., frame synchronization of P+W bits, also known as identifier locking operation). By achieving frame synchronization, the synchronization of internal codewords and concatenated deinterleaving can be guaranteed. In other words, the data processing method provided in this application allows the receiving end processing module to perform frame synchronization without needing to design additional operations for internal codeword synchronization and concatenated deinterleaving synchronization, thus achieving both simultaneously and simplifies implementation. The requirements for the values ​​of P and W are described in detail below.

[0493] Considering an 800GbE scenario, the transmitting device encodes the 800GbE service data stream to be transmitted using KP4 RS(544,514) external code, resulting in a data stream with a total rate of 850Gbps. After PMA processing, this data stream is sent to the transmitting processing module via the 800GAUI interface. The transmitting processing module performs first data processing, including internal code encoding, on multiple first data streams to obtain m second data streams with a total rate of... The m second data streams are periodically inserted with alignment markers, resulting in m third data streams after the second data processing. The total rate is... After the third data stream undergoes third data processing including PAM4 modulation, four modulation symbol streams are obtained, with a baud rate of [value missing]. ,here This indicates the rate of modulation symbols transmitted per second.

[0494] It should be noted that, for the 1.6TbE scenario, the transmitting device encodes the 1.6TbE service data stream to be transmitted using KP4RS (544,514) external code encoding to obtain a data stream with a total rate of 1.7Tbps. After PMA processing, this data stream is sent to the transmitting processing module via the connection unit interface (AUI). After the first, second, and third data processing steps described above, the transmitting processing module obtains eight PAM4 modulated symbol streams with a baud rate of... It should be noted that the modulation used in the third data stream processing described above may not be PAM4 modulation, but rather PAM8 modulation. In this case, eight PAM8 modulated symbol streams are obtained, with a baud rate of... .

[0495] Assuming the reference clock frequency is MHz, the following description will take the 800GBE scenario as an example. The baud rate value of the PAM4 modulated symbol stream is an integer multiple of the typical Ethernet reference clock frequency, with Where N is the code length of the internal code, K is the information bit length of the internal code, and a is a positive integer. G represents... M represents At this point, clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and minimal jitter. A typical Ethernet reference clock frequency is 156.25MHz. In some 800GbE scenarios, considering a baud rate of 112.5G, there are... .

[0496] It should be noted that the parameter combination N, K, P, W used for the aforementioned 800GbE scenario can also be used for higher speed scenarios, such as 1.6TbE. For example, when 1.6TbE uses PAM4 modulation, there are... The 1.6TbE uses integers. It is twice the integer 'a' in the 800GbE scenario. In some 1.6TbE scenarios, considering a 225G baud rate, we have... .

[0497] Furthermore, when P is a multiple of the internal code length N, that is... Where b is a positive integer. After the receiving end processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also known as the flag locking operation), it can guarantee the synchronization of the internal codewords. That is to say, the receiving end processing module can determine the frame boundary based on the alignment flag, thereby completing frame synchronization. Since P is a multiple of the internal code length N, the boundary of the internal codeword can be obtained after frame synchronization, thus completing the internal codeword synchronization. In some 800GbE scenarios using PAM4 modulation and a baud rate of 112.5G, or in 1.6TbE scenarios considering a baud rate of 225G, there are... Combining ,have .

[0498] Furthermore, for the transmitting processing module, which employs cascaded interleaving including convolutional interleaving, the receiving processing module, in order to ensure synchronization of convolutional deinterleaving during frame synchronization, should ensure that the starting position of each frame (W+P bits) corresponds to the starting position of the input and output switches of the convolutional deinterleaving unit, typically at the topmost positions, such as the position of delay line 0 shown in Figures 4(a) and 4(b). More specifically, the output of the convolutional interleaving unit and the convolutional deinterleaving unit... With 1 bit, its input / output switch positions are located at the top, and K×b is divisible by f, ensuring convolutional deinterleaving synchronization during frame synchronization. One specific method is as follows: r d c= , where r is the number of delay lines in the convolutional interleaver and convolutional deinterleaver, d is the number of bits stored in the memory cells in the convolutional interleaver and convolutional deinterleaver, and c is a positive integer.

[0499] In this way, based on the improvements to the transmitting end processing module in this application, as long as the receiving end processing module realizes frame synchronization of the received data according to the alignment identifier added by the transmitting end processing module, it is equivalent to simultaneously realizing internal code codeword synchronization and convolution deinterleaving synchronization, which simplifies the operations of receiving end frame synchronization, internal code codeword synchronization, and concatenated interleaving synchronization, and has low implementation complexity.

[0500] Figure 6This is another schematic flowchart illustrating the data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied at the receiving end, and for example, it can be specifically implemented by the receiving end processing module 04 shown in Figure 2(a) above.

[0501] 601. Perform fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams.

[0502] It should be understood that the Y modulated symbol streams originate from the transmitting end processing module 02. For information on the characteristics and generation method of the modulated symbol streams, please refer to the above. Figure 3 The relevant descriptions of the illustrated embodiment will not be repeated here. The receiving end processing module 04 performs fourth data processing, including demodulation, on the Y modulated symbol streams to obtain m fourth data streams. The fourth data processing performed by the receiving end processing module 04 is the inverse operation of the third data processing performed by the transmitting end processing module 02.

[0503] 602. Perform frame synchronization for each fourth data stream based on the alignment identifier in each fourth data stream.

[0504] The receiving end processing module 04 can identify and lock each fourth data stream according to the alignment identifier added by the sending end processing module 02, so as to determine the boundary of each frame (P+W bits) in the fourth data stream, thereby achieving frame synchronization.

[0505] It should be understood that after the receiving end processing module 04 completes frame synchronization, it will also perform fifth data processing on the m fourth data streams. The fifth data processing can be understood as the inverse operation of the first data processing performed by the sending end processing module 02. For example, the fifth data processing includes, but is not limited to, internal code decoding and concatenated deinterleaving. The concatenated deinterleaving includes convolutional deinterleaving, which will not be elaborated here.

[0506] The following example uses a specific application scenario to illustrate the operation of the sending end processing module 02 and the receiving end processing module 04.

[0507] The transmitting processing module 02 performs first data processing on the first data stream encoded with external code, including concatenated interleaving and internal code encoding, to obtain m second data streams, where concatenated interleaving includes convolutional interleaving. Next, each of the m second data streams is inserted with an alignment identifier of W bits at a period of P bits to obtain P+W bits, i.e., second data processing is performed to obtain m third data streams. The third data streams undergo third data processing including PAM4 modulation to obtain Y modulation symbol streams, where Y is a positive integer. For 800GbE service scenarios, Y=4; for 1.6TbE service scenarios, Y=8. This application material describes the data processing method using an 800GbE service scenario as an example, which can be easily extended to 1.6TbE service scenarios. The specific implementation method is known to those skilled in the art and will not be elaborated here.

[0508] The receiving-end processing module 04 performs fourth data processing on the received Y modulated symbol streams to obtain m fourth data streams. This fourth data processing is the inverse operation of the third data processing and includes PAM4 demodulation. Then, based on the W-bit alignment identifier inserted by the transmitting-end processing module 02, each fourth data stream is identified and locked to obtain the P+W-bit frame boundary in the fourth data stream, i.e., frame synchronization. Subsequently, the m fourth data streams undergo fifth data processing, which includes internal code decoding and concatenated deinterleaving, where concatenated deinterleaving includes convolutional deinterleaving. It should be understood that the receiving-end processing module 04 can also identify and lock each received modulated symbol stream based on the W-bit alignment identifier inserted by the transmitting-end processing module 02 and the characteristics of the third data processing to further achieve frame synchronization.

[0509] It should be noted that before performing internal code decoding, the receiving end processing module 04 needs to determine the internal code codeword boundaries, also known as internal codeword synchronization. It should also be noted that before performing convolutional deinterleaving, the receiving end processing module 04 needs to determine the positions of the input / output switches in the convolutional deinterleaving, also known as convolutional deinterleaving synchronization. Based on the above description, as long as the receiving end processing module 04 achieves frame synchronization of the received data according to the alignment identifier added by the transmitting end processing module 02, it is equivalent to simultaneously achieving internal codeword synchronization and convolutional deinterleaving synchronization. No additional operations are needed to synchronize internal codewords and concatenated deinterleaving, simplifying the receiving end's frame synchronization, internal codeword synchronization, and convolutional deinterleaving operations, resulting in lower implementation complexity.

[0510] The following examples, based on different internal code encoding methods, illustrate the possible values ​​of P and W.

[0511] Example 1: The internal code uses Hamming(128,120).

[0512] Consider using a block code with an information length K = 120 bits and a codeword length N = 128 bits, such as Hamming (128, 120). The baud rate of the PAM4 modulated symbol stream is... Assuming the above baud rate values... It is an integer multiple of the typical Ethernet reference clock frequency of 156.25MHz, i.e. Where a is a positive integer, and G represents M represents .have The value is an integer. The implementation of clock extraction and clock synchronization at the receiving end is simple, and it can perform fast phase locking. The PLL has low complexity and low jitter.

[0513] When P is a multiple of the internal code length N, that is The receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as the identifier locking operation), which ensures the synchronization of the internal codewords, and thus obtains the boundary of the internal codewords, where b is a positive integer. At this time, there is , positive integer Divisible by a positive integer b, and the positive integer b It is divisible by 3.

[0514] Consider some commonly used alignment identifier bit lengths W of 48, 56, 64, 120, and N=128. The corresponding possible positive integer combinations a, b, and P, and their corresponding baud rates are shown in Table 1 below:

[0515] Table 1

[0516]

[0517] For higher baud rates, optical module power consumption is typically higher. Considering baud rates below 114 GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 2 below:

[0518] Table 2

[0519]

[0520] The aforementioned internal code information has a length of K=120 bits, and one RS symbol of the external code KP4 contains 10 bits. For the convolutional interleaver between the internal and external codes, there exists a type where the input and output switches are located at the top for every 120 bits of output. For example, the convolutional interleaver has 3 delay lines (r=3) and each storage unit stores d=40 bits; or, the convolutional interleaver has 6 delay lines (r=6) and each storage unit stores d=20 bits. In this case, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as identifier locking operation), which ensures internal codeword synchronization, thus obtaining the internal codeword boundary; it also ensures convolutional deinterleaving synchronization, thus obtaining the input and output switch positions for convolutional deinterleaving, simplifying the implementation of the receiving end processing module.

[0521] It should be noted that the above embodiments consider the 800GbE scenario, which can be easily extended to the 1.6TbE scenario; for example, the parameter combinations W, P, and b in Table 1 can be directly used in the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and its baud rate is twice that of the 800GbE scenario.

[0522] Example 2: The internal code uses Hamming(170,160).

[0523] Consider using block codes with an information length K = 160 bits and a codeword length N = 170 bits, such as Hamming (170, 160). The baud rate of the PAM4 modulated symbol stream is... Assuming the above baud rate values... It is an integer multiple of the typical Ethernet reference clock frequency of 156.25MHz, i.e. Where a is a positive integer, and G represents M represents .have The value is an integer. The implementation of clock extraction and clock synchronization at the receiving end is simple, and it can perform fast phase locking. The PLL has low complexity and low jitter.

[0524] When P is a multiple of the internal code length N, that is The receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as the identifier locking operation), which ensures the synchronization of the internal codewords, and thus obtains the boundary of the internal codewords, where b is a positive integer. At this time, there is , positive integer Divisible by a positive integer b, and the positive integer b It is divisible by 4.

[0525] Consider some commonly used alignment identifier bit lengths W of 48, 56, 64, 120, and N=170. The corresponding possible positive integer combinations a, b, and P, and their corresponding baud rates are shown in Table 3 below:

[0526] Table 3

[0527]

[0528] For higher baud rates, optical module power consumption is typically higher. Considering baud rates below 114 GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 4 below:

[0529] Table 4

[0530]

[0531] The aforementioned inner code information has a length of K=160 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner and outer codes, there exists a convolutional interleaver where, for every 160 bits of output, its input and output switches are located at the top. For example, the convolutional interleaver has 4 delay lines (r=4) and each storage unit stores d=40 bits; or, for another example, the convolutional interleaver has 8 delay lines (r=8) and each storage unit stores d=20 bits. In this case, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as identifier locking operation), which ensures the synchronization of the inner codewords, thus obtaining the boundary of the inner codewords; it also ensures convolutional deinterleaving synchronization, thus obtaining the positions of the input and output switches for convolutional deinterleaving, simplifying the implementation of the receiving end processing module.

[0532] It should be noted that the above embodiments consider the 800GbE scenario, which can be easily extended to the 1.6TbE scenario; for example, the parameter combinations W, P, and b in Table 3 can be directly used in the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and its baud rate is twice that of the 800GbE scenario.

[0533] Example 3: The internal code uses Hamming(144,136).

[0534] Consider using block codes with an information length of K = 136 bits and a codeword length of N = 144 bits, such as Hamming (144, 136). The baud rate of the PAM4 modulated symbol stream is... Assuming the above baud rate values... It is an integer multiple of the typical Ethernet reference clock frequency of 156.25MHz, i.e. Where a is a positive integer, and G represents M represents .have The value is an integer. The implementation of clock extraction and clock synchronization at the receiving end is simple, and it can perform fast phase locking. The PLL has low complexity and low jitter.

[0535] When P is a multiple of the internal code length N, that is The receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as the identifier locking operation), which ensures the synchronization of the internal codewords, and thus obtains the boundary of the internal codewords, where b is a positive integer. At this time, there is , positive integer It is divisible by a positive integer b.

[0536] Consider some commonly used alignment identifier bit lengths W of 48, 56, 64, 120, and N=144. The corresponding possible positive integer combinations a, b, and P, and their corresponding baud rates are shown in Table 5 below:

[0537] Table 5

[0538]

[0539]

[0540]

[0541] For higher baud rates, optical module power consumption is typically higher. Considering baud rates below 114 GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 6 below:

[0542] Table 6

[0543]

[0544] It should be noted that the length of the internal code information mentioned above is K=136 bits, and one RS symbol of the external code KP4 contains 10 bits. For the convolutional interleaver between the internal and external codes, there exists a convolutional interleaver whose output r... With d = 160 bits, and its input / output switches located at the top, for example, if the convolutional interleaver has 4 delay lines (r = 4), each memory cell stores d = 40 bits. Alternatively, if the convolutional interleaver has 8 delay lines (r = 8), each memory cell stores d = 20 bits. Considering the inner code information length K = 136, the least common multiple of 160 is 2720 = 136 × 20. Therefore, the convolutional interleaver outputs 2720 = 17 × 160 bits, with its input / output switches at the top, and the output 2720 bits serve as the information bits for 20 inner codes. That is, when b is a multiple of 20, 2720 = r d c= Where c is a positive integer. At this time, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as identifier locking operation), which can guarantee the synchronization of the internal codewords, that is, obtain the boundary of the internal codewords; it can also guarantee the synchronization of convolution deinterleaving, that is, obtain the positions of the input and output switches of convolution deinterleaving. The corresponding combinations of positive integers a, b, and P, and their corresponding baud rates are shown in Table 7 below:

[0545] Table 7

[0546]

[0547] It should be noted that the length of the internal code information mentioned above is K=136 bits, and one RS symbol of the external code KP4 contains 10 bits. For the convolutional interleaver between the internal and external codes, there exists a convolutional interleaver whose output r... d = 140 bits, with its input / output switches located at the very top. For example, in a convolutional interleaver, the number of delay lines r = 7, and each memory cell stores d = 20 bits. Considering the internal code information length K = 136, the least common multiple of 140 is 4760 = 136. The above convolutional interleaver outputs 4760 = 34. The system uses 140 bits, with its input / output switches located at the top, and the output 4760 bits serve as 35 information bits for the internal code. That is, when b is a multiple of 35, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as identifier locking operation), which ensures internal codeword synchronization, thus obtaining the internal codeword boundary; it also ensures convolution deinterleaving synchronization, thus obtaining the positions of the input and output switches for convolution deinterleaving. The corresponding positive integer combinations a, b, and P, and their corresponding baud rates, are shown in Table 8 below.

[0548] Table 8

[0549]

[0550] It should be noted that the above embodiments consider the 800GbE scenario, which can be easily extended to the 1.6TbE scenario; for example, the parameter combinations W, P, and b in Table 5 can be directly used in the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and the baud rate used is twice that of the 800GbE scenario.

[0551] Example 4: The internal code encoding uses FEC code with information length K=140 bits and codeword length N=148 bits.

[0552] Consider using FEC codes with an information length K = 140 bits and a codeword length N = 148 bits, such as Hamming (148, 140) codes. Alternatively, consider using... Figure 10 The encoding method shown represents the 140 bits of data to be encoded as B[139:0]. Each consecutive two bits are XORed to obtain 1 bit of data C[i], resulting in a total of 70 bits, represented as C[69:0]. Where C[i] = B[2... i]^B[2 i+1], Then, C[69:0] is used as information data and Hamming(78,70) is used to encode 8 bits of check data, represented as P[7:0]. Finally, B[139:0] and P[7:0], a total of 148 bits, are concatenated to form the output of the internal code, represented as D[147:0]. D[139:0] comes from B[139:0], and D[147:140] comes from P[7:0].

[0553] The baud rate of the PAM4 modulated symbol stream is Assuming the above baud rate values... It is an integer multiple of the typical Ethernet reference clock frequency of 156.25MHz, i.e. Where a is a positive integer, and G represents M represents .have The value is an integer. The implementation of clock extraction and clock synchronization at the receiving end is simple, and it can perform fast phase locking. The PLL has low complexity and low jitter.

[0554] When P is a multiple of the internal code length N, that is The receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as the identifier locking operation), which ensures the synchronization of the internal codewords, and thus obtains the boundary of the internal codewords, where b is a positive integer. At this time, there is , positive integer Divisible by a positive integer b, and the positive integer b It is divisible by 7.

[0555] Consider some commonly used alignment identifier bit lengths W of 48, 56, 64, 120, and N=148. The corresponding possible positive integer combinations a, b, and P, and their corresponding baud rates are shown in Table 9 below:

[0556] Table 9

[0557]

[0558] For higher baud rates, optical module power consumption is typically higher. Considering baud rates below 114 GBaud, the optimal combinations of positive integers a, b, and P, and their corresponding baud rates, are shown in Table 10 below:

[0559] Table 10

[0560]

[0561] The aforementioned inner code information has a length of K=140 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner and outer codes, there exists a convolutional interleaver where, for every 140 bits of output, its input / output switches are located at the top. For example, the convolutional interleaver has a delay line count r=7, and each storage unit stores d=20 bits. In this case, the receiving end processing module performs frame synchronization of the received data (i.e., frame synchronization of P+W bits, also known as identifier locking operation), which ensures the synchronization of the inner codewords, thus obtaining the boundary of the inner codewords; it also ensures convolutional deinterleaving synchronization, i.e., obtaining the positions of the input and output switches for convolutional deinterleaving, simplifying the implementation of the receiving end processing module.

[0562] It should be noted that the above embodiments consider the 800GbE scenario, which can be easily extended to the 1.6TbE scenario; for example, the parameter combinations W, P, and b in Table 9 can be directly used in the 1.6TbE scenario. For example, the 1.6TbE scenario still uses PAM4 modulation, and the baud rate used is twice that of the 800GbE scenario.

[0563] In some 800GbE scenarios using PAM4 modulation and a baud rate of 112.5G, or in 1.6TbE scenarios considering a baud rate of 225G, there are Combining ,have .because , ,have Considering b is an integer, there are integers... The integer b is a multiple of 4, and the integer b is a multiple of 17.

[0564] Example 5: The internal code encoding uses FEC code with information length K=120 bits and codeword length N=128 bits.

[0565] Consider using FEC codes with an information length of K = 120 bits and a codeword length of N = 128 bits, such as Hamming (128, 120) codes. For example, the 120 bits of data to be encoded are represented as B[119:0]. Performing a bitwise XOR operation on every two consecutive bits yields 1 bit of data C[i], resulting in a total of 60 bits, represented as C[59:0]. Where C[i] = B[2... i]^B[2 i+1], Then, C[59:0] is used as information data and Hamming(68,60) is performed to obtain 8 bits of check data, represented as P[7:0]. Finally, B[119:0] and P[7:0], a total of 128 bits, are concatenated to form the output of the internal code, represented as D[127:0]. Among them, D[119:0] comes from B[119:0], and D[127:120] comes from P[7:0].

[0566] Considering an 800GE scenario and using PAM4 modulation, data processing yields four PAM modulated symbol streams. Without considering the alignment identifier of W bits per period, the baud rate of the PAM4 modulated symbol stream is... Its baud rate is approximately 725.3333 times the reference clock frequency of 156.25 MHz. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering the alignment flag of W bits inserted per P bits, the baud rate of the PAM4 modulated symbol stream is 113.4375. Its baud rate is 726 times that of the reference clock frequency of 156.25 MHz.

[0567] In conjunction with Example 1 ,have ,at this time Considering that W is an integer multiple of the internal codeword length N=128, the corresponding value of P is also an integer multiple of 128, enabling the receiver to perform frame synchronization and codeword synchronization with low complexity. Several typical values ​​of W and P are shown in Table 13.

[0568] Table 13

[0569]

[0570] Figure 14This is a schematic diagram illustrating one implementation method of data processing in this application. (In conjunction with...) Figure 14 The specific data processing flow is described below:

[0571] The 32 data streams that have undergone the first FEC encoding are internally encoded to obtain 32 internally encoded data streams. Specifically, each K=120 information bits in each data stream is internally encoded, that is, S=8 parity bits are added to obtain a total of N=128 internal codewords.

[0572] Channel interleaving is performed on every 8 encoded data streams from the 32 internal codes to obtain one second data stream, resulting in a total of m=4 second data streams. (Refer to...) Figure 14 For the 800GE scenario, data processing includes four data sub-processing steps, namely... Figure 14 The data is divided into data subprocessing 0, data subprocessing 1, data subprocessing 2, and data subprocessing 3. Each data subprocessing contains one channel interleaving. The channel interleaving starts from the input... After bar encoding, the data stream acquires one 128-bit internal codeword for a total of eight internal codewords. Then, it round-robins to extract two bits from each internal codeword as bits for the second data stream, resulting in 1024 consecutive bits in the second data stream. This channel interleaving is also known as 8-way Hamming codeword interleaving, or internal codeword interleaving.

[0573] Alignment identifiers are periodically inserted into each of the m=4 second data streams to obtain m=4 third data streams. Specifically, P bits are periodically extracted from each second data stream, and an alignment identifier of length W bits is inserted, so that each third data stream contains an alignment identifier of length W bits for every P+W bits.

[0574] The m=4 third data streams are processed to obtain Y=4 modulated symbol streams by performing third data processing including PAM4 modulation.

[0575] Figure 15 This is a schematic diagram of one structure of the alignment mark in an embodiment of this application. This embodiment uses... , The specific structure of the alignment identifier with a periodic insertion length of W=384 bits will be described using an example. Figure 15 As shown in (a), the 1024-bit alignment identifier contains at least one set of frame synchronization sequences for receiver synchronization. This set of frame synchronization sequences comprises a total of 48 bits, distributed as two frame synchronization sub-sequences within the alignment identifier. Figure 15 Frame synchronization subsequence 1 and frame synchronization subsequence 2 in (b). Each frame synchronization subsequence contains 24 bits. The two frame synchronization subsequences are not consecutive in the 1024-bit alignment identifier, but are separated by 8 bits (one byte). Their specific structure is as follows: Figure 15 As shown in (b). Here, the interval between two consecutive bits is defined as 0 bits.

[0576] In some specific applications, the 24-bit frame synchronization subsequence 1 has the following values: 0x9A, 0x4A, 0x26, and the 24-bit frame synchronization subsequence 2 has the following values: 0x65, 0xB5, 0xD9. It should be noted that the frame synchronization subsequence 1 (or frame synchronization subsequence 2) is transmitted in the following order: 0x9A, 0x4A, 0x26 (or 0x65, 0xB5, 0xD9). More specifically, for frame synchronization subsequence 1, 0x9A is the first byte transmitted, and 0x26 is the last byte transmitted; and for a byte of 8 bits, the LSB is transmitted first, and the MSB is transmitted last. For example, 0x9A corresponds to 8 bits transmitted from left to right according to the bit sequence 01011100.

[0577] Figure 16 This is a schematic diagram of the computer architecture used for synchronization. It should be noted that the two frame synchronization sub-sequences in the set of frame synchronization sequences are spaced 8 bits (one byte) apart in the 1024-bit alignment identifier. This allows the receiving end to reuse the synchronization hardware implementation architecture in existing 100GE 802.3bj and 400GE 802.3bs standards during frame synchronization. Figure 16 Figure (a) shows the relevant calculator architecture used for alignment identifier synchronization in the 100GE 802.3bj standard. Figure 16 Figure (b) shows the relevant computer architecture used for alignment identifier synchronization in the 400GE 802.3bs standard. Figure 16 (c) shows the related computer architecture used for frame synchronization in this invention. It can be seen that the proposed frame synchronization sequence structure can reuse the synchronization hardware implementation architecture in the existing 100GE 802.3bj and 400GE 802.3bs standards, which is convenient for implementation.

[0578] Example 6:

[0579] Figure 17 This is a schematic diagram of another structure for the alignment identifier in an embodiment of this application. Based on embodiment 5, consider... , In the data processing operation, P bits are periodically acquired from each second data stream, and an alignment identifier of length W bits is inserted. The alignment identifier contains multiple sets of frame synchronization sequences used for receiver synchronization. For example... Figure 17 (a) and Figure 17 As shown in (b), the alignment identifier contains three sets of frame synchronization sequences for receiver synchronization. Figure 17 As shown in (c), the alignment identifier contains two sets of frame synchronization sequences for receiver synchronization.

[0580] It should be noted that there may be intervals or no intervals between each set of frame synchronization sequences. For example... Figure 17 As shown in (a), the three sets of frame synchronization sequences are without gaps in the alignment identifier of W = 1024 bits in length. Figure 17 As shown in (b), the two adjacent frame synchronization sequences in the three sets of frame synchronization sequences are spaced 8 bits apart in the alignment identifier of W=1024 bits. It should be noted that the number of bits between the two adjacent frame synchronization sequences in the alignment identifier of W=1024 bits can be any other positive integer that is a multiple of 8.

[0581] It should be noted that the specific values ​​of the multiple frame synchronization sequences can be the same or different. For example... Figure 17 As shown in (a), the values ​​of the three sets of frame synchronization sequences are the same, and the 48 bits in each set of frame synchronization sequences are: 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9. Figure 17 As shown in (b), in the three sets of frame synchronization sequences, the values ​​of the first and second sets of frame synchronization sequences are the same, and the 48 bits in each set of frame synchronization sequences are: 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9; the values ​​of the third set of frame synchronization sequences are different from those of the first and second sets of frame synchronization sequences, and its 48 bits are: 0x01, 0x71, 0xF3, 0xFE, 0x8E, 0x0C. Figure 17 As shown in (c), the values ​​of the two sets of frame synchronization sequences are different. The 48 bits in the first frame synchronization sequence are: 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9; the 48 bits in the second frame synchronization sequence are: 0x01, 0x71, 0xF3, 0xFE, 0x8E, 0x0C.

[0582] Example 7:

[0583] Figure 18 This is a schematic diagram illustrating another implementation of data processing in this application. Based on Embodiment 5, considering a 1.6TE scenario and employing PAM4 modulation, data processing yields 8 PAM modulated symbol streams. Without considering the alignment identifier with a periodic insertion length of W bits, the baud rate of the PAM4 modulated symbol stream is... Its baud rate is approximately 725.3333 times the reference clock frequency of 156.25 MHz. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering the alignment flag with a periodic insertion of W bits, the baud rate of the PAM4 modulated symbol stream is 113.4375. Its baud rate is 726 times that of the reference clock frequency of 156.25 MHz.

[0584] In conjunction with Example 1 ,have ,at this time Considering that W is an integer multiple of the internal codeword length N=128, the corresponding value of P is also an integer multiple of 128, enabling the receiver to perform low-complexity frame synchronization and codeword synchronization. Several typical values ​​for W and P are shown in Table 13 of Example 5. For the specific data processing flow, please refer to... Figure 18 To understand this, the data processing includes eight data sub-processes, namely data sub-processes 0-7. The specific operation of each data sub-process can be understood by referring to Example 5.

[0585] Example 8:

[0586] Figure 19 This is a schematic diagram illustrating another implementation of data processing in this application. Based on Embodiment 5, before the internal code encoder performs internal code encoding on every K=120 information bits in each first data stream, it also performs a cyclic shift operation. For example... Figure 19 As shown, the cyclic shift operation shifts each K=120 information bits to the right in a cyclic shift to improve the overall burst resistance of the concatenated code.

[0587] Example 9:

[0588] Figure 20 This is a schematic diagram illustrating another implementation of data processing in this application. Based on Embodiment 5, before the internal code encoder performs internal code encoding on every K=120 information bits in each first data stream, it also performs a convolutional interleaving operation. For example... Figure 20 As shown, in the 32 first data streams, every 8 first data streams are first convolutionally interleaved, then cyclically shifted by 120 bits per K, then encoded using internal codes, and finally interleaved using channel interleaving (internal codeword interleaving) to obtain 1 second data stream, for a total of 4 second data streams. The convolutional interleaving before internal code encoding improves the overall performance of the concatenated code under AWGN.

[0589] Example 10:

[0590] Figure 21This is a schematic diagram illustrating another implementation of data processing in this application. Based on Embodiment 9, every two first data streams out of the eight first data streams form a group of two input data streams for a data sub-process. In each data sub-process, each group of two first data streams undergoes convolutional interleaving to obtain two convolutionally interleaved data streams. Each convolutionally interleaved data stream undergoes data distribution to obtain four distributed data streams, resulting in a total of eight distributed data streams. The data distribution is based on... Bits represent granularity. For example... Figure 21 As shown, the data stream after convolutional interleaving is composed of... When bits are grouped together, for a total of 4 consecutive groups bits, group 0 Bits are sent to the 0th data stream and the 1st group of the 4 distributed data streams. Bits are sent to the first data stream and the second group of the four distributed data streams. Bits are sent to the second data stream and the third group of the four distributed data streams. The bits are fed into the third data stream of the four distributed data streams. Typically, the granularity of the distributed bits is... .

[0591] It should be noted that for the 800GE scenario, data processing includes four data sub-processing steps, such as... Figure 21 As shown, each data subprocess receives two first data streams as input. These two first data streams correspond to a rate of approximately 200 Gbps, or approximately 100 Gbps per second for each first data stream. Correspondingly, the distributed data stream corresponds to a rate of approximately 25 Gbps.

[0592] It should also be noted that when the bit distribution granularity is At times, such as Figure 21 The data processing described can be described as follows: two first data streams are convolutionally interleaved to obtain a total of two convolutionally interleaved data streams. Four bit packets, each 120 bits in length, are obtained from each convolutionally interleaved data stream. Each bit packet undergoes cyclic shifting and internal code encoding to obtain four internal codewords. A total of eight bit packets are obtained from the two convolutionally interleaved data streams, which are then cyclically shifted and encoded to obtain eight internal codewords. These are then channel interleaved to obtain 1024 bits in the second data stream.

[0593] It should be noted that in some specific application scenarios with low latency requirements, the aforementioned... Figure 21 The convolutional interleaving in the code is removed, and the convolutional interleaving operation is bypassed.

[0594] It should be noted that, for the 1.6TE scenario, data processing includes eight data sub-processes, each of which receives two first data streams as input. These two first data streams correspond to a rate of approximately 200 Gbps, or approximately 100 Gbps per second. Correspondingly, the distributed data stream corresponds to a rate of approximately 25 Gbps.

[0595] Example 11:

[0596] Figure 22(a) is a schematic diagram of another implementation of data processing in this application. Based on embodiment 9, each of the four first data streams is used as the input data stream for a data sub-process. In each data sub-process, the first data stream undergoes convolutional interleaving to obtain one convolutionally interleaved data stream. The one convolutionally interleaved data stream is then distributed to obtain eight distributed data streams. The data distribution is based on... Bits represent granularity. As shown in Figure 22(a), the data stream after convolutional interleaving is granular. When bits are grouped together, for a total of 8 consecutive groups bits, group 0 Bits are sent to the 0th data stream and the 1st group of the 8 distributed data streams. Bits are sent to the first, ..., seventh group of the eight distributed data streams. The bits are fed into the 7th data stream of the 8 distributed data streams. Typically, the granularity of the distributed bits is... .

[0597] It should be noted that for the 800GE scenario, the data processing includes four data sub-processes, as shown in Figure 22(a). Each data sub-process receives one first data stream as input, corresponding to a rate of approximately 200 Gbps. Correspondingly, the distributed data stream corresponds to a rate of approximately 25 Gbps.

[0598] It should also be noted that for bit distribution granularity of... As shown in Figure 22(a), the data processing can be described as follows: each first data stream undergoes convolutional interleaving to obtain one convolutionally interleaved data stream. Eight bit groups, each 120 bits long, are obtained from the convolutionally interleaved data stream. Each bit group is then cyclically shifted and encoded using internal codes to obtain eight internal codewords, which are then channel interleaved to obtain 1024 bits in the second data stream.

[0599] It should be noted that in some specific application scenarios with low latency requirements, the convolutional interleaving in Figure 22(a) can be removed, and the convolutional interleaving operation can be bypassed. Furthermore, to achieve lower latency, lower complexity, and lower power consumption, in some possible scenarios, the cyclic shift operation and / or channel interleaving (internal codeword interleaving) operation can also be bypassed. If the channel interleaving (internal codeword interleaving) operation is bypassed, one-way Hamming codeword interleaving can be performed on the 8 encoded data streams, which is equivalent to codeword merging of the 8 encoded data streams.

[0600] Figure 22(b) is a schematic diagram of another implementation of data processing in this application. Each of the four first data streams serves as the input data stream for a data sub-process. Unlike the implementation shown in Figure 22(a), as shown in Figure 22(b), in each data sub-process, instead of performing convolutional interleaving on one first data stream, data distribution is directly performed to obtain eight distributed data streams. The data distribution is based on… Bits refer to granularity, meaning the first data stream before data distribution. When each bit is grouped into a set, for 8 consecutive sets of bits, the total... bits, group 0 Each bit is sent into the 0th data stream after distribution, group 1. One bit is sent into the first data stream after distribution, ..., the seventh group. Each bit is sent to the 7th data stream after distribution. Typically, the bit distribution granularity is... .

[0601] Figure 22(c) is a schematic diagram of another implementation of data processing in this application. In one possible implementation, the implementation of Figure 22(b) is simplified to obtain the implementation shown in Figure 22(c), which is equivalent to Figure 22(b). Specifically, as shown in Figure 22(c), in each data subprocessing, the first data stream is encoded using an internal code to obtain a second data stream, and an alignment identifier is inserted into the second data stream period to obtain a third data stream, which is then PAM4 modulated to obtain a modulation symbol stream.

[0602] It should be noted that the modulated symbol stream obtained by the data processing shown in Figure 22(b) or Figure 22(c) is transmitted through the actual channel and then the received symbol stream is obtained at the receiving end. PAM4 demodulation is then performed to obtain the demodulated data stream. As an example, the data processing method at the receiving end is to use the frame synchronization sequence in the alignment identifier to perform frame synchronization to obtain the start position of each frame and the inner code boundary. Then, soft-decision decoding of the inner code is performed to obtain the decoded data stream, which is then sent to the client-side equipment for KP4 decoding of the outer code. The bit error rate before correction of the entire cascaded system can reach approximately 3.3E-3.

[0603] As another example, the data processing method at the receiving end is to use the frame synchronization sequence in the alignment identifier to perform frame synchronization to obtain the start position of each frame and the internal code boundary, and then perform hard-decision decoding of the internal code to obtain the decoded data stream, which is then sent to the client-side equipment for external code KP4 decoding. The bit error rate before correction of the entire cascaded system can reach approximately 6E-4. It should be understood that the internal code decoding uses hard-decision decoding, which has low decoding complexity.

[0604] As another example, in scenarios with good link quality, the receiver can use the frame synchronization sequence in the alignment identifier to perform frame synchronization to obtain the start position of each frame and the internal code boundary. Then, it does not perform (bypass) internal code decoding; that is, it directly removes the parity bits in each received internal code codeword in the data stream, retaining only the information bits. Then, it uses the frame synchronization sequence in the alignment identifier to perform frame synchronization again to obtain the start position of each frame, removes the alignment identifier, and then sends it to the client-side equipment for external code KP4 decoding. In this case, the receiver has the advantages of extremely low latency and extremely low complexity.

[0605] In some possible implementations, the length W of the alignment identifier is an integer multiple of the inner codeword length N, and the specific pattern of the alignment identifier is one or more inner codewords. As an example, the inner codewords constituting the alignment identifier are obtained by encoding the alignment identifier information using inner code, which is the aforementioned second FEC encoding. The length of the inner codeword obtained after encoding the alignment identifier information is the same as the length of the inner codeword obtained by the second FEC encoding in the aforementioned second data stream. For ease of description, the inner codewords constituting the alignment identifier can also be called target codewords, meaning that the length of the target codeword is the same as the length of the inner codeword in the aforementioned second data stream. Specifically, each target codeword is obtained by encoding the alignment identifier information, which includes K target bits, using inner code. The target codeword includes N bits, which include K target bits and S encoded parity bits.

[0606] Figure 22(d) is a schematic diagram of one embodiment of generating alignment identifiers in this application. As shown in Figure 22(d), two possible methods for generating alignment identifiers are provided.

[0607] Taking alignment identifier generation method 0 as an example, the length W of the alignment identifier is an integer multiple of the target codeword length N, that is... .in, It must be a multiple of 8, for example, At this point, the specific pattern of the alignment identifier can be selected as one or more target codewords. Optionally, the alignment identifier is obtained by interleaving multiple target codewords. Specifically, it includes... The alignment identifier information of each target bit is obtained by encoding with internal code. One target code word, The target codewords are then interleaved through 8-way codewords to obtain the alignment identifier. It should be understood that the alignment identifier obtained by interleaving multiple target codewords should also be considered to include multiple target codewords.

[0608] Taking alignment identifier generation method 1 as an example, the length W of the alignment identifier is an integer multiple of the target codeword length N, that is... .For example, For example, At this point, the specific pattern of the alignment identifier can be selected as one or more target codewords. Optionally, the alignment identifier is obtained by merging multiple target codewords. Specifically, it includes... The alignment identifier information of each target bit is obtained by encoding with internal code. One target code word, The target codewords are then merged to obtain the alignment identifier.

[0609] It should be noted that, for the implementation shown in Figure 22(a), the alignment identifier generation method 0 shown in Figure 22(d) or the alignment identifier generation method 1 shown in Figure 22(d) can be used. In this case, the corresponding data processing method at the receiving end is to perform internal codeword self-synchronization on the demodulated data stream after demodulation to obtain the internal codeword boundaries, then obtain the 8-channel internal codeword deinterleaved data stream and perform internal code decoding, and then use the frame synchronization sequence in the alignment identifier information after internal code decoding to perform frame synchronization to obtain the start position of each frame. It should be understood that, since the reliability of the frame synchronization sequence and status field contained in the alignment identifier information after internal code decoding is further improved, the time required for frame synchronization can be shortened.

[0610] It should be noted that, for the implementation shown in Figure 22(b) or Figure 22(c), the alignment identifier generation method 0 shown in Figure 22(d) or the alignment identifier generation method 1 shown in Figure 22(d) can be used. In this case, the corresponding data processing method at the receiving end is to perform internal code self-synchronization on the demodulated data stream after demodulation to obtain the internal code codeword boundaries, then perform internal code decoding, and then use the frame synchronization sequence in the alignment identifier information after internal code decoding to perform frame synchronization to obtain the start position of each frame. It should be understood that, since the reliability of the frame synchronization sequence and status field contained in the alignment identifier information after internal code decoding is further improved, the time required for frame synchronization can be shortened.

[0611] It should be noted that in the data processing methods shown in Figures 22(a), 22(b), and 22(c), the third data stream obtained after inserting the alignment identifier contains W bits of alignment identifier every P+W bits, and the synchronization sequence in the alignment identifier is located at a fixed position. Therefore, for the data processing methods shown in Figures 22(a), 22(b), and 22(c), the same operation can be used in the corresponding receiving end data processing to perform frame synchronization and obtain the frame start position, which facilitates a single hardware set to be compatible with the receiving end data processing corresponding to the transmitting end data processing shown in Figures 22(a), 22(b), and 22(c).

[0612] It should be noted that, for the 1.6TE scenario, the data processing includes eight data sub-processes, each of which receives one first data stream as input, corresponding to a rate of approximately 200 Gbps. Correspondingly, the distributed data stream corresponds to a rate of approximately 25 Gbps.

[0613] It should be noted that in some specific applications, the length W of the alignment identifier is an integer multiple of the length N of the second FEC code (also known as internal code encoding), and P is an integer multiple of N. In this case, the alignment identifier can be protected by internal code encoding, that is, the W-bit alignment identifier contains... One internal code character, among which Each bit corresponds to an information bit in the internal codeword. correspond The parity bits of each internal codeword. Typically, the... In bits The bits serve as the frame synchronization sequence mentioned above, with another portion used to transmit link information and / or control information, including receiver status, FEC status, etc., also known as the status field. Specifically, to improve the accuracy of the transmitted link information and / or control information, the... The remaining bits after removing the aforementioned frame synchronization sequence bits, of which One bit is used for the type of the indicated link information and / or control information. Each bit is used to represent the specific content of the indicated link information and / or control information. 10 bits are used for Cyclic Redundancy Check (CRC). Typically, , The value can be 8, 16, or 32. In some specific applications, multiple frames are needed to collaboratively transmit the indicated link information and / or control information to further improve the accuracy of the transmitted information. In this case, the... Bit One bit is used to refer to the multiple frames, These bits are also called multi-frame synchronization signals. Typically, .

[0614] In some specific applications, such as Figure 15 The frame synchronization sequence contains 48 bits, distributed as two frame synchronization sub-sequences with an 8-bit interval between them. The 8-bit interval can be used for the 8 bits required for the CRC8 check, or for the 8 bits required for the type of the link information and / or control information, or for the 8 bits required for the multi-frame synchronization signal.

[0615] In summary, this embodiment of the application periodically inserts an alignment marker into the data stream after concatenated FEC encoding. Specifically, P bits are periodically extracted from the concatenated FEC encoded data stream, and an alignment marker of length W bits (also called a frame header, which may contain padding bits or a status field) is inserted, so that there are W bits of alignment markers in every P+W bits (called a frame) of the data stream. By selecting positive integers P and W, the baud rate of the modulation symbol data stream can be made an integer multiple of the Ethernet common reference clock frequency, simplifying the clock extraction and synchronization method at the receiver, enabling fast phase locking, and resulting in low PLL complexity and low jitter. Furthermore, P is required to be a multiple of the inner code length N, i.e. After the receiving end performs frame synchronization (i.e., frame synchronization of P+W bits, also known as identifier locking operation) on the received data, the internal codeword synchronization can be guaranteed, simplifying the frame synchronization and internal codeword synchronization operations at the receiving end and reducing implementation complexity. Furthermore, the convolutional interleaver and convolutional deinterleaver output each... K×b has 1 bit, and its input / output switch position is at the top. K×b is divisible by f, which ensures that the convolutional deinterleaver is synchronized during frame synchronization.

[0616] When the receiving end uses a W-bit alignment identifier (also called a frame header, which may contain padding bits or a status field) for frame synchronization, it needs to perform bit-by-bit position identification. Considering that the integer P is usually large, the complexity of frame synchronization operation for bit-by-bit position identification is greater than the complexity of internal codeword synchronization operation. In some application scenarios, the length W of the alignment identifier can be selected as an integer multiple of the length N of the second FEC code (also called internal code), and the specific pattern of the alignment identifier can be selected as one or more internal codewords, so that the receiving end can perform frame synchronization and codeword synchronization with low complexity. The above-mentioned operation method of performing internal code encoding first and then periodically inserting the alignment identifier can be equivalent to the following operation method of periodically inserting the identifier first and then performing internal code encoding. That is, the internal code encoding scheme used in the above embodiment of "performing internal code encoding first and then periodically inserting the alignment identifier" can also be used in the internal code encoding scheme of "periodically inserting the identifier first and then performing internal code encoding" in the following embodiments. For example, the block code with information length K=120 bits and codeword length N=128 bits used in embodiment 1 can also be used in the following specific embodiments. The following describes the specific implementation plan for "periodic insertion of identifiers followed by internal code encoding".

[0617] Figure 7 This is another schematic flowchart illustrating a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied at the sending end and includes the following steps.

[0618] 401. Process the m first data streams to obtain m second data streams.

[0619] In this embodiment, all m first-order data streams are data streams obtained through the first FEC encoding, which is the data stream encoded by the external code as described above. Typically, m takes the value 4, 8, 16, 32, or 64.

[0620] Specifically, a first identifier is periodically inserted into each of the m first data streams to obtain a total of m second data streams. Specifically, the identifier is periodically obtained from each first data stream. 1 bit, and insert 1 bit The first identifier, with a length of 1 bit, makes each bit in the second data stream... + There are bits in The first identifier is one bit long.

[0621] Figure 8This is a schematic diagram of one structure of the second data stream in an embodiment of this application. For example... Figure 8 As shown, the second data stream includes at least one first bit sequence, each first bit sequence including + Each of the first bit sequences contains bits, and each bit sequence contains bits. Each bit comes from the first data stream, and each first bit sequence contains... Each bit is the first identifier to be added. It should be noted that the first identifier may include padding bits and / or a status field. The padding bits may be preset bits, such as all 0s, or random bits; the status field is used to indicate the status of the FEC. In other scenarios, the above... The first identifier of each bit may not be consecutive; for The alignment identifier of each bit is in + The position of each bit is not specifically constrained here.

[0622] It should be noted that each of the above... + In the bits, the The first identifier of each bit can be located in the... + The first of the bits A series of consecutive bits, the The first identifier of each bit can also be located in the... + The last of the bits A series of consecutive bits.

[0623] In some possible implementations, a cascaded interleaver is added between the inner and outer codes to improve the overall performance of the cascaded FEC scheme. The cascaded interleaver operation typically includes convolutional interleaver to achieve lower latency. That is, all m first-order data streams are obtained through cascaded interleavering. One specific implementation of cascaded interleavering includes channel permutation and convolutional interleavering. Channel permutation permutes the input g data streams to obtain g permuted data streams, which are then convolved and interleaved to obtain g convolutionally interleaved data streams. Another specific implementation of cascaded interleavering includes channel multiplexing and convolutional interleavering. Channel multiplexing permutes symbolically multiplexes the input g data streams to obtain g1 symbolically multiplexed data streams, where g is divisible by g1. These g1 data streams are then convolved and interleaved to obtain g1 convolutionally interleaved data streams, where g1 is not equal to g. In other words, the number of first data streams and the number of second data streams obtained after the first data processing may be the same or different, depending on the actual application scenario; no limitation is made here. The possible implementations of convolutional interleaving can be understood by referring to step 301.

[0624] In some possible implementations, the first data processing described above may include at least one of the following operations: alignment lock, lane de-skew, and lane reorder.

[0625] In some possible implementations, the first data processing operation described above may also include scrambling. For example, each first data stream is first scrambled before periodically inserting a first identifier. This can improve the synchronization quality when the receiving end performs synchronization.

[0626] 402. Perform second data processing on m second data streams to obtain m third data streams.

[0627] In this embodiment, the second data processing operation includes, but is not limited to, performing a second FEC encoding on each second data stream. This second FEC encoding can be understood as the internal code encoding described above. That is, all m third data streams are obtained after second FEC encoding, where m is an integer greater than 1. Typically, m takes the value 4, 8, 16, 32, or 64. As an example, an internal code encoder is used to perform internal code encoding on every K information bits in each second data stream, that is, after adding S check bits, a total of N bits of internal codeword are obtained, i.e., N = K + S, where K ≥ 1 and S ≥ 1.

[0628] Figure 9 This is a schematic diagram of the structure of the third data stream in an embodiment of this application. For example... Figure 9As shown, each third data stream includes at least one second bit sequence, each second bit sequence includes P+W bits, and the P bits in each second bit sequence are composed of... The first bit is obtained by encoding the second FEC. The W bits in each second bit sequence are the second identifier. The second identifier is obtained by encoding the first identifier by the second FEC. P=N×b, W=N×e.

[0629] It should be noted that the length of the first identifier inserted in step 401 for each first data stream... It is a multiple of the length K of the internal code information. , where integer It is an integer greater than 0. Furthermore, it is periodically acquired in step 401. The bits mentioned The first identifier is encoded using an internal code to obtain a length of... The second identifier. Periodically acquired in step 401. 1 bit and add The first identifier of the bit is obtained + bits, the + The 10 bits are encoded using an internal code to obtain a length of P+W bits, where P In each second data stream, after internal code encoding, there are W bits of second identifier within every P+W bits. Figure 9 by W For example, in some specific implementations, the P+W bits are called a frame, and the W-bit second identifier is called the frame header.

[0630] In some possible implementations, the second data processing operation described above may also include at least one of channel interleaving and scrambling. For example, after each second data stream is encoded by the second FEC, it also undergoes at least one of channel interleaving and scrambling.

[0631] It should be noted that, Figure 9 The second identifier shown is the structure of the data stream after internal code encoding. The data stream after internal code encoding may also undergo other operations, such as channel interleaving to scramble the order. In this case, the second identifier will be scrambled in the data stream after channel interleaving. However, the channel interleaving method is fixed and preset. The receiving end can recover the specific position of the second identifier in the data stream when performing internal code synchronization according to the channel interleaving method.

[0632] 403. Perform third data processing on m third data streams to obtain Y modulated symbol streams.

[0633] In this embodiment, after performing third data processing including modulation on m third data streams, Y modulation symbol streams are obtained, where Y is an integer greater than or equal to 1.

[0634] In some possible implementations, the third data processing operation described above may further include at least one of codeword interleaving and symbol interleaving. For example, each third data stream is first subjected to codeword interleaving before modulation. Another example is that each third data stream is subjected to symbol interleaving after modulation; this symbol interleaving is also called channel interleaving. It can interleave and shuffle colored noise in the channel transmission, resulting in better signal quality recovery at the receiving end.

[0635] It should be noted that in some specific applications, each of the m third data streams The third data stream is first channel-interleaved to obtain a channel-interleaved data stream, totaling... The data stream after channel interleaving. After interleaving the channels, the data stream is modulated to obtain A modulated symbol data stream, in which The channel interleaving will The third data stream acquires a total of one N-bit internal codeword. The internal codeword, the The internal codewords include Each bit is used to obtain two bits from each inner codeword in a round-robin fashion as bits in the second data stream, so as to obtain continuous bits in the channel-interleaved data stream. Each bit. The channel interleaving is also called... - Road Hamming's code intertwined ( -wayHammingcodeword interleaver), also known as internal codeword interleaving.

[0636] Consider each of the above m third data streams The third data stream undergoes channel interleaving followed by modulation, resulting in a total of Striped modulation symbol data stream. Corresponding to the aforementioned... In each of the third data streams in the second data stream Bits, total After internal code encoding and channel interleaving, the total number of bits is obtained. One bit. One bit is called a frame. The first identifier is obtained after interleaving through the coding channel. This bit is called the frame identifier. In some specific implementations, the frame identifier is also called the frame header.

[0637] It should be noted that the above The first identifier of 1 bit may include a synchronization subsequence for receiving frame synchronization, the length of which is less than 1 bit. Each of the m second data streams contains a periodically inserted synchronization subsequence, for a total of m synchronization subsequences. In some specific applications, the length of the m synchronization subsequences is the same. Bits. Each of the m synchronization subsequences Each synchronization subsequence is encoded using internal codes and interleaved via channel ( -Inter-channel codeword interleaving) to obtain the data stream after channel interleaving. One bit. These bits can be called a frame synchronization sequence, or simply a synchronization sequence. Data stream after channel interleaving, corresponding A synchronization sequence. It should be noted that, in some specific embodiments, the... The specific bit patterns of each synchronization subsequence are not exactly the same, but The specific bit pattern of each synchronization sequence is the same.

[0638] It should be noted that in some other specific applications, each of the m second data streams contains a periodically inserted synchronization subsequence, for a total of m synchronization subsequences, and the lengths of the m synchronization subsequences are not all the same.

[0639] It should be noted that in some specific applications, in order to further improve the overall burst resistance of the concatenated code, the period is inserted... Before the first identifier of each bit, a cyclic shift operation is performed on the data in the data stream. The cyclic shift operation shifts each K information bits in the data stream either to the left or to the right.

[0640] It should be noted that this application selects positive integers. and This allows the baud rate of the modulated symbol data stream to be an integer multiple of the reference clock frequency, simplifying clock extraction and synchronization at the receiver, enabling fast phase locking, and resulting in low PLL complexity and low jitter. It should be understood that this application does not limit the specific value of the reference clock frequency; for example, it could be the Ethernet common reference clock. As an example, the baud rate of the modulated symbol data stream is an integer multiple of 156.25 MHz. It should also be understood that a certain error range is acceptable in practical applications; for example, the baud rate of the modulated symbol data stream can be ±V (ppm) of an integer multiple of 156.25 MHz, where V can be 20, 50, or 100.

[0641] Further select positive integers All values ​​are divisible by the length K of the internal code information, enabling the receiving end processing module to perform frame synchronization of received data (i.e., frame synchronization of P+W bits or...). Frame synchronization (also known as identifier locking operation) and codeword synchronization (using 1 bit of data) have low hardware implementation complexity. Furthermore, selecting a positive integer... This allows the synchronization of internal codewords to guarantee the synchronization of concatenated deinterleaving. In other words, the data processing method provided in this application reduces the complexity of frame synchronization, internal codeword synchronization, and concatenated deinterleaving synchronization in the receiving end processing module.

[0642] It should be noted that the above-mentioned receiving end performs codeword synchronization first and then frame synchronization. Alternatively, it can directly use the first or second identifier to perform bit-by-bit frame synchronization, which can guarantee the synchronization of codeword synchronization and concatenated deinterleaving. Specific limitations are not specified here.

[0643] The following is about The requirements for the values ​​are explained in detail.

[0644] Considering an 800GbE scenario, the transmitting device encodes the 800GbE service data stream to be transmitted using KP4 RS(544,514) external code, obtaining a data stream with a total rate of 850Gbps. After PMA processing, this data stream is sent to the transmitting processing module via the 800GAUI interface. The transmitting processing module periodically inserts the first identifier into each of the m first data streams, i.e., after processing the first data stream, it obtains m second data streams with a total rate of... After processing the m second data streams with internal code encoding, m third data streams are obtained, with a total rate of... After the third data stream undergoes third data processing including PAM4 modulation, four modulation symbol streams are obtained, with a baud rate of [value missing]. ,here This represents the rate of modulation symbols transmitted per second. Assume the reference clock frequency is... MHz, the baud rate value of the PAM4 modulated symbol stream is an integer multiple of the typical Ethernet reference clock frequency, and has Where N is the code length of the internal code, K is the information bit length of the internal code, and a is a positive integer. G represents... M represents At this point, clock extraction and synchronization at the receiving end are simple to implement, enabling fast phase locking, low PLL complexity, and minimal jitter. A typical Ethernet reference clock frequency is 156.25MHz. In some 800GbE scenarios, considering a baud rate of 112.5G, there are... At this point, the overall PLL implementation is simpler.

[0645] Furthermore, when It is a multiple of the length K of the internal code information and When it is a multiple of the length K of the internal code information, that is... , Where b and e are positive integers, in the data stream after the second FEC encoding of the second data stream, W bits at fixed positions in every P+W bits are the second identifier, which corresponds to The first identifier of the bits, where P , Furthermore, each N bits in these P+W bits constitutes an internal codeword. In some specific embodiments, the P+W bits are called a frame, and the W-bit second identifier is called a frame header. The receiving end can first perform internal codeword synchronization on the received data stream to identify the internal codeword boundaries. Combining the fixed position of the first bit of the first identifier or the second identifier in the internal codeword, simple frame synchronization can be performed using the aforementioned first identifier or the second identifier to identify the first identifier or the second identifier. When the receiving end processing module performs frame synchronization on the received data (i.e., frame synchronization of P+W bits, also known as identifier locking operation), it does not need to perform complex bit-by-bit position identification.

[0646] It should be noted that, considering each of the above m third data streams... The third data stream undergoes channel interleaving followed by modulation, resulting in a total of A stream of modulated symbols. At this point, each data stream after channel interleaving... Fixed position in bits Each bit is a frame synchronization sequence, and its corresponding Bit The first identifier.

[0647] Furthermore, the transmitting processing module employs concatenated interleaving including convolutional interleaving. To ensure synchronization of convolutional deinterleaving during frame synchronization, the receiving processing module should satisfy the requirement that each frame (W+P bits or...) The starting position of the frame synchronization (each bit) corresponds to the input and output switches of the convolutional deinterleaver being located at the beginning of the switch position, typically at the topmost positions, such as the position of delay line 0 shown in Figures 4(a) and 4(b). More specifically, the convolutional interleaver and convolutional deinterleaver output each bit... With 1 bit, its input / output switch positions are located at the top, and K×b is divisible by f, ensuring convolutional deinterleaving synchronization during frame synchronization. One specific method is as follows: r d c= Where r is the number of delay lines in the convolutional interleaver and convolutional deinterleaver, d is the number of bits stored in the storage cells of the convolutional interleaver and convolutional deinterleaver, and c is a positive integer. Thus, based on the improvements to the transmitting end processing module in this application, the receiving end processing module can achieve frame synchronization and codeword synchronization with lower complexity. Simultaneously, frame synchronization of received data ensures convolutional deinterleaving synchronization, simplifying operations such as receiving end frame synchronization, internal codeword synchronization, and concatenated interleaving synchronization, resulting in lower implementation complexity.

[0648] It should be noted that in this embodiment, during data processing, the data stream is first periodically inserted. The first bit identifier is followed by internal code encoding; in the first embodiment of this application, the data stream is first internally encoded, and then the internally encoded data stream is periodically inserted with W bits of alignment identifier. The second embodiment describes... The first identifier of the bit is encoded into an internal code to obtain the second identifier of W bits. When the second identifier is the same as the alignment identifier of W bits in the first embodiment, the two embodiments achieve the same effect, that is, the two embodiments are equivalent at this time.

[0649] The following provides several implementation methods based on different internal code encoding schemes to illustrate the above. and Possible values ​​for .

[0650] Implementation method 1: The internal code encoding adopts FEC code with information length K=140 bits and codeword length N=148 bits.

[0651] Consider using FEC codes with an information length of K=140 bits and a codeword length of N=148 bits for the internal code, such as Hamming(148,140).

[0652] Figure 10 This is a schematic diagram illustrating one implementation of the internal code encoding in this application. For example, using... Figure 10 The encoding method shown represents the 140 bits of data to be encoded as B[139:0]. Each consecutive two bits are XORed to obtain 1 bit of data C[i], resulting in a total of 70 bits, represented as C[69:0]. Where C[i] = B[2... i]^B[2 i+1], Then, C[69:0] is used as information data and Hamming(78,70) is used to encode 8 bits of check data, represented as P[7:0]. Finally, B[139:0] and P[7:0], a total of 148 bits, are concatenated to form the output of the internal code, represented as D[147:0]. D[139:0] comes from B[139:0], and D[147:140] comes from P[7:0].

[0653] Considering the 800GbE scenario, the baud rate of the PAM4 modulated symbol stream is... Assuming the above baud rate values... It is an integer multiple of the typical Ethernet reference clock frequency of 156.25MHz, i.e. Where a is a positive integer, and G represents M represents .have The value is an integer. The implementation of clock extraction and clock synchronization at the receiving end is simple, and it can perform fast phase locking. The PLL has low complexity and low jitter.

[0654] when and It is a multiple of the length K of the internal code information, that is... , The frame synchronization and internal code codeword synchronization operations performed at the receiving end have relatively low complexity. At this time, there are... , positive integer Divisible by a positive integer b, and the positive integer b It is divisible by 7. Table 11 below gives some parameter combinations and their corresponding baud rates.

[0655] Table 11

[0656]

[0657] Parameter combinations in Table X1 , , b, and e can also be used in 1.6TbE scenarios; for 1.6TbE using PAM4 modulation, the corresponding parameter 'a' and the corresponding baud rate are twice that of 800GbE. In some 800GbE scenarios using PAM4 modulation and a baud rate of 112.5G, or in 1.6TbE scenarios considering a baud rate of 225G, ,have .

[0658] The aforementioned inner code information has a length of K=140 bits, and one RS symbol of the outer code KP4 contains 10 bits. For the convolutional interleaver between the inner and outer codes, there exists a convolutional interleaver where the input / output switches are located at the top for every 140 bits of output. For example, the convolutional interleaver has 7 delay lines (r=7) and each storage unit stores d=20 bits. In this case, the receiving end processing module can achieve frame synchronization and codeword synchronization with lower complexity. Simultaneously, frame synchronization of the received data ensures convolutional deinterleaving synchronization, i.e., obtaining the positions of the input and output switches for convolutional deinterleaving, simplifying operations such as receiving end frame synchronization, inner codeword synchronization, and concatenated interleaving synchronization, resulting in lower implementation complexity.

[0659] Implementation method 2: The internal code encoding adopts FEC code with information length K=120 bits and codeword length N=127 bits.

[0660] Consider using FEC codes with an information length of K=120 bits and a codeword length of N=127 bits for the internal code, such as Hamming(127,120).

[0661] Figure 11 This is a schematic diagram illustrating another implementation of the internal code encoding in the embodiments of this application. For example, using... Figure 11 The encoding method shown uses 120 bits of data to be encoded, represented as B[119:0]. Each consecutive two bits are XORed to obtain 1 bit of data C[i], resulting in a total of 60 bits, represented as C[59:0]. Where C[i] = B[2... i]^B[2 i+1], Then, C[59:0] is used as information data and Hamming(67,60) is performed to obtain 7 bits of check data, represented as P[6:0]. Finally, B[119:0] and P[6:0], a total of 127 bits, are concatenated to form the output of the internal code, represented as D[126:0]. Among them, D[119:0] comes from B[119:0], and D[126:120] comes from P[6:0].

[0662] Considering the 800GbE scenario, the baud rate of the PAM4 modulated symbol stream is... Assuming the above baud rate values... It is an integer multiple of the typical Ethernet reference clock frequency of 156.25MHz, i.e. Where a is a positive integer, and G represents M represents .have The value is an integer. The implementation of clock extraction and clock synchronization at the receiving end is simple, and it can perform fast phase locking. The PLL has low complexity and low jitter.

[0663] when and It is a multiple of the length K of the internal code information, that is... , The frame synchronization and internal code codeword synchronization operations performed at the receiving end have relatively low complexity. At this time, there are... , positive integer Divisible by a positive integer b, and the positive integer b It is divisible by 3. Table 12 below gives some parameter combinations and their corresponding baud rates.

[0664] Table 12

[0665]

[0666] In some 800GbE scenarios using PAM4 modulation and a baud rate of 112.5G, or in 1.6TbE scenarios considering a baud rate of 225G, ,have At this point, the overall PLL implementation is simpler.

[0667] The aforementioned internal code information has a length of K=120 bits, and one RS symbol of the external code KP4 contains 10 bits. For the convolutional interleaver between the internal and external codes, there exists a type where the input / output switches are located at the top for every 120 bits of output. For example, the convolutional interleaver has 3 delay lines (r=3) and each storage unit stores d=40 bits; or, the convolutional interleaver has 6 delay lines (r=6) and each storage unit stores d=20 bits. In this case, the receiving end processing module can achieve frame synchronization and codeword synchronization with lower complexity. Simultaneously, frame synchronization of the received data ensures convolutional deinterleaving synchronization, i.e., obtaining the positions of the input and output switches for convolutional deinterleaving, simplifying operations such as receiving end frame synchronization, internal codeword synchronization, and concatenated interleaving synchronization, resulting in lower implementation complexity.

[0668] It should be noted that when PAM4 modulation is used, each PAM4 symbol corresponds to 2 bits, where the bit error rates of the MSB (Most Significant Bit) and LSB (Least Significant Bit) are different. When the codeword bit length N is odd (such as the 127-bit FEC used in Implementation 2), it will cause two consecutive inner codewords to be... Figure 12 This is a schematic diagram of the structure of a code character. For example... Figure 12 As shown, the first bit of the K-bit information sequence (also referred to as information bits) of one codeword is MSB, while the first bit of the K-bit information sequence of the other codeword is LSB, which is not conducive to the hardware implementation of internal code decoding at the receiving end.

[0669] To overcome the above problems, in some possible application scenarios, the t internal codewords after internal code encoding can be interleaved, where t is an even number, such as 2, 4, 8, or 16. The internal codeword interleaving process is described in detail below.

[0670] Figure 13 This is a schematic diagram of another type of codeword structure. For example... Figure 13 As shown, consider t internal codewords. … Among them, code words K-bit information sequence and a check sequence of length S bits More specifically, there are t information sequences. … t check sequences are … The interleaving process of the inner codewords will total [number] t inner codewords. Bit interleaving yields a length of The interleaved sequence of bits, wherein the interleaved sequence comprises two consecutive subsequences of length [number missing]. The first subsequence of bits and its length is The second subsequence of bits. The first subsequence of consecutive bits contains the t information sequences. … The second subsequence, consisting of consecutive bits, contains the t check sequences. … For reference. Figure 13 This needs to be understood. The above codeword interleaving is also a specific implementation scheme of channel interleaving.

[0671] It should be noted that the above will The length of the bit is t. The information sequence is … Encode the internal code to obtain t internal codewords of bits ,…, Then, the codewords are interleaved to obtain the inner code. Bit interleaved sequence ,…, , ,…, In some possible scenarios, the above internal code (N,K) encoding and t internal codewords are interleaved and combined to form the internal code (N,K). , (N,K) encoding. Those skilled in the art can distinguish between the (N,K) encoding and the (N,K) encoding based on the context. , The encoding will not be elaborated here.

[0672] It should be noted that the above t codewords undergo internal codeword interleaving ,…, It is in the same second data stream It can be obtained through internal code encoding; it can also be obtained from multiple second data streams through internal code encoding, for example, t / 2 internal codewords come from one second data stream. The codewords are obtained through internal encoding. The additional t / 2 internal codewords come from another second data stream. The specific implementation method, obtained through internal encoding, is known to those skilled in the art and will not be elaborated here.

[0673] Implementation method 3: The internal code encoding adopts FEC code with information length K=120 bits and codeword length N=128 bits.

[0674] Consider using FEC codes with an information length of K = 120 bits and a codeword length of N = 128 bits, such as Hamming (128, 120) codes. For example, the 120 bits of data to be encoded are represented as B[119:0]. Performing a bitwise XOR operation on every two consecutive bits yields 1 bit of data C[i], resulting in a total of 60 bits, represented as C[59:0]. Where C[i] = B[2... i]^B[2 i+1], Then, C[59:0] is used as information data and Hamming(68,60) is performed to obtain 8 bits of check data, represented as P[7:0]. Finally, B[119:0] and P[7:0], a total of 128 bits, are concatenated to form the output of the internal code, represented as D[127:0]. Among them, D[119:0] comes from B[119:0], and D[127:120] comes from P[7:0].

[0675] Considering an 800GE scenario and using PAM4 modulation, data processing yields four PAM modulated symbol streams. (Ignoring the periodic insertion...) With the first identifier of a bit length, the baud rate of the PAM4 modulation symbol stream is [value missing]. Its baud rate is approximately 725.3333 times the reference clock frequency of 156.25 MHz. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering the... Bit insertion The baud rate of the PAM4 modulated symbol stream with a first identifier of 1 bit length is 113.4375. Its baud rate is 726 times that of the reference clock frequency of 156.25 MHz.

[0676] Considering the 800GbE scenario, the baud rate of the PAM4 modulation symbol stream is ,have ,at this time .consider and Since the internal code information length K is an integer multiple of K, the frame synchronization and internal code codeword synchronization operations at the receiving end have low complexity. Typically, , .

[0677] Figure 23 This is a schematic diagram illustrating another implementation of data processing in the embodiments of this application. (In conjunction with...) Figure 23 The specific data processing flow is described below:

[0678] By periodically inserting a first identifier into each of the m=32 data streams encoded by the first FEC, a total of m=32 second data streams are obtained. Specifically, from each of the data streams, periodically... 1 bit, and insert 1 bit The first identifier, with a length of 1 bit, makes each bit in the second data stream... + There are bits in The first identifier is one bit long.

[0679] Each of the m=32 second data streams is encoded using internal code to obtain m=32 third data streams. Specifically, each K=120 information bits in each of the second data streams is encoded using internal code, i.e., S=8 parity bits are added to obtain a total of N=128 bits of internal codeword.

[0680] For each of the 3rd data streams with m=32 lines The third data stream undergoes third data processing including PAM4 modulation to obtain the total The 32 modulated symbol streams are further divided into four channels. More specifically, every eight third data streams out of the original 32 streams are first channel-interleaved to obtain one channel-interleaved data stream, resulting in a total of four channel-interleaved data streams. (See reference...) Figure 23 For the 800GE scenario, data processing includes four data sub-processing steps, namely... Figure 23 The dataset consists of data subprocessing 0, data subprocessing 1, data subprocessing 2, and data subprocessing 3. Each data subprocessing includes one channel interleaving. The channel interleaving extracts one 128-bit internal codeword from each of the eight input third data streams, for a total of eight internal codewords. It then round-robin-processes two bits from each internal codeword to be used as bits in the channel-interleaved data stream, resulting in 1024 consecutive bits in the channel-interleaved data stream. This channel interleaving is also called 8-way Hamming codeword interleaving, or internal codeword interleaving. Then, PAM4 modulation is applied to the four channel-interleaved data streams to obtain Y=4 modulation symbol streams.

[0681] Figure 24 This is a schematic diagram of one structure of the first identifier in an embodiment of this application. This embodiment uses... , For example, regarding the periodic insertion The specific structure of the first identifier, which is 120 bits in length, will be described below. Figure 24 As shown, for each of the m=32 data streams encoded by the first FEC, periodic insertion is performed. The first identifier of the bits yields a total of m=32 second data streams. The first identifier of a bit contains the bit length. The synchronization subsequence. The synchronization subsequence contained in the 8 first identifiers of the 8 second data streams corresponding to each data subprocess, i.e. Figure 24 Synchronization subsequences 0, 1, ..., 7, combined together, total One bit can be used for frame synchronization at the receiving end.

[0682] In some specific applications, the The synchronization subsequence of bits is located in the second data stream. The first consecutive bits in the first bit identifier Each bit position. For example... Figure 24 As shown, this embodiment uses The following is an example. The specific bit patterns of the eight synchronization sub-sequences are shown in Table 14.

[0683] Table 14

[0684]

[0685] Figure 25 This is a schematic diagram of a synchronization sequence after channel interleaving in an embodiment of this application. It should be noted that the specific bit patterns of the eight synchronization sub-sequences are not entirely identical. (Refer to...) Figure 25 The eight synchronization sub-sequences total After internal code encoding and codeword interleaving, each bit is a consecutive 48 bits in the corresponding channel-interleaved data stream, with the specific bit pattern 010110010101001001100100101001101010110110011011 (transmitted from left to right). These 48 bits can be used for frame synchronization at the receiving end, also known as the frame synchronization sequence, or simply the synchronization sequence. Here, the leftmost bit in the bit pattern is sent first in actual transmission. The synchronization sequence of the consecutive 48 bits in the corresponding channel-interleaved data stream can be represented in hexadecimal as 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9 (where the 8 bits within a byte have their LSB transmitted first). It should be noted that although the specific bit patterns of the eight synchronization sub-sequences are not exactly the same, the specific bit patterns of the four synchronization sequences corresponding to the data streams after the four channels are interleaved are the same, namely 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

[0686] Implementation Method 4:

[0687] Figure 26 This is another structural diagram of the first identifier in an embodiment of this application. Based on embodiment 3, each data stream in the m=32 data streams encoded by the first FEC is periodically inserted. The first identifier of the bit yields a total of m=32 second data streams. The lengths of the synchronization subsequences contained in the periodically inserted first identifiers in the m=32 second data streams are not exactly equal. Figure 26 The specific structure of the eight synchronization subsequences in each data subprocess is given.

[0688] The specific bit patterns of the eight synchronization subsequences are shown in Table 15. The lengths of the eight synchronization subsequences are not all the same. Among them, the bit lengths of synchronization subsequences 0, 1, 2, and 3 are 8, and the bit lengths of synchronization subsequences 4, 5, 6, and 7 are 4.

[0689] Table 15

[0690]

[0691] Figure 27This is a schematic diagram of another structure of the synchronization sequence after channel interleaving in an embodiment of this application. (Refer to...) Figure 27 The eight synchronization sub-sequences total After internal code encoding and codeword interleaving, each bit corresponds to 48 bits in the interleaved data stream. These 48 bits are used for frame synchronization at the receiving end, also known as the frame synchronization sequence, or simply the synchronization sequence. This 48-bit synchronization sequence is not entirely continuous in the interleaved data stream; it consists of two parts: a first part containing 24 bits and a second part containing 24 bits. The first and second parts are separated by an 8-bit interval (one byte). Here, a 0-bit interval is defined as the interval between two consecutive bits.

[0692] In some specific applications, the first part of the 24-bit bit sequence is specifically 0101100101010010 01100100 (transmitted from left to right), and the second part of the 24-bit bit sequence is specifically 10100110 10101101 10011011 (transmitted from left to right). Here, the leftmost bit in the bit pattern is sent first in actual transmission. The first and second part bit sequences can be represented in hexadecimal. The first part bit sequence is 0x9A, 0x4A, 0x26, and the second part bit sequence is 0x65, 0xB5, 0xD9. It should be noted that the specific bit patterns of the four synchronization sequences corresponding to the data streams after the four channels are interleaved are the same, all being 0x9A, 0x4A, 0x26, 0x65, 0xB5, 0xD9.

[0693] It should be noted that in the 48-bit synchronization sequence, the first part of the bit sequence contains 24 bits, the second part of the bit sequence contains 24 bits, and the first part of the bit sequence and the second part of the bit sequence are separated by 8 bits (one byte). (Reference) Figure 16 It can be seen that the data processing method of this embodiment can reuse the synchronization hardware implementation architecture in the existing 100GE 802.3bj and 400GE 802.3bs standards for the related computer architecture used for receiver synchronization, which is convenient to implement.

[0694] Implementation Method 5:

[0695] Figure 28 This is a schematic diagram illustrating another implementation of data processing in this application. Based on implementation 3, considering a 1.6TE scenario and using PAM4 modulation, data processing yields 8 PAM modulated symbol streams. Without considering the periodic insertion... With the first identifier of a bit length, the baud rate of the PAM4 modulation symbol stream is [value missing]. Its baud rate is approximately 725.3333 times the reference clock frequency of 156.25MHz. Considering that 725.3333 is not an integer, the smallest positive integer greater than 725.3333 is 726. Therefore, considering the periodic insertion... The baud rate of the PAM4 modulated symbol stream with a first identifier of 1 bit length is 113.4375. Its baud rate is 726 times that of the reference clock frequency of 156.25 MHz.

[0696] Considering the 1.6TE scenario, the baud rate of the PAM4 modulated symbol stream is... ,have ,at this time .consider and Since the internal code information length K is an integer multiple of K, the frame synchronization and internal code codeword synchronization operations at the receiving end have low complexity. Typically, , For detailed data processing procedures, please refer to [link / reference]. Figure 28 To understand this, the data processing includes eight data sub-processes, namely data sub-processes 0-7. The specific operation of each data sub-process can be understood by referring to Implementation Method 3.

[0697] Implementation method 6:

[0698] Figure 29 This is another structural schematic diagram of the first identifier in an embodiment of this application. Based on embodiment 3, each data stream in m=32 data streams encoded by the first FEC is periodically inserted. The first identifier of the bits yields a total of m=32 second data streams. For example... Figure 29 As shown, each of the second data streams The first identifier of a bit contains the bit length. The synchronization subsequence. In the 8 second data streams corresponding to each data subprocessing. The first identifier of a bit contains the bit length. The synchronization subsequence, i.e. Figure 29 The synchronization subsequences are 0, 1, ..., 7. The specific bit patterns of these eight synchronization subsequences are identical. It should be noted that, based on implementation method 6, channel interleaving is not necessarily required during data processing; that is, implementation method 6 is decoupled from channel interleaving.

[0699] More specifically, the bit length of each of the synchronization subsequences is 1. The bits are not arranged consecutively in the first identifier. Each synchronization subsequence comprises two bit sequences: a first bit sequence containing 24 bits and a second bit sequence containing 24 bits, spaced 8 bits apart. Here, the interval between two consecutive bits is defined as 0 bits.

[0700] In some specific applications, the first part of the 24-bit bit sequence has the following values: 0x9A, 0x4A, 0x26, and the second part of the 24-bit bit sequence has the following values: 0x65, 0xB5, 0xD9.

[0701] In some specific applications, using the specific data processing scheme of this invention, the receiving end can perform frame synchronization based on the eight synchronization sub-sequences totaling 384 bits, that is, the receiving end performs frame synchronization based on a received data stream at a rate of approximately 200G. In other specific applications, the receiving end can first de-interleave the received data stream at a rate of approximately 200G according to the channel interleaving rules to obtain eight channel de-interleaved data streams, each with a rate of approximately 25G, and then synchronize each channel de-interleaved data stream according to the known synchronization sub-sequences. It should be noted that when the receiving end adopts the above-mentioned synchronization scheme based on a rate of 25G, the eight channel de-interleaved data streams are not completely aligned. The order of the channel de-interleaved data streams among the eight channel de-interleaved data streams can be determined based on the position of the synchronization sub-sequence obtained after the synchronization of each channel de-interleaved data stream, so as to achieve correct recovery of the data stream order and synchronization alignment.

[0702] Implementation Method 7:

[0703] Figure 30 This is a schematic diagram illustrating another implementation of data processing in this application. Based on implementation 3, the periodic insertion... Before the first bit identifier, a cyclic shift operation was performed on the data in the data stream. For example... Figure 30 As shown, the cyclic shift operation shifts each K=120 bits to the right in a cyclic shift to improve the overall burst resistance of the concatenated code.

[0704] Implementation Method 8:

[0705] Figure 31 This is a schematic diagram illustrating another implementation of data processing in this application. Based on implementation 3, the periodic insertion... Before the first identifier of each bit, convolutional interleaving operations were performed on the data in the data stream. For example... Figure 31As shown, for every 8 first data streams out of the 32 first data streams, they are first convolved and interleaved to obtain 8 convolved and interleaved data streams. Then, a cyclic shift of 120 bits per K is performed, followed by periodic insertion of the first identifier to obtain 8 second data streams. Next, internal code encoding is performed to obtain 8 third data streams, and then channel interleaving (internal codeword interleaving) is performed to obtain 1 channel-interleaved data stream. Convolved interleaving is performed before internal code encoding, which improves the performance of the overall concatenated code under AWGN.

[0706] Implementation Method 9:

[0707] Figure 32 This is a schematic diagram illustrating another implementation of data processing in this application. Based on implementation 8, in each data sub-processing step, the two input data streams undergo convolutional interleaving to obtain two convolutionally interleaved data streams. Each convolutionally interleaved data stream is then distributed to obtain four distributed first data streams, resulting in a total of eight distributed first data streams. The data distribution is based on... Bits represent granularity. For example... Figure 32 As shown, the data stream after convolutional interleaving is composed of... When bits are grouped together, for a total of 4 consecutive groups bits, group 0 Bits are sent to the 0th data stream and the 1st group of the 4 distributed data streams. Bits are sent to the first data stream of the first data stream after the four distributed data streams, the second group. Bits are sent to the second data stream and the third group of the first data stream after the four distributed data streams. The bits are fed into the third data stream of the first data stream after the four distributions. Typically, the granularity of the distributed bits is... .

[0708] It should be noted that for the 800GE scenario, data processing includes four data sub-processing steps, such as... Figure 32 As shown, each data subprocess corresponds to two input data streams. These two input data streams correspond to a rate of approximately 200 Gbps, or approximately 100 Gbps per input data stream. Correspondingly, the first distributed data stream corresponds to a rate of approximately 25 Gbps.

[0709] It should also be noted that for bit distribution granularity of... At times, such as Figure 32The data processing described can be summarized as follows: two input data streams are convolutionally interleaved to obtain a total of two convolutionally interleaved data streams. Each convolutionally interleaved data stream acquires four bit packets, each 120 bits in length. Each bit packet undergoes cyclic shifting and internal code encoding to obtain four internal codewords. The two convolutionally interleaved data streams acquire a total of eight bit packets, which are then cyclically shifted and encoded to obtain eight internal codewords. Finally, channel interleaving is performed to obtain 1024 bits in the channel-interleaved data stream.

[0710] It should be noted that, for the 1.6TE scenario, data processing includes eight data sub-processes, each corresponding to two input data streams. These two input data streams correspond to a rate of approximately 200 Gbps, or approximately 100 Gbps per input data stream. Correspondingly, the first distributed data stream corresponds to a rate of approximately 25 Gbps.

[0711] Implementation Method 10:

[0712] Figure 33 This is a schematic diagram illustrating another implementation of data processing in this application. Based on implementation 8, the data processing includes four input data streams, with each data sub-process containing one input data stream. Each input data stream undergoes convolutional interleaving to obtain one convolutionally interleaved data stream. This one convolutionally interleaved data stream is then distributed to obtain eight distributed first data streams. The data distribution is based on... Bits represent granularity. For example... Figure 33 As shown, in the first data stream after convolutional interleaving, ... When bits are grouped together, for a total of 8 consecutive groups bits, group 0 Bits are sent to the 0th data stream and the 1st group of the 8 distributed data streams. Bits are sent to the first data stream of the first data stream after the eight distributed data streams, ..., the seventh group. The bits are fed into the 7th data stream of the first data stream after the 8 distributed bits. Typically, the granularity of the distributed bits is... .

[0713] It should be noted that for the 800GE scenario, data processing includes four data sub-processing steps, such as... Figure 33 As shown. Each data subprocessing receives one data stream as input, corresponding to a rate of approximately 200 Gbps. Correspondingly, the first distributed data stream corresponds to a rate of approximately 25 Gbps.

[0714] It should be noted that, for the 1.6TE scenario, the data processing includes 8 data sub-processes, each of which receives one data stream as input, corresponding to a rate of approximately 200 Gbps. Correspondingly, the first distributed data stream corresponds to a rate of approximately 25 Gbps.

[0715] It should be noted that, as Figure 32 The input data stream shown is distributed into four first data streams after convolutional interleaving, as follows: Figure 33 The input data stream shown is distributed into 8 first data streams after convolutional interleaving, which can all be understood as each first data stream undergoing convolutional interleaving.

[0716] It should be noted that in embodiments 3 to 10, each of the eight second data streams includes periodically inserted... The first bit identifier, the total length is Bit. The... A portion of the bits are used for receiver frame synchronization, serving as the aforementioned frame synchronization sequence. The remaining bits can be used to transmit link information and / or control information, including receiver status, FEC status, etc., also known as the status field. Specifically, to improve the accuracy of the transmitted link information and / or control information, the... Of the bits remaining after removing the aforementioned frame synchronization sequence, One bit is used for the type of the indicated link information and / or control information. Each bit is used to represent the specific content of the indicated link information and / or control information. 10 bits are used for Cyclic Redundancy Check (CRC). Typically, , The value can be 8, 16, or 32. In some specific applications, multiple frames are needed to collaboratively transmit the indicated link information and / or control information to further improve the accuracy of the transmitted information. In this case, the... Bit One bit is used to refer to the multiple frames, These bits are also called multi-frame synchronization signals. Typically, .

[0717] In some specific applications, such as Figure 26The frame synchronization sequence comprises 8 synchronization sub-sequences, totaling 48 bits, distributed across 8 second data streams. Four of these second data streams each contain 8 bits of the frame synchronization sequence (i.e., synchronization sub-sequences 0-3), while the other four contain 4 bits of the frame synchronization sequence (i.e., synchronization sub-sequences 4-7). The 4 bits of each synchronization sub-sequence 4-7 are located within the... The positions of bits 0, 1, 4, and 5 in the first identifier (i.e., first identifier 4, first identifier 5, first identifier 6, and first identifier 7) can be understood with reference to Table 15. A total of 16 bits are allocated to positions 2, 3, 6, and 7 in the first identifiers 4, 5, 6, and 7. Eight of these positions are used for the 8 bits required for the CRC8 check, or eight of these positions are used for the 8 bits required for the type of the indicated link information and / or control information, or eight of these positions are used for the 8 bits required for the multi-frame synchronization signal.

[0718] It should be noted that, based on the above Figure 7 The data processing method shown for the transmitting end includes the following steps for the corresponding data processing method for the receiving end. First, the received Y modulated symbol streams are processed to obtain m fourth data streams. For information on the characteristics and generation methods of the modulated symbol streams, please refer to the above. Figure 7 The relevant descriptions of the illustrated embodiments will not be repeated here. After performing a fourth data processing, including demodulation, on the Y modulated symbol streams, m fourth data streams are obtained. The fourth data processing performed by the receiver is the inverse operation of the third data processing performed by the transmitter. Furthermore, frame synchronization is performed on each fourth data stream. It should be understood that the receiver performs identifier locking based on the identifier added by the transmitter to the data stream to determine the boundary of each frame (P+W bits) in the fourth data stream, thereby achieving codeword synchronization and / or frame synchronization.

[0719] It should be understood that after the receiving end completes codeword synchronization and / or frame synchronization, it will also perform fifth data processing on m fourth data streams. The fifth data processing can be understood as the inverse operation of the second data processing performed by the sending end. For example, the fifth data processing includes, but is not limited to, internal code decoding and concatenated deinterleaving. Concatenated deinterleaving includes convolutional deinterleaving, which will not be elaborated here.

[0720] The data processing apparatus provided in the embodiments of this application is described below.

[0721] Figure 34 This is a schematic diagram of a data processing device applied to the sending end in an embodiment of this application. For example... Figure 34As shown, the data processing device includes a first data processing unit 701, a second data processing unit 702, and a third data processing unit 703. The first data processing unit 701 is used to perform the above-described... Figure 3 The operation of step 301 in the illustrated embodiment or the above Figure 7 The operation of step 401 in the illustrated embodiment. The second data processing unit 702 is used to perform the above. Figure 3 The operation of step 302 in the illustrated embodiment or the above Figure 7 The operation of step 402 in the illustrated embodiment. The third data processing unit 703 is used to perform the above. Figure 3 The operation of step 303 in the illustrated embodiment or the above Figure 7 The operation of step 403 in the illustrated embodiment can be referred to the above for specific operation. Figure 3 and Figure 7 The relevant descriptions of the embodiments shown will not be repeated here.

[0722] Figure 35 This is a schematic diagram of a data processing device applied at the receiving end in an embodiment of this application. Figure 35 As shown, the data processing device includes a data processing unit 801 and a synchronization unit 802. The data processing unit 801 is used to perform the above-described... Figure 6 The operation of step 601 in the illustrated embodiment. Synchronization unit 802 is used to perform the above... Figure 6 The operation of step 602 in the illustrated embodiment can be referred to the above for specific operation. Figure 6 The relevant descriptions of the embodiments shown will not be repeated here.

[0723] It should be understood that the apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0724] Figure 36 This is a schematic diagram of another structure of the data processing device in an embodiment of this application. For example... Figure 36As shown, the data processing device includes a processor 901, a memory 902, and a transceiver 903. The processor 901, memory 902, and transceiver 903 are interconnected via lines. The memory 902 stores program instructions and data. Specifically, the processor 901 performs data processing operations, and the transceiver 903 performs data transmission and reception operations. In one possible implementation, the processor 901 may include the aforementioned... Figure 34 The first data processing unit 701, the second data processing unit 702, and the third data processing unit 703 are shown. In another possible embodiment, the processor 901 may include the above-described... Figure 35 The data processing unit 801 and the synchronization unit 802 are shown.

[0725] It should be noted that the above Figure 36 The processor shown can be a general-purpose central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Figure 36 The memory shown can store the operating system and other applications. When the technical solutions provided in the embodiments of this application are implemented by software or firmware, the program code used to implement the technical solutions provided in the embodiments of this application is stored in the memory and executed by the processor. In one embodiment, the processor may include memory internally. In another embodiment, the processor and the memory are two independent structures.

[0726] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0727] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory or random access memory. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0728] When implemented using software, the method steps described in the above embodiments can be implemented, in whole or in part, in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

Claims

1. A data processing method, characterized in that, include: A first data stream encoded by a first forward error correction (FEC) is processed to obtain a second data stream, the second data stream comprising at least one first bit sequence, each of the first bit sequences comprising: Each of the first bit sequences contains bits, and each bit in the first bit sequence contains bits. Each bit in the first bit sequence comes from the first data stream. Each bit is a first identifier added during the first data processing; The second data stream is subjected to a second data processing step to obtain a third data stream. This second data processing step includes a second FEC encoding. Each codeword after the second FEC encoding comprises N bits, where N = K + S, K represents the number of information bits, S represents the number of parity bits, and K and S are both integers greater than or equal to 1. =K×b, Where b is an integer greater than 1, and e is an integer greater than or equal to 1; The third data stream is processed to obtain Y modulated symbol streams, where Y is an integer greater than or equal to 1. Each modulated symbol stream is modulated, and the baud rate of each modulated symbol stream is an integer multiple of 156.25M.

2. The method according to claim 1, characterized in that, The third data stream includes at least one second bit sequence, each second bit sequence comprising P+W bits, wherein the P bits in each second bit sequence are composed of... The first bit is obtained by encoding the second FEC. The W bits in each second bit sequence are the second identifier. The second identifier is obtained by encoding the first identifier by the second FEC. P=N×b, W=N×e.

3. The method according to claim 1 or 2, characterized in that, ， 。 4. The method according to claim 1 or 2, characterized in that, The first data processing step of obtaining the second data stream from the first data stream encoded by the first FEC includes: The first data streams encoded by FEC are processed to obtain m second data streams, where m is an integer greater than 1, and each second data stream includes at least one of the first bit sequences; The process of performing a second data processing on the second data stream to obtain a third data stream includes: The m second data streams are processed to obtain m third data streams; The third data processing of the third data stream to obtain Y modulation symbol streams includes: The m third data streams are processed to obtain Y modulated symbol streams.

5. The method according to claim 1 or 2, characterized in that, The first data stream also undergoes convolutional interleaving, which involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits in the input data stream are sequentially input into the r delay lines according to their indices. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r... The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

6. The method according to claim 5, characterized in that, After convolutional interleaving, each output has f bits. The input / output switch corresponding to the convolutional interleaving is located on the 0th delay line, and K×b is divisible by f.

7. The method according to claim 5, characterized in that, r×d×c=K×b, where c is an integer greater than or equal to 1.

8. The method according to claim 1 or 2, characterized in that, The baud rate of the modulation symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, and G represents... M represents .

9. The method according to claim 1 or 2, characterized in that, N=128, K=120.

10. The method according to claim 1 or 2, characterized in that, The baud rate of the modulated symbol stream is 113.4375 Gbaud.

11. The method according to claim 4, characterized in that, The third data processing of the m third data streams to obtain Y modulation symbol streams includes: Channel interleaving is performed on each group of 8 third data streams in the m third data streams to obtain 1 fourth data stream, resulting in a total of Y fourth data streams; The Y fourth data streams are modulated to obtain the Y modulated symbol streams.

12. The method according to claim 11, characterized in that, The first identifier in each of the second data streams includes a length of A synchronization subsequence of bits, wherein the synchronization subsequence is located in a continuous sequence starting from the start position in the first identifier. 1 bit.

13. The method according to claim 12, characterized in that, The set of 8 third data streams in the m third data streams is obtained by the second FEC encoding of the set of 8 second data streams in the m second data streams. The fourth data stream obtained by the set of 8 third data streams through channel interleaving includes a synchronization sequence of 48 bits in length. The synchronization sequence of 48 bits in length is continuous in the fourth data stream. The synchronization sequence of 48 bits in length includes a synchronization subsequence included in each of the set of 8 second data streams, for a total of 8 synchronization subsequences.

14. The method according to claim 13, characterized in that, The 48 bits of the synchronization sequence have values ​​of 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

15. The method according to claim 13 or 14, characterized in that, The synchronization subsequence 0 included in the 0th second data stream of the set of 8 second data streams is 010110; The synchronization subsequence 1 of the first of the group of 8 second data streams is 011010; The synchronization subsequence 2 of the second data stream in the set of 8 second data streams is 100111; The synchronization subsequence 3 of the third second data stream in the set of eight second data streams is 010001; The synchronization subsequence 4 of the fourth second data stream in the set of eight second data streams is 011010; The synchronization subsequence 5 of the fifth second data stream in the group of eight second data streams is 011001; The synchronization subsequence 6 of the 6th second data stream in the set of 8 second data streams is 000110; The synchronization subsequence 7 of the 7th second data stream in the set of 8 second data streams is 101011.

16. The method according to claim 11, characterized in that, When N=128 and K=120, channel interleaving of each group of 8 third data streams to obtain 1 fourth data stream includes: One 128-bit internal codeword is obtained from each of the eight third data streams in each group, resulting in a total of eight internal codewords; Polling retrieves 2 bits from each of the 8 internal codewords to obtain 1024 consecutive bits in the fourth data stream.

17. The method according to claim 1 or 2, characterized in that, The first data processing for m of the first data streams includes: Perform cyclic shifting on each of the m first data streams.

18. The method according to claim 17, characterized in that, Before performing cyclic shift on each of the m first data streams, the first data processing on the m first data streams includes: Perform convolutional interleaving on each of the m first data streams.

19. The method according to claim 17, characterized in that, Before performing cyclic shifts on the m first data streams respectively, the method further includes: Perform convolutional interleaving on each of the m / 8 input data streams; Each input data stream after convolutional interleaving is distributed to obtain 8 first data streams, resulting in a total of m first data streams.

20. A data processing method, characterized in that, include: The received Y modulated symbol streams are processed by a fourth data process to obtain m fourth data streams, where Y is an integer greater than or equal to 1. Each fourth data stream is demodulated, and the baud rate of each modulated symbol stream is an integer multiple of 156.25 MHz. The Y modulated symbol streams are obtained by processing m third data streams, each of which has been modulated. The m third data streams are obtained by processing m second data streams, and the m second data streams are obtained by processing m first data streams encoded with first forward error correction (FEC), where m is an integer greater than 1. Each second data stream includes at least one first bit sequence, and each first bit sequence includes... Each of the first bit sequences contains bits, and each bit in the first bit sequence contains bits. Each bit in the first bit sequence comes from the first data stream. The first identifier is added during the first data processing. The second data processing includes second FEC encoding. Each codeword after the second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, S represents the number of check bits, and K and S are integers greater than or equal to 1. =K×b, Where b is an integer greater than 1, and e is an integer greater than or equal to 1; Codeword synchronization and / or frame synchronization are performed on each of the fourth data streams.

21. The method according to claim 20, characterized in that, ， 。 22. The method according to claim 20 or 21, characterized in that, The baud rate of the modulation symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, and G represents... M represents .

23. The method according to claim 20 or 21, characterized in that, N=128, K=120.

24. The method according to claim 20 or 21, characterized in that, The baud rate of the modulated symbol stream is 113.4375 Gbaud.

25. The method according to claim 20 or 21, characterized in that, Y=4, or Y=8.

26. A data processing method, characterized in that, include: A first data stream encoded by a first forward error correction (FEC) is processed to obtain a second data stream, the second data stream comprising at least one first bit sequence, each of the first bit sequences comprising: Each of the first bit sequences contains bits, and each bit in the first bit sequence contains bits. Each bit in the first bit sequence comes from the first data stream. Each bit is a first identifier added during the first data processing; The second data stream is subjected to a second data processing step to obtain a third data stream. This second data processing step includes a second FEC encoding. Each codeword after the second FEC encoding comprises N bits, where N = K + S, K represents the number of information bits, S represents the number of parity bits, and K and S are both integers greater than or equal to 1. , , =K×b, Where b is an integer greater than 1, and e is an integer greater than or equal to 1; The third data stream is subjected to third data processing to obtain Y modulation symbol streams, where Y is an integer greater than or equal to 1, and each modulation symbol stream is modulated.

27. The method according to claim 26, characterized in that, The third data stream includes at least one second bit sequence, each second bit sequence comprising P+W bits, wherein the P bits in each second bit sequence are composed of... The first bit is obtained by encoding the second FEC. The W bits in each second bit sequence are the second identifier. The second identifier is obtained by encoding the first identifier by the second FEC. P=N×b, W=N×e.

28. The method according to claim 26 or 27, characterized in that, The baud rate of each of the modulated symbol streams is an integer multiple of 156.25 MHz.

29. The method according to claim 26 or 27, characterized in that, The first data processing step of obtaining the second data stream from the first data stream encoded by the first forward error correction (FEC) includes: The first data streams encoded by the first forward error correction (FEC) are processed to obtain m second data streams, where m is an integer greater than 1, and each second data stream includes at least one of the first bit sequences. The process of performing a second data processing on the second data stream to obtain a third data stream includes: The m second data streams are processed to obtain m third data streams; The third data processing of the third data stream to obtain Y modulation symbol streams includes: The m third data streams are processed to obtain Y modulated symbol streams.

30. The method according to claim 26 or 27, characterized in that, The first data stream also undergoes convolutional interleaving, which involves delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units containing 0 units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit stores d bits. Bits in the input data stream are sequentially input into the r delay lines according to their indices. Each delay line inputs d bits at a time and outputs d bits at a time. After convolutional interleaving, the output data stream contains consecutive r... The d bits include the d bits output from each delay line, where Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1.

31. The method according to claim 30, characterized in that, After convolutional interleaving, each output has f bits. The input / output switch corresponding to the convolutional interleaving is located on the 0th delay line, and K×b is divisible by f.

32. The method according to claim 30, characterized in that, r×d×c=K×b, where c is an integer greater than or equal to 1.

33. The method according to claim 26 or 27, characterized in that, The baud rate of the modulation symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, and G represents... M represents .

34. The method according to claim 26 or 27, characterized in that, N=128, K=120.

35. The method according to claim 26 or 27, characterized in that, The baud rate of the modulated symbol stream is 113.4375 Gbaud.

36. The method according to claim 29, characterized in that, The third data processing of the m third data streams to obtain Y modulation symbol streams includes: Channel interleaving is performed on each group of 8 third data streams in the m third data streams to obtain 1 fourth data stream, resulting in a total of Y fourth data streams; The Y fourth data streams are modulated to obtain the Y modulated symbol streams.

37. The method according to claim 36, characterized in that, The first identifier in each of the second data streams includes a length of A synchronization subsequence of bits, wherein the synchronization subsequence is located in a continuous sequence starting from the start position in the first identifier. 1 bit.

38. The method according to claim 37, characterized in that, The set of 8 third data streams in the m third data streams is obtained by the second FEC encoding of the set of 8 second data streams in the m second data streams. The fourth data stream obtained by the set of 8 third data streams through channel interleaving includes a synchronization sequence of 48 bits in length. The synchronization sequence of 48 bits in length is continuous in the fourth data stream. The synchronization sequence of 48 bits in length includes a synchronization subsequence included in each of the set of 8 second data streams, for a total of 8 synchronization subsequences.

39. The method according to claim 38, characterized in that, The 48 bits of the synchronization sequence have values ​​of 0x9A, 0x4A, 0x26, 0x65, 0xB5, and 0xD9.

40. The method according to claim 38 or 39, characterized in that, The synchronization subsequence 0 included in the 0th second data stream of the set of 8 second data streams is 010110; The synchronization subsequence 1 of the first of the group of 8 second data streams is 011010; The synchronization subsequence 2 of the second data stream in the set of 8 second data streams is 100111; The synchronization subsequence 3 of the third second data stream in the set of eight second data streams is 010001; The synchronization subsequence 4 of the fourth second data stream in the set of eight second data streams is 011010; The synchronization subsequence 5 of the fifth second data stream in the group of eight second data streams is 011001; The synchronization subsequence 6 of the 6th second data stream in the set of 8 second data streams is 000110; The synchronization subsequence 7 of the 7th second data stream in the set of 8 second data streams is 101011.

41. The method according to claim 36, characterized in that, When N=128 and K=120, channel interleaving of each group of 8 third data streams to obtain 1 fourth data stream includes: One 128-bit internal codeword is obtained from each of the eight third data streams in each group, resulting in a total of eight internal codewords; Polling retrieves 2 bits from each of the 8 internal codewords to obtain 1024 consecutive bits in the fourth data stream.

42. The method according to claim 26 or 27, characterized in that, The first data processing for m of the first data streams includes: Perform cyclic shifting on each of the m first data streams.

43. The method according to claim 42, characterized in that, Before performing cyclic shift on each of the m first data streams, the first data processing on the m first data streams includes: Perform convolutional interleaving on each of the m first data streams.

44. The method according to claim 42, characterized in that, Before performing cyclic shifts on the m first data streams respectively, the method further includes: Perform convolutional interleaving on each of the m / 8 input data streams; Each input data stream after convolutional interleaving is distributed to obtain 8 first data streams, resulting in a total of m first data streams.

45. A data processing method, characterized in that, include: The received Y modulated symbol streams are processed by a fourth data process to obtain m fourth data streams, where Y is an integer greater than or equal to 1. Each fourth data stream is demodulated. The Y modulated symbol streams are obtained by processing m third data streams, each of which has been modulated. The m third data streams are obtained by processing m second data streams, and the m second data streams are obtained by processing m first data streams encoded with first forward error correction (FEC), where m is an integer greater than 1. Each second data stream includes at least one first bit sequence, and each first bit sequence includes... Each of the first bit sequences contains bits, and each bit in the first bit sequence contains bits. Each bit in the first bit sequence comes from the first data stream. The first identifier is added during the first data processing. The second data processing includes second FEC encoding. Each codeword after the second FEC encoding includes N bits, where N = K + S, K represents the number of information bits, S represents the number of check bits, and K and S are integers greater than or equal to 1. , , =K×b, Where b is an integer greater than 1, and e is an integer greater than or equal to 1; Codeword synchronization and / or frame synchronization are performed on each of the fourth data streams.

46. ​​The method according to claim 45, characterized in that, The baud rate of each of the modulated symbol streams is an integer multiple of 156.25 MHz.

47. The method according to claim 45 or 46, characterized in that, The baud rate of the modulation symbol stream is And the baud rate value is Where a is an integer greater than or equal to 1, and G represents... M represents .

48. The method according to claim 45 or 46, characterized in that, N=128, K=120.

49. The method according to claim 45 or 46, characterized in that, The baud rate of the modulated symbol stream is 113.4375 Gbaud.

50. The method according to claim 45 or 46, characterized in that, Y=4, or Y=8.

51. A data processing apparatus, characterized in that, The apparatus includes a processor and a transceiver, the transceiver being configured to perform data transmission and reception operations, and the processor being configured to perform the method as described in any one of claims 1-50.

52. A chip, characterized in that, The chip includes a processor and a transceiver, the transceiver being used to perform data transmission and reception operations, and the processor being used to perform the method as described in any one of claims 1-50.

53. An optical module, characterized in that, The optical module includes a processor and a transceiver, the transceiver being used to perform data transmission and reception operations, and the processor being used to perform the method as described in any one of claims 1-50.

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