Pulse amplitude modulation (PAM) encoding for a communication bus

Abstract

Pulse amplitude modulation (PAM) encoding for communication buses is disclosed. In particular, various two-wire communication buses can use three-level PAM (PAM-3) or five-level PAM (PAM-5) to encode bits to increase bit transmission without requiring an increase in clock frequency or the addition of additional pins. Avoiding an increase in clock frequency helps reduce the risk of electromagnetic interference (EMI), and avoiding the use of extra pins can avoid an increase in the cost of integrated circuits (ICs).

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 076190, filed October 21, 2020, entitled “PULSE AMPLITUDE MODULATION (PAM) ENCODING FOR A COMMUNICATION BUS,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology disclosed herein generally relates to increasing the bandwidth on a communication bus by providing pulse amplitude modulation (PAM). Background Technology

[0004] Computing devices are ubiquitous in modern society. These devices rely on countless integrated circuits (ICs) to provide different functions. The abundance of ICs necessitates communication between them. Various protocols have been developed to guide how different ICs can communicate. The increasing amount of data transferred between ICs requires ever-increasing bandwidth. As IC sizes shrink, conventional techniques for increasing bandwidth (such as increasing bus frequency or adding pins to add data channels) become less suitable. Summary of the Invention

[0005] The aspects disclosed in the detailed description include pulse amplitude modulation (PAM) encoding for communication buses. Specifically, various two-wire communication buses can use three-level PAM (PAM-3) or five-level PAM (PAM-5) to encode bits, increasing bit transmission without requiring increased clock frequency or additional pins. Avoiding increased clock frequency helps reduce the risk of electromagnetic interference (EMI), and avoiding the use of additional pins avoids increased costs for integrated circuits (ICs).

[0006] In this regard, on one hand, an integrated circuit (IC) is disclosed. The IC includes a bus interface coupled to a communication bus. The IC also includes a clock source coupled to the bus interface. The IC further includes control circuitry. The control circuitry is configured to transmit a clock signal, derived from the clock source and embedding parity bits, on the clock line of the communication bus via the bus interface. The control circuitry is also configured to transmit PAM data signals on the data line of the communication bus.

[0007] In another aspect, an IC is disclosed. This IC includes a bus interface coupled to a communication bus. The IC also includes control circuitry. The control circuitry is configured to receive, via the bus interface, a clock signal containing a parity check bit embedded in it on the clock line of the communication bus. The control circuitry is also configured to receive PAM data signals on the data lines of the communication bus.

[0008] In another aspect, a computing system is disclosed. The computing system includes a communication bus. The computing system also includes a first IC. The first IC includes a first bus interface coupled to the communication bus. The first IC also includes a clock source coupled to the first bus interface. The first IC also includes a first control circuit. The first control circuit is configured to transmit a clock signal, derived from the clock source and embedding parity bits, on a clock line of the communication bus via the first bus interface. The first control circuit is further configured to transmit PAM data signals on a data line of the communication bus. The computing system also includes a second IC. The second IC includes a second bus interface coupled to the communication bus. The second IC also includes a second control circuit. The second control circuit is configured to receive a clock signal embedding parity bits. The second control circuit is further configured to receive PAM data signals. Attached Figure Description

[0009] Figure 1 This is a block diagram of an exemplary mobile terminal having various internal communication buses that interconnect various integrated circuits (ICs);

[0010] Figure 2A The diagram illustrates the waveform used in the five-level pulse amplitude modulation (PAM-5) coding scheme;

[0011] Figure 2B The diagram illustrates the waveform used in the three-level PAM (PAM-3) coding scheme;

[0012] Figure 2C The diagram illustrates the data bits related to the clock signal;

[0013] Figures 3A-3D The illustration shows four exemplary encoding possibilities for using the PAM-5 encoding scheme on a data line;

[0014] Figures 4A-4D The illustration shows four exemplary encoding possibilities for using the PAM-5 encoding scheme to provide two bits and a parity bit on the clock line;

[0015] Figures 5A-5D The illustration shows four exemplary encoding possibilities for using the PAM-5 encoding scheme to provide two bits and a parity bit on the clock line;

[0016] Figure 6A and Figure 6B The diagram illustrates two coded signals and their sampling.

[0017] Figure 7A It is a block diagram of a system with a single-ended communication bus;

[0018] Figure 7BIt is a block diagram of a system with a differential communication bus;

[0019] Figure 8A and Figure 8B The diagram illustrates the differences between single-ended signaling and differential signaling as used in this disclosure;

[0020] Figure 9 This is a diagram illustrating the input / output requirements for the data lines of the System Power Management Interface (SPMI) bus used by the master and slave devices;

[0021] Figure 10 This is a diagram illustrating the input / output requirements of the clock lines for the SPMI bus used by master and slave devices; and

[0022] Figure 11 This is a flowchart illustrating an exemplary process for increasing bandwidth on a communication bus using PAM encoding. Detailed Implementation

[0023] Several exemplary aspects of this disclosure are now described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than the others.

[0024] The aspects disclosed in the detailed description include pulse amplitude modulation (PAM) encoding for communication buses. Specifically, various two-wire communication buses can use three-level PAM (PAM-3) or five-level PAM (PAM-5) to encode bits, increasing bit transmission without requiring increased clock frequency or additional pins. Avoiding increased clock frequency helps reduce the risk of electromagnetic interference (EMI), and avoiding the use of additional pins avoids increased costs for integrated circuits (ICs).

[0025] Before explaining the details of using PAM encoding for the communication bus, refer to... Figure 1 A brief overview of mobile terminals with various communication buses is provided. Details of PAM encoding technology are then presented starting with Figure 2.

[0026] in this regard, Figure 1 This is a system-level block diagram of an exemplary mobile terminal 100 (such as a smartphone, mobile computing device, tablet, etc.), which may include one or more communication buses that can use the PAM encoding technology disclosed herein. For example, the PAM encoding technology disclosed herein is well-suited for use with System Power Management Interface (SPMI) bus, Radio Frequency Front-End (RFFE) bus, I3C bus, etc.

[0027] Continue to refer to Figure 1Mobile terminal 100 includes application processor 104 (sometimes referred to as the host device), which communicates with mass storage device 106 via Universal Flash Memory (UFS) bus 108. Application processor 104 can also be connected to display 110 via Display Serial Interface (DSI) bus 112 and to camera 114 via Camera Serial Interface (CSI) bus 116. Various audio components, such as microphone 118, speaker 120, and audio codec 122, can be coupled to application processor 104 via Serial Low Power Inter-Chip Multimedia Bus (SLIMbus) 124. Furthermore, audio components can communicate with each other via SOUNDWIRE bus 126. Modem 128 can also be coupled to SLIMbus 124 and / or SOUNDWIRE bus 126. Modem 128 can also be connected to application processor 104 via Peripheral Component Interconnect (PCI) or PCI Express (PCIE) bus 130 and / or SPMI bus 132. SPMI bus 132 can be a two-wire bus including clock and data lines. Figure 1 (Not shown in the figure). In its simplest case, SPMI is a protocol used for communication between a host and a power management integrated circuit (e.g., PMIC 136 described below) to control the voltage regulator from the host and transmit voltage increases and decreases back from the PMIC 136.

[0028] Continue to refer to Figure 1 The SPMI bus 132 can also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 134, a power management integrated circuit (PMIC) 136, an accompanying IC (sometimes referred to as a bridge chip) 138, and a radio frequency IC (RFIC) 140. In an exemplary aspect, one or more of these ICs can be a master or slave device. More details regarding master and slave devices within the SPMI system are provided below with reference to Figure 2. It should be understood that separate PCI buses 142 and 144 can also couple the application processor 104 to the accompanying IC 138 and the WLAN IC 134. The application processor 104 can also be connected to a sensor 146 via a sensor bus 148. The modem 128 and the RFIC 140 can communicate using bus 150.

[0029] Continue to refer to Figure 1RFIC 140 can be coupled to one or more RFFE components, such as antenna tuner 152, switch 154, and power amplifier 156, via RFFE bus 158. Furthermore, RFIC 140 can be coupled to envelope tracking power supply (ETPS) 160 via bus 162, and ETPS 160 can communicate with power amplifier 156. In general, the RFFE components (including RFIC 140) can be considered as RFFE system 164. It should be understood that RFFE bus 158 can be formed by clock lines and data lines (not shown). Although not shown, additional buses such as I2C or I3C may exist within mobile terminal 100.

[0030] The exemplary aspects of this disclosure are well-suited for use on two-wire single-ended buses such as the SPMI bus, RFFE bus, or I3C bus, but this disclosure is not limited thereto, and PAM encoding techniques can also be used in differential buses. However, for the sake of illustration, the initial discussion will focus on single-ended two-wire buses such as the SPMI bus. The following references... Figure 7B and Figure 8B A discussion of differential buses is provided.

[0031] Figure 2A An overview of the PAM-5 encoding technique 200 is provided, including the possible states of the data line 202 and the clock line 204. Specifically, the clock line 204 can have a normal period 206, which is divided into three time slots as shown in row 208. An internal clock signal 210 with a frequency twelve times faster than the normal period 206 (although six times or even three times faster is also possible) can be used to help divide the normal period into three time slots 208A-208C. The voltage level of the data line 202 can be divided into five levels 202A-202E, where level 202A is zero volts (0V) and level 202E is the maximum voltage level of the bus (e.g., Vdd). Levels 202B-202D are 25%, 50%, and 75% of Vdd, respectively. In each of time slots 208A-208C, data line 202 can be driven at any of five levels 202A-202E, providing 125 (i.e., 5*5*5) possible states in a single standard cycle 206. Similarly, the voltage level of clock line 204 can be divided into five levels 204A-204E, where in each of time slots 208A-208C, clock line 204 can be driven at any of the five levels 204A-204E, providing an additional 125 possible states in a single standard cycle 206. Therefore, the theoretical number of possible states would be 15625 (i.e., 525*525).

[0032] While PAM-5 is a robust encoding technique, there may be situations where bus noise prevents differentiation between the five different voltage levels. In such cases, PAM-3 encoding technique 200B can be used, such as... Figure 2B As shown in the diagram. In PAM-3 encoding, the voltage level of data line 202 can be divided into only three levels 202A, 202C, and 202E, while the clock line 204 can be divided into three levels 204A, 204C, and 204E. Using the three voltage levels across the two lines 202 and 204 generates a total of eighty-one (81) possible states.

[0033] Assuming PAM-5 is used, Figure 2C An exemplary two-bit encoding scheme 200C is illustrated, which allows six bits to be transmitted on data line 202 or clock line 204. Specifically, each time slot 208A-208C holds two bits determined by the voltage level at that time slot. Thus, for example, levels 202A, 204A correspond to [0, 0]; levels 202B, 204B correspond to [0, 1]; levels 202D, 204D correspond to [1, 0]; and levels 202E, 204E correspond to [1, 1]. Levels 202C, 204C correspond to idle levels and are not assigned specific bits.

[0034] As a further example, Figures 3A-3D The diagram illustrates four possible signals with corresponding codes. Therefore, by positioning time slot 208A at horizontal 202A, time slot 208B at horizontal 202B, and time slot 208C at horizontal 202D, Figure 3A Signal 300A in the diagram is [0, 0, 0, 1, 1, 0]. Similarly, by positioning time slot 208A at horizontal 202D, time slot 208B at horizontal 202B, and time slot 208C at horizontal 202E, Figure 3B Signal 300B in the diagram is [1, 0, 0, 1, 1, 1]. This is achieved by positioning time slot 208A at horizontal 202E, time slot 208B at horizontal 202A, and time slot 208C at horizontal 202B. Figure 3C Signal 300C in the diagram is [1, 1, 0, 0, 0, 1]. This is achieved by positioning time slot 208A at horizontal 202B, time slot 208B at horizontal 202E, and time slot 208C at horizontal 202A. Figure 3D Signal 300D in the equation is [0, 1, 1, 1, 0, 0]. Clearly, other signals can be constructed using PAM-5 coding techniques, and... Figures 3A-3D The examples are not intended to be restrictive.

[0035] It should be understood that many signals on a communication bus are eight bits and one parity bit. For example... Figures 3A-3DAs shown, encoding on only data line 202 provides six bits, which is three bits less than the required nine bits. However, as Figure 2B As shown in the diagram, clock line 204 can also be used for encoding, enabling an additional 512 possible states. Forming nine bits does not require all of these states. Therefore, the first time slot is encoded with the first bit, the third time slot with the second bit, and the duty cycle of clock line 204 is used, such as... Figures 4A-5D The diagram is illustrated in the image. Bits are encoded in the first time slot 208A and the third time slot 208C according to their displacement (horizontally) from the center level 204C. Therefore, levels 204A and 204E, which are two levels away from the center level 204C, are 1, and levels 204B and 204D, which are only one level away from the center level 204C, are 0. Other encoding schemes can be used.

[0036] in this regard, Figures 4A-4D The diagrams illustrate signals 400A-400D on clock line 204, where the first time slot 208A is encoded with bits, the third time slot 208C is encoded with bits, and the duty cycle indicates the parity bit. Therefore, Figure 4A It has a signal 400A, wherein the first time slot 208A is set at level 204D (one shift or 0), the third time slot 20C is set at level 204B (one shift or 0), and has a duty cycle of 33%, which reflects the encoding of [0,0] and the parity bit [0]. Figure 4B The signal is 400B, in which the first time slot 208A is also set at the level 204D, but the third time slot 208C is set at 204A (two shifts or 1) and has a duty cycle of 33%, which reflects the encoding of [0, 1] and the parity bit [0]. Figure 4C It has a signal 400C, in which the first time slot 208A is set at level 204E (two shifts or 1), the third time slot 208C is set at level 204B (one shift or 0), and has a duty cycle of 33%, which reflects the encoding of [1, 0] and the parity bit [0]. Figure 4D It has a signal 400D, in which the first time slot 208A is set at level 204E (two shifts or 1), the third time slot 208C is set at level 204A (two shifts or 1), and has a duty cycle of 33%, which reflects the encoding of [1,1] and the parity bit [0].

[0037] Figures 5A-5D Signals 500A-500D on clock line 204 are illustrated respectively, wherein the first time slot 208A is encoded with the first bit, the third time slot 208C is encoded with the second bit, and a 66% duty cycle indicates the parity bit [1]. Therefore, Figure 5AIt has a signal 500A, wherein the first time slot 208A is set at level 204D (one shift or 0), the third time slot 208C is set at level 204B (one shift or 0), and has a duty cycle of 66%, which reflects the encoding of [0,0] and the parity bit [1]. Figure 5B It has a signal 500B, in which the first time slot 208A is also set at level 204D (one shift or 0), the third time slot 208C is set at level 204A (two shifts or 1), and has a duty cycle of 66%, which reflects the encoding of [0, 1] and the parity bit [1]. Figure 5C It has a signal 500C, in which the first time slot 208A is set at level 204E (two shifts or 1), the third time slot 208C is set at level 204B (one shift or 0), and has a duty cycle of 66%, which reflects the encoding of [1, 0] and the parity bit [1]. Figure 5D It has a signal 500D, in which the first time slot 208A is set at level 204E (two shifts or 1), the third time slot 208C is set at level 204A (two shifts or 1), and has a duty cycle of 66%, which reflects the encoding of [1,1] and the parity bit [1].

[0038] To further illustrate, Figure 6A and Figure 6B Examples of encoding and sampling to extract encoded bits are provided. Specifically, Figure 6A The diagram illustrates the data signal 600A on data line 202 and the clock signal 602A on clock line 204. A raw period 206 is provided for reference. An internal clock signal 210 is used to help set the sampling points 604A-604C for both the data signal 600A and the clock signal 602A. By sampling in each time slot of timeslots 208A-208C in this manner, the control circuitry can determine the signal level and, from this, determine the encoded bits and the duty cycle of clock line 204 used to derive the parity bit. As illustrated, the data signal 600A is encoded as [0, 0, 0, 1, 1, 0], and the clock signal 602A is encoded as [1, 0] and the parity bit as [0]. Furthermore, the internal clock 210 can be synchronized with the reference clock via an initial rising edge 606. Other phase / polarity options can be covered by implementing programmable options (e.g., the encoded value is 00 or 01, and a falling edge is present at the beginning of the clock cycle).

[0039] Figure 6BSimilarly, but data signal 600B encoded [0, 1, 0, 0, 1, 1] and clock signal 602B encoded [1, 0] and parity bit [1] are shown. Again, it should be understood that these signals are exemplary and other values ​​can be used. Similarly, different internal clocks 210 can specify different sampling periods, but sampling should be performed for each time slot 208A-208C.

[0040] Figure 7A and Figure 7B Systems with different types of buses are provided. Specifically, Figure 7A This includes the System 700A, which features a single-ended bus 702A, while Figure 7B This includes a system 700B with a differential bus 702B. In system 700A, the master or host device 704 is coupled to a single-ended bus 702A in the same way as the slave devices 706(1)-706(N). The single-ended bus 702A includes a data line 708 (similar to data line 202) and a clock line 710 (similar to clock line 204). A voltage line 712 is provided, which provides a common voltage reference line for the master device 704 and the slave devices 706(1)-706(N). When determining what level 202A-202E or 204A-204E is being used, the slave devices 706(1)-706(N) can refer to the voltage level on the voltage line 712. A single-ended bus such as bus 702A may be appropriate when the bus frequency is below 1 GHz.

[0041] In system 700B, the master device or host 704 is coupled to the differential bus 702B in the same way as the slave devices 706(1)-706(N). The differential bus 702B includes a positive data line 720+ and a negative data line 720- (commonly similar to data line 202), and includes a positive clock line 722+ and a negative clock line 722- (commonly similar to clock line 204). A voltage line 712 is provided, which provides a common voltage reference line for the master 704 and the slave devices 706(1)-706(N). The slave devices 706(1)-706(N) can refer to the voltage level on the voltage line 712 when determining what level 202A-202E or 204A-204E is being used. When the bus frequency is higher than 1GHz, a differential bus such as bus 702B may be appropriate.

[0042] Figure 8A and Figure 8B The diagram illustrates the differences between signals on a single-ended bus and a differential bus. Therefore, in Figure 8A In this context, a single-ended signal 800, which is essentially the same as signals 600B and 602B, is provided. Figure 8BThe same signal as the differential signal 810 appears the same on the positive data line 720+ and the positive clock line 722+, but is out of phase on the negative data line 720- and the negative clock line 722-.

[0043] It should also be understood that exemplary aspects of this disclosure allow for easy migration to differential mode operation through negotiation between the host and slave devices.

[0044] To help to further and more fully understand possible use cases Figure 9 and Figure 10 A master and slave device attached to a communication bus are shown, which may be an SPMI bus, an RFFE bus, etc. While specific hardware is considered for a master or slave device on an SPMI bus, it should be understood that other architectures may be suitable for RFFE, I3C, etc., and may be used without departing from this disclosure.

[0045] in this regard, Figure 9 This is a schematic diagram illustrating the input / output requirements of the data line 202 of the SPMI bus used by master device 704 and slave device 706. Specifically, the bus interface 900 for master device 704 is illustrated together with the bus interface 902 for slave device 706. Bus interface 900 includes a data output amplifier 904 for transmitting data on data line 202 and a data input amplifier 906 for amplifying incoming signals received on data line 202. The data output / input amplifiers 904 and 906 are switched by a read / write or data input enable signal 908. Master device 704 may also include control circuitry 910 (sometimes referred to as CC in the figure) and a memory element 912 (sometimes referred to as MEM in the figure), in which register 914 is stored. Register 914 can be read from or written to by slave device 706.

[0046] Bus interface 902 includes a data output amplifier 916 that transmits data on data line 202, and a data input amplifier 918 that amplifies incoming signals received on data line 202. Data output / input amplifiers 916 and 918 are switched by a read / write or data input enable signal 920. Slave device 706 may also include control circuitry 922 (sometimes referred to as CC in the figure) and a memory element 924 (sometimes referred to as MEM in the figure). Additional pull-down resistors 926 and 928 may be associated with data line 202 to help provide logic lows when needed. Note that both, one, or both of the pull-down resistors 926 and 928 may be present. Slave device 706 may also include register 930, which master device 704 can write to or read from according to the conventional SPMI protocol.

[0047] Figure 10This is a schematic diagram illustrating the input / output requirements of clock line 204 for the SPMI bus used by master device 704 and slave device 706. Specifically, bus interface 900 for master device 704 is illustrated together with bus interface 902 for slave device 706. Bus interface 900 includes a clock output amplifier 1030 that transmits a clock signal from a clock source (not shown) on clock line 204, and a clock input amplifier 1032 that amplifies incoming signals (including any reflections) received on clock line 204. Clock output amplifier 1030 is enabled by SCLK OUT ENABLE signal 1034, while clock input amplifier 1032 is enabled by SCLK IN ENABLE signal 1036.

[0048] Bus interface 902 includes a clock input amplifier 1038 that amplifies the incoming signal received on clock line 204. Additional pull-down resistors 1040 and 1042 may be associated with clock line 204 to help provide a logic low when needed. Note that both, one, or neither of the pull-down resistors 1040 and 1042 may be present. Slave device 706 may have an internal clock source, which may be a phase-locked loop (PLL) (not shown), a crystal oscillator, or slave device 706 may derive a clock signal from the signal on clock line 204, in which case a PLL may be used to provide the sampling frequency. Slave device 706 may synchronize with master device 704 on the initial rising edge of the clock signal.

[0049] refer to Figure 11 A brief overview of the process 1100 using PAM encoding is provided. Specifically, process 1100 begins when the host 704 or slave device 706 generates data or commands to be transmitted on the bus (box 1102). The data or commands are encoded using PAM encoding technology (box 1104) and transmitted on the bus (box 1106). The receiver decodes the signal by sampling (box 1108).

[0050] The PAM encoding for communication buses disclosed herein can be provided in or integrated into any processor-based device. Examples include, but are not limited to: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, wireless equipment, satellite wireless equipment, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0051] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As an example, the devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in varying ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0052] The various illustrative logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0053] The aspects disclosed herein can be embodied in hardware and instructions stored in that hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0054] It should also be noted that the operational steps described in any exemplary aspect of this document are described to provide examples and discussion. The described operations can be performed in many different orders besides the order illustrated. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps illustrated in the flowcharts can be modified in many different ways, as will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing specification can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0055] The prior description of this disclosure is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is consistent with the widest scope of the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC), comprising: The bus interface is coupled to the communication bus. A clock source, coupled to the bus interface; as well as The control circuit is configured as follows: A clock signal is transmitted on the clock line of the communication bus through the bus interface. The clock signal originates from the clock source and contains a parity check bit. Transmit pulse amplitude modulation (PAM) data signals on the data lines of the communication bus; and The data lines are sampled for the incoming signal at a rate at least three times the frequency of the clock signal. The clock signal is divided into three time slots, in which the data line is driven at a voltage level of the PAM data signal in each of the three time slots, and the control circuit is further configured to sample the data line in each of the three time slots.

2. The IC of claim 1, wherein the control circuitry is configured to provide eight bits of data and the parity bit across a single clock cycle of the clock source.

3. The IC according to claim 1, wherein the bus interface is configured to be coupled to one of a radio frequency front-end (RFFE) bus, a system power management interface (SPMI) bus, or an I3C bus.

4. The IC according to claim 2, wherein the PAM data signal comprises six bits of data per clock cycle.

5. The IC according to claim 4, wherein in addition to the parity bit, the clock signal further includes two bits of data.

6. The IC according to claim 1, wherein the control circuit is configured to encode the PAM data signal using three-level PAM (PAM-3) encoding technology.

7. The IC of claim 1, wherein the control circuit is configured to: encode the parity bit into the clock signal by setting the duty cycle of the clock signal.

8. The IC according to claim 1, wherein the bus interface includes a single-ended bus interface.

9. The IC according to claim 1, wherein the bus interface includes a differential bus interface.

10. The IC of claim 1, wherein the IC is integrated into a device selected from the group consisting of: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radio equipment, satellite radio equipment, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, unmanned aerial vehicles, and multi-rotor aircraft.

11. An integrated circuit (IC), comprising: The bus interface is coupled to the communication bus. The control circuit is configured as follows: Through the bus interface, a clock signal containing a parity check bit is received on the clock line of the communication bus. Pulse amplitude modulation (PAM) data signals are received on the data lines of the communication bus; as well as The data lines are sampled at a rate at least three times the frequency of the clock signal, wherein the sampling is performed in each of the three time slots of one cycle of the clock signal. The period of the clock signal is divided into the three time slots, and in each of the three time slots, the PAM data signal includes a corresponding voltage level.

12. The IC of claim 11 further includes a clock source that operates at a frequency at least three times that of the clock signal.

13. The IC according to claim 11, wherein the bus interface includes a system power management interface (SPMI) bus interface, a radio frequency front-end (RFFE) bus interface, or an I3C bus interface.

14. The IC of claim 11, wherein the control circuit is configured to receive a five-level PAM (PAM-5) encoded data signal on the data line.

15. The IC of claim 11, wherein the control circuit is configured to receive a three-level PAM (PAM-3) encoded data signal on the data line.

16. The IC of claim 11, wherein the control circuitry is configured to decode six bits from the PAM data signal.

17. The IC of claim 11, wherein the control circuitry is configured to decode two bits and the parity bit from the clock signal.

18. The IC of claim 12, wherein the clock source comprises a phase-locked loop (PLL).

19. The IC of claim 11, wherein the IC is integrated into a device selected from the group consisting of: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radio equipment, satellite radio equipment, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, unmanned aerial vehicles, and multi-rotor aircraft.

20. A computing system, comprising: Communication bus; The first integrated circuit (IC) includes: The first bus interface is coupled to the communication bus; The clock source is coupled to the first bus interface; and The first control circuit is configured as follows: A clock signal is transmitted on the clock line of the communication bus via the first bus interface. The clock signal originates from the clock source and includes a parity check bit. Pulse amplitude modulation (PAM) data signals are transmitted on the data lines of the communication bus. The clock signal is divided into three time slots, and the first control circuit is configured to drive the data line at a voltage level of the PAM data signal in each of the three time slots; and The second IC includes: A second bus interface is coupled to the communication bus; and The second control circuit is configured as follows: Receive the clock signal in which the parity check bit is embedded; Receive the PAM data signal; and The data lines are sampled at a rate at least three times the frequency of the clock signal, wherein the sampling is performed in each of the three time slots of one cycle of the clock signal. The period of the clock signal is divided into the three time slots, and in each of the three time slots, the PAM data signal includes a corresponding voltage level.

21. The computing system of claim 20, wherein the second IC includes a second clock source that operates at a frequency at least three times the frequency of the clock signal.

22. The computing system of claim 20, wherein the first control circuit is further configured to allow programmable selection of clock-to-data phase and polarity relationships.

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