Display devices

Abstract

A display device includes: a data driver for supplying a data voltage to a data output line; a data distributor for coupling the data output line to a data line; and a data compensator for compensating the data voltage based on a load difference between data voltages in adjacent pixel rows.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0144509 filed on November 12, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a display device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information increases. Therefore, display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices are increasingly used.

[0005] Display devices display image frames using a combination of light emitted from multiple pixels. Line crosstalk defects can occur, deteriorating display quality depending on the image frame pattern. When line crosstalk defects occur, unexpected bright or dark lines are displayed, and users may mistake them for errors. Summary of the Invention

[0006] The embodiment provides a display device capable of minimizing a line crosstalk defect when using a data distributor.

[0007] According to aspects of the present disclosure, a display device is provided, comprising: a data driver configured to supply a first data voltage to a data output line during a first period, supply a second data voltage to the data output line during a second period following the first period, supply a third data voltage to the data output line during a third period following the second period, and supply a fourth data voltage to the data output line during a fourth period following the third period; and a data distributor configured to couple the data output line to the first data line during the first period, couple the data output line to the second data line during the second period, and couple the data output line to the second data line during the third period. an output line coupled to the first data line, and coupling the data output line to the second data line during a fourth time period; a first pixel, which is configured to receive the voltage charged in the first data line and the second data line after an initial moment of the second time period and before an initial moment of the third time period; a second pixel, which is configured to receive the voltage charged in the first data line and the second data line after an initial moment of the fourth time period; and a data compensator, which is configured to compensate for the third data voltage and the fourth data voltage based on a first load difference between the first data voltage and the third data voltage and a second load difference between the second data voltage and the fourth data voltage.

[0008] The data compensator may include: a first load calculator configured to sequentially output a load value of the first data voltage and a load value of the third data voltage; and a second load calculator configured to sequentially output a load value of the second data voltage and a load value of the fourth data voltage.

[0009] The data compensator may further include a first delay part configured to output a load value of the first data voltage after a predetermined delay time; and a second delay part configured to output a load value of the second data voltage after a predetermined delay time.

[0010] The predetermined delay time may be one horizontal period.

[0011] The data compensator may further include: a first load difference calculator configured to output a first load difference based on an output of the first load calculator and an output of the first delay section; and a second load difference calculator configured to output a second load difference based on an output of the second load calculator and an output of the second delay section.

[0012] The data compensator may further include a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage and a second crosstalk amount with respect to the fourth data voltage based on the first load difference and the second load difference.

[0013] The first crosstalk amount may be a value obtained by adding a first load difference applied with a first weight value and a second load difference applied with a second weight value, and the second crosstalk amount may be a value obtained by adding the first load difference applied with a third weight value and the second load difference applied with a fourth weight value.

[0014] A sign of each of the first weight value, the third weight value, and the fourth weight value may be different from a sign of the second weight value.

[0015] The data compensator may further include a crosstalk compensator configured to compensate the third data voltage based on the first crosstalk amount and to compensate the fourth data voltage based on the second crosstalk amount.

[0016] Each of the first pixel and the second pixel may include a P-type transistor. Each of the first weight value, the third weight value, and the fourth weight value may be a positive number, and the second weight value may be a negative number. The crosstalk compensator may increase the third data voltage as the first crosstalk amount increases, and increase the fourth data voltage as the second crosstalk amount increases.

[0017] The data driver may provide a fifth data voltage to the data output line during a fifth period between the second period and the third period, and provide a sixth data voltage to the data output line during a sixth period after the fourth period. The data distributor may couple the data output line to the third data line during the fifth period, and couple the data output line to the third data line during the sixth period. The first pixel may receive the voltage charged in the first data line, the second data line, and the third data line after the initial moment of the fifth period and before the initial moment of the third period, and the second pixel may receive the voltage charged in the first data line, the second data line, and the third data line after the start of the sixth period.

[0018] The data compensator may compensate for the third data voltage, the fourth data voltage, and the sixth data voltage based on the first load difference, the second load difference, and a third load difference between the fifth data voltage and the sixth data voltage.

[0019] The data compensator may further include a third load calculator configured to sequentially output a load value of the fifth data voltage and a load value of the sixth data voltage.

[0020] The data compensator may further include a third delay part configured to output the load value of the fifth data voltage after a predetermined delay time.

[0021] The data compensator may further include a third load difference calculator configured to output a third load difference based on an output of the third load calculator and an output of the third delay section.

[0022] The data compensator may further include a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage, a second crosstalk amount with respect to the fourth data voltage, and a third crosstalk amount with respect to the sixth data voltage based on the first load difference, the second load difference, and the third load difference.

[0023] The first crosstalk amount may be a value obtained by adding a first load difference applied with a first weight value, a second load difference applied with a second weight value, and a third load difference applied with a third weight value, the second crosstalk amount may be a value obtained by adding the first load difference applied with a fourth weight value, the second load difference applied with a fifth weight value, and the third load difference applied with a sixth weight value, and the third crosstalk amount may be a value obtained by adding the first load difference applied with a seventh weight value, the second load difference applied with an eighth weight value, and the third load difference applied with a ninth weight value.

[0024] The sign of each of the first, fourth, fifth, seventh, eighth, and ninth weight values ​​may be different from the sign of each of the second, third, and sixth weight values.

[0025] The data compensator may further include a crosstalk compensator configured to compensate the third data voltage based on the first crosstalk amount, compensate the fourth data voltage based on the second crosstalk amount, and compensate the sixth data voltage based on the third crosstalk amount.

[0026] Each of the first pixel and the second pixel may include a P-type transistor. Each of the first weight value, the fourth weight value, the fifth weight value, the seventh weight value, the eighth weight value, and the ninth weight value may be a positive number, and each of the second weight value, the third weight value, and the sixth weight value may be a negative number. The crosstalk compensator may increase the third data voltage as the first crosstalk amount increases, increase the fourth data voltage as the second crosstalk amount increases, and increase the sixth data voltage as the third crosstalk amount increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0028] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, the same reference numerals refer to the same elements.

[0029] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 and Figure 3 is a diagram illustrating a gray voltage generator according to an embodiment of the present disclosure.

[0031] Figure 4 is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0032] Figure 5 and Figure 6 is a diagram illustrating a data distributor and pixels according to an embodiment of the present disclosure.

[0033] Figure 7 is a diagram illustrating a driving method of a display device according to an embodiment of the present disclosure.

[0034] Figure 8 、 Figure 9 、 Figure 10 and Figure 11 is a diagram illustrating a line crosstalk defect that may occur when a data distributor is used.

[0035] Figure 12 is a diagram illustrating a data compensator according to an embodiment of the present disclosure.

[0036] Figure 13 is a diagram illustrating a data distributor and pixels according to another embodiment of the present disclosure.

[0037] Figure 14 is a diagram illustrating a driving method of a display device according to another embodiment of the present disclosure.

[0038] Figure 15 is a diagram illustrating a data compensator according to another embodiment of the present disclosure.

[0039] Figure 16 is a diagram illustrating a data distributor and pixels according to still another embodiment of the present disclosure.

[0040] Figure 17 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0041] Figure 18 is a diagram illustrating a display device according to still another embodiment of the present disclosure.

[0042] Figure 19 is a diagram illustrating a data distributor according to still another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various forms and is not limited to the exemplary embodiments described in this specification.

[0044] Parts not related to the description will be omitted to clearly describe the present disclosure, and the same or similar constituent elements will be represented by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements.

[0045] In addition, for better understanding and ease of description, the size and thickness of each component illustrated in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. For clarity of expression, the thickness of several parts and regions is exaggerated.

[0046] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0047] refer to Figure 1 , the display device 10 according to an embodiment of the present disclosure may include a timing controller 11 , a data driver 12 , a scan driver 13 , pixels 14 , a gray voltage generator 15 , a data distributor 16 , and a data compensator 17 .

[0048] The timing controller 11 can receive the grayscale value and control signal of each frame from an external processor. The timing controller 11 can convert the grayscale value into a signal corresponding to the specifications of the display device 10. For example, the external processor can provide the red grayscale value, green grayscale value, and blue grayscale value for each unit point. For example, when the pixel 14 has RGB stripes, the pixel can correspond one-to-one with the corresponding grayscale value. Therefore, it may not be necessary to convert the grayscale value. However, when the pixel 14 has a honeycomb structure, adjacent unit points share pixels, and therefore, the pixel may not correspond one-to-one with the corresponding grayscale value. Therefore, it may be necessary to convert the grayscale value. The converted or unconverted grayscale value GVs1 can be provided to the data driver 12. In addition, the timing controller 11 can provide the data control signal DCS to the data driver 12. In addition, the timing controller 11 can provide the scan control signal SCS to the scan driver 13.

[0049] The data driver 12 may generate a data voltage by using the gray value GVs1 and the data control signal DCS and supply the generated data voltage to the data output lines DO1, DO2, ... The data driver 12 may generate the data voltage by performing analog-to-digital conversion on the gray value GVs3 compensated by the data compensator 17 using the gray voltage DVs provided from the gray voltage generator 15.

[0050] For example, the data driver 12 may provide a first data voltage to the data output lines DO1, DO2, ... during a first period, provide a second data voltage to the data output lines DO1, DO2, ... during a second period after the first period, provide a third data voltage to the data output lines DO1, DO2, ... during a third period after the second period, and provide a fourth data voltage to the data output lines DO1, DO2, ... during a fourth period after the third period.

[0051] The scan driver 13 may generate scan signals in response to a clock signal, a scan start signal, etc. supplied from the timing controller 11, and supply the generated scan signals to the scan lines SL1 and SL2. The scan driver 13 may sequentially supply scan signals having pulses at an on-level to the scan lines SL1, SL2, ... The scan driver 13 may include scan stages configured in the form of a shift register. The scan driver 13 may generate scan signals by sequentially transmitting a scan start signal in the form of a pulse at an on-level to the next scan stage under the control of a clock signal. The scan lines SL1, SL2, ... may extend in a second direction DR2.

[0052] The pixel 14 may include a plurality of pixels PX arranged in a matrix configuration. Each of the pixels PX may be coupled to a corresponding data line and a corresponding scan line. The pixels PX may include a pixel that emits light of a first color, a pixel that emits light of a second color, and a pixel that emits light of a third color. The first color, the second color, and the third color may be different colors. For example, the first color may be one of red, green, and blue, the second color may be another color of red, green, and blue that is not the first color, and the third color may be another color of red, green, and blue that is not the first color and the second color. In addition, magenta, cyan, and yellow may be used as the first to third colors instead of red, green, and blue. However, for ease of description, in this embodiment, a case where red, green, and blue are used as the first, second, and third colors, respectively, is described. Magenta is represented as a combination of red and blue, cyan is represented as a combination of green and blue, and yellow is represented as a combination of red and green.

[0053] The grayscale voltage generator 15 can generate a grayscale voltage DVs based on the input maximum brightness value DBVI. Hereinafter, for ease of description, a case where there are 256 grayscales from grayscale 0 (minimum grayscale) to grayscale 255 (maximum grayscale) is described as an example. However, when the grayscale value has eight or more bits, there may be more grayscales. The minimum grayscale can be the darkest grayscale, and the maximum grayscale can be the brightest grayscale (e.g., full white).

[0054] The maximum brightness value may be the brightness value of light emitted from a pixel corresponding to the maximum grayscale. For example, the maximum brightness value may be the brightness value of white light generated when a pixel of a first color emits light corresponding to grayscale 255, a pixel of a second color emits light corresponding to grayscale 255, and a pixel of a third color emits light corresponding to grayscale 255. The pixels of the first color, the second color, and the third color constitute a single point. The unit of the brightness value may be nits.

[0055] Thus, the pixel PX can display an image frame that is partially (spatially) dark or partially bright, but the maximum brightness of the image frame is limited to a maximum brightness value. The maximum brightness value can be manually set by a user operating the display device 10, or can be automatically set by an algorithm associated with an illuminance sensor, etc. The set maximum brightness value is represented as an input maximum brightness value DBVI. The grayscale voltage generator 15 can be configured to receive the input maximum brightness value DBVI directly from an external processor, or can be configured to receive the input maximum brightness value DBVI through the timing controller 11.

[0056] The maximum brightness value may vary depending on the product. However, for example, the maximum value of the maximum brightness value may be 1200 nits, and the minimum value of the maximum brightness value may be 4 nits. When the input maximum brightness value DBVI is changed, the gray voltage generator 15 can provide different gray voltages DVs in response to the same gray value, and thus the light luminance of the pixel changes.

[0057] The data distributor 16 can selectively couple the data output lines DO1, DO2, ... and the data lines DL1, DL2, DL3, DL4, ... to each other. The number of data lines DL1, DL2, DL3, DL4, ... can be greater than the number of data output lines DO1, DO2, ... For example, the number of data lines DL1, DL2, DL3, DL4, ... can correspond to a multiple of the data output lines DO1, DO2, ... The data distributor 16 can be a demultiplexer. The data lines DL1, DL2, DL3, DL4, ... can extend in a first direction DR1. The first direction DR1 and the second direction DR2 can be different directions. For example, the first direction DR1 and the second direction DR2 can be orthogonal to each other.

[0058] For example, the ratio of the data output lines DO1, DO2, ... to the data lines DL1, DL2, DL3, DL4, ... may be 1:2. The data distributor 16 may alternately couple the data output lines DO1, DO2, ... to the odd-numbered data lines or the even-numbered data lines. For example, the data distributor 16 may couple the data output lines DO1, DO2, ... to the first data lines DL1, DL3, ... during a first period, couple the data output lines DO1, DO2, ... to the second data lines DL2, DL4, ... during a second period, couple the data output lines DO1, DO2, ... to the first data lines DL1, DL3, ... during a third period, and couple the data output lines DO1, DO2, ... to the second data lines DL2, DL4, ... during a fourth period.

[0059] For example, the ratio of the data output lines DO1, DO2, ... to the data lines DL1, DL2, DL3, DL4, ... may be 1:3. This will be referred to later. Figures 13 to 15 Describe in detail.

[0060] The data compensator 17 may generate a gray value GVs3 by compensating the received gray value GVs2 received from the data driver 12. The gray value GVs2 may be a gray value before the line crosstalk defect is compensated, and the gray value GVs3 may be a gray value after the line crosstalk defect is compensated.

[0061] In this embodiment, when the data compensator 17 compensates the received grayscale value GVs2 as the compensated grayscale value GVs3, the input maximum brightness value DBVI may be further used. When the grayscale value GVs2 and the input maximum brightness value DBVI are provided, the data voltage of the corresponding image frame can be obtained, and thus the data compensator 17 can more accurately compensate for the line crosstalk defect. In another embodiment, the data compensator 17 may refer to another value instead of the input maximum brightness value DBVI to obtain the data voltage of the corresponding image frame.

[0062] The data compensator 17 can compensate the grayscale value GVs2 of the current pixel row by using the load difference between the load value of the previous pixel row and the load value of the current pixel row. The data driver 12 can perform digital-to-analog conversion on the compensated grayscale value GVs3 so that the data voltage of the current pixel row is also compensated. In another embodiment, the data compensator 17 can directly compensate the data voltage of the current pixel row by using the load difference between the load value of the previous pixel row and the load value of the current pixel row.

[0063] A pixel row may refer to pixels coupled to the same scan line. That is, a previous pixel row may refer to pixels coupled to a previous scan line supplied with a scan signal having an on-level at a previous moment. A current pixel row may refer to pixels coupled to a current scan line supplied with a scan signal having an on-level at a current moment. The previous moment and the current moment may differ from each other by one horizontal period. One horizontal period may be the minimum interval between rising moments of scan signals in adjacent scan lines.

[0064] For example, the data compensator 17 may compensate the third data voltage and the fourth data voltage based on a first load difference between the first data voltage and the third data voltage and a second load difference between the second data voltage and the fourth data voltage, respectively.

[0065] Figure 2 and Figure 3 is a diagram illustrating a gray voltage generator according to an embodiment of the present disclosure.

[0066] For example, when the image frame includes three primary colors (red, green, and blue), the grayscale voltage generator 15 needs to provide a grayscale voltage for each of the three primary colors. The grayscale voltage generator 15 may include a first grayscale voltage generator 15R for the first color, a second grayscale voltage generator (not shown) for the second color, and a third grayscale voltage generator (not shown) for the third color. Hereinafter, the first grayscale voltage generator 15R will be described. The second grayscale voltage generator and the third grayscale voltage generator may basically have the same configuration as the first grayscale voltage generator 15R, and therefore, repeated descriptions will be omitted.

[0067] refer to Figure 2 The first gray voltage generator 15R may include a selection value provider 1511, a gray voltage output portion 1512, resistor strings RS1 to RS11, multiplexers MX1 to MX12, and resistors R1 to R10. The first gray voltage generator 15R may generate first gray voltages RV0, RV1, RV2, RV3, RV4, ..., RV253, RV254, and RV255.

[0068] The selection value provider 1511 may provide a selection value to the multiplexers MX1 to MX12 in response to the input maximum brightness value DBVI. The selection value according to the input maximum brightness value DBVI may be pre-stored in a memory device (e.g., a device such as a register in the selection value provider 1511 or connected to the selection value provider 1511).

[0069] The resistor string RS1 can generate an intermediate voltage between a first high voltage applied to the first high voltage terminal VH1 and a second low voltage applied to the first low voltage terminal VL1. The multiplexer MX1 ​​can output a reference voltage VT by selecting one of the intermediate voltages provided from the resistor string RS1 according to a selection value. The multiplexer MX2 can output a 255 grayscale voltage RV255 by selecting one of the intermediate voltages provided from the resistor string RS1 according to a selection value.

[0070] The resistor string RS11 may generate an intermediate voltage between the reference voltage VT and the 255 gray voltage RV255. The multiplexer MX12 may output the 203 gray voltage RV203 by selecting one of the intermediate voltages provided from the resistor string RS11 according to a selection value.

[0071] The resistor string RS10 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV203. The multiplexer MX11 may output a gray voltage RV151 by selecting one of the intermediate voltages provided from the resistor string RS10 according to a selection value.

[0072] The resistor string RS9 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV151. The multiplexer MX10 may output the gray voltage RV87 by selecting one of the intermediate voltages provided from the resistor string RS9 according to a selection value.

[0073] The resistor string RS8 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV87. The multiplexer MX9 may output the gray voltage RV51 by selecting one of the intermediate voltages provided from the resistor string RS8 according to a selection value.

[0074] The resistor string RS7 may generate an intermediate voltage between the reference voltage VT and the gray voltage RV51. The multiplexer MX8 may output the gray voltage RV35 by selecting one of the intermediate voltages provided from the resistor string RS7 according to a selection value.

[0075] The resistor string RS6 may generate an intermediate voltage between the reference voltage VT and the 35 gray voltage RV35. The multiplexer MX7 may output the 23 gray voltage RV23 by selecting one of the intermediate voltages provided from the resistor string RS6 according to a selection value.

[0076] The resistor string RS5 may generate an intermediate voltage between the reference voltage VT and the 23 gray voltage RV23. The multiplexer MX6 may output the 11 gray voltage RV11 by selecting one of the intermediate voltages provided from the resistor string RS5 according to a selection value.

[0077] The resistor string RS4 may generate an intermediate voltage between the first high voltage and the 11 gray voltage RV11. The multiplexer MX5 may output the 7 gray voltage RV7 by selecting one of the intermediate voltages provided from the resistor string RS4 according to a selection value.

[0078] The resistor string RS3 may generate an intermediate voltage between the first high voltage and the 7 gray voltage RV7. The multiplexer MX4 may output the 1 gray voltage RV1 by selecting one of the intermediate voltages provided from the resistor string RS3 according to a selection value.

[0079] The resistor string RS2 may generate an intermediate voltage between the first high voltage and the 1 gray voltage RV1. The multiplexer MX3 may output the 0 gray voltage RV0 by selecting one of the intermediate voltages provided from the resistor string RS2 according to a selection value.

[0080] The grayscales 0, 1, 7, 11, 23, 35, 51, 87, 151, 203, and 255 described above may be referred to as reference grayscales. Furthermore, the grayscale voltages RV255, RV0, RV1, RV7, RV11, RV23, RV35, RV51, RV87, RV151, and RV203 generated by multiplexers MX2 to MX12 may be referred to as reference grayscale voltages. The number of reference grayscales and the number of grayscales corresponding to the reference grayscales may be set differently depending on the product. Hereinafter, for ease of description, grayscales 0, 1, 7, 11, 23, 35, 51, 87, 151, 203, and 255 are described as reference grayscales.

[0081] The gray voltage output portion 1512 may generate first gray voltages RV0 to RV255 by dividing the reference gray voltages RV0, RV1, RV7, RV11, RV23, RV35, RV51, RV87, RV151, RV203, and RV255. For example, the gray voltage output portion 1512 may generate first gray voltages RV2 to RV6 by dividing the reference gray voltages RV1 and RV7.

[0082] refer to Figure 3 , which illustrates white light curves WC1, WC2, ..., WC(k-1), and WCk of output luminance relative to grayscale values. Here, k may be an integer greater than 0.

[0083] The maximum brightness values ​​of the white light curves WC1 to WCk may be different from each other. For example, the maximum brightness value of the white light curve WC1 (eg, 4 nits) may be the lowest, and the maximum brightness value of the white light curve WCk (eg, 1200 nits) may be the highest.

[0084] In order to generate white light, it is assumed that pixels PX of all colors receive data voltages having the same grayscale.

[0085] exist Figure 3 The dotted points illustrated on the white light curves WC1 to WCk shown in may correspond to selection values ​​pre-stored in the selection value provider 1511 described above. A more accurate white light curve may be directly represented as the number of selection values ​​increases. However, in order to increase the number of selection values, physical devices such as multiplexers, registers, etc. corresponding to the increased number of selection values ​​are further required, and therefore there are limitations. Therefore, only selection values ​​regarding the above-mentioned reference gray voltages may be pre-stored and used, and other gray voltages may be generated by dividing the reference gray voltages. In addition, for the same reason, selection values ​​regarding some maximum brightness values ​​(e.g., reference maximum brightness values) between 4 nits and 1200 nits may be pre-stored and used, and other maximum brightness values ​​may be generated by interpolating the selection values.

[0086] The pre-stored selection values ​​can be set for each individual product through multiple-time programming (MTP). That is, the selection values ​​can be set and stored through experimental values ​​obtained through repeated measurements to find the conditions under which white light with desired brightness can be emitted relative to the grayscale value.

[0087] Figure 4 is a diagram illustrating a data driver according to an embodiment of the present disclosure.

[0088] refer to Figure 4 , the data driver 12 according to an embodiment of the present disclosure may include a shift register SHR, a sampling latch SLU, a first holding latch HLU1 , a second holding latch HLU2 , a digital-to-analog converter DAU, and a buffer BFU.

[0089] The data control signal DCS received from the timing controller 11 may include a source shift clock SSC, a source start pulse SSP, source output enable signals SOE1 and SOE2 , and the like.

[0090] The shift register SHR may sequentially generate sampling signals while shifting a source start pulse SSP in response to a source shift clock SSC.

[0091] The sampling latches SLU may sequentially receive gray values ​​GVs1 for an image frame from the timing controller 11. The sampling latches SLU may store the gray values ​​GVs1 sequentially provided from the timing controller 11 in corresponding sampling latches in response to sampling signals sequentially supplied from the shift register SHR.

[0092] The first holding latch HLU1 can receive and store the grayscale value GVs1 stored in the sampling latch in response to the first source output enable signal SOE1 being input. The data compensator 17 can receive the grayscale value GVs2 output from the first holding latch HLU1 and the input maximum brightness value DBVI output from the timing controller 11, and output a compensated grayscale value GVs3.

[0093] The second holding latch HLU2 may store the compensated gray value GVs3 output from the data compensator 17 in response to the second source output enable signal SOE2 being input.

[0094] The digital-to-analog converter may perform analog-to-digital conversion on the grayscale value GVs3 compensated by the data compensator 17 by using the grayscale voltage DVs provided from the grayscale voltage generator 15 .

[0095] Each of the buffers BFU can receive the output of the digital-to-analog converter DAU as a data voltage and apply the data voltage to the corresponding data output line. For example, each of the buffers BFU can be an operational amplifier. Each of the buffers BFU can be a voltage follower to apply the output of the digital-to-analog converter DAU as a data voltage to the corresponding data output line.

[0096] Figure 5 and Figure 6 is a diagram illustrating a data distributor and pixels according to an embodiment of the present disclosure.

[0097] refer to Figure 5 Data distributor 16 may include first transistors M11, M12, ... connected to odd-numbered data lines and second transistors M21, M22, ... connected to even-numbered data lines. The gate electrodes of first transistors M11 and M12 may be coupled to a first control line CL1, the first electrodes of first transistors M11 and M12 may be coupled to data output lines DO1 and DO2, respectively, and the second electrodes of first transistors M11 and M12 may be coupled to first data lines (odd-numbered data lines: DL1, DL3, ...). The gate electrodes of second transistors M21 and M22 may be coupled to a second control line CL2, the first electrodes of second transistors M21 and M22 may be coupled to data output lines DO1 and DO2, respectively, and the second electrodes of second transistors M21 and M22 may be coupled to second data lines (even-numbered data lines: DL2, DL4, ...). For example, data distributor 16 may be a demultiplexer having an input-to-output ratio of 1:2.

[0098] The turn-on period of the first transistors M11 and M12 and the turn-on period of the second transistors M21 and M22 may not overlap with each other. The timing controller 11 may sequentially provide control signals having a turn-on level to the first control line CL1 and the second control line CL2, so that the first transistors M11 and M12 and the second transistors M21 and M22 are sequentially turned on.

[0099] For example, the number of first transistors M11 and M12 and the number of second transistors M21 and M22 may be the same. In addition, the number of first data lines DL1, DL3, ... (odd-numbered data lines) and the number of second data lines DL2, DL4, ... (even-numbered data lines) may be the same. The first data lines DL1 and DL3 and the second data lines DL2 and DL4 may be alternately arranged.

[0100] For example, the pixel 14 may include a plurality of pixels PX1, PX2, PX3, PX4, PX5, PX6, PX7, and PX8 arranged in a honeycomb structure. The first pixels PX1, PX2, PX5, and PX6 may be coupled to a first scan line SL1. The first pixels PX1, PX2, PX5, and PX6 may be arranged such that red, green, blue, and green colors are sequentially repeated along the extending direction of the first scan line SL1. The first pixels PX1, PX2, PX5, and PX6 may be coupled to different data lines DL1, DL2, DL3, and DL4.

[0101] In addition, the second pixels PX3, PX4, PX7, and PX8 can be coupled to the second scan line SL2. The second pixels PX3, PX4, PX7, and PX8 can be arranged so that blue, green, red, and green colors are sequentially repeated along the extension direction of the second scan line SL2. The second pixels PX3, PX4, PX7, and PX8 can be coupled to different data lines DL1, DL2, DL3, and DL4.

[0102] Red pixels and blue pixels may be coupled to the first data line DL1 to be sequentially repeated along the extending direction of the first data line DL1. Green pixels may be coupled to the second data lines DL2 and DL4 along the extending direction of the second data lines DL2 and DL4. Blue pixels and red pixels may be coupled to the first data line DL3 to be sequentially repeated along the extending direction of the first data line DL3.

[0103] refer to Figure 6 , an exemplary first pixel PX1 is illustrated. The other pixels PX2 to PX8 may have substantially the same configuration, and therefore, repeated descriptions will be omitted.

[0104] A gate electrode of the first transistor T1 may be coupled to the second electrode of the storage capacitor Cst, a first electrode of the first transistor T1 may be coupled to the first power line ELVDDL, and a second electrode of the first transistor T1 may be coupled to the anode of the light emitting diode LD. The first transistor T1 may be referred to as a driving transistor.

[0105] A gate electrode of the second transistor T2 may be coupled to the first scan line SL1, a first electrode of the second transistor T2 may be coupled to the first data line DL1, and a second electrode of the second transistor T2 may be coupled to the second electrode of the storage capacitor Cst. The second transistor T2 may be referred to as a scan transistor.

[0106] A first electrode of the storage capacitor Cst may be coupled to the first power line ELVDDL, and a second electrode of the storage capacitor Cst may be coupled to the gate electrode of the first transistor T1.

[0107] An anode of the light emitting diode LD may be coupled to the second electrode of the first transistor T1 , and a cathode of the light emitting diode LD may be coupled to the second power line ELVSSL.

[0108] During the emission period of the light emitting diode LD, the first power voltage applied to the first power line ELVDDL may be higher than the second power voltage applied to the second power line ELVSSL.

[0109] Although the transistors T1, T2, M11, M12, M21 and M22 are implemented with P-type transistors, those skilled in the art may replace at least one of the transistors T1, T2, M11, M12, M21 and M22 with an N-type transistor by inverting the phase of the signal.

[0110] Figure 7 is a diagram illustrating a driving method of a display device according to an embodiment of the present disclosure.

[0111] First, at time t1a, a first control signal having an on-level (low level) may be applied to the first control line CL1. Consequently, the first transistors M11 and M12 are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL3 are coupled to each other. The data driver 12 may output a first data voltage PXD1 to the first data output line DO1 and a first data voltage PXD5 to the second data output line DO2. Consequently, the first data line DL1 may be charged with the first data voltage PXD1, and the first data line DL3 may be charged with the first data voltage PXD5. The period from time t1a to the moment when the first control signal having an off-level is applied may be referred to as a first period.

[0112] Next, at time t2a, a second control signal having an on-level may be applied to the second control line CL2. Consequently, the second transistors M21 and M22 are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL4 are coupled to each other. The second data line DL2 may be charged with the second data voltage PXD2, and the second data line DL4 may be charged with the second data voltage PXD6. The period from time t2a to the time when the second control signal having an off-level is applied may be referred to as a second period.

[0113] Next, at time t3a, a first scan signal having an on-level may be applied to the first scan line SL1. Thus, the first pixels PX1, PX2, PX5, and PX6 may receive the data voltages charged in the first data lines DL1 and DL3 and the second data lines DL2 and DL4. In this embodiment, time t3a may overlap with the second period.

[0114] Next, at time t4a, a first control signal having an on-level may be applied to the first control line CL1. Consequently, the first transistors M11 and M12 are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL3 are coupled to each other. The first data line DL1 may be charged with a third data voltage PXD3, and the first data line DL3 may be charged with a third data voltage PXD7. The period from time t4a to the time when the first control signal having an off-level is applied may be referred to as a third period.

[0115] Next, at time t5a, a second control signal having an on-level may be applied to the second control line CL2. Consequently, the second transistors M21 and M22 are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL4 are coupled to each other. The second data line DL2 may be charged with a fourth data voltage PXD4, and the second data line DL4 may be charged with a fourth data voltage PXD8. The period from time t5a to the time when the second control signal having an off-level is applied may be referred to as a fourth period.

[0116] Next, at time t6a, a second scan signal having an on level may be applied to the second scan line SL2. Thus, the second pixels PX3, PX4, PX7, and PX8 may receive the data voltages charged in the first data lines DL1 and DL3 and the second data lines DL2 and DL4. In this embodiment, time t6a may overlap with the fourth period.

[0117] Figures 8 to 11 is a diagram illustrating a line crosstalk defect that may occur when a data distributor is used.

[0118] For example, pixels coupled to the first to p-1 scan lines SL(p-1) may receive a data voltage corresponding to a grayscale of 128. In the next scan period, some of the pixels coupled to the p-th scan line SLp may receive a data voltage corresponding to a grayscale of 128, and the other pixels may receive a data voltage corresponding to a grayscale of 0.

[0119] In such Figure 8In the ideal case shown in , the pixel PXpu coupled to the scan line SLp and the data line DLu can emit light of 128 gray levels. In addition, the pixel PXp(u+1) coupled to the scan line SLp and the data line DL(u+1) can emit light of 128 gray levels. For example, the pixel PXpu can be a red pixel or a blue pixel. For example, the pixel PXp(u+1) can be a green pixel. Here, each of p and u is an integer greater than 0.

[0120] However, when data compensation is not performed, the pixel PXp(u+1) emits light of a grayscale higher than 128 grayscale, as shown in FIG. Figure 9 As shown in , and therefore, a green bright line may be generated. The grayscale change of the pixel PXpu may be smaller than the grayscale change of the pixel PXp(u+1). The bright line may be caused by a line crosstalk defect caused by the data line DLv and DL(v+1) where the data voltage suddenly changes from 128 grayscale to 0 grayscale. Here, v can be an integer greater than 0.

[0121] For example, pixels coupled to the q-1th scan line SL(q-1) may receive a data voltage corresponding to grayscale 128 or a data voltage corresponding to grayscale 0. In the next scan period, all pixels coupled to the qth scan line SLq may receive a data voltage corresponding to grayscale 128.

[0122] In such Figure 8 In the ideal case shown in , the pixel PXqu coupled to the scan line SLq and the data line DLu can emit light of 128 gray levels. In addition, the pixel PXq(u+1) coupled to the scan line SLq and the data line DL(u+1) can emit light of 128 gray levels. Here, q is an integer greater than 0.

[0123] However, when data compensation is not performed, the pixel PXq(u+1) emits light of a grayscale lower than 128 grayscale, as shown in FIG. Figure 9 As shown in , and therefore, dark lines may be generated. The grayscale change of pixel PXqu may be smaller than the grayscale change of pixel PXq(u+1). Dark lines may be caused by line crosstalk defects caused by the data lines DLv and DL(v+1) where the data voltage suddenly changes from 0 grayscale to 128 grayscale.

[0124] refer to Figure 10 and Figure 11 , the causes of the line crosstalk defect will be described in detail.

[0125] refer to Figure 10 , the reason why a green bright line is generated in a pixel coupled to the p-th scan line SLp after reception of a data voltage of a pixel coupled to the p-th scan line SL(p-1) is completed will be described.

[0126] First, at time t1b, a first control signal having an on level may be supplied to the first control line CL1. The data voltage applied to the vth data line DLv may suddenly increase (change from 128 gray to 0 gray).

[0127] refer to Figure 11 , parasitic capacitance Cpr may be formed between the first power line ELVDDL and the data line DLs. The first power line ELVDDL may be commonly coupled to all pixels PX. Therefore, instantaneous voltage fluctuations of the first power line ELVDDL may have an impact on all data lines DLs.

[0128] When the data voltage of the data line DLv suddenly increases, the first power voltage of the first power line ELVDDL may increase instantaneously while parasitic current flows from the data driver 12 to the first power source 18. The data voltages of the data lines DLu and DL(u+1) may also increase instantaneously due to coupling of the parasitic capacitance Cpr.

[0129] The data line DLu can be in a state where it is coupled to the data output line, and the data line DL(u+1) can be in a floating state where it is not coupled to the data output line. Therefore, the data voltage of the data line DLu can be quickly stabilized (decreased) to a voltage V128 corresponding to grayscale 128. Since the data line DL(u+1) is in a floating state, the wavelength of the data voltage of the data line DL(u+1) can be similar to the wavelength of the first power supply voltage.

[0130] The first power supply 18 may be a DC-DC converter that supplies a first power supply voltage to the first power line ELVDDL. Because the first power supply 18 includes a feedback circuit, it can maintain the first power supply voltage at voltage V1. Therefore, the first power supply voltage can stabilize (or decrease) to voltage V1 at time t2b. The sudden change in the first power supply voltage at time t2b may be caused by the supply of a first control signal having an off level.

[0131] At time t2b, the data voltages of the data lines DLu and DL(u+1) may be less than the voltage V128 corresponding to grayscale 128. This is caused by the parasitic current increasing the voltage Vcpr charged in the parasitic capacitor Cpr. Due to the influence of the data driver 12, the voltage reduction width VD11 of the data line DLu may be greater than the voltage reduction width VD21 of the data line DL(u+1).

[0132] At time t3b, the second control signal having the on level may be supplied to the second control line CL2. The data voltage applied to the v+1th data line DL(v+1) may suddenly increase (change from 128 gray to 0 gray).

[0133] When the data voltage of the data line DL(v+1) increases rapidly, the first power voltage of the first power line ELVDDL may increase instantaneously while parasitic current flows from the data driver 12 to the first power source 18. The data voltages of the data lines DLu and DL(u+1) may also increase instantaneously due to coupling of the parasitic capacitance Cpr.

[0134] The data line DLu can be in a floating state where it is not coupled to the data output line, and the data line DL(u+1) can be in a state where it is coupled to the data output line. Therefore, the data voltage of the data line DL(u+1) can be quickly stabilized (decreased) to a voltage V128 corresponding to grayscale 128. Since the data line DLu is in a floating state, the waveform of the data voltage of the data line DLu can be similar to the waveform of the first power supply voltage.

[0135] Although the second control signal with an off level is supplied, the first power supply voltage may not change rapidly, unlike at time t2b. This is caused by the scan signal with an on level being supplied to the scan line SLp at time t4b before the second control signal with an off level is supplied. The data lines DLu and DL(u+1) are coupled to the pixels PXpu and PXp(u+1), respectively, by the scan signal with an off level, and therefore, the first power supply voltage does not decrease rapidly.

[0136] Therefore, at time t4b, the data voltage of the data line DLu may be similar to voltage V128 corresponding to grayscale 128. That is, referring to time t2b, the voltage increase width VD12 at time t4b may be mostly offset by the voltage decrease width VD11.

[0137] On the other hand, referring to the time t2b, the data voltage of the data line DL(u+1) decreases by the voltage decrease width VD22 at the time t4b and thus may become a voltage V4 lower than the voltage V3.

[0138] Therefore, at time t4b, the pixel PXpu may receive a voltage V128 corresponding to grayscale 128, and the pixel PXp(u+1) may receive a voltage V4 corresponding to a grayscale higher than grayscale 128. Therefore, a green bright line may be generated as the color of the pixel PXp(u+1).

[0139] Figure 12 is a diagram illustrating a data compensator according to an embodiment of the present disclosure.

[0140] The data compensator 17 according to an embodiment of the present disclosure may include a lookup table 169, a data voltage value extractor 170, a first load calculator 171, a second load calculator 172, a first delay section 173, a second delay section 174, a first load difference calculator 175, a second load difference calculator 176, a crosstalk calculator 177 and a crosstalk compensator 178.

[0141] The data compensator 17 may compensate the third data voltages PXD3 and PXD7 and the fourth data voltages PXD4 and PXD8 based on a first load difference LDD1 between the first data voltages PXD1 and PXD5 and the third data voltages PXD3 and PXD7 and a second load difference LDD2 between the second data voltages PXD2 and PXD6 and the fourth data voltages PXD4 and PXD8.

[0142] The lookup table 169 may pre-store data voltage values ​​corresponding to input maximum brightness values ​​and grayscale values. The lookup table 169 may be a separate memory device or exist as data in a part of another memory device.

[0143] The data voltage value extractor 170 can receive the input maximum brightness value DBVI from the timing controller 11 and the grayscale value GVs2 from the data driver 12, and extract the data voltage value VVs2 corresponding to the input maximum brightness value DBVI and the grayscale value GVs2 from the lookup table 169. As described above, the grayscale voltage generator 15 can output various grayscale voltages DVs for each grayscale, such as the first grayscale voltages RV0, RV1, RV2, RV3, RV4, ..., RV253, RV254, and RV255, according to the input maximum brightness value DBVI. Therefore, in this embodiment, crosstalk is compensated based on the data voltage value VVs2, so that crosstalk compensation is performed more accurately than when crosstalk is compensated based on the grayscale value GVs2.

[0144] The first load calculator 171 may calculate the load value by using some of the data voltage values ​​VVs2. For example, the first load calculator 171 may calculate the load value by adding data voltage values ​​corresponding to the data voltages supplied to the first data lines DL1 and DL3 among the data voltage values ​​VVs2.

[0145] Since the data voltage value VVs2 is sequentially supplied in units of pixel rows, the first load calculator 171 can sequentially calculate and output load values. Figure 7, the first load calculator 171 may first calculate and output the load values ​​of the first data voltages PXD1 and PXD5. Next, the first load calculator 171 may calculate and output the load values ​​of the third data voltages PXD3 and PXD7. That is, the first load calculator 171 may sequentially output the load values ​​of the first data voltages PXD1 and PXD5 and the load values ​​of the third data voltages PXD3 and PXD7.

[0146] The second load calculator 172 may calculate the load value by using some of the data voltage values ​​VVs2. For example, the second load calculator 172 may calculate the load value by adding data voltage values ​​corresponding to the data voltages supplied to the second data lines DL2 and DL4 among the data voltage values ​​VVs2.

[0147] Since the data voltage value VVs2 is sequentially supplied in units of pixel rows, the second load calculator 172 can sequentially calculate and output load values. Figure 7 , the second load calculator 172 may first calculate and output the load values ​​of the second data voltages PXD2 and PXD6. Next, the second load calculator 172 may calculate and output the load values ​​of the fourth data voltages PXD4 and PXD8. That is, the second load calculator 172 may sequentially output the load values ​​of the second data voltages PXD2 and PXD6 and the load values ​​of the fourth data voltages PXD4 and PXD8.

[0148] In an embodiment, each of the load values ​​output from the first load calculator 171 and the second load calculator 172 may be the most significant bit (MSB) of a value obtained by adding the data voltage values. That is, only some bits corresponding to the MSB containing the largest amount of information are transmitted, so that the capacity (number of bits) of the registers required for the first delay section 173 and the second delay section 174 can be minimized.

[0149] The first delay unit 173 can output the load value of the first data voltages PXD1 and PXD5 after a predetermined delay time. For example, the first delay unit 173 can be configured as a delay register. The capacity of the register can correspond to the number of bits of the load value. The predetermined delay time can be one horizontal period.

[0150] The second delay unit 174 can output the load value of the second data voltages PXD2 and PXD6 after a predetermined delay time. For example, the second delay unit 174 can be configured as a delay register. The capacity of the register can correspond to the number of bits of the load value. The predetermined delay time can be one horizontal period.

[0151] The first load difference calculator 175 can output a first load difference LDD1 based on the output LD1n of the first load calculator 171 and the output LD1(n-1) of the first delay unit 173. For example, the output LD1n of the first load calculator 171 can be the load value of the third data voltages PXD3 and PXD7. The output LD1(n-1) of the first delay unit 173 can be the load value of the first data voltages PXD1 and PXD5. Therefore, the first load difference calculator 175 can calculate the first load difference LDD1 between the first data voltages PXD1 and PXD5 and the third data voltages PXD3 and PXD7.

[0152] The second load difference calculator 176 can output a second load difference LDD2 based on the output LD2n of the second load calculator 172 and the output LD2(n-1) of the second delay unit 174. For example, the output LD2n of the second load calculator 172 can be the load value of the fourth data voltages PXD4 and PXD8. The output LD2(n-1) of the second delay unit 174 can be the load value of the second data voltages PXD2 and PXD6. Therefore, the second load difference calculator 176 can calculate the second load difference LDD2 between the second data voltages PXD2 and PXD6 and the fourth data voltages PXD4 and PXD8.

[0153] The crosstalk calculator 177 can calculate a first crosstalk amount XT1 with respect to the third data voltages PXD3 and PXD7 and a second crosstalk amount XT2 with respect to the fourth data voltages PXD4 and PXD8 based on the first load difference LDD1 and the second load difference LDD2. For example, the first crosstalk amount XT1 and the second crosstalk amount XT2 can be calculated as shown in the following formula 1.

[0154] Formula 1

[0155]

[0156] C11 may be a first weight value, C12 may be a second weight value, C21 may be a third weight value, and C22 may be a fourth weight value.

[0157] For example, the first crosstalk amount XT1 may be a value obtained by adding the first load difference LDD1 to which the first weight value C11 is applied and the second load difference LDD2 to which the second weight value C12 is applied. In addition, the second crosstalk amount XT2 may be a value obtained by adding the first load difference LDD1 to which the third weight value C21 is applied and the second load difference LDD2 to which the fourth weight value C22 is applied.

[0158] The sign of each of the first weight value C11, the third weight value C21, and the fourth weight value C22 may be different from the sign of the second weight value C12. For example, each of the first weight value C11, the third weight value C21, and the fourth weight value C22 may be a positive number, and the second weight value C12 may be a negative number. For example, Figure 10 The magnitude and sign of the first weight value C11 are predetermined based on the voltage reduction width VD11 shown in FIG. Figure 10 The voltage increase width VD12 shown in FIG is used to predetermine the size and sign of the second weight value C12, which can be based on Figure 10 The magnitude and sign of the third weight value C21 are predetermined by the voltage reduction width VD21 shown in FIG. Figure 10 The voltage reduction width VD22 shown in FIG2 is used to predetermine the size and sign of the fourth weight value C22.

[0159] The crosstalk compensator 178 may compensate the third data voltages PXD3 and PXD7 based on the first crosstalk amount XT1 and compensate the fourth data voltages PXD4 and PXD8 based on the second crosstalk amount XT2. The grayscale value GVs3 output from the crosstalk compensator 178 may include the compensated third data voltages PXD3 and PXD7 and the compensated fourth data voltages PXD4 and PXD8.

[0160] For example, the crosstalk compensator 178 may increase the third data voltages PXD3 and PXD7 as the first crosstalk amount XT1 increases, and may increase the fourth data voltages PXD4 and PXD8 as the second crosstalk amount increases.

[0161] For example, in Figure 10 In the case shown in , the first crosstalk amount XT1 may be relatively small, and the second crosstalk amount XT2 may be relatively large. Therefore, the crosstalk compensator 178 may suppress the green component of the bright line by increasing the fourth data voltages PXD4 and PXD8.

[0162] Therefore, the display device 10 according to the present disclosure may minimize a line crosstalk defect that may occur when the data distributor 16 is used.

[0163] Figure 13 is a diagram illustrating a data distributor and pixels according to another embodiment of the present disclosure.

[0164] refer to Figure 13The data distributor 16' may include first transistors M11' and M12', second transistors M21' and M22', and third transistors M31' and M32'. Gate electrodes of the first transistors M11' and M12' may be coupled to the first control line CL1, first electrodes of the first transistors M11' and M12' may be coupled to the data output lines DO1 and DO2, and second electrodes of the first transistors M11' and M12' may be coupled to the first data lines DL1 and DL4. Gate electrodes of the second transistors M21' and M22' may be coupled to the second control line CL2, first electrodes of the second transistors M21' and M22' may be coupled to the data output lines DO1 and DO2, and second electrodes of the second transistors M21' and M22' may be coupled to the second data lines DL2 and DL5. Gate electrodes of the third transistors M31' and M32' may be coupled to the third control line CL3, first electrodes of the third transistors M31' and M32' may be coupled to the data output lines DO1 and DO2, and second electrodes of the third transistors M31' and M32' may be coupled to the third data lines DL3 and DL6. For example, the data distributor 16' may be a demultiplexer having an input-to-output ratio of 1:3.

[0165] The on-periods of the first transistors M11' and M12', the on-periods of the second transistors M21' and M22', and the on-periods of the third transistors M31' and M32' may not overlap with each other. The timing controller 11 may provide a control signal having an on-level to the first control line CL1, the second control line CL2, and the third control line CL3, so that the first transistors M11' and M12', the second transistors M21' and M22', and the third transistors M31' and M32' are sequentially turned on.

[0166] For example, the number of first transistors M11' and M12', the number of second transistors M21' and M22', and the number of third transistors M31' and M32' may be the same. In addition, the number of first data lines DL1 and DL4, the number of second data lines DL2 and DL5, and the number of third data lines DL3 and DL6 may be the same. The first data lines DL1 and DL4, the second data lines DL2 and DL5, and the third data lines DL3 and DL6 may be sequentially arranged.

[0167] For example, the pixels 14' may include pixels PX1', PX2', PX3', PX4', PX5', PX6', PX7', PX8', PX9', PX10', PX11', and PX12' arranged in an RGB stripe structure. The first pixels PX1', PX2', PX5', PX7', PX8', and PX11' may be coupled to a first scan line SL1. The first pixels PX1', PX2', PX5', PX7', PX8', and PX11' may be configured such that red, green, and blue colors are sequentially repeated along the extending direction of the first scan line SL1. The first pixels PX1', PX2', PX5', PX7', PX8', and PX11' may be coupled to different data lines DL1, DL2, DL3, DL4, DL5, and DL6, respectively.

[0168] In addition, the second pixels PX3', PX4', PX6', PX9', PX10', and PX12' can be coupled to the second scan line SL2. The second pixels PX3', PX4', PX6', PX9', PX10', and PX12' can be arranged so that red, green, and blue colors are sequentially repeated along the extending direction of the second scan line SL2. The second pixels PX3', PX4', PX6', PX9', PX10', and PX12' can be coupled to different data lines DL1 to DL6, respectively.

[0169] The red pixels may be coupled to the first data lines DL1 and DL4 to be sequentially repeated along the extending direction of the first data lines DL1 and DL4. The green pixels may be coupled to the second data lines DL2 and DL5 to be sequentially repeated along the extending direction of the second data lines DL2 and DL5. The blue pixels may be coupled to the third data lines DL3 and DL6 to be sequentially repeated along the extending direction of the third data lines DL3 and DL6.

[0170] The configuration of each of the pixels PX1' to PX12' may be the same as Figure 6 The configuration shown in is the same as that shown in , and therefore, repeated description will be omitted.

[0171] Figure 14 is a diagram illustrating a driving method of a display device according to another embodiment of the present disclosure.

[0172] First, at time t1c, a first control signal having an on-level (low level) may be applied to the first control line CL1. Consequently, the first transistors M11' and M12' are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL4 are coupled to each other. The data driver 12' may output a first data voltage PXD1' to the first data output line DO1 and a first data voltage PXD7' to the second data output line DO2. Consequently, the first data line DL1 may be charged with the first data voltage PXD1', and the first data line DL4 may be charged with the first data voltage PXD7'. The period from time t1c to the moment the first control signal having an off-level is applied may be referred to as a first period.

[0173] Next, at time t2c, a second control signal having an on-level may be applied to the second control line CL2. Consequently, the second transistors M21' and M22' are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL5 are coupled to each other. The second data line DL2 may be charged with the second data voltage PXD2', and the second data line DL5 may be charged with the second data voltage PXD8'. The period from time t2c to the time when the second control signal having an off-level is applied may be referred to as a second period.

[0174] Next, at time t3c, a third control signal having an on-level may be applied to the third control line CL3. Consequently, the third transistors M31' and M32' are turned on, the first data output line DO1 and the third data line DL3 are coupled to each other, and the second data output line DO2 and the third data line DL6 are coupled to each other. The third data line DL3 may be charged with a fifth data voltage PXD5', and the third data line DL6 may be charged with a fifth data voltage PXD11'. The period from time t3c to the time when the third control signal having an off-level is applied may be referred to as a fifth period.

[0175] Next, at time t4c, a first scan signal having an on-level may be applied to the first scan line SL1. Thus, the first pixels PX1', PX2', PX5', PX7', PX8', and PX11' may receive the data voltages charged in the first data lines DL1 and DL4, the second data lines DL2 and DL5, and the third data lines DL3 and DL6, respectively. In this embodiment, time tc4 may overlap with the fifth period.

[0176] Next, at time t5c, a first control signal having an on-level may be applied to the first control line CL1. Consequently, the first transistors M11' and M12' are turned on, the first data output line DO1 and the first data line DL1 are coupled to each other, and the second data output line DO2 and the first data line DL4 are coupled to each other. The first data line DL1 may be charged with a third data voltage PXD3', and the first data line DL4 may be charged with a third data voltage PXD9'. The period from time t5c to the time when the first control signal having an off-level is applied may be referred to as a third period.

[0177] Next, at time t6c, a second control signal having an on-level may be applied to the second control line CL2. Consequently, the second transistors M21' and M22' are turned on, the first data output line DO1 and the second data line DL2 are coupled to each other, and the second data output line DO2 and the second data line DL5 are coupled to each other. The second data line DL2 may be charged with the fourth data voltage PXD4', and the second data line DL5 may be charged with the fourth data voltage PXD10'. The period from time t6c to the time when the second control signal having an off-level is applied may be referred to as a fourth period.

[0178] Next, at time t7c, a third control signal having an on-level may be applied to the third control line CL3. Consequently, the third transistors M31' and M32' are turned on, the first data output line DO1 and the third data line DL3 are coupled to each other, and the second data output line DO2 and the third data line DL6 are coupled to each other. The third data line DL3 may be charged with the sixth data voltage PXD6', and the third data line DL6 may be charged with the sixth data voltage PXD12'. The period from time t7c to the time when the third control signal having an off-level is applied may be referred to as a sixth period.

[0179] Next, at time t8c, a second scan signal having an on-level may be applied to the second scan line SL2. Thus, the second pixels PX3', PX4', PX6', PX9', PX10', and PX12' may receive the data voltages charged in the first data lines DL1 and DL4, the second data lines DL2 and DL5, and the third data lines DL3 and DL6. In this embodiment, time t8c may overlap with the sixth period.

[0180] Figure 15 is a diagram illustrating a data compensator according to another embodiment of the present disclosure.

[0181] The data compensator 17' according to another embodiment of the present disclosure may include a lookup table 169, a data voltage value extractor 170, a first load calculator 171, a second load calculator 172, a third load calculator 179, a first delay section 173, a second delay section 174, a third delay section 180, a first load difference calculator 175, a second load difference calculator 176, a third load difference calculator 181, a crosstalk calculator 177', and a crosstalk compensator 178'. Figure 12 The parts of the data compensator 17 shown in FIG.

[0182] The data compensator 17' may compensate for the third data voltages PXD3' and PXD9', the fourth data voltages PXD4' and PXD10', and the sixth data voltages PXD6' and PXD12' based on the first load difference LDD1, the second load difference LDD2, and the third load difference LDD3 between the fifth data voltages PXD5' and PXD11' and the sixth data voltages PXD6' and PXD12'.

[0183] The third load calculator 179 may calculate the load value by using some of the data voltage values ​​VVs2. For example, the third load calculator 179 may calculate the load value by adding data voltage values ​​corresponding to the data voltages supplied to the third data lines DL3 and DL6 among the data voltage values ​​VVs2.

[0184] Since the data voltage value VVs2 is sequentially supplied in units of pixel rows, the third load calculator 179 can sequentially calculate and output load values. Figure 14 , the third load calculator 179 may calculate and output the load values ​​of the fifth data voltages PXD5' and PXD11'. Next, the third load calculator 179 may calculate and output the load values ​​of the sixth data voltages PXD6' and PXD12'. That is, the third load calculator 179 may sequentially output the load values ​​of the fifth data voltages PXD5' and PXD11' and the load values ​​of the sixth data voltages PXD6' and PXD12'.

[0185] In an embodiment, each of the load values ​​output from the third load calculator 179 may be the MSB of a value obtained by adding the data voltage values. That is, only the bit corresponding to the MSB containing the largest amount of information is transmitted, so that the capacity (number of bits) of the register required for the third delay section 180 can be minimized.

[0186] The third delay unit 180 can output the load value of the fifth data voltage PXD5' and PXD11' after a predetermined delay time. For example, the third delay unit 180 can be configured as a delay register. The capacity of the register can correspond to the number of bits of the load value. The predetermined delay time can be one horizontal period.

[0187] The third load difference calculator 181 may output a third load difference LDD3 based on the output LD3n of the third load calculator 179 and the output LD3(n-1) of the third delay unit 180. For example, the output LD3n of the third load calculator 179 may be the load value of the sixth data voltages PXD6' and PXD12'. The output LD3(n-1) of the third delay unit 180 may be the load value of the fifth data voltages PXD5' and PXD11'. Therefore, the third load difference calculator 181 may calculate the third load difference LDD3 between the fifth data voltages PXD5' and PXD11' and the sixth data voltages PXD6' and PXD12'.

[0188] The crosstalk calculator 177' can calculate a first crosstalk amount XT1' with respect to the third data voltages PXD3' and PXD9', a second crosstalk amount XT2' with respect to the fourth data voltages PXD4' and PXD10', and a third crosstalk amount XT3' with respect to the sixth data voltages PXD6' and PXD12' based on the first load difference LDD1, the second load difference LDD2, and the third load difference LDD3. For example, the first crosstalk amount XT1', the second crosstalk amount XT2', and the third crosstalk amount XT3' can be calculated as shown in the following Formula 2.

[0189] Formula 2

[0190]

[0191] D11 may be a first weight value, D12 may be a second weight value, D13 may be a third weight value, D21 may be a fourth weight value, D22 may be a fifth weight value, D23 may be a sixth weight value, D31 may be a seventh weight value, D32 may be an eighth weight value, and D33 may be a ninth weight value.

[0192] For example, the first crosstalk amount XT1′ may be a value obtained by adding the first load difference LDD1 to which the first weight value D11 is applied, the second load difference LDD2 to which the second weight value D12 is applied, and the third load difference LDD3 to which the third weight value D13 is applied. The second crosstalk amount XT2′ may be a value obtained by adding the first load difference LDD1 to which the fourth weight value D21 is applied, the second load difference LDD2 to which the fifth weight value D22 is applied, and the third load difference LDD3 to which the sixth weight value D23 is applied. The third crosstalk amount XT3′ may be a value obtained by adding the first load difference LDD1 to which the seventh weight value D31 is applied, the second load difference LDD2 to which the eighth weight value D32 is applied, and the third load difference LDD3 to which the ninth weight value D33 is applied.

[0193] Here, the sign of each of the first weight value D11, the fourth weight value D21, the fifth weight value D22, the seventh weight value D31, the eighth weight value D32, and the ninth weight value D33 may be different from the sign of each of the second weight value D12, the third weight value D13, and the sixth weight value D23. For example, each of the first weight value D11, the fourth weight value D21, the fifth weight value D22, the seventh weight value D31, the eighth weight value D32, and the ninth weight value D33 may be a positive number. Each of the second weight value D12, the third weight value D13, and the sixth weight value D23 may be a negative number. As shown in FIG. Figure 10 As described, the size and sign of each of the weight values ​​may be predetermined by considering the voltage decrease width and the voltage increase width.

[0194] The crosstalk compensator 178 ′ may compensate the third data voltages PXD3 ′ and PXD9 ′ based on the first crosstalk amount XT1 ′, the fourth data voltages PXD4 ′ and PXD10 ′ based on the second crosstalk amount XT2 ′, and the sixth data voltages PXD6 ′ and PXD12 ′ based on the third crosstalk amount XT3 ′.

[0195] The gray value GVs3 ′ output from the crosstalk compensator 178 ′ may include the compensated third data voltages PXD3 ′ and PXD9 ′, the compensated fourth data voltages PXD4 ′ and PXD10 ′, and the compensated sixth data voltages PXD6 ′ and PXD12 ′.

[0196] For example, the crosstalk compensator 178' may increase the third data voltages PXD3' and PXD9' as the first crosstalk amount XT1' increases, increase the fourth data voltages PXD4' and PXD10' as the second crosstalk amount XT2' increases, and increase the sixth data voltages PXD6' and PXD12' as the third crosstalk amount XT3' increases.

[0197] Therefore, the display device 10 according to the present disclosure may minimize a line crosstalk defect that may occur when using the data distributor 16 ′.

[0198] Figure 16 is a diagram illustrating a data distributor and pixels according to still another embodiment of the present disclosure.

[0199] refer to Figure 16 , illustrating a data driver 12 ″, a data distributor 16 ″ and a pixel 14 ′ according to yet another embodiment of the present disclosure. The structure of the pixel 14 ′ may be an RGB stripe structure, and Figure 13 The same as the pixel 14' shown in FIG.

[0200] The data distributor 16" may include first transistors M11", M12" and M13" and second transistors M21", M22" and M23". The gate electrodes of the first transistors M11", M12" and M13" may be coupled to the first control line CL1, the first electrodes of the first transistors M11", M12" and M13" may be coupled to the data output line DO1, and the second electrodes of the first transistors M11", M12" and M13" may be coupled to the first data lines DL1, DL2 and DL3, respectively. Gate electrodes of the second transistors M21″, M22″, and M23″ may be coupled to the second control line CL2, first electrodes of the second transistors M21″, M22″, and M23″ may be coupled to the data output line DO2, and second electrodes of the second transistors M21″, M22″, and M23″ may be coupled to the second data lines DL4, DL5, and DL6, respectively. For example, the data distributor 16″ may be a demultiplexer having an input-to-output ratio of 1:3.

[0201] The turn-on periods of the first transistors M11″, M12″, and M13″ and the turn-on periods of the second transistors M21″, M22″, and M23″ may not overlap with each other. The timing controller 11 may sequentially provide control signals having a turn-on level to the first control line CL1 and the second control line CL2, so that the first transistors M11″, M12″, and M13″ and the second transistors M21″, M22″, and M23″ are sequentially turned on.

[0202] For example, the number of first transistors M11", M12", and M13" may be the same as the number of second transistors M21", M22", and M23". In addition, the number of first data lines DL1, DL2, and DL3 may be the same as the number of second data lines DL4, DL5, and DL6.

[0203] First data lines DL1 , DL2 , and DL3 corresponding to the first transistors M11 ″, M12 ″, and M13 ″ may be continuously arranged, and next, second data lines DL4 , DL5 , and DL6 corresponding to the second transistors M21 ″, M22 ″, and M23 ″ may be continuously arranged.

[0204] Figure 16 The data distributor 16" and the pixel 14' shown in FIG can be used with Figure 10 The same method as shown in the method to drive. Therefore, as Figure 12 The data compensator disclosed in the invention can be applied to Figure 16 The data distributor 16" and the pixel 14' are shown in FIG.

[0205] Figure 17 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0206] Figure 17 The display device 10a shown in FIG may include a modified timing controller 11a, a data compensator 17a, and a data driver 12a.

[0207] First, the timing controller 11a may provide the grayscale value GVs2 to the data compensator 17a. Next, and Figure 12 or Figure 15 Like the embodiment shown in , the data compensator 17a may provide the data driver 12a with a grayscale value GVs3 in which the line crosstalk defect is compensated.

[0208] According to this embodiment, Figure 4 Unlike the embodiment shown in , the data driver 12a may include a single holding latch. Therefore, the configuration of the data driver 12a may be simplified and the cost of the data driver 12a may be reduced.

[0209] Figure 18 is a diagram illustrating a display device according to still another embodiment of the present disclosure. Figure 19 is a diagram illustrating a data distributor according to still another embodiment of the present disclosure.

[0210] Figure 18 The display device 10b shown in FIG may include a modified timing controller 11b, a data compensator 17b, and a data driver 12b.

[0211] First, the timing controller 11b may provide the grayscale value GVs2 to the data compensator 17b. The data compensator 17b may not include any data voltage value extractor or any lookup table. That is, the first load calculator 171b and the second load calculator 172b may directly use the grayscale value GVs2. The data compensator 17b may generate a grayscale value GVs3 whose line crosstalk defect is compensated by using the grayscale value GVs2 instead of the data voltage value. Next, the timing controller 11b may provide the data driver 12b with a grayscale value GVs1 corresponding to the compensated grayscale value GVs3.

[0212] According to this embodiment, Figure 4 Unlike the embodiment shown in , the data driver 12b may include a single holding latch. Therefore, the configuration of the data driver 12b may be simplified and the cost of the data driver 12b may be reduced.

[0213] Furthermore, according to this embodiment, the data compensator 17b does not include any data voltage value extractor and any lookup table. Therefore, the configuration of the data compensator 17b can be simplified and the cost of the data compensator 17b can be reduced.

[0214] In the display device according to the present disclosure, when the data distributor is used, the line crosstalk defect can be minimized.

[0215] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: a data driver configured to supply a first data voltage to a data output line during a first period, supply a second data voltage to the data output line during a second period following the first period, supply a third data voltage to the data output line during a third period following the second period, and supply a fourth data voltage to the data output line during a fourth period following the third period; a data distributor configured to couple the data output line to a first data line during the first period, to couple the data output line to a second data line during the second period, to couple the data output line to the first data line during the third period, and to couple the data output line to the second data line during the fourth period; a first pixel configured to start receiving the voltage charged in the first data line and the second data line after an initial time of the second period and before an end time of the second period; a second pixel configured to start receiving the voltage charged in the first data line and the second data line after an initial time of the fourth period and before an end time of the fourth period; as well as A data compensator configured to compensate the third and fourth data voltages based on a first load difference between the first and third data voltages and a second load difference between the second and fourth data voltages.

2. The display device according to claim 1, wherein The data compensator includes: a first load calculator configured to sequentially output a load value of the first data voltage and a load value of the third data voltage; and A second load calculator is configured to sequentially output a load value of the second data voltage and a load value of the fourth data voltage.

3. The display device according to claim 2, wherein The data compensator further comprises: a first delay part configured to output the load value of the first data voltage after a predetermined delay time; and A second delay part is configured to output the load value of the second data voltage after the predetermined delay time.

4. The display device according to claim 3, wherein The predetermined delay time is one horizontal period.

5. The display device according to claim 3, wherein The data compensator further comprises: a first load difference calculator configured to output the first load difference based on an output of the first load calculator and an output of the first delay section; and A second load difference calculator is configured to output the second load difference based on an output of the second load calculator and an output of the second delay section. The display device according to claim 5 , wherein: The data compensator further includes a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage and a second crosstalk amount with respect to the fourth data voltage based on the first load difference and the second load difference. wherein the first crosstalk amount is a value obtained by adding the first load difference to which a first weight value is applied and the second load difference to which a second weight value is applied, wherein the second crosstalk amount is a value obtained by adding the first load difference to which a third weight value is applied and the second load difference to which a fourth weight value is applied, wherein the sign of each of the first weight value, the third weight value, and the fourth weight value is different from the sign of the second weight value, wherein the data compensator further includes a crosstalk compensator configured to compensate the third data voltage based on the first crosstalk amount and to compensate the fourth data voltage based on the second crosstalk amount, Each of the first pixel and the second pixel includes a P-type transistor, wherein each of the first weight value, the third weight value, and the fourth weight value is a positive number, and the second weight value is a negative number, and The crosstalk compensator increases the third data voltage as the first crosstalk amount increases, and increases the fourth data voltage as the second crosstalk amount increases.

7. The display device according to claim 5, wherein the data driver supplies a fifth data voltage to the data output line during a fifth period between the second period and the third period, and supplies a sixth data voltage to the data output line during a sixth period after the fourth period, wherein the data distributor couples the data output line to a third data line during the fifth period, and couples the data output line to the third data line during the sixth period, The first pixel receives the voltage charged in the first data line, the second data line and the third data line after the initial moment of the fifth period and before the initial moment of the third period, and The second pixel receives the voltage charged in the first data line, the second data line, and the third data line after an initial moment of the sixth period.

8. The display device according to claim 7, wherein The data compensator compensates the third data voltage, the fourth data voltage, and the sixth data voltage based on the first load difference, the second load difference, and a third load difference between the fifth data voltage and the sixth data voltage.

9. The display device according to claim 8, wherein The data compensator further comprises: a third load calculator configured to sequentially output a load value of the fifth data voltage and a load value of the sixth data voltage; a third delay section configured to output the load value of the fifth data voltage after the predetermined delay time; a third load difference calculator configured to output the third load difference based on an output of the third load calculator and an output of the third delay section; and a crosstalk calculator configured to calculate a first crosstalk amount with respect to the third data voltage, a second crosstalk amount with respect to the fourth data voltage, and a third crosstalk amount with respect to the sixth data voltage based on the first load difference, the second load difference, and the third load difference, wherein the first crosstalk amount is a value obtained by adding the first load difference to which a first weight value is applied, the second load difference to which a second weight value is applied, and the third load difference to which a third weight value is applied, The second crosstalk amount is a value obtained by adding the first load difference to which a fourth weight value is applied, the second load difference to which a fifth weight value is applied, and the third load difference to which a sixth weight value is applied, and The third crosstalk amount is a value obtained by adding the first load difference to which a seventh weight value is applied, the second load difference to which an eighth weight value is applied, and the third load difference to which a ninth weight value is applied, and The sign of each of the first weight value, the fourth weight value, the fifth weight value, the seventh weight value, the eighth weight value and the ninth weight value is different from the sign of each of the second weight value, the third weight value and the sixth weight value.

10. The display device according to claim 9, wherein The data compensator further includes a crosstalk compensator configured to compensate the third data voltage based on the first crosstalk amount, compensate the fourth data voltage based on the second crosstalk amount, and compensate the sixth data voltage based on the third crosstalk amount, Each of the first pixel and the second pixel includes a P-type transistor, wherein each of the first weight value, the fourth weight value, the fifth weight value, the seventh weight value, the eighth weight value, and the ninth weight value is a positive number, and Each of the second weight value, the third weight value, and the sixth weight value is a negative number, and The crosstalk compensator increases the third data voltage as the first crosstalk amount increases, increases the fourth data voltage as the second crosstalk amount increases, and increases the sixth data voltage as the third crosstalk amount increases.

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