Method for processing a semiconductor substrate

Abstract

A method for processing a semiconductor substrate (100) is presented. An example of the method includes forming a cavity (104) in the semiconductor substrate (100) by implanting ions through a first surface (102) of the semiconductor substrate (100). The cavity (104) defines a separation layer (106) in the semiconductor substrate (100). Thereafter, a semiconductor layer (108) is formed on the first surface (102) of the semiconductor substrate (100). A semiconductor device element is formed in the semiconductor layer (108). Thereafter, the semiconductor substrate (100) is separated along the separation layer (106) into a first substrate portion (1001) including the semiconductor layer (108) and a second substrate portion (1002).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method for processing a semiconductor substrate, in particular to a method in which a semiconductor substrate is separated into a first substrate portion and a second substrate portion. BACKGROUND

[0002] A method for processing a semiconductor substrate, for example when forming a semiconductor device in a semiconductor substrate, can comprise grinding a semiconductor wafer, for example to reduce the electrical resistance of the semiconductor device. Grinding can be time consuming and can comprise a high consumption of semiconductor material, resulting in a high cost for the semiconductor device. For example, in such a case, a re-use concept for using the semiconductor substrate for forming a further semiconductor device is not possible.

[0003] A semiconductor substrate, for example a silicon carbide wafer or a silicon wafer, can be diced to enable a re-use concept. However, dicing a semiconductor substrate can limit some semiconductor processing required for forming a semiconductor device, or can result in an inaccurate thickness of the diced semiconductor substrate portion. For example, a required thickness of the diced semiconductor substrate portion can not be achievable by using some dicing concepts. There can be a desire for an improved concept for processing a semiconductor substrate. SUMMARY

[0004] An example of the present disclosure relates to a method for processing a semiconductor substrate. The method comprises forming a cavity in the semiconductor substrate by implanting ions through a first surface of the semiconductor substrate, wherein the cavity defines a separation layer in the semiconductor substrate. Thereafter, the method further comprises forming a semiconductor layer on the first surface of the semiconductor substrate. The method further comprises forming a semiconductor device element in the semiconductor layer. Thereafter, the method further comprises separating the semiconductor substrate along the separation layer into a first substrate portion comprising the semiconductor layer and a second substrate portion.

[0005] Another example of the present disclosure relates to another method for processing a semiconductor substrate. The method comprises implanting ions through a first surface of the semiconductor substrate to define a separation layer in the semiconductor substrate. The method further comprises separating the semiconductor substrate along the separation layer into a first substrate portion and a second substrate portion by at least illuminating the semiconductor substrate with electromagnetic radiation of a first wavelength and illuminating the semiconductor substrate with electromagnetic radiation of a second wavelength different from the first wavelength.

[0006] Those skilled in the art will realize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate examples of methods for processing semiconductor substrates and, together with the description, serve to explain the principles of the examples. Further examples are described in the following detailed description and claims.

[0008] Figures 1A-1D This is a schematic cross-sectional view used to illustrate a method of processing a semiconductor substrate.

[0009] Figure 2 This is a schematic cross-sectional view used to illustrate the processing characteristics when processing a semiconductor substrate.

[0010] Figure 3A and Figure 3B This is a schematic cross-sectional view used to illustrate another method for processing a semiconductor substrate.

[0011] Figure 4A and Figure 4B It is used for illustration and can be made by Figures 1A-3B A schematic cross-sectional view of an example of a semiconductor device manufactured using this method. Detailed Implementation

[0012] In the following detailed description, reference is made to the accompanying drawings, which form part of this document, and which illustrate specific examples in which a semiconductor substrate can be processed. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. For example, a feature illustrated or described for one example may be used on or in combination with other examples to produce yet another further example. It is intended that this disclosure include such modifications and variations. Examples are described using specific language, but this specific language should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements are indicated by the same reference numerals in different drawings.

[0013] The terms “having,” “containing,” “including,” and “including” are open-ended and indicate the presence of the stated structure, element, or feature but do not exclude the presence of additional elements or features. The quantifiers “a,” “one,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0014] The term "electrically connected" describes a permanent low-resistance connection between the elements that are electrically connected, for example a direct contact between the elements involved or a low-resistance connection via a metal and / or a heavily doped semiconductor material. The term "electrically coupled" includes that one or more intermediate elements adapted for signal and / or power transmission can be connected between the elements that are electrically coupled, for example electrically decoupled elements that are controllable to temporarily provide a low resistance in a first state and a high resistance in a second state.

[0015] An ohmic contact is a non-rectifying electrical junction with linear or almost linear current-voltage characteristics. A Schottky contact is a metal-semiconductor junction with rectifying characteristics, wherein the work function of the metal and the dopant concentration in the semiconductor material are chosen such that a depletion region in the semiconductor material along the metal-semiconductor junction is formed without an externally applied electric field. In the case of a Schottky contact, the term "metal-semiconductor junction" can also refer to a junction between a metal-like semiconductor and a semiconductor, wherein the junction has the same characteristics as a metal-semiconductor junction. For example, it can be possible to form a Schottky contact between polysilicon and silicon carbide. If two components (for example two regions) form an ohmic contact or a Schottky contact, respectively, this can mean that there is an ohmic contact or a Schottky contact between the two components. In both cases, it can be possible for the two regions to directly adjoin one another. However, it can also be possible for further components to be positioned between the two components.

[0016] Ranges given for physical sizes include the boundary values. For example, a range from a to b for a parameter y reads as a < y < b. The same applies to ranges with one boundary value, such as "at most" and "at least".

[0017] The main components of a layer or structure from a chemical compound or an alloy are elements whose atoms form the chemical compound or the alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0018] The term "on" is not to be interpreted as meaning "directly on" only. Rather, if an element is located "on" another element (for example, a layer is "on" another layer or on a substrate), further components (for example, further layers) can be located between the two elements (for example, if a layer is "on" a substrate, further layers can be located between the layer and the substrate).

[0019] An example of a method for processing a semiconductor substrate can include forming a cavity in a semiconductor substrate by implanting ions through a first surface of the semiconductor substrate. The cavity defines a separation layer in the semiconductor substrate. Thereafter, a semiconductor layer can be formed on the first surface of the semiconductor substrate. A semiconductor device element can be formed in the semiconductor layer. Thereafter, the semiconductor substrate can be separated along the separation layer into a first substrate portion including the semiconductor layer and a second substrate portion.

[0020] The semiconductor substrate can include or be composed of a semiconductor material from a Group IV elemental semiconductor, a Group IV-IV compound semiconductor material, a Group III-V compound semiconductor material, or a Group II-VI compound semiconductor material. Examples of semiconductor materials from a Group IV elemental semiconductor include silicon (Si) and germanium (Ge), among others. Examples of Group IV-IV compound semiconductor materials include silicon carbide (SiC) and silicon germanium (SiGe), among others. Examples of Group III-V compound semiconductor materials include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs), among others. Examples of Group II-VI compound semiconductor materials include cadmium telluride (CdTe), cadmium mercury telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe), among others.

[0021] For example, the semiconductor substrate can be a crystalline SiC semiconductor substrate. For example, the silicon carbide crystal can have a hexagonal polytype, such as 4H or 6H. The silicon carbide semiconductor body can be uniformly doped, or can include portions of the SiC layer that are doped differently. The silicon carbide semiconductor body can include one or more layers from additional materials that have a melting point close to or above that of crystalline silicon carbide. For example, layers from additional materials can be embedded in a crystalline silicon carbide substrate. The silicon carbide semiconductor substrate can have two substantially parallel major surfaces of the same shape and size, and a lateral surface region connecting edges of the two major surfaces. For example, the silicon carbide semiconductor body can be a right rectangular prism with or without rounded corners, or a right circular cylinder or a slightly inclined cylinder (e.g., where the sides are inclined at an angle of at most 8° or at most 5° or at most 3°) with or without one or more flat faces or notches along the outer periphery.

[0022] The cavity can be caused by coalescence of vacancies, where vacancies can be formed by interaction of the implanted ions and the lattice of the semiconductor substrate. The cavity can define the separation layer at an end of the range of the implanted ions, such as at a peak at the depth of penetration of the implanted ions.

[0023] The semiconductor layer can be formed by at least one layer deposition process, such as an epitaxial layer deposition process. For example, a chemical vapor deposition (CVD) technique can be used to form the semiconductor layer. The doping concentration profile and / or thickness of the semiconductor layer can be selected in view of target device parameters, such as voltage blocking capability and / or on-state resistance of a particular region. For example, a first portion of the semiconductor layer can be a drift region. A second portion of the semiconductor layer can be a field stop region. The field stop region can be disposed between the drift region and the backside contact. For example, the doping concentration in the field stop region can be greater than the doping concentration in the drift region, such as by one or two orders of magnitude.

[0024] Forming the semiconductor device elements in the semiconductor layer can include forming one or more features of semiconductor regions (such as p-doped regions and / or n-doped regions), insulating layers (such as gate dielectric(s) and / or field dielectric(s) and / or interlayer dielectric(s)), conductive layers (such as metal layer(s) for electrical contacts and / or wiring), protective layer(s), and / or passivation layer(s) (such as imide). For example, the semiconductor regions, such as drain regions, source regions, body regions, body contact regions, current spreading regions, shield regions, anode regions, cathode regions, can be formed by ion implantation and / or diffusion from a diffusion source. Planar gate structures including gate dielectric and gate electrode or trench gate structures including gate dielectric and gate electrode in a trench can be formed by thermal oxidation and / or layer deposition of gate dielectric and layer deposition of highly doped semiconductor (such as polysilicon) and / or metal layer(s).

[0025] For example, at least a portion of the semiconductor device elements can be active device elements formed in an active device region of the semiconductor substrate. The active device region is a region of the semiconductor substrate in which a load current flow through a surface into / out of the semiconductor substrate / semiconductor layer is carried. In the case of an IGFET or IGBT, the active device region can include a source region electrically connected through the surface to a contact electrode. A source-to-drain current or an emitter-to-collector current can flow from the contact electrode through the surface into the source region. In the case of a diode, the active device region can include an anode region or a cathode region electrically connected through the surface to a contact electrode. An anode-to-cathode current can flow from the contact electrode through the surface into the anode region or the cathode region. Thus, for example, the active device region can be constrained to a first portion of the surface through which a load current flow is directed. For example, in addition to the active device elements, edge termination elements can be formed in an edge termination region, which is a region of the semiconductor substrate that partially or completely surrounds the active device region. Since a pn junction within the semiconductor substrate, such as a pn junction between a body region and a drift region of an IGFET or IGBT or a pn junction between a cathode region and an anode region of a diode, is not infinite but terminates at an edge region of the semiconductor body, this edge effect limits the device breakdown voltage below an ideal value set by an infinite parallel plane junction. Care must be taken to ensure proper and efficient termination of the pn junction at the edge of the semiconductor substrate. The edge termination region is a measure for ensuring proper and efficient termination of the pn junction. Examples of edge termination structures in the edge termination region include, for example, field plates, junction termination extension (JTE) structures, variable lateral doping (VLD) structures. Unlike the active device region, the edge termination region can be constrained to a second portion of the surface that: i) completely or partially surrounds the first portion of the active device region; and ii) has no load current flow directed through it through the surface to the contact electrode; and iii) contributes to termination of the pn junction. There can be a transition region between the active device region and the edge termination region, for example, for electrically connecting the edge termination structures.

[0026] For example, a semiconductor device element can define a vertical power semiconductor device. A vertical power semiconductor device can be a power semiconductor diode, or a power semiconductor IGBT (Insulated Gate Bipolar Transistor), or a power semiconductor transistor such as a power semiconductor IGFET (Insulated Gate Field Effect Transistor, e.g., a Metal-Oxide-Semiconductor Field Effect Transistor). A vertical power semiconductor device can be configured to conduct current greater than 1 A and can be further configured to block voltages between load terminals, such as the voltage between the drain and source of a MOSFET, or the voltage between the emitter and collector of an IGBT, or the voltage between the cathode and anode of a diode, in the range of several hundred volts to several thousand volts (e.g., 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV). For example, the blocking voltage can correspond to the voltage level specified in the power semiconductor device's datasheet.

[0027] The dose(s) of implanted ions can be selected within an appropriate range, making it possible to process the semiconductor substrate prior to separation without undesirable early separation due to thermomechanical stress affecting the semiconductor substrate. For example, thermomechanical stress can affect the semiconductor substrate when forming semiconductor device elements. For example, the ions can include helium ions, and the implantation dose of helium ions can be from 5 × 10⁻⁶. 14 cm -2 Up to 5×10 15 cm -2 Within the range. Alternatively, ions may include protons, and the proton injection dose, for example, is from 5 × 10⁻⁶. 15 cm -2 Up to 5×10 16 cm -2 Within the range.

[0028] Separating a semiconductor substrate into a first substrate portion and a second substrate portion, which include a semiconductor layer, can be achieved by irradiating the semiconductor substrate with light (e.g., a laser) at least using a target wavelength. For example, the separation of the semiconductor substrate can be performed simply by irradiating a silicon carbide wafer, or additional processes (e.g., heating, applying mechanical stress and / or force and / or ultrasonic treatment) can be performed to separate the semiconductor substrate into the first substrate portion and the second substrate portion.

[0029] To separate the semiconductor substrate, the energy of the light of the target wavelength can be selected, for example, based on the energy needed to cleave the semiconductor substrate, based on the absorption coefficient of the separation layer, based on the thickness of the semiconductor substrate, based on the thickness of the separation layer, and / or based on the position of the separation layer within the semiconductor substrate (e.g., to account for additional absorption due to the semiconductor substrate). The light of the target wavelength can be irradiated onto the front side and / or onto the back side of the semiconductor substrate. Due to the higher absorption coefficient of the separation layer, a larger portion of the light of the target wavelength can be absorbed within the separation layer than in the material of the semiconductor substrate outside the separation layer. For example, the light of the target wavelength absorbed within the separation layer can cause a decomposition or a destruction of at least a portion of the separation layer (e.g., a region connected in the lateral direction), so that the semiconductor substrate can be separated along the separation layer. The released energy of the light of the target wavelength absorbed within the separation layer can cause a cleaving of the semiconductor substrate.

[0030] For example, both the first semiconductor substrate portion and the second substrate portion can comprise or can consist of the material of the semiconductor substrate outside the separation layer as a main material. For example, compared to other separation methods, cleaving the semiconductor substrate along the separation layer can enable a more accurate definition of the thickness of the first substrate portion, and / or a definition of the thickness of the first substrate portion with a reduced variation along the lateral extension of the first substrate portion, and / or a more uniform definition of the thickness of the first substrate portion along the lateral extension of the first substrate portion. For example, the method can improve the control of the thickness of the first semiconductor substrate portion. The thickness of the separation layer can be smaller compared to the thickness of other cleave regions, so that a variation of the thickness of the first semiconductor substrate portion can be reduced. In addition, the consumption of material of the semiconductor substrate for cleaving can be reduced by providing the separation layer with a reduced thickness.

[0031] Examples relate to aspects which can enable forming a separation layer having an absorption coefficient which is 5 times higher or even 100 times higher compared to the absorption coefficient of the semiconductor material of the semiconductor substrate outside the separation layer.

[0032] Some methods can be based on irradiation using a focused laser. For example, the laser can have a peak wavelength within the absorption gap of the semiconductor substrate. At the focus, due to the high photon density, a charge carrier plasma can be generated, which in turn can, for example, increase the absorption. Thus, a positive feedback mechanism can be obtained, which, for example, allows locally decomposing the semiconductor material of the semiconductor substrate and thus generating a cleave layer which can subsequently be used for a separation process with support of thermal mechanical stress. For example, the separation process can be performed when the processing of the device has been more or less completed. For example, the semiconductor substrate can already be metallized at the front side.

[0033] In addition to or as an alternative to irradiating the semiconductor substrate with light of the target wavelength for separating the semiconductor substrate, the separation process can further comprise at least one of the following processes (i)-(iii): (i) heating the semiconductor substrate; (ii) applying mechanical stress and / or force to the semiconductor substrate; and (iii) subjecting the semiconductor substrate to ultrasonic treatment. For example, at least one additional process (i)-(iii) can be applied during and / or after irradiating the silicon carbide wafer with light of the target wavelength. At least one of the processes (i)-(iii) can be applied for separating the semiconductor substrate. For example, heating or annealing the semiconductor substrate (process (i)) can facilitate separating the semiconductor substrate, e.g. by introducing thermal mechanical stress at the separation layer to support dicing the semiconductor substrate. For example, mechanical force and / or stress can be applied (process (ii)) by forming an additional layer on the silicon carbide wafer, which can be mechanically pre-stressed (e.g. twisted and / or stretched) with respect to the semiconductor substrate. For example, the additional layer can be a polyimide layer. Additionally or as an alternative, applying mechanical force and / or stress in process (ii) can involve applying compressed gas or compressed air to the side of the semiconductor substrate. Ultrasonic treatment (process (iii)) can comprise applying ultrasonic radiation to the semiconductor substrate. Similar to process (i), ultrasonic treatment can also cause heating the semiconductor substrate.

[0034] For example, the method can further comprise implanting protons through the semiconductor layer into the semiconductor substrate. For example, the protons can be implanted after forming the semiconductor layer. The protons can be implanted after ion implantation of the dopant and after thermal activation of the dopant for forming the semiconductor device element in the semiconductor layer. For example, the protons can be implanted before gate oxide formation. For example, the range end of the implanted protons can at least partially overlap with the range end of the ions implanted for forming the cavity. The implanted protons can contribute to the formation of a complex, e.g. SiH2. This can support the mechanical stress required for separating the semiconductor substrate, which can be further amplified by any of the processes described above or below.

[0035] For example, the ions can further comprise ions comprising carbon. The range end of the implanted carbon can at least partially overlap with the range end of the implanted ions used to form the cavities. The carbon implantation can result in a carbon-rich interface of the cavities. This can allow for increased light absorption by the separation layer, and thus can allow for improved separation processing, for example. For example, the temperature of the semiconductor substrate during ion implantation can be set in a range from 20 °C to 700 °C or in a range between 25 °C and 550 °C. Minimizing self- annealing effects can allow for improved absorption behavior of the separation layer and / or allow for low ion implantation doses. Minimizing self- annealing effects can be achieved by using a low semiconductor substrate temperature during ion implantation, for example a semiconductor substrate temperature in a range from 20 °C to 150 °C or from 20 °C to 250 °C.

[0036] For example, the cavities can be formed in a porous portion of the semiconductor substrate. For example, the porous portion can be formed within the semiconductor substrate or on a surface of the semiconductor substrate. Forming the porous portion can enable increasing the absorption coefficient of the separation layer and / or providing a surface of the semiconductor substrate with a defect density at or below a critical limit, which can allow for growing a high-quality epitaxial layer on the surface after forming the porous portion, for example.

[0037] The porous portion can be formed in the semiconductor substrate, for example, by an anodic electroplating, for example, in an electrolyte comprising fluorine. The electrolyte can comprise hydrofluoric acid (HF) and / or ethanol. The anodic electroplating electrochemically decomposes the semiconductor substrate crystal in a region of the porous portion to some extent. Instead of uniformly decomposing the semiconductor substrate crystal, the electrochemical decomposition can locally remove atoms out of the semiconductor substrate crystal lattice, forming small pores or voids within the semiconductor substrate. For example, the crystal structure of the semiconductor substrate outside the porous portion can remain unaffected by the anodic electroplating.

[0038] The porosity of the porous portion can be measured as a ratio of the effective void volume (e.g., the volume of the voids) in the porous portion to the total volume of the porous portion (including the semiconductor substrate volume and the void volume within the porous portion). For example, a higher porosity value can indicate a higher void density or a higher void volume in the porous portion, while a lower porosity value can indicate a lower void density or a lower void volume in the porous portion. For example, the porous portion can have a porosity of, for example, between 5% and 95% (or between 10% and 80%, or between 25% and 60%). For example, the porous portion can have a density (weight per volume) of approximately 90%, 80%, or 70% of the semiconductor substrate material surrounding the porous portion.

[0039] For example, ions can be implanted through at least a portion of the porous portion (e.g., a vertical portion). For example, the porous portion can be formed prior to implanting ions to form the separation layer. The separation layer can be formed within the porous portion (e.g., the separation layer can be formed entirely within the porous portion), and ions can be implanted through a first vertical portion of the porous portion. For example, at least a first vertical portion of the separation layer can be formed below the porous portion, e.g., the porous portion can be vertically located between a surface of the semiconductor substrate that is implanted through by the ions and the first vertical portion of the separation layer.

[0040] Implanting ions for forming the separation layer through at least a portion of the porous portion can increase the depth of implantation (e.g., an increased distance between a surface of the semiconductor substrate and the separation layer), while surface damage can be kept close to its intrinsic value, e.g., for the applied implantation dose. Thus, the distance of the separation layer and, e.g., an electrically active device layer of the semiconductor substrate (e.g., formed after forming the separation layer and prior to separating the semiconductor substrate) can be increased, and less interaction with active semiconductor device elements can occur, e.g., during separation (e.g., by irradiation with light (e.g., laser light)).

[0041] As mentioned, the separation layer or at least a vertical portion of the separation layer can be formed within the porous portion. Forming the separation layer into the porous portion of the semiconductor substrate can increase the absorption capacity of the layer (e.g., can cause a higher absorption coefficient), e.g., enabling a combination of mechanical and electrically / optically active light absorption centers. For example, it can enable a cleaving (e.g., by light irradiation, e.g., laser light irradiation) with a lower implantation dose (e.g., a combined implantation dose to form the absorption layer), causing a lower surface damage and thus a surface quality suitable for epitaxial growth.

[0042] Implanting ions into the semiconductor substrate prior to the porosification process can enable adapting the porosification strength (e.g., porosity) and / or depth profile of the porous portion. This can increase the absorption coefficient in the separation layer (e.g., a higher absorption of the irradiated light) and / or can cause a better surface quality for epitaxial growth at a sufficiently high absorption coefficient in the separation layer and / or can have the beneficial effect that the porous portion (e.g., a porous silicon carbide layer) develops due to the thermal budget of further processing of the semiconductor substrate (e.g., epitaxial growth, activation annealing, etc.).

[0043] For example, a surface layer (e.g., a thin surface layer) of the porous portion can be converted or transformed into a non-porous layer (e.g., a so-called surface layer or seed layer) before forming a semiconductor layer on the porous portion of the semiconductor substrate. Additionally or alternatively, the porosification can be performed such that a non-porous portion remains at the surface. For example, the quality of an epitaxial layer grown on the non-porous semiconductor layer can be higher than the quality of an epitaxial layer grown on a porous semiconductor layer.

[0044] For example, the porous portion can be formed with at least two porous layers having different porosities, e.g., adjacent to each other in a vertical direction. The porosity of the upper layer (which, for example, provides a surface of the semiconductor substrate) can be chosen in a way that allows for forming a suitable surface layer on the surface, e.g., before growing an epitaxial layer on the surface of the semiconductor substrate. For example, after forming the separation layer, the surface layer of the porous portion can be converted into a non-porous layer. For example, the surface layer converted into the non-porous layer can be a surface layer and, for example, can be used as a seed layer for growing an epitaxial layer.

[0045] To convert the surface layer of the porous portion into a non-porous crystalline seed layer, the surface layer of the porous portion can be heated, for example, in a reducing atmosphere comprising hydrogen. The heat treatment can cause a rearrangement of atoms in a thin layer along the exposed surface of the semiconductor substrate, wherein the atoms in the thin surface layer of the porous portion can be reordered in a reflow process to form a continuous non-porous crystalline seed layer, for example, having a high crystalline quality. Alternatively or additionally, the non-porous crystalline seed layer can be formed by epitaxial growth on the porous portion or by laser annealing causing a rearrangement of atoms on the surface of the porous silicon carbide layer.

[0046] The non-porous crystalline seed layer can be used as a base for growing an epitaxial layer, e.g., a semiconductor layer. Since the non-porous crystalline seed layer can have a high crystalline quality, the epitaxial layer can be grown on the non-porous crystalline seed layer with a high crystalline quality. For example, the epitaxial layer grown on the non-porous crystalline seed layer can have a crystalline defect density comparable to an epitaxial layer grown directly on a conventional non-porous single crystalline semiconductor substrate.

[0047] For example, the porous portion can have a thickness of at least 0.3 μιη (or at least 0.5 μιη, at least 0.8 μιη, or at least 1.2 μιη) and / or at most 3 μιη (or at most 2 μιη or at most 1.5 μιη).

[0048] For example, the porous portion can limit the penetration of critical defects from the semiconductor substrate (e.g., between a backside surface of the semiconductor substrate and the porous portion) into a drift region of a device (e.g., formed after forming the separation layer and before separating the semiconductor substrate), thereby at least reducing the defect density and / or detrimental bipolar degradation effects in the drift region.

[0049] For example, the porous portions can be arranged between non-porous single-crystalline portions of the semiconductor substrate.

[0050] For example, prior to forming the cavity in the semiconductor substrate, the semiconductor substrate can be processed by forming a semiconductor layer on a first portion of the semiconductor substrate, wherein the semiconductor layer is a second portion of the semiconductor substrate exposed at a first surface of the semiconductor substrate, and wherein a thickness of the second portion of the semiconductor substrate is in a range from 5 μιη to 60 μιη.

[0051] For example, separating the semiconductor substrate along the separation layer can comprise simultaneously illuminating the semiconductor substrate with superimposed electromagnetic radiation from at least two radiation sources, the superimposed electromagnetic radiation having intensity peaks at two or more wavelengths. Using at least two radiation sources for illuminating the semiconductor substrate with electromagnetic radiation at two different wavelengths can allow for an improved separation process. For example, first radiation of a first wavelength of a first radiation source can be absorbed within the separation layer and can cause generation of electron-hole pairs in the separation layer. Second radiation of a second radiation source can provide further energy to the electron and hole pairs in the separation layer. This additional local energy application by the second radiation source can at least partially be transferred to the lattice in or around the separation layer. This can cause local heating of the semiconductor substrate and thus improved disturbance of the lattice in or around the separation layer, which can improve the separation process of the semiconductor substrate.

[0052] The process details described with respect to the above examples apply equally to the examples described below, and vice versa.

[0053] An example of a method for processing a semiconductor substrate can comprise implanting ions through a first surface of the semiconductor substrate to define a separation layer in the semiconductor substrate. The method can further comprise separating the semiconductor substrate along the separation layer into a first substrate portion and a second substrate portion by at least illuminating the semiconductor substrate with electromagnetic radiation of a first wavelength and with electromagnetic radiation of a second wavelength different from the first wavelength. Similar to the examples described above, the separation process can be improved by locally heating the free carriers (e.g. electron and hole pairs) generated by absorption of the radiation of the first wavelength. This local heating can be caused by radiation of the second wavelength, which can deposit energy to the lattice in the separation layer via the electron and hole pairs, e.g. by absorption or further interaction with the electron and hole pairs.

[0054] For example, electromagnetic radiation of the first wavelength can be emitted by a first radiation source, and electromagnetic radiation of the second wavelength can be emitted by a second radiation source different from the first radiation source. For example, electromagnetic radiation of the first and second wavelengths can simultaneously irradiate a semiconductor substrate. For example, electromagnetic radiation of the first and / or second wavelengths can be laser pulses. Laser pulses can be time-coordinated. For example, laser pulses of different wavelengths can overlap in the time domain, or they can not overlap, for example, due to short time shifts.

[0055] For example, for electromagnetic radiation of the first wavelength, the absorption coefficient of the separation layer can be at least 100 times or at least 1000 times that of the semiconductor material outside the separation layer of the semiconductor substrate.

[0056] For example, the second wavelength can be greater than the first wavelength. For example, the second wavelength can be used to deposit energy into the lattice of the separation layer, for example, via free carriers (e.g., electrons and holes) in the separation layer.

[0057] For example, the implanted ions may include at least one of nitrogen (N) ions, phosphorus (P) ions, vanadium (V) ions, boron (B) ions, argon (Ar) ions, carbon (C) ions, nickel (N) ions, silicon (Si) ions, titanium (Ti) ions, tantalum (Ta) ions, molybdenum (Mo), tungsten (W) ions, gallium (Ga) ions, and aluminum (Al) ions. The implanted ions can be integrated into a crystal lattice within a separation layer of the semiconductor substrate to form an absorption barrier for light of the target wavelength. For example, nitrogen (N) ions, vanadium (V) ions, boron (B) ions, argon (Ar) ions, carbon (C) ions, nickel (Ni) ions, silicon (Si) ions, and / or titanium (Ti) ions can form a strong absorption band after they are integrated into the semiconductor substrate. For example, aluminum ions, tantalum ions, boron ions, titanium ions, and / or nickel ions can be implanted into the semiconductor substrate, and the semiconductor substrate can be annealed after ion implantation. For example, at least 2 × 10⁻⁶ ions can be implanted. 15 cm -2 (or at least 1×10) 16 cm -2 Or at least 5×10 16 cm -2 The implanted ions (e.g., phosphorus ions) are injected at a specific dose. For example, nitrogen ions can be used, which, compared to other ions, can cause, for example, low damage at the implanted surface. In cases where the implanted ions are donors or acceptors, the resulting locally enhanced charge carrier density can support absorption processing, especially when using high implantation doses.

[0058] For example, the method can further comprise forming a semiconductor layer on the first surface of the semiconductor substrate after implanting the ions. The method can further comprise forming a semiconductor device element in the semiconductor layer before separating the semiconductor substrate along the separation layer. The further details described above in relation to the examples of the semiconductor layer and the semiconductor device element apply equally.

[0059] For example, forming the semiconductor device element in the semiconductor layer can comprise forming at least one doped semiconductor region in the semiconductor layer by introducing a dopant into the semiconductor layer. The at least one doped semiconductor region is part of at least one of the devices (power MOSFET, diode, IGBT, and JFET). The at least one doped semiconductor region is formed before separating the semiconductor substrate into the first substrate portion and the second substrate portion.

[0060] For example, separating the semiconductor substrate along the separation layer can comprise at least one of: i) irradiating the semiconductor substrate with electromagnetic radiation; the electromagnetic radiation can be configured to be at least partially absorbed in the separation layer and / or can be configured to heat (e.g. by interacting with free charge carriers (i.e. electrons and holes) in the semiconductor device) at least a portion of the semiconductor substrate (e.g. the separation layer of the semiconductor substrate), ii) heating the semiconductor substrate, iii) applying a mechanical force and / or stress to the semiconductor substrate, iv) subjecting the semiconductor substrate to ultrasonic treatment, v) irradiating the semiconductor substrate with protons.

[0061] For example, applying a mechanical force and / or stress to the semiconductor substrate can comprise forming a stress inducing layer on a second surface of the semiconductor substrate opposite the first surface. The introduction of the thermo-mechanical stress can be based on a difference in the expansion coefficient of the semiconductor material of the semiconductor substrate and the stress inducing layer. One example is known as the so-called “chill-off dicing” process, which utilizes a polymer coating on the surface of the semiconductor substrate, followed by a pre-cooling and cooling process for the introduction of the thermo-mechanical stress. This causes the crack to propagate from the local damage in the separation layer and results in the separation of the semiconductor substrate into the first substrate portion and the second substrate portion by dicing.

[0062] For example, the semiconductor substrate can be a SiC substrate, and the thickness of the separation layer can be in the range from 300 nm to 600 nm, for example, before the separation process and after the ion implantation. In some other examples, the thickness of the separation layer can be even larger, for example, up to several μm or even up to 50 μm.

[0063] For example, the separation layer can be formed within the semiconductor substrate at a vertical distance from the first surface of the semiconductor substrate ranging from 500 nm to 70 pm or from 800 nm to 5 pm. For example, when protons are used for forming the separation layer, the vertical distance can be larger compared to other ions, such as helium ions. For protons, the vertical distance can for example be around the upper limit of the above range.

[0064] The details described in the above examples apply equally to the illustrated examples described below. To avoid repeating details (e.g. material, dimensions, function of elements or processes described in the above examples), these details apply correspondingly to the illustrated examples described further below.

[0065] The description and drawings merely illustrate the principles of the disclosure. Further, all examples recited herein are principally intended expressly to be only for illustrative purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Thus, all statements recited herein il lustrating the principles of the disclosure, aspects and examples thereof, as well as specific examples thereof, are intended to encompass just a and equivalents.

[0066] It is to be understood that the disclosure of a number of actions, processes, operations, steps or functionalities in the specification or claims can not be interpreted as a requirement to perform the acts, processes, operations, steps or functionalities in the specific order in which they are recited, unless specifically stated as such or is clearly implied from the specification. Therefore, the disclosure should not be construed as being limited to the specific order in which the acts or functionality were recited, unless specifically stated as such or clearly implied from the specification. Further, in some examples, a single act, function, process, operation or step can include multiple sub-acts, sub- functions, sub-processes, sub-operations or sub-steps, or can be split into multiple acts, functions, processes, operations or steps, unless specifically stated as such or clearly implied from the specification. Unless explicitly stated, no act or function is a prerequisite to another.

[0067] Figures 1A-1D A method for processing a semiconductor substrate is illustrated.

[0068] Reference is made to Figure 1A Fig. 1 1 schematically illustrates a cross-sectional view of a semiconductor substrate 100. Ions are implanted into the semiconductor substrate 100 through a first surface 102 of the semiconductor substrate 100. In Figure 1A The ion implantation is schematically indicated in Fig. 1 1 by arrows 103 pointing onto the first surface 102. The ions implanted into the semiconductor substrate 100 result in cavities 104. The cavities 104 define a separation layer 106 in the semiconductor substrate 100. Details regarding the ion implantation and the cavities described in the above examples apply correspondingly.

[0069] Reference is made to Figure 1BA schematic cross-sectional view of the semiconductor substrate 100 is shown in FIG. 1A. The semiconductor substrate 100 includes a first surface 102 and a second surface 104. The first surface 102 and the second surface 104 are opposite to each other. The semiconductor substrate 100 includes a porous portion 112. The porous portion 112 is arranged between non-porous single-crystalline portions 1131, 1132 of the semiconductor substrate 100. The porous portion 112 is arranged in a region of the semiconductor substrate 100 that is to be processed. Details regarding the porous portion 112 described in the above examples apply correspondingly.

[0070] Referring to Figure 1C A schematic cross-sectional view of the semiconductor substrate 100 is shown in FIG. 1A. The semiconductor substrate 100 includes a first surface 102 and a second surface 104. The first surface 102 and the second surface 104 are opposite to each other. The semiconductor substrate 100 includes a porous portion 112. The porous portion 112 is arranged between non-porous single-crystalline portions 1131, 1132 of the semiconductor substrate 100. The porous portion 112 is arranged in a region of the semiconductor substrate 100 that is to be processed. Details regarding the porous portion 112 described in the above examples apply correspondingly.

[0071] Referring to Figure 1D A schematic cross-sectional view of the semiconductor substrate 100 is shown in FIG. 1A. The semiconductor substrate 100 includes a first surface 102 and a second surface 104. The first surface 102 and the second surface 104 are opposite to each other. The semiconductor substrate 100 includes a porous portion 112. The porous portion 112 is arranged between non-porous single-crystalline portions 1131, 1132 of the semiconductor substrate 100. The porous portion 112 is arranged in a region of the semiconductor substrate 100 that is to be processed. Details regarding the porous portion 112 described in the above examples apply correspondingly.

[0072] In Figure 2 A schematic cross-sectional view of the semiconductor substrate 100 is shown in FIG. 1A. The semiconductor substrate 100 includes a first surface 102 and a second surface 104. The first surface 102 and the second surface 104 are opposite to each other. The semiconductor substrate 100 includes a porous portion 112. The porous portion 112 is arranged between non-porous single-crystalline portions 1131, 1132 of the semiconductor substrate 100. The porous portion 112 is arranged in a region of the semiconductor substrate 100 that is to be processed. Details regarding the porous portion 112 described in the above examples apply correspondingly.

[0073] Figure 3A , Figure 3B An example of another method for processing a semiconductor substrate is illustrated.

[0074] Referring to Figure 3A A schematic cross-sectional view of the semiconductor substrate 100 is shown in FIG. 1A. The semiconductor substrate 100 includes a first surface 102 and a second surface 104. The first surface 102 and the second surface 104 are opposite to each other. The semiconductor substrate 100 includes a porous portion 112. The porous portion 112 is arranged between non-porous single-crystalline portions 1131, 1132 of the semiconductor substrate 100. The porous portion 112 is arranged in a region of the semiconductor substrate 100 that is to be processed. Details regarding the porous portion 112 described in the above examples apply correspondingly.

[0075] Subsequent further processing can be performed similar to the processing described with reference to Figure 1B , Figure 1C

[0076] Referring to Figure 3B ​A schematic cross-sectional view shows that the semiconductor substrate 100 is separated into a first substrate portion 1001 and a second substrate portion 1002 along the separation layer 106, at least by irradiating the semiconductor substrate 100 with electromagnetic radiation of a first wavelength λ1 and electromagnetic radiation of a second wavelength λ2 different from the first wavelength λ1. The electromagnetic radiation of the first wavelength λ1 is emitted by a first radiation source 114, and the electromagnetic radiation of the second wavelength λ2 is emitted by a second radiation source 116 different from the first radiation source 114. Details regarding the separation process based on the electromagnetic radiation of the first wavelength λ1 and the second wavelength λ2 described in the example above apply accordingly.

[0077] Examples of methods for processing semiconductor substrate 100 may be provided as shown in the following reference. Figures 4A-4B The semiconductor device described.

[0078] Figure 4A This is a schematic cross-sectional view of a portion of an example vertical semiconductor device. The vertical semiconductor device includes a first substrate portion 1001, such as a silicon semiconductor body or a silicon carbide semiconductor body. Precise adjustment of the thickness d1 of the drift region of the first substrate portion 1001 includes the steps outlined above with reference to Figure 1. Figure 3B The described processing characteristics.

[0079] The vertical semiconductor device includes a first load terminal structure 720 at a first surface 707 (e.g., the front surface of the first substrate portion 1001). The first load terminal structure 720 includes multiple doped semiconductor regions. For example, the multiple doped semiconductor regions may be formed by a doping process of the semiconductor body 704 at the first surface 707, for example by a process as described in reference... Figure 1C The semiconductor device elements described herein are formed by diffusion and / or ion implantation processes. For example, the multiple doped semiconductor regions in the semiconductor body 704 of the first load terminal structure 720 may include the doped source and body regions of the collector of a vertical power IGFET (e.g., a superjunction FET) or IGBT, or the doped source and body regions of the anode or cathode of a vertical power semiconductor diode or thyristor. Depending on the power semiconductor device to be formed in the semiconductor body, control terminal structures including multiple gate dielectrics and multiple gate electrodes may be formed, such as planar gate structures and / or trench gate structures.

[0080] The vertical semiconductor device further includes a second load terminal structure 725 at a second surface 708 (e.g., a back surface of the semiconductor body 704 opposite the first surface 707). The second load terminal structure 725 includes doped semiconductor region(s). The doped semiconductor region(s) can be formed by a doping process of the semiconductor body 704 at the second surface 708, e.g., by a diffusion and / or ion implantation process. For example, the doped semiconductor region(s) of the second load terminal structure 725 in the semiconductor body 704 can include doped field stop region(s), a doped drain region of a vertical power FET, or an emitter of an IGBT, or an anode region or a cathode region of a vertical power semiconductor diode. Implanted ions can be “activated”, i.e., incorporated into the crystal lattice in the region 725 by a thermal anneal step (e.g., melting from the back surface or non-melting laser anneal after implantation).

[0081] A first electrical load terminal contact LI to the first load terminal structure 720 and an electrical control terminal contact C to the control terminal structure (if present in the vertical power semiconductor device) are portions of a wiring region over the first surface 707. A second electrical load contact L2 to the second load terminal structure 725 is provided at the second surface 708. The electrical load contacts LI, L2 and the electrical control terminal contact C can be formed by one or more patterned conductive layers, such as metallization layers, electrically isolated by interlayer dielectric layer(s) sandwiched therebetween. For example, contact openings in the interlayer dielectric layer(s) can be filled with conductive material(s) to provide electrical contact between the one or more patterned conductive layers and / or active region(s) in the silicon semiconductor body, such as the first load terminal structure 720. For example, the patterned conductive layer(s) and the interlayer dielectric layer(s) can form a wiring region over the semiconductor body 704 at the first surface 707. For example, a conductive layer, e.g., a metallization layer or a metallization layer stack, can be provided at the second surface 708.

[0082] In the vertical semiconductor device illustrated in Figure 4A , the current flow direction is between the first load terminal contact LI and the second load terminal contact L2 along a vertical direction between the opposing first surface 707 and the second surface 708.

[0083] Figure 4Bis a schematic cross-sectional view of a portion of a lateral semiconductor device according to an embodiment. The lateral semiconductor device differs from the vertical semiconductor device in that the second load terminal structure 725 and the second load terminal contact L2 are formed at the first surface 707. The first load terminal structure 720 and the second load terminal structure 725 can be formed simultaneously by the same process. Likewise, the first load terminal contact L1 and the second load terminal contact L2 can be formed simultaneously by the same process.

[0084] Aspects and features mentioned and described in connection with the previously detailed examples and one or more of the figures can also be combined with one or more of the other examples in order to replace similar features of the other examples or in order to additionally introduce features to the other examples.

[0085] More details and aspects are mentioned in connection with the embodiments described above or below. Processing a wide bandgap semiconductor wafer can include one or more optional additional features corresponding to one or more aspects mentioned in connection with the presented concepts or one or more embodiments described above or below.

Claims

1. A method for processing a semiconductor substrate (100), the method comprising: forming a cavity (104) in the semiconductor substrate (100) by implanting ions through a first surface (102) of the semiconductor substrate (100), wherein the cavity (104) defines a separation layer (106) in the semiconductor substrate (100); thereafter forming a semiconductor layer (108) on the first surface (102) of the semiconductor substrate; forming a semiconductor device element in the semiconductor layer (108); and thereafter separating the semiconductor substrate (100) along the separation layer into a first substrate portion (1001) comprising the semiconductor layer (108) and a second substrate portion (1002), wherein the method further comprises implanting protons through the semiconductor layer (108) into the semiconductor substrate (100).

2. The method of claim 1, wherein the ions comprise helium ions, and the implantation dose of the helium ions is in a range from 5 x 1013 cm"2 to 5 x 1015 cm"2. 14 cm -2 to 5 x 1015 cm"2. 15 cm -2 to 5 x 1015 cm"2.

3. The method of claim 1, wherein the ions comprise protons, and the implantation dose of protons is in a range from 5 x 1013 cm"2 to 5 x 1015 cm"2. 15 cm -2 16 cm -2 ​​ 4. The method according to any one of claims 1 to 3, wherein the ions further comprise ions comprising carbon.

5. The method according to any one of claims 1 to 3, wherein a temperature of the semiconductor substrate (100) is set in a range from 20 °C to 700 °C during the implanting of the ions.

6. The method according to any one of claims 1 to 3, wherein the cavity (104) is formed in a porous portion (112) of the semiconductor substrate (100).

7. The method according to claim 6, wherein the porous portion (112) is arranged between non-porous single-crystalline portions (1141, 1142) of the semiconductor substrate (100).

8. The method according to claim 7, wherein prior to forming the cavity (104) in the semiconductor substrate (100), the semiconductor substrate (100) is processed by forming a semiconductor layer on a first portion of the semiconductor substrate (100), wherein the semiconductor layer is a second portion of the semiconductor substrate (100) exposed at the first surface of the semiconductor substrate, and wherein a thickness of the second portion of the semiconductor substrate (100) is in a range from 5 pm to 60 pm.

9. The method according to any one of claims 1 to 3, wherein separating the semiconductor substrate (100) along the separation layer (106) comprises simultaneously illuminating the semiconductor substrate (100) with superimposed electromagnetic radiation from at least two radiation sources, the superimposed electromagnetic radiation having intensity peaks at two or more wavelengths.

10. The method of any one of claims 1 to 3, wherein, forming the semiconductor device element in the semiconductor layer comprises forming at least one doped semiconductor region in the semiconductor layer by introducing a dopant into the semiconductor layer, wherein the at least one doped semiconductor region is part of at least one of a power MOSFET, a diode, an IGBT, and a JFET.

11. A method for processing a semiconductor substrate (100), the method comprising: implanting ions through a first surface (102) of the semiconductor substrate (100) to define a separation layer (106) in the semiconductor substrate (100); and and separating the semiconductor substrate (100) into a first substrate portion (1001) and a second substrate portion (1002) along the separation layer (106) by irradiating the semiconductor substrate (100) at least by electromagnetic radiation of a first wavelength and by electromagnetic radiation of a second wavelength different from the first wavelength, wherein free carriers are generated in the separation layer by the electromagnetic radiation of the first wavelength and the generated free carriers are locally heated by the electromagnetic radiation of the second wavelength.

12. The method of claim 11, wherein the electromagnetic radiation of the first wavelength is emitted by a first radiation source and the electromagnetic radiation of the second wavelength is emitted by a second radiation source different from the first radiation source.

13. The method of any one of claims 11 to 12, wherein an absorption coefficient of the separation layer is at least 100 times larger for the electromagnetic radiation of the first wavelength than an absorption coefficient of a semiconductor material of the semiconductor substrate outside the separation layer.

14. The method of any one of claims 11 to 12, wherein the second wavelength is larger than the first wavelength.

15. The method of any one of claims 11 to 12, wherein the implanted ions are at least one of nitrogen ions, phosphorous ions, vanadium ions, boron ions, argon ions, carbon ions, nickel ions, silicon ions, titanium ions, tantalum, molybdenum, tungsten ions, gallium ions, and aluminum ions.

16. The method of any one of claims 11 to 12, further comprising: forming a semiconductor layer on the first surface of the semiconductor substrate after implanting the ions; and forming a semiconductor device element in the semiconductor layer before separating the semiconductor substrate along the separation layer.

17. The method of claim 16, wherein, forming the semiconductor device element in the semiconductor layer comprises forming at least one doped semiconductor region in the semiconductor layer by introducing a dopant into the semiconductor layer, wherein the at least one doped semiconductor region is part of at least one of a power MOSFET, a diode, an IGBT, and a JFET.

18. The method of any one of claims 11 to 12, wherein, separating the semiconductor substrate along the separation layer comprises at least one of i) irradiating the semiconductor substrate at least partially with electromagnetic radiation; ii) heating the semiconductor substrate; iii) applying a mechanical force and / or stress to the semiconductor substrate; iv) subjecting the semiconductor substrate to ultrasonic treatment; v) irradiating the semiconductor substrate with protons.

19. The method of claim 18, wherein, applying a mechanical force and / or stress to the semiconductor substrate comprises forming a stress inducing layer on a second surface of the semiconductor substrate opposite the first surface.

20. The method of any one of claims 11 to 12, wherein, the semiconductor substrate is a SiC substrate and the thickness of the separation layer is in a range from 300 nm to 600 nm.

21. The method of any one of claims 11 to 12, wherein the separation layer is formed within the semiconductor substrate at a vertical distance from the first surface of the semiconductor substrate in a range from 500 nm to 5 pm.

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