Semiconductor device comprising electrical contacts and a metal layer arranged on the electrical contacts

Abstract

A semiconductor device includes a semiconductor die, an electrical contact disposed on a surface of the semiconductor die, and a metal layer disposed on the electrical contact, wherein the metal layer includes singulated portions of at least one of a metal foil, a metal sheet, a metal lead frame, and a metal plate. An area of coverage of the electrical contact and an area of coverage of the metal layer are substantially coincident when viewed in a direction normal to the surface of the semiconductor die.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor technology. In particular, the present disclosure relates to a semiconductor device comprising an electrical contact and a metal layer arranged on the electrical contact. The present disclosure further relates to a method for manufacturing such a semiconductor device. BACKGROUND

[0002] Semiconductor wafers for manufacturing semiconductor devices are becoming thinner and thinner, so that the semiconductor wafers and semiconductor dies obtained therefrom can suffer from weak mechanical stability. However, high thermo-mechanical stresses can occur when the semiconductor wafers are processed and the semiconductor dies are attached. Manufacturers of semiconductor devices are constantly striving to improve their products and their manufacturing methods. It is desirable to develop semiconductor devices with improved mechanical stability and methods for manufacturing such semiconductor devices. SUMMARY

[0003] An aspect of the present disclosure relates to a semiconductor device. The semiconductor device comprises a semiconductor die. The semiconductor device further comprises an electrical contact arranged on a surface of the semiconductor die. The semiconductor device further comprises a metal layer arranged on the electrical contact, wherein the metal layer comprises a singulated cut portion of at least one of a metal foil, a metal sheet, a metal lead frame, and a metal plate. A footprint of the electrical contact and a footprint of the metal layer substantially coincide when viewed in a direction perpendicular to the surface of the semiconductor die.

[0004] Another aspect of the present disclosure relates to a method. The method comprises providing a metal layer comprising a plurality of recesses. The method further comprises providing a semiconductor wafer comprising a plurality of semiconductor dies, wherein each semiconductor die comprises an electrical contact arranged on a surface of the semiconductor wafer. The method further comprises aligning a section of the metal layer between adjacent recesses with the electrical contact. The method further comprises joining the electrical contact and the section of the metal layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] The accompanying drawings are included to provide a further understanding of a number of aspects, and are incorporated in and constitute a part of this specification. The drawings illustrate a number of aspects and, together with the description, serve to explain principles of each aspect. Other aspects and many of the intended advantages of various aspects are discussed in greater detail below. Elements of the drawings can not be to scale as the primary purpose of the drawings is to convey principles. Like reference numerals can designate like parts throughout the specification.

[0006] Figure 1 A side cross-sectional view of a semiconductor device according to the present disclosure is schematically shown.

[0007] Figure 2A , Figure 2B , Figure 2C ,Figure 2D A side cross-sectional view of a method for manufacturing a semiconductor device according to the present disclosure is schematically illustrated.

[0008] Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D 、 Figure 3E 、 Figure 3F 、 Figure 3G 、 Figure 3H 、 Figure 3I 、 Figure 3J 、 Figure 3K 、 Figure 3L 、 Figure 3M 、 Figure 3N 、 Figure 3O 、 Figure 3P A method for manufacturing a semiconductor device according to the present disclosure is schematically illustrated.

[0009] Figure 4 A side cross-sectional view of a semiconductor device according to the present disclosure is schematically illustrated.

[0010] Figure 5 A side cross-sectional view of a semiconductor device according to the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0011] In the following detailed description, reference is made to the accompanying drawings, which illustrate, by way of example, particular aspects of the present disclosure. In this regard, directional terminology, such as "top," "bottom," "front," "back," etc., can be used with reference to the orientation of the described drawings. Because these devices can be positioned in a number of different orientations, the directional terminology can be used for purposes of explanation without limiting the scope of the present disclosure. Other aspects can be utilized and structural or logical changes can be made without departing from the concept of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense as the concept of the present disclosure is defined by the appended claims.

[0012] A semiconductor device 100 of Figure 1 is shown in general terms so as to qualitatively specify aspects of the present disclosure. Semiconductor device 100 can include other aspects not shown for simplicity. For example, semiconductor device 100 can be extended by any of the aspects described in connection with other semiconductor devices and methods according to the present disclosure.

[0013] The semiconductor device 100 can comprise a semiconductor die 2. Electrical contacts 4 can be arranged on a surface 6 of the semiconductor die 2. Further, a metal layer 8 can be arranged on the electrical contacts 4, wherein the metal layer 8 comprises singulated separated portions of at least one of a metal foil, a metal sheet, a metal lead frame, and a metal plate. When viewed in a direction perpendicular to the surface 6 of the semiconductor die 2, i.e. in the y-direction, the footprint of the electrical contacts 4 and the footprint of the metal layer 8 can substantially coincide. In this regard, the expression “substantially coincide” can not necessarily mean that the footprints coincide in an ideal geometrical sense, but that the footprints can also slightly deviate from each other when manufacturing tolerances in the manufacturing of the electrical contacts 4 and the metal layer 8 are taken into account. Thus, the footprints of the electrical contacts 4 and the metal layer 8 can comprise small non-overlapping portions. For example, the footprint of the electrical contacts 4 can be arranged (in particular completely) in the footprint of the metal layer 8 and vice versa. The term “footprint” which can be used herein is similar to the terms “outline”, “outer contour”, “profile” or “outer profile”.

[0014] Generally, the semiconductor die 2 can comprise an integrated circuit, a passive electronic device, an active electronic device, etc. The integrated circuit can be designed as a logic integrated circuit, an analog integrated circuit, a mixed-signal integrated circuit, a power integrated circuit, etc. In one example, the semiconductor die 2 can be made of a semiconductor elemental material (e.g. Si). In another example, the semiconductor die 2 can be made of a wide bandgap semiconductor material or a compound semiconductor material (e.g. SiC, GaN, SiGe, GaAs). The semiconductor die 2 can be used in any type of power application, e.g. a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a half-bridge circuit, a power module comprising a gate driver, etc. In particular, the semiconductor die 2 can comprise or can be part of a power device, e.g. a power MOSFET, a LV (low voltage) power MOSFET, a power IGBT (Insulated Gate Bipolar Transistor), a power diode, a super junction power MOSFET, etc.

[0015] The method of Figures 2A-2D is also shown in a general way in order to qualitatively specify aspects of the present disclosure. The method can comprise further aspects which are not shown for the sake of simplicity. For example, the method can be extended by any aspect described in connection with the method of Figures 3A-3P The method of Figures 2A-2D The method of Figure 1 The semiconductor device of

[0016] InFigure 2A In this process, a metal layer 8 may be provided, comprising multiple recesses (or trenches or cavities) 10. Figure 2A In the example, for simplicity, only the section of metal layer 8 including the three recesses 10 is shown. Metal layer 8 may further extend in the x and z directions (see horizontal dashed lines), and therefore may include any number of additional recesses 10.

[0017] exist Figure 2B In this process, a semiconductor wafer 12 comprising a plurality of semiconductor dies 2 may be provided. Each semiconductor die 2 may include one or more electrical contacts 4 disposed on a surface 14 of the semiconductor wafer 12. The vertical dashed lines indicate locations where the semiconductor wafer 12 may later be individually divided into a plurality of semiconductor dies 2.

[0018] exist Figure 2C In this configuration, the section 16 between adjacent recesses 10 of the metal layer 8 can be aligned with the electrical contact portion 4 of the semiconductor die 2. When viewed along the y-direction, the coverage area of ​​the electrical contact portion 4 and the coverage area of ​​the section 16 can be substantially the same.

[0019] exist Figure 2D In this process, the electrical contact 4 of the semiconductor die 2 and the segment 16 of the metal layer 8 can be bonded together. Exemplary bonding techniques are described in detail below and may be particularly relevant to specific materials of the electrical contact 4 and the metal layer 8.

[0020] Figures 3A-3P The method can be seen as Figures 2A-2D A more detailed implementation of the method is described below. The details of the method described below can therefore be applied in the same way to... Figures 2A-2D The method. Furthermore, the manufactured semiconductor device 300 can be considered as... Figure 1 A more detailed implementation of the semiconductor device 100.

[0021] Figure 3A A top view of metal layer 8 is shown. The shape of metal layer 8 can be similar to that of a semiconductor wafer or semiconductor panel used to manufacture a semiconductor device according to this disclosure. Figure 3A In one example, the shape of metal layer 8 can be circular. In another example, the shape of metal layer 8 can be square or rectangular. The semiconductor wafer can later be individualized into multiple semiconductor dies. Individualization can be performed along scribe lines, which can be formed as follows: Figure 3A The grid shown consists of small squares or rectangles.

[0022] The metal layer 8 can be made of or can comprise a metal or a metal alloy which is configured to be subsequently bonded with electrical contacts of semiconductor dies. In particular, the metal layer 8 can be made of at least one of copper, a copper alloy, molybdenum and a molybdenum alloy. The metal layer 8 can be made of or comprise at least one of a metal foil, a metal sheet, a metal lead frame and a metal plate. In this regard, the metal layer 8 can be formed by only one metal layer or by a stack of multiple metal layers.

[0023] In Figure 3B , the metal layer 8 can be structured by manufacturing a plurality of recesses 10 in an upper surface of the metal layer 8. The metal layer 8 can be structured separately from the semiconductor wafer. The recesses 10 can be manufactured by any suitable technique such as sawing, cutting, applying a laser beam, milling, wet etching, plasma etching, etc. The recesses 10 can have a depth-to-width (depth: width) ratio of e.g. 2:1. In Figure 3B , the recesses 10 can have a rectangular shape. In another example, the recesses 10 can have a circular shape, a V-shape, a polygonal shape, etc. depending on the manufacturing technique chosen. For the sake of simplicity, Figure 3B , the example only shows two recesses 10 arranged in the upper surface of the metal layer 8. As will become apparent later, the positions of the recesses 10 in the metal layer 8 can be related to the positions of at least one of the scribe lines of the semiconductor wafer and the electrical contacts of the semiconductor dies to be manufactured from the semiconductor wafer.

[0024] The thickness of the metal layer 8 in the y-direction can be greater than about 20 micrometers, or greater than about 30 micrometers, or greater than about 40 micrometers, or greater than about 50 micrometers. The maximum thickness of the metal layer 8 can e.g. be related to the kerf width. For example, when the metal layer 8 is structured on only one surface, a kerf width of about 30 micrometers can result in a maximum thickness of the metal layer 8 in the range of about 55 micrometers to about 65 micrometers (see Figure 3B ). In case of a double-sided structuring (see Figure 3D ), a kerf width of about 30 micrometers can result in a thickness of the metal layer 8 in the range of about 90 micrometers to about 130 micrometers.

[0025] In Figure 3C , the recesses 10 can be filled with an electrically insulating material 18. After the filling operation, the upper surface of the metal layer 8 and the upper surface of the electrically insulating material 18 can be coplanar, i.e. can lie in a common plane. The electrically insulating material 18 can comprise at least one of a resist, an epoxy, an imide and a molding compound. The molding compound can comprise at least one of the following materials: an epoxy, a filled epoxy, a glass fiber filled epoxy, an imide, a thermoplastic, a thermoset polymer, a polymer blend. InFigure 3C In an example, the recess 10 can extend only partially into the metal layer 8, such that a bottom surface of the recess 10 can be formed by the material of the metal layer 8. In another example, the recess 10 can extend completely from an upper surface of the metal layer 8 to a lower surface of the metal layer 8. Here, the recess 10 can be completely filled with the electrically insulating material 18. In particular, an upper surface of the electrically insulating material 18 can be coplanar with the upper surface of the metal layer 18, and a lower surface of the electrically insulating material 18 can be coplanar with the lower surface of the metal layer 8.

[0026] Figure 3D One alternative example of a metal layer 8 that can be structured on both surfaces is shown. In manufacturing the metal layer 8, recesses 10 can be formed on opposite sides of the metal layer 8. The electrically insulating material 18 can be filled in one of the surfaces of the metal layer 8. In an example, the electrically insulating material 18 can form a bottom surface of the recess 10 arranged in the lower surface of the metal layer 8. The operations described below are based on a metal layer 8 structured on only one surface (see Figure 3D Figure 3D Figure 3B ), but can be similarly applied to a double-sided structured metal layer 8 (see Figure 3D ).

[0027] In Figure 3E , at least two openings 20 in the metal layer 8 can be manufactured, for example, by at least one of etching and stamping. The openings 20 can be configured as alignment marks for aligning the metal layer 8 with a semiconductor wafer. For example, the openings 20 can be manufactured by removing semiconductor dies from the semiconductor wafer. Figure 3E The metal layer 8 in

[0028] In Figure 3F , a semiconductor wafer 12 can be provided. The semiconductor wafer 12 can comprise a semiconductor substrate 22 and a device layer 24 arranged in the semiconductor substrate 22. The device layer 24 can comprise microelectronic devices that can have been integrated in the semiconductor substrate 22 by applying various microfabrication processes such as doping, ion implantation, etching, thin film deposition of various materials, photolithographic patterning, etc.

[0029] In Figure 3F ​​In the example of FIG. 1, the device layer 24 can exemplarily comprise a plurality of semiconductor devices located between the vertical dashed lines. In particular, the semiconductor devices can be power semiconductor devices such as power transistors, power diodes, etc. In the shown example, the semiconductor devices can be power MOSFETs 26, wherein each integrated power MOSFET 26 comprises two electrical contacts 4A, 4B arranged on the upper surface of the semiconductor wafer 12. For example, the electrical contacts 4A, 4B can be made of at least one of copper, copper alloys, molybdenum and molybdenum alloys. The electrical contacts 4A and 4B can correspond to source and gate contacts of the power MOSFET 26, respectively, and can be electrically coupled to a respective electronic structure in the device layer 24. The drain contact of the power MOSFET 26 can be manufactured later. In Figure 3F In the example of FIG. 1, the power MOSFETs 26 can have a vertical structure, i.e. the power MOSFETs 26 can comprise electrodes arranged on both major faces of the power MOSFETs 26 such that the current can flow substantially in the vertical y-direction. In another example, the power MOSFETs 26 can have a lateral structure, i.e. the power MOSFETs 26 can comprise electrodes arranged on one of the major faces such that the current can flow substantially in the lateral x-direction.

[0030] In the example of FIG. 1, the device layer 24 can exemplarily comprise a plurality of semiconductor devices located between the vertical dashed lines. In particular, the semiconductor devices can be power semiconductor devices such as power transistors, power diodes, etc. In the shown example, the semiconductor devices can be power MOSFETs 26, wherein each integrated power MOSFET 26 comprises two electrical contacts 4A, 4B arranged on the upper surface of the semiconductor wafer 12. For example, the electrical contacts 4A, 4B can be made of at least one of copper, copper alloys, molybdenum and molybdenum alloys. The electrical contacts 4A and 4B can correspond to source and gate contacts of the power MOSFET 26, respectively, and can be electrically coupled to a respective electronic structure in the device layer 24. The drain contact of the power MOSFET 26 can be manufactured later. In Figure 3F In the example of FIG. 1, the device layer 24 can exemplarily comprise a plurality of semiconductor devices located between the vertical dashed lines. In particular, the semiconductor devices can be power semiconductor devices such as power transistors, power diodes, etc. In the shown example, the semiconductor devices can be power MOSFETs 26, wherein each integrated power MOSFET 26 comprises two electrical contacts 4A, 4B arranged on the upper surface of the semiconductor wafer 12. For example, the electrical contacts 4A, 4B can be made of at least one of copper, copper alloys, molybdenum and molybdenum alloys. The electrical contacts 4A and 4B can correspond to source and gate contacts of the power MOSFET 26, respectively, and can be electrically coupled to a respective electronic structure in the device layer 24. The drain contact of the power MOSFET 26 can be manufactured later. In

[0031] The segments 16 of the metal layer 8 can be aligned with the electrical contacts 4A, 4B such that one segment 16 can be arranged on a respective one of the electrical contacts 4A, 4B. Thus, the recesses filled with the electrically insulating material 18 can be aligned with the scribe lines 28 of the semiconductor wafer 12 and / or with segments of the semiconductor wafer 12 arranged between the electrical contacts 4A, 4B. By using the openings 20 of the metal layer 8 as alignment marks, a correct alignment can be provided (see FIG. 2). During the alignment operation, the metal layer 8 can be arranged on a temporary carrier (not shown) which can be removed later. For example, the metal layer 8 can be fixed to the temporary carrier by at least one of glue, clamping rings and clamping plates. Figure 3E ) In the example of FIG. 1, the device layer 24 can exemplarily comprise a plurality of semiconductor devices located between the vertical dashed lines. In particular, the semiconductor devices can be power semiconductor devices such as power transistors, power diodes, etc. In the shown example, the semiconductor devices can be power MOSFETs 26, wherein each integrated power MOSFET 26 comprises two electrical contacts 4A, 4B arranged on the upper surface of the semiconductor wafer 12. For example, the electrical contacts 4A, 4B can be made of at least one of copper, copper alloys, molybdenum and molybdenum alloys. The electrical contacts 4A and 4B can correspond to source and gate contacts of the power MOSFET 26, respectively, and can be electrically coupled to a respective electronic structure in the device layer 24. The drain contact of the power MOSFET 26 can be manufactured later. In

[0032] In the example of FIG. 1, the device layer 24 can exemplarily comprise a plurality of semiconductor devices located between the vertical dashed lines. In particular, the semiconductor devices can be power semiconductor devices such as power transistors, power diodes, etc. In the shown example, the semiconductor devices can be power MOSFETs 26, wherein each integrated power MOSFET 26 comprises two electrical contacts 4A, 4B arranged on the upper surface of the semiconductor wafer 12. For example, the electrical contacts 4A, 4B can be made of at least one of copper, copper alloys, molybdenum and molybdenum alloys. The electrical contacts 4A and 4B can correspond to source and gate contacts of the power MOSFET 26, respectively, and can be electrically coupled to a respective electronic structure in the device layer 24. The drain contact of the power MOSFET 26 can be manufactured later. In Figure 3GIn particular, the upper surfaces of the electrical contact portions 4A, 4B can be bonded to the lower surfaces of the segments 16. For example, the bonding operation can include at least one of a diffusion bonding operation, a pre-sintering operation, and a sintering operation. A metal-to-metal bond can be obtained between the electrical contact portions 4A, 4B and the respective segments 16 of the metal layer 8. Depending on the selected bonding technique, the metal-to-metal bond can include at least one of a bonded joint and a sintered joint. For example, the metal-to-metal bond can include inhomogeneities in the grain structure of the bonded metals. That is, even when the electrical contact portions 4A, 4B and the metal layer 8 can be made of the same or similar materials, the metal-to-metal bond can still be detected by appropriate detection techniques.

[0033] In one example, the electrical contact portions 4A, 4B and the segments 16 of the metal layer 8 can be bonded by applying a diffusion bonding operation. The temperature of the diffusion bonding operation can be in the range of about 100 degrees Celsius to about 260 degrees Celsius, more particularly in the range of about 160 degrees Celsius to about 240 degrees Celsius, more particularly about 180 degrees Celsius to about 220 degrees Celsius. An exemplary specific temperature value for the diffusion bonding operation can be about 200 degrees Celsius. The duration of the diffusion bonding operation can be in the range of about 5 minutes to about 3 hours, more particularly in the range of about 15 minutes to about 2 hours, more particularly in the range of about 30 minutes to about 1 hour. In one example, the diffusion bonding operation can be based on a two-step approach, including a first step based on the process parameters mentioned above. In a second step, the temperature can be increased to a higher value in the range of about 380 degrees Celsius to about 420 degrees Celsius.

[0034] In another example, the electrical contact portions 4A, 4B and the segments 16 of the metal layer 8 can be bonded by applying a pre-sintering operation. The temperature of the pre-sintering operation can be in the range of about 160 degrees Celsius to about 240 degrees Celsius, more particularly in the range of about 180 degrees Celsius to about 220 degrees Celsius. An exemplary specific temperature value for the pre-sintering operation can be about 200 degrees Celsius. The duration of the pre-sintering operation can be in the range of about 1 minute to about 30 minutes, more particularly in the range of about 5 minutes to about 30 minutes. The pressure applied during the pre-sintering operation can be particularly related to the materials to be bonded and can be in the range of about 15 MPa to about 30 MPa. An additional sintering operation can be subsequently applied.

[0035] In Figure 3HIn particular, material can be removed (see arrow) from the upper surface of the metal layer 8 until the upper surface of the electrically insulating material 18 is exposed. For the case that the electrically insulating material 18 already extends completely from the upper surface of the metal layer 8 to the lower surface of the metal layer 8, no material removal can be required. The removal of material can comprise at least one of a grinding operation and an etching operation, for example. In this regard, the electrically insulating material 18 can be configured to protect the upper structure of the power MOSFET 26 during the material removal operation. Further, the electrically insulating material 18 can be configured to stabilize the metal layer 8 during the removal of material. The removal of material from the metal layer 8 can result in a planarization of the upper surface of this configuration. That is, after the removal of material from the metal layer 8, the upper surface of the metal layer 8 and the upper surface of the electrically insulating material 18 can be coplanar, i.e. can lie in a common plane. The removal of the electrically conductive material can eliminate the risk of short circuits. In addition, the electrically conductive material can be removed from areas where laser radiation can be applied in a subsequent singulation operation.

[0036] In Figure 3I particular, the (sacrificial) electrically insulating material 18 can be removed. In this regard, the distance between the electrical contacts 4A, 4B can be sufficiently large in particular to allow for such a removal process. The technique of removing the electrically insulating material 18 can be related to the respective material type. For example, the resist can be removed by applying a resist cleaner. After the removal of the electrically insulating material 18, a further sintering operation can be applied. The temperature of the sintering operation can be in the range of about 250 degrees Celsius to about 400 degrees Celsius. In addition, a packaging operation (not shown) can be performed by applying at least one of a resist, a molding compound and an epoxy resin to the upper surface of the semiconductor wafer 12.

[0037] In Figure 3J particular, the (sacrificial) electrically insulating material 18 can be removed. In this regard, the distance between the electrical contacts 4A, 4B can be sufficiently large in particular to allow for such a removal process. The technique of removing the electrically insulating material 18 can be related to the respective material type. For example, the resist can be removed by applying a resist cleaner. After the removal of the electrically insulating material 18, a further sintering operation can be applied. The temperature of the sintering operation can be in the range of about 250 degrees Celsius to about 400 degrees Celsius. In addition, a packaging operation (not shown) can be performed by applying at least one of a resist, a molding compound and an epoxy resin to the upper surface of the semiconductor wafer 12. Figures 3A-3P The material properties of the glue 30 can have a limiting effect on the manufacturing operations. For example, the glue 30 can only withstand a maximum temperature for a limited time. An exemplary value of such a maximum temperature can be about 270 degrees Celsius. In a more specific example, the glue 30 can only withstand a temperature of about 200 degrees Celsius for about 20 minutes. In particular, the material properties of the glue 30 can have a limiting effect on the temperature and / or the duration of the sintering process.

[0038] In Figure 3K particular, the (sacrificial) electrically insulating material 18 can be removed. In this regard, the distance between the electrical contacts 4A, 4B can be sufficiently large in particular to allow for such a removal process. The technique of removing the electrically insulating material 18 can be related to the respective material type. For example, the resist can be removed by applying a resist cleaner. After the removal of the electrically insulating material 18, a further sintering operation can be applied. The temperature of the sintering operation can be in the range of about 250 degrees Celsius to about 400 degrees Celsius. In addition, a packaging operation (not shown) can be performed by applying at least one of a resist, a molding compound and an epoxy resin to the upper surface of the semiconductor wafer 12. Figure 3JThe arrangement of the semiconductor wafer 12 can be flipped, i.e. turned by 180 degrees (see arrow). Additionally, the backside of the semiconductor wafer 12 can be thinned, e.g. by applying at least one of a grinding operation and an etching operation. By thinning the semiconductor wafer 12, excess semiconductor material of the semiconductor wafer 12 can be removed. After the thinning operation, at least the device layer 24 can be left. The thickness of the thinned semiconductor wafer 12 along the y-direction can be related to the type of microelectronic device integrated in the semiconductor material. For example, the thickness can be less than about 80 micrometers, or less than about 60 micrometers, or less than about 40 micrometers, or less than about 20 micrometers, or less than about 10 micrometers, or less than about 5 micrometers. Exemplary values for the thickness of the thinned semiconductor wafer 12 including LV power MOSFETs can even be as low as about 3 micrometers.

[0039] In Figure 3L , the electrical contact 4C can be fabricated on the upper surface of the device layer 24, e.g. by applying a suitable metallization technique. In Figure 3L , the electrical contact 4C can already be structured after the metallization process. In another example, an unstructured metallization layer can be fabricated over substantially the entire upper surface of the device layer 24, and the electrical contact 4C can be formed later by a singulation process, e.g. using a multi-beam nanosecond laser.

[0040] In Figure 3L , the electrical contact 4C can correspond to a drain contact of the power MOSFET 26, which can be electrically connected to a corresponding electronic structure in the device layer 24. Similar to the electrical contacts 4A, 4B, the electrical contact 4C can be made of at least one of copper, a copper alloy, molybdenum and a molybdenum alloy. The thickness of the electrical contact 4C in the y-direction can be related to the technique that can be used later to bond the electrical contact 4C to a metal layer. In case of a sintering technique, the thickness of the electrical contact 4C in the y-direction can be in the range of about 10 micrometers to about 100 micrometers. More particularly, the thickness can be in the range of about 10 micrometers to about 30 micrometers, or in the range of about 50 micrometers to about 100 micrometers. In case of a diffusion bonding technique, the thickness of the electrical contact 4C in the y-direction can be less than about 10 micrometers, more particularly less than about 5 micrometers.

[0041] In Figure 3L , a further metal layer 8 can be provided. The metal layer 8 can include a plurality of recesses 10 and segments 16 arranged therebetween. The footprint of the segments 16 can substantially coincide with the footprint of the electrical contact 4C when viewed along the y-direction. In Figure 3L , the recesses 10 in the metal layer 8 can remain unfilled. In another example, the recesses 10 can be filled with an (sacrificial) electrically insulating material, as discussed in connection with previous figures.

[0042] The segments 16 of the metal layer 8 can be aligned with the electrical contacts 4C such that one segment 16 can be arranged over one of the electrical contacts 4C, respectively. Thus, the recesses 10 can be aligned with the scribe lines 28 of the semiconductor wafer 12. A correct alignment can be obtained by using the openings 20 of the metal layer 8 as alignment marks.

[0043] In Figure 3M , similar to Figure 3G , the electrical contacts 4C and the segments 16 of the metal layer 8 can be brought into mechanical contact and can be bonded together. After the bonding operation, material can be removed from the upper surface of the metal layer 8 until the segments 16 of the metal layer 8 are separated from each other. The material can be removed, for example, by applying at least one of a grinding operation and an etching operation. Removing the material can result in a planarization of the upper surface of the arrangement. That is, after removing the material of the metal layer 8, the upper surfaces of the separated segments of the metal layer 8 can be coplanar, i.e. can lie in a common plane.

[0044] In Figure 3N , the arrangement of Figure 3M may be flipped (see arrow). The flipped arrangement can be placed on a temporary carrier 34 of, for example, a sawing frame. The glue 30 can be cured, for example, by applying UV radiation through the carrier 32, such that the carrier 32 and the glue 30 can be removed.

[0045] In Figure 3O , the arrangement can be singulated into a plurality of semiconductor devices 300 by removing semiconductor material between the individual power MOSFETs 26 of the semiconductor wafer 12. The singulation operation can comprise at least one of sawing, dicing, applying a laser beam, milling, etching. The drain contacts 4C of the power MOSFETs 26 after singulation can substantially cover the entire lower surface of the semiconductor devices 300.

[0046] In Figure 3O , each manufactured semiconductor device 300 can comprise the metal layer 8 over each electrical contact 4A to 4C, respectively, in an example. In another example, the manufactured semiconductor device can comprise the metal layer only over the electrical contacts 4A, 4B on the upper surface of the semiconductor device. In yet another example, the manufactured semiconductor device can comprise the metal layer only over the electrical contacts 4C on the lower surface of the semiconductor device.

[0047] In Figure 3PIn this process, the carrier 34 can be removed during the die attachment operation, and one or more semiconductor devices 300 can be arranged on the lead frame 36. The semiconductor device 300 can be further processed, wherein, for simplicity, other possible processing operations are not explicitly described herein. In an exemplary further operation, the semiconductor device 300 can be encapsulated by a molding compound and subsequently individualized into multiple packaged semiconductor devices.

[0048] Figure 4 The semiconductor device 400 can be regarded as Figure 1 A more detailed embodiment of the semiconductor device 100. For example, the semiconductor device 400 can be implemented according to... Figures 3A-3P The method is used to manufacture it.

[0049] Semiconductor device 400 may include semiconductor die 2. Figure 4 In the example, the semiconductor die 2 may include a power MOSFET having two electrical contacts 4A and 4B disposed on the upper surface of the semiconductor die 2 and a third electrical contact 4C disposed on the lower surface of the semiconductor die 2. An intermediate conductive layer may be disposed between the semiconductor die 2 and the electrical contacts 4A and 4B. The electrical contacts 4A and 4B may correspond to the source contact and gate contact of the semiconductor die 2, respectively. In addition, the electrical contact 4C may correspond to the drain contact of the semiconductor die 2. Metal layers 8A to 8C may be disposed on the electrical contacts 4A to 4C, respectively. Each of the metal layers 8A to 8C may include or may correspond to a single-divided portion of at least one of a metal foil, a metal sheet, a metal lead frame, and a metal plate. When viewed along the y-direction, the coverage areas of the electrical contacts 4A to 4C and the coverage areas of the metal layers 8A to 8C may be substantially consistent. In another example (not shown), the semiconductor die 2 may include a bipolar transistor, wherein electrical contacts 4A to 4C may correspond to the base, emitter, and collector.

[0050] The thickness of the semiconductor die 2 in the y-direction can be less than about 80 micrometers, or less than about 60 micrometers, or less than about 40 micrometers, or less than about 20 micrometers, or less than about 10 micrometers, or less than about 5 micrometers. Exemplary values ​​for the thickness of the LV power MOSFET can even be as low as about 3 micrometers.

[0051] The thickness of the metal layers 8A to 8C in the y direction can range from about 40 micrometers to about 130 micrometers.

[0052] The thickness of the electrical contact portions 4A, 4B in the y-direction can be less than about 15 micrometers, or less than about 10 micrometers. The thickness of the electrical contact portion 4C in the y-direction can be related to the technology that can have been used to join the electrical contact portion 4C and the metal layer 8C. In case of a sintering technology, the thickness of the electrical contact portion 4C in the y-direction can be in the range of about 10 micrometers to about 100 micrometers. More particularly, the thickness can be in the range of about 10 micrometers to about 30 micrometers, or in the range of about 50 micrometers to about 100 micrometers. In case of a diffusion bonding technology, the thickness of the electrical contact portion 4C in the y-direction can be less than about 10 micrometers, more particularly less than about 5 micrometers.

[0053] Due to the additional metal layers 8A to 8C arranged on top of the electrical contact portions 4A to 4C, the total thickness of the semiconductor device 400 in the y-direction can increase compared to conventional semiconductor devices. The increased thickness can provide increased mechanical stability, for example, to withstand thermo-mechanical stresses when the die is attached. This can, for example, increase the efficiency in pick-and-place processes.

[0054] Due to the additional metal layers 8A to 8C arranged on top of the electrical contact portions 4A to 4C, the thickness of the electrical contact portions 4A to 4C can be chosen to be smaller than the thickness of the corresponding electrical contact portions of conventional semiconductor devices. Thus, the metallization operations for manufacturing the electrical contact portions 4A to 4C can be reduced or even completely omitted. The reduced metallization operations can save costs for manufacturing the corresponding semiconductor devices.

[0055] Figure 5 The semiconductor device 500 can at least partially resemble the semiconductor device 400 of Figure 4 Compared to the semiconductor device 400 of Figure 4 The semiconductor device 500 can only comprise one metal layer 8C arranged on top of the electrical contact portion 4C on the lower surface of the semiconductor die 2. In yet another example (not shown), a manufactured semiconductor device can only comprise metal layers 4A, 4B arranged on top of the electrical contact portions 4A, 4B on the upper surface of the semiconductor die 2.

[0056] Example

[0057] In the following, semiconductor devices and methods of manufacturing thereof will be explained by means of examples.

[0058] Example 1 is a semiconductor device comprising: a semiconductor die; an electrical contact portion arranged on a surface of the semiconductor die; and a metal layer arranged on the electrical contact portion, wherein the metal layer comprises a singulated portion of at least one of a metal foil, a metal sheet, a metal lead frame, and a metal plate, wherein a footprint of the electrical contact portion and a footprint of the metal layer substantially coincide when viewed in a direction perpendicular to the surface of the semiconductor die.

[0059] Example 2 is the semiconductor device according to Example 1, wherein a thickness of the semiconductor die in a direction perpendicular to a surface of the semiconductor die is less than 80 micrometers.

[0060] Example 3 is the semiconductor device according to Example 1 or 2, wherein a thickness of the metal layer in a direction perpendicular to a surface of the semiconductor die is in a range of 40 micrometers to 130 micrometers.

[0061] Example 4 is the semiconductor device according to any one of the preceding Examples, wherein a thickness of the electrical contact in a direction perpendicular to a surface of the semiconductor die is less than 15 micrometers.

[0062] Example 5 is the semiconductor device according to any one of the preceding Examples, wherein the semiconductor die comprises a power semiconductor device.

[0063] Example 6 is the semiconductor device according to any one of the preceding Examples, wherein at least one of the metal layer and the electrical contact is made of at least one of copper, a copper alloy, molybdenum, and a molybdenum alloy.

[0064] Example 7 is the semiconductor device according to any one of the preceding Examples, further comprising a metal-to-metal joint between the electrical contact and the metal layer, wherein the metal-to-metal joint comprises at least one of a bond joint and a sinter joint.

[0065] Example 8 is the semiconductor device according to any one of the preceding Examples, wherein each of the metal layer and the electrical contact covers an entire surface of the semiconductor die.

[0066] Example 9 is the semiconductor device according to any one of the preceding Examples, further comprising another electrical contact arranged on another surface of the semiconductor die, and another metal layer arranged on the another electrical contact, wherein a coverage area of the another electrical contact and a coverage area of the another metal layer are substantially coincident when viewed in a direction perpendicular to the another surface.

[0067] Example 10 is a method comprising: providing a metal layer comprising a plurality of recesses; providing a semiconductor wafer comprising a plurality of semiconductor dies, wherein each semiconductor die comprises an electrical contact arranged on a surface of the semiconductor wafer; aligning a section of the metal layer between adjacent recesses with the electrical contact; and joining the electrical contact and the section of the metal layer.

[0068] Example 11 is the method according to Example 10, wherein a coverage area of the electrical contact and a coverage area of the section of the metal layer are substantially coincident when viewed in a direction perpendicular to the surface of the semiconductor wafer.

[0069] Example 12 is the method of Examples 10 or 11, wherein joining the electrical contacts and the segments of the metal layer includes at least one of a diffusion bonding operation, a pre-sintering operation, and a sintering operation.

[0070] Example 13 is the method of any of Examples 10-12, further comprising aligning the recess of the metal layer with the scribe line of the semiconductor wafer.

[0071] Example 14 is the method of any of Examples 10-13, further comprising filling the recess with an electrically insulating material prior to joining the electrical contacts and the segments of the metal layer.

[0072] Example 15 is the method of Example 14, wherein the electrically insulating material includes at least one of a resist, an epoxy, an imide, and a molding compound.

[0073] Example 16 is the method of Examples 14 or 15, further comprising, after joining the electrical contacts and the segments of the metal layer, removing material from a surface of the metal layer until the electrically insulating material is exposed on the surface of the metal layer; and removing the electrically insulating material.

[0074] Example 17 is the method of any of Examples 10-16, wherein the metal layer includes at least one of a metal foil, a metal sheet, a metal lead frame, and a metal plate.

[0075] Example 18 is the method of any of Examples 10-17, further comprising providing at least two openings in the metal layer; and aligning the metal layer with the semiconductor wafer based on using the openings as alignment marks.

[0076] Example 19 is the method of any of Examples 10-18, further comprising singulating the metal layer and the semiconductor wafer into a plurality of semiconductor devices.

[0077] As employed in this specification, the terms "connected," "coupled," "electrically connected," and / or "electrically coupled" can not necessarily mean that elements are directly connected or coupled together. An intervening element can be present between "connected," "coupled," "electrically connected," or "electrically coupled" elements.

[0078] Further, the word "over" as used in, for example, the phrase "forming or positioning a material layer over a surface" of an object can be used herein to mean that the material layer can be "directly" on (e.g., formed, deposited, etc. on) the respective surface, e.g., in direct contact with the respective surface. The word "over" as used in, for example, the phrase "forming or positioning a material layer over a surface" can also be used herein to mean that the material layer can be "indirectly" on (e.g., formed, deposited, etc. on) the respective surface, e.g., with one or more additional layers disposed between the respective surface and the material layer.

[0079] Also, as used in the specification and claims, the phrase "has", "having", "includes" or "including" and variations thereof are intended to be open-ended terms that mean the same as the term "comprising". That is, as used herein, the terms "has", "having", "includes" or "including" and variations thereof are intended to be inclusive (i.e., to mean both "including" and "comprising") unless explicitly stated otherwise. The articles "a", "an" and "the" are intended to mean "one or more" unless otherwise indicated.

[0080] Also, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations. The use of the term "exemplary" is intended to present concepts in a concrete form. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Additionally, at least one of A and B and the like should generally be construed to mean A or B or both A and B, unless otherwise indicated herein or clearly contradicted by context. Furthermore, to the extent that "comprising" is used in the specification and / or claims, it is always intended to require the features recited in the

[0081] Devices and methods for making devices are described herein. Comments made in connection with a described device can also hold true for a corresponding method, and vice versa. For example, if a specific feature of a device is described, then a corresponding method can include the operation that provides the feature of the device, even if the operation is not explicitly described or illustrated in the figures. It will be appreciated that the devices and methods explained herein with reference to the figures are by way of example only, and that the scope of the claims is not limited by the examples given.

[0082] While the present disclosure has been illustrated and described in relation to one or more implementations, various equivalents, modifications and alternative applications thereof can be made by persons skilled in the art employing the teachings disclosed herein and the descriptions provided above. The present disclosure includes all such modifications and alternatives and is limited only by the scope of the claims. In particular, with respect to the various functions performed by the above-described components (e.g., elements, resources, etc.), the terms used to describe certain of these components are intended to correspond, unless otherwise indicated, to any component which performs the specified function (e.g., functionally equivalent), even if not structurally equivalent to the structure shown in the exemplary implementations herein. In addition, although a particular feature of the present disclosure can have been disclosed with respect to only one of several implementations, such feature can be combined with one or more other features of the other implementations as possible and advantageous to any given or particular application.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a metal layer (8) comprising a plurality of recesses (10); providing a semiconductor wafer (12) comprising a plurality of semiconductor dies (2), wherein each of the semiconductor dies (2) comprises an electrical contact (4) arranged on a surface (14) of the semiconductor wafer (12); aligning a section (16) of the metal layer (8) between adjacent recesses (10) with the electrical contact (4); joining the electrical contact (4) and the section (16) of the metal layer (8); after the joining, thinning a backside of semiconductor wafer (12), wherein the method further comprises: filling the recesses (10) with an electrically insulating material (18) before joining the electrical contact (4) and the section (16) of the metal layer (8); after joining the electrical contact (4) and the section (16) of the metal layer (8), removing material from a surface of the metal layer (8) until the electrically insulating material (18) is exposed at the surface of the metal layer (8); and removing the electrically insulating material (18).

2. The method of claim 1, wherein, before thinning a backside of semiconductor wafer (12), a glue (30) is applied to the surface (14) of the semiconductor wafer (12), the glue (30) covering a lateral surface and an upper side of the electrical contact (4).

3. The method of claim 1 or 2, wherein, a footprint of the electrical contact (4) and a footprint of the section (16) of the metal layer (8) coincide when viewed in a direction perpendicular to the surface (14) of the semiconductor dies (2).

4. The method of claim 1 or 2, wherein, joining the electrical contact (4) and the section (16) of the metal layer (8) comprises at least one of a diffusion bonding operation, a pre-sintering operation, and a sintering operation.

5. The method of claim 1 or 2, wherein, the method further comprises: aligning a recess (10) of the metal layer (8) with a scribe line of the semiconductor wafer (12).

6. The method of claim 1 or 2, wherein, the electrically insulating material (18) comprises at least one of a resist, an epoxy, and an imide.

7. The method of claim 1 or 2, wherein, the metal layer (8) comprises at least one of a metal foil and a metal leadframe.

8. The method of claim 1 or 2, wherein, the method further comprises: providing at least two openings (20) in the metal layer (8); and aligning the metal layer (8) with the semiconductor wafer (12) based on using the openings (20) as alignment marks.

9. The method of claim 1 or 2, wherein, the method further comprises: singulating the metal layer (8) and the semiconductor wafer (12) into a plurality of semiconductor devices.

10. The method of claim 1 or 2, wherein, the metal layer (8) comprises at least one of a metal sheet and a metal leadframe.

11. The method of claim 1 or 2, wherein, the metal layer (8) comprises at least one of a metal leadframe and a metal plate.

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