Array substrate and manufacturing method thereof and display panel

Abstract

The present application provides an array substrate and a preparation method thereof and a display panel, wherein the array substrate comprises an array area and an external circuit area surrounding the array area, the array substrate comprises a substrate layer, a binding pad and a fan-shaped routing layer, the substrate layer comprises a first surface and a second surface arranged opposite to the first surface; in the external circuit area, the substrate layer is provided with a prefabricated hole, the prefabricated hole penetrates the substrate layer, the binding pad is arranged in the prefabricated hole, the fan-shaped routing layer is arranged on the second surface of the substrate layer, and the fan-shaped routing layer is electrically connected to the binding pad. By arranging the prefabricated hole on the substrate layer, arranging the binding pad in the prefabricated hole, and then arranging the fan-shaped routing layer on the back of the array substrate, the border of the array substrate is reduced, thereby realizing a narrow border design.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the development of commercial ultra-large-size display applications such as outdoor film and television, splicing relatively small ultra-narrow-border screens to achieve ultra-large-size displays has become a technology with broad development prospects.

[0003] In order to realize narrow bezel technology, two methods are usually used to achieve it. One is to use side binding technology, but it is limited by the height of the fan-shaped routing layer and cannot further reduce the bezel; the other is to use a double substrate of glass and polyimide film layer, cut off the glass of the edge non-display area, and bend the polyimide film layer with the circuit pattern to the back for binding. However, when using this method to prepare narrow bezel products, problems such as peeling or breakage will occur between the film layers at the bend, thereby reducing the yield and affecting the performance of the display panel. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a manufacturing method thereof and a display panel, so as to reduce the frame of the array substrate.

[0005] An embodiment of the present application provides an array substrate, the array substrate comprising an array area and an external circuit area surrounding the array area, including:

[0006] A substrate layer, the substrate layer comprising a first surface and a second surface arranged opposite to the first surface; in the external circuit area, the substrate layer is provided with a prefabricated hole, the prefabricated hole penetrates the substrate layer;

[0007] a binding pad disposed in the prefabricated hole; and

[0008] The fan-shaped routing layer is disposed on the second surface of the substrate layer, and the fan-shaped routing layer is electrically connected to the binding pad.

[0009] Optionally, in some embodiments of the present application, the array substrate further includes a chip-on-chip film, and the chip-on-chip film is disposed on a side of the fan-out wiring layer away from the substrate layer.

[0010] Optionally, in some embodiments of the present application, the array substrate further includes a light shielding layer, and in the array region, the light shielding layer is disposed on the first surface of the substrate layer.

[0011] Optionally, in some embodiments of the present application, the array substrate further includes a buffer layer, and the buffer layer covers the substrate layer, the binding pad and the light shielding layer.

[0012] Accordingly, an embodiment of the present application further provides a method for preparing an array substrate, wherein the array substrate includes an array area and an external circuit area surrounding the array area, including:

[0013] providing a sacrificial layer;

[0014] A substrate layer is arranged on the sacrificial layer, the substrate layer comprising a first surface and a second surface arranged opposite to the first surface, the second surface of the substrate layer being located on a side close to the sacrificial layer; in the external circuit area, the substrate layer is provided with a prefabricated hole, the prefabricated hole penetrates the substrate layer to expose the sacrificial layer;

[0015] providing a binding pad in the preformed hole;

[0016] Peeling the sacrificial layer off the substrate layer, and turning over the substrate layer;

[0017] In the external circuit area, a fan-shaped routing layer is disposed on the second surface of the substrate layer, and the fan-shaped routing layer is electrically connected to the binding pad.

[0018] Optionally, in some embodiments of the present application, after the step of setting a binding pad in the prefabricated hole and before the step of peeling the sacrificial layer from the substrate layer and flipping the substrate layer, the method further includes:

[0019] Disposing a glue layer on the substrate layer and the binding pad;

[0020] A cover plate is arranged on the adhesive layer.

[0021] Optionally, in some embodiments of the present application, after the step of providing a fan-out wiring layer on the second surface of the substrate layer in the external circuit area and electrically connecting the fan-out wiring layer to the binding pad, the method further includes:

[0022] A chip-on-chip film is disposed on the fan-out wiring layer.

[0023] Optionally, in some embodiments of the present application, after the step of providing a flip chip film on the fan-out wiring layer, the method further includes:

[0024] The glue layer and the cover plate are subjected to heat treatment to remove the glue layer and the cover plate.

[0025] Optionally, in some embodiments of the present application, the step of providing a binding pad in the prefabricated hole includes:

[0026] A metal layer material is disposed on the first surface of the substrate layer, and a light shielding layer and a binding pad are formed by etching, wherein the light shielding layer is located in the array area, and the binding pad is located in the prefabricated hole in the external circuit area.

[0027] Correspondingly, an embodiment of the present application further provides a display panel, comprising the array substrate as described in any one of the above items.

[0028] The present application provides an array substrate and a preparation method thereof and a display panel, wherein the array substrate comprises an array area and an external circuit area surrounding the array area, the array substrate comprises a substrate layer, a binding pad and a fan-shaped routing layer, the substrate layer comprises a first surface and a second surface arranged opposite to the first surface; in the external circuit area, the substrate layer is provided with a prefabricated hole, the prefabricated hole penetrates the substrate layer, the binding pad is arranged in the prefabricated hole, the fan-shaped routing layer is arranged on the second surface of the substrate layer, and the fan-shaped routing layer is electrically connected to the binding pad. By arranging the prefabricated hole on the substrate layer, arranging the binding pad in the prefabricated hole, and then arranging the fan-shaped routing layer on the back of the array substrate, the border of the array substrate is reduced, thereby realizing a narrow border design. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 It is a schematic cross-sectional view of the structure of the array substrate provided in an embodiment of the present application.

[0031] Figure 2 It is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application.

[0032] Figure 3-Figure 11 It is a structural cross-sectional flow chart of a method for preparing an array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0034] See also Figure 1 , Figure 1 A schematic cross-sectional view of the structure of an array substrate provided in an embodiment of the present application. The present application provides an array substrate 10. The array substrate 10 includes an array area 11 and an external circuit area 12 surrounding the array area 11. The array area 11 is used to set a driving circuit structure including a thin film transistor. The external circuit area 12 is used to set an external circuit structure so that the driving circuit structure of the array area 11 is electrically connected to the external circuit. The array substrate 10 includes a substrate layer 100, a binding pad 200 and a fan-shaped routing layer 300. The specific description is as follows:

[0035] The substrate layer 100 includes a first surface 110 and a second surface 120 disposed opposite to the first surface 110. In the outer circuit area 12, the substrate layer 100 is provided with a preformed hole 101. The preformed hole 101 penetrates the substrate layer 100. The vertical cross-sectional shape of the preformed hole 101 can be an isosceles trapezoid, a rectangle, a circle or an irregular shape, etc. The material of the substrate layer 100 includes polyimide, but is not limited thereto.

[0036] The binding pad 200 is disposed in the prefabricated hole 101. The material of the binding pad 200 includes one or a combination of Mo, Cu, Al, Ti and indium tin oxide (ITO). The binding pad 200 is electrically connected to the driving circuit of the thin film transistor.

[0037] The fan-shaped routing layer 300 is disposed on the second surface 120 of the substrate layer 100, and the fan-shaped routing layer 300 is electrically connected to the binding pad 200. The material of the fan-shaped routing layer 300 includes one or a combination of Mo, Cu, Al, Ti and ITO. The fan-shaped routing layer 300 is used to connect the data line and the flip chip film. The fan-shaped routing layer 300 is called a fan-shaped routing layer 300 because the shape of the entire routing layer is similar to a fan.

[0038] The array substrate further includes a chip-on-film 400. The chip-on-film 400 is disposed on a side of the fan-shaped wiring layer 300 away from the substrate layer 100. The chip-on-film 400 is electrically connected to the fan-shaped wiring layer 300.

[0039] In the present application, by setting the binding pad in the prefabricated hole, the fan-shaped routing layer set on the front side of the array substrate in the prior art is connected to the second surface of the substrate layer, thereby saving the routing space on the front side of the array substrate, and avoiding the problem of film peeling or film breakage at the bending point when the substrate layer needs to be bent sideways to the second surface of the substrate layer in the prior art, thereby improving the yield of the array substrate, thereby improving the performance of the array substrate, and reducing the border of the array substrate, thereby realizing a narrow border design.

[0040] In one embodiment, the array substrate 10 further includes a light shielding layer 500. The light shielding layer 500 is disposed on the first surface 110 of the substrate layer 100 in the same layer as the binding pad 200. The light shielding layer 500 is located in the array region 11. The material of the light shielding layer 500 includes one or a combination of Mo, Cu, Al, Ti and ITO.

[0041] The light shielding layer 500 is used to shield the external light from entering the array substrate 10 , thereby preventing the external light from having a bad influence on the active layer 500 , thereby improving the performance of the array substrate 10 .

[0042] In one embodiment, a reflective surface 501 is provided on one side of the light shielding layer 500 close to the substrate layer 100. The reflective surface 501 is used to reflect external light entering the array substrate 10, further improving the light shielding effect of the light shielding layer 500 and further improving the performance of the array substrate 10.

[0043] In one embodiment, the reflective surface 501 is a concave-convex microstructure.

[0044] In one embodiment, the array substrate 10 further includes a buffer layer 600. The buffer layer 600 covers the substrate layer 100, the binding pad 200 and the light shielding layer 500. The material of the buffer layer 600 includes Si x O y and Si x N y One or a combination of the following.

[0045] In one embodiment, the array substrate 10 further includes an active layer 700. The active layer 700 is disposed on the buffer layer 600, and the active layer 700 is located on the light shielding layer 500. The material of the active layer 700 includes indium gallium zinc oxide.

[0046] In one embodiment, the array substrate 10 further includes a gate insulating layer 800 and a gate 900. The gate insulating layer 800 and the gate 900 are sequentially stacked on the active layer 700. The material of the gate insulating layer 800 includes Si x O y and Si x N y The material of the gate 900 includes one or a combination of Ag, Fe, Mo, Cu, Al, Ti and ITO.

[0047] In one embodiment, the array substrate 10 further includes an interlayer insulating layer 1000. The interlayer insulating layer 1000 covers the buffer layer 600, the active layer 700, the gate insulating layer 800 and the gate 900. The interlayer insulating layer 1000 includes a first through hole 1001, a second through hole 1002 and a third through hole 1003. The first through hole 1001 penetrates the interlayer insulating layer 1000 and the buffer layer 600 to expose the light shielding layer 500. The second through hole 1002 penetrates the interlayer insulating layer 1000 to expose one side of the active layer 700. The first through hole 1001 and the second through hole 1002 are located on the same side of the active layer 700. The third through hole 1003 penetrates the interlayer insulating layer 1000 to expose the other side of the active layer 700. The material of the interlayer insulating layer 1000 includes Si x O y and Si x N y One or a combination of the following.

[0048] In one embodiment, the array substrate 10 further includes a source electrode 1100 and a drain electrode 1200. The source electrode 1100 is disposed on the interlayer insulating layer 1000, and extends into the first through hole 1001 to be electrically connected to the light shielding layer 500, and extends into the second through hole 1002 to be electrically connected to the active layer 700. The drain electrode 1200 is disposed on the interlayer insulating layer 1000, and extends into the third through hole 1003 to be electrically connected to the active layer 700. The material of the source electrode 1100 and the drain electrode 1200 includes one or a combination of Ag, Fe, Mo, Cu, Al, Ti and ITO.

[0049] In one embodiment, the array substrate 10 further includes a planar layer 1300. The planar layer 1300 covers the interlayer insulating layer 1000, the source electrode 1100, and the drain electrode 1200. The planar layer 1300 is used to planarize the structure in the array substrate 10 to avoid damage in subsequent processes or use, thereby improving the performance of the array substrate 10.

[0050] The present application provides an array substrate, which saves the wiring space on the front side of the array substrate by setting a binding pad in the prefabricated hole, thereby connecting the fan-shaped routing layer on the first surface of the prior art to the second surface of the substrate layer, and the substrate layer does not need to be bent laterally to the second surface of the substrate layer, thereby reducing the frame of the array substrate, thereby realizing a narrow frame design and improving the performance of the array substrate.

[0051] See also Figure 2 and Figure 3-Figure 11 , Figure 2It is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application. Figure 3-Figure 11 : is a structural cross-sectional flow chart of a method for preparing an array substrate provided in an embodiment of the present application. The present application also provides a method for preparing an array substrate. The array substrate 10 includes an array area 11 and an external circuit area 12 surrounding the array area 11. The array area 11 is used to set a driving circuit structure including a thin film transistor. The external circuit area 12 is used to set an external circuit structure so that the driving circuit structure of the array area 11 is electrically connected to the external circuit. The specific preparation steps of the method for preparing the array substrate 10 are as follows:

[0052] Step B21, providing a sacrificial layer.

[0053] See also Figure 3 Specifically, the sacrificial layer 1400 is a glass substrate.

[0054] Step B22, disposing a substrate layer on the sacrificial layer, the substrate layer comprising a display surface and a second surface disposed opposite to the display surface, the second surface of the substrate layer being located on a side close to the sacrificial layer; in the external circuit area, the substrate layer is provided with a prefabricated hole, the prefabricated hole penetrates the substrate layer to expose the sacrificial layer.

[0055] See also Figure 3-Figure 5 Specifically, the substrate layer 100 material is coated on the sacrificial layer 1400, and then a mask plate 1500 is provided, and the mask plate 1500 is located on the side of the substrate layer 100 away from the sacrificial layer 1400. Then, the substrate layer 100 material is exposed by extreme ultraviolet rays, and then the substrate layer 100 material is developed to form the substrate layer 100. The substrate layer 100 is provided with a prefabricated hole 101. The prefabricated hole 101 penetrates the substrate layer 100 to expose the sacrificial layer 1400. The vertical cross-sectional shape of the prefabricated hole 101 can be an isosceles trapezoid, a rectangle, a circle or an irregular shape. The material of the substrate layer 100 includes polyimide, polyphthalate, cycloolefin polymer and polyethylene terephthalate.

[0056] In the present application, the substrate layer 100 is formed of polyimide, and the prefabricated holes 101 can be formed on the substrate layer 100 without coating photoresist, thereby simplifying the preparation process of the array substrate and reducing the production cost.

[0057] Extreme ultraviolet rays refer to ultraviolet rays that are emitted by emitting electricity to excite the negative pole of the ultraviolet tube.

[0058] Step B23: setting a binding pad in the prefabricated hole.

[0059] See also Figure 6Specifically, a binding pad 200 material is disposed on the first surface 110 of the substrate layer 100, and the binding pad 200 material is etched to form a binding pad 200 disposed in the prefabricated hole 101. The material of the binding pad 200 includes one or a combination of Mo, Cu, Al, Ti and ITO. The binding pad 200 is used to be electrically connected to the driving circuit structure of the thin film transistor.

[0060] In one embodiment, after the step of providing the binding pad 200 on the first surface 110 of the substrate layer 100, the method further includes:

[0061] In the array area 11, a light shielding layer 500 material is disposed on the first surface 100 of the substrate layer 100, and the light shielding layer 500 is formed by etching. The material of the light shielding layer 500 includes one or a combination of Mo, Cu, Al, Ti and ITO.

[0062] In the present application, two preparation processes are used to form the binding pad 200 and the light shielding layer 500 respectively, thereby improving the precision of preparing the array substrate 10 .

[0063] In another embodiment, a binding pad 200 material and a light shielding layer 500 material are disposed on the first surface 110 of the substrate layer 100, and the binding pad 200 material and the light shielding layer 500 material are etched to form the binding pad 200 and the light shielding layer 500. The binding pad 200 is disposed in the prefabricated hole 101. The light shielding layer 500 is located in the array area 11.

[0064] The light shielding layer 500 is used to shield the external light from entering the array substrate 10 , thereby preventing the external light from having a bad influence on the active layer 500 , thereby improving the performance of the array substrate 10 .

[0065] In the present application, the binding pad 200 and the light shielding layer 500 are prepared by the same process, which reduces the cost of the array substrate 10 and shortens the preparation period.

[0066] In one embodiment, after step B23, the method further includes:

[0067] A buffer layer 600 is disposed on the substrate layer 100, the binding pad 200 and the light shielding layer 500. The material of the buffer layer 600 includes Si x O y and Si x N y One or a combination of the following.

[0068] In one embodiment, after the step of providing a buffer layer 600 on the substrate layer 100, the binding pad 200 and the light shielding layer 500, the method further includes:

[0069] The material of the active layer 700 is disposed on the buffer layer 600, and the active layer 700 is formed by etching. The active layer 700 is located on the light shielding layer 500. The material of the active layer 700 includes indium gallium zinc oxide.

[0070] In one embodiment, after the step of forming the active layer 700 on the buffer layer 600, the method further includes:

[0071] A gate insulating layer 800 and the gate 900 are sequentially stacked on the active layer 700. The material of the gate insulating layer 800 includes Si x O y and Si x N y The material of the gate 900 includes one or a combination of Ag, Fe, Mo, Cu, Al, Ti and ITO.

[0072] In one embodiment, after the step of sequentially stacking the gate insulating layer 800 and the gate 900 on the active layer 700, the method further includes:

[0073] An interlayer insulating layer 1000 material is disposed on the buffer layer 600, the active layer 700, the gate insulating layer 800 and the gate 900, and the interlayer insulating layer 1000 is formed by etching. The interlayer insulating layer 1000 includes a first through hole 1001, a second through hole 1002 and a third through hole 1003. The first through hole 1001 penetrates the interlayer insulating layer 1000 and the buffer layer 600 to expose the light shielding layer 500. The second through hole 1002 penetrates the interlayer insulating layer 1000 to expose one side of the active layer 700. The first through hole 1001 and the second through hole 1002 are located on the same side of the active layer 700. The third through hole 1003 penetrates the interlayer insulating layer 1000 to expose the other side of the active layer 700. The material of the interlayer insulating layer 1000 includes Si x O y and Si x N y One or a combination of the following.

[0074] In one embodiment, after the step of forming an interlayer insulating layer 1000 on the buffer layer 600 , the active layer 700 , the gate insulating layer 800 and the gate 900 , the method further includes:

[0075] The source electrode 1100 material and the drain electrode 1200 material are disposed on the interlayer insulating layer 1000, and the source electrode 1100 and the drain electrode 1200 are formed by etching, and the source electrode 1100 extends into the first through hole 1001 to be electrically connected to the light shielding layer 500 and extends into the second through hole 1002 to be electrically connected to the active layer 700, and the drain electrode 1200 extends into the third through hole 1003 to be electrically connected to the active layer 700. The material of the source electrode 1100 and the drain electrode 1200 includes one or a combination of Ag, Fe, Mo, Cu, Al, Ti and ITO.

[0076] In one embodiment, after the step of forming the source electrode 1100 material and the drain electrode 1200 on the interlayer insulating layer 1000, the method further includes:

[0077] A planarization layer 1300 is formed on the interlayer insulating layer 1000, the source electrode 1100 and the drain electrode 1200. The planarization layer 1300 is used to planarize the structure in the array substrate 10 to avoid damage in subsequent processes or use, thereby improving the performance of the array substrate 10.

[0078] In one embodiment, after the step of forming a planarization layer 1300 on the interlayer insulating layer 1000 , the source electrode 1100 , and the drain electrode 1200 , the method further includes:

[0079] See also Figure 7 , a glue layer 1600 is disposed on the substrate layer 100 and the binding pad 200 , and then a cover plate 1700 is disposed on the glue layer 1600 .

[0080] Specifically, a glue layer 1600 and a cover plate 1700 are sequentially stacked on the flat layer 1300. The glue layer 1600 is a heat-sensitive glue. The cover plate 1700 is a glass cover plate.

[0081] In the present application, the glue layer 1600 is first arranged on the flat layer 1300 to ensure the subsequent bonding accuracy of the cover plate 1700, thereby ensuring the stable progress of the subsequent process; the cover plate 1700 is arranged on the glue layer 1600 to avoid the substrate layer 100 being in a soft state and unable to perform subsequent processes after being processed by the laser stripping technology in the subsequent process, that is, the deformation of the substrate layer 100 is controlled by the cover plate 1700, thereby ensuring the progress of the subsequent process; the cover plate 1700 is arranged on the glue layer 1600 to protect other structures in the array substrate 10, thereby improving the yield of the array substrate 10, and thereby improving the performance of the array substrate 10.

[0082] Step B24, peeling the sacrificial layer from the substrate layer, and turning over the substrate layer.

[0083] See also Figure 8 and Fig. 9 Specifically, the sacrificial layer 1400 is peeled off from the substrate layer 100 by laser lift-off technology, and then the semi-finished product is turned over. The semi-finished product includes the substrate layer 100, the binding pad 200, the fan-shaped wiring layer 300, the flip chip film 400, the light shielding layer 500, the buffer layer 600, the active layer 700, the gate insulation layer 800, the gate 900, the interlayer insulation layer 1000, the source 1100, the drain 1200, the planar layer 1300, the glue layer 1600 and the cover plate 1700.

[0084] Step B25: in the external circuit region, a fan-out wiring layer is provided on the second surface of the substrate layer, and the fan-out wiring layer is electrically connected to the binding pad.

[0085] Please continue reading Fig. 9 Specifically, a fan-shaped routing layer 300 material is disposed on the second surface 120 of the substrate layer 100, and the fan-shaped routing layer 300 material is subjected to yellow light processing and etching processing to form the fan-shaped routing layer 300. The fan-shaped routing layer 300 is electrically connected to the binding pad 200. The material of the fan-shaped routing layer 300 includes one or a combination of Mo, Cu, Al, Ti and ITO.

[0086] In one embodiment, after the step of providing the fan-out wiring layer 300 on the second surface 120 of the substrate layer 100, the method further includes:

[0087] See also Fig.10 A chip-on-film 400 is disposed on the fan-shaped wiring layer 300. The chip-on-film 400 is electrically connected to the fan-shaped wiring layer 300.

[0088] In one embodiment, after the step of providing a chip-on-chip film 400 on the fan-out wiring layer 300, the method further includes:

[0089] See also Fig.11 , heat-treating the adhesive layer 1600 and the cover plate 1700, and peeling the adhesive layer 1600, the cover plate 1700 and the flat layer 1300 to obtain the array substrate 10 of the present application. The heat-treating temperature is 40 degrees Celsius to 200 degrees Celsius.

[0090] The present application provides a method for preparing an array substrate, by pre-setting a prefabricated hole 101 on the substrate layer 100, and then setting the metal pad 200 in the prefabricated hole 101, and then continuing the subsequent process on the first surface 110 of the substrate layer 100. After the process on the first surface 110 of the substrate layer 100 is completed, it is turned over to form a fan-shaped wiring layer 300 on the second surface 120 of the substrate layer 100, so as to achieve the fan-shaped wiring layer 300 being connected to the second surface 120 of the substrate layer 100, thereby saving the wiring space of the array substrate 10, thereby reducing the frame of the array substrate 10, and realizing a narrow frame design; the array substrate 10 is prepared by the preparation method provided by the present application, and the preparation process is simple, the yield is high, and the production cost is reduced.

[0091] The present application also provides a display panel, including the array substrate 10 provided in the present application. The display panel of the present application can be a top-emitting organic light-emitting diode display panel, a top-emitting micro light-emitting diode display panel, or a top-emitting mini light-emitting diode display panel.

[0092] The present application provides a display panel, in which the array substrate 10 is applied, wherein the first surface 110 faces the display surface of the display panel, and the second surface 120 faces the non-display surface of the display panel, thereby reducing the border of the display panel and improving the screen-to-body ratio of the display panel.

[0093] The present application provides an array substrate and a preparation method thereof and a display panel, wherein the array substrate comprises a display area and an external circuit area surrounding the display area, the array substrate comprises a substrate layer, a binding pad and a fan-shaped routing layer, the substrate layer comprises a first surface and a second surface arranged opposite to the first surface; in the external circuit area, the substrate layer is provided with a prefabricated hole, the prefabricated hole penetrates the substrate layer, the binding pad is arranged in the prefabricated hole, the fan-shaped routing layer is arranged on the second surface of the substrate layer, and the fan-shaped routing layer is electrically connected to the binding pad. By arranging the prefabricated hole on the substrate layer, arranging the binding pad in the prefabricated hole, and then arranging the fan-shaped routing layer on the back of the array substrate, the frame of the array substrate is reduced, thereby realizing a narrow frame design.

[0094] The above is a detailed introduction to an array substrate, a preparation method thereof, and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate for a narrow-frame display panel, characterized in that: The array substrate includes an array area and an external circuit area surrounding the array area, including: A flexible substrate layer, the flexible substrate layer comprising a first surface and a second surface arranged opposite to the first surface; in the external circuit area, the flexible substrate layer is provided with a prefabricated hole, the prefabricated hole penetrates the flexible substrate layer, and the flexible substrate layer is a polyimide layer; A binding pad, disposed on the first surface, the binding pad filling the prefabricated hole; a buffer layer, disposed on a side of the binding pad facing away from the first surface, the buffer layer covering the flexible substrate layer and the binding pad; and A fan-shaped routing layer, the fan-shaped routing layer is arranged on the second surface of the flexible substrate layer, the fan-shaped routing layer is connected to the data line, the entire routing layer of the fan-shaped routing layer is fan-shaped, and the fan-shaped routing layer is in contact with the binding pad, and the material of the fan-shaped routing layer includes one or more combinations of Mo, Cu, Al, Ti and ITO; The array substrate further comprises a light shielding layer and a thin film transistor located in the array area, the light shielding layer is arranged on the first surface, and the thin film transistor is arranged on the light shielding layer and corresponding to the light shielding layer; The binding pad is arranged in the same layer as the light shielding layer, and the binding pad is connected to the fan-out wiring only through the flexible substrate layer.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises a chip-on-chip film, and the chip-on-chip film is arranged on a side of the fan-shaped routing layer away from the flexible substrate layer.

3. The array substrate according to claim 1, characterized in that: The buffer layer also covers the light shielding layer.

4. A method for preparing an array substrate of a narrow-frame display panel, characterized in that: The array substrate includes an array area and an external circuit area surrounding the array area, including: providing a sacrificial layer; A flexible substrate layer is arranged on the sacrificial layer, wherein the flexible substrate layer comprises a first surface and a second surface arranged opposite to the first surface, wherein the second surface of the flexible substrate layer is located on a side close to the sacrificial layer; in the external circuit area, the flexible substrate layer is provided with a prefabricated hole, wherein the prefabricated hole penetrates the flexible substrate layer to expose the sacrificial layer; Forming a binding pad and a light shielding layer on the first surface by one process, wherein the light shielding layer is located in the array area, and the binding pad is located in the external circuit area and fills the prefabricated hole; providing a buffer layer on the substrate layer and the binding pad; forming an active layer on the buffer layer, wherein the active layer corresponds to the light shielding layer; Peeling the sacrificial layer off the flexible substrate layer, and turning over the flexible substrate layer; In the external circuit area, a fan-shaped routing layer is arranged on the second surface of the flexible substrate layer, the fan-shaped routing layer is connected to the data line, the entire routing layer of the fan-shaped routing layer is fan-shaped, and the fan-shaped routing layer is in contact with the binding pad.

5. The method for preparing an array substrate according to claim 4, characterized in that: After the step of setting the binding pad in the prefabricated hole and before the step of peeling the sacrificial layer from the flexible substrate layer and turning over the flexible substrate layer, the method further includes: Disposing a glue layer on the flexible substrate layer and the binding pad; A cover plate is arranged on the adhesive layer.

6. The method for preparing an array substrate according to claim 5, characterized in that: In the external circuit area, after the step of providing a fan-shaped wiring layer on the second surface of the flexible substrate layer, and the fan-shaped wiring layer is in contact with the binding pad, the method further includes: A chip-on-chip film is disposed on the fan-out wiring layer.

7. The method for preparing an array substrate according to claim 6, characterized in that: After the step of providing a flip chip film on the fan-out wiring layer, the method further includes: The glue layer and the cover plate are subjected to heat treatment to remove the glue layer and the cover plate.

8. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 3.

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