High voltage semiconductor device with stepped passivation layer stack

Abstract

A high voltage semiconductor device includes a high voltage conductive structure and a stepped topography at or near the high voltage conductive structure. A layer stack covers the stepped topography. The layer stack includes an electrically insulating buffer layer, a SiC layer over the electrically insulating buffer layer, and a silicon nitride layer over the SiC layer or a nitrided surface region of the SiC layer.

Description

Technical Field

[0001] This disclosure generally relates to the field of high-voltage semiconductor devices, and particularly to passivation structures for high-voltage semiconductor devices. Background Technology

[0002] High-voltage semiconductor devices require precautions to prevent moisture from entering the active regions. A conventional approach is to provide a thick passivation layer (e.g., silicon nitride) to cover and protect the underlying structure, such as a metal layer or other semiconductor or oxide device structure. However, the metal layer expands in volume when corroded by moisture, potentially causing the passivation layer to crack and leading to device failure. Moisture-driven ion transport into the gate oxide or bulk semiconductor material can undesirably alter the device's on / off hysteresis characteristics. Therefore, extremely high degrees of impermeability and stability are required for the passivation layer. This is particularly challenging at stepped topography, where passivation layer vulnerability is more likely to occur at the edges of such topography. Summary of the Invention

[0003] According to one aspect of this disclosure, a high-voltage semiconductor device includes a high-voltage conductive structure and a step morphology at or near the high-voltage conductive structure. A layer stack covers the step morphology. The layer stack includes an electrically insulating buffer layer, a SiC layer above the electrically insulating buffer layer, and a silicon nitride layer above the SiC layer or a nitride surface region of the SiC layer. Attached Figure Description

[0004] Elements in the accompanying drawings are not necessarily drawn to scale relative to each other. The same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive, and / or can be selectively omitted if not described as necessary. Embodiments are depicted in the accompanying drawings and are exemplarily detailed in the following description.

[0005] Figure 1A This is a schematic cross-sectional view of an exemplary step morphology of a high-voltage semiconductor device covered by a stack of layers including a silicon nitride layer on top of a SiC layer.

[0006] Figure 1B This is a schematic cross-sectional view of an exemplary step morphology of a high-voltage semiconductor device covered by a stack of SiC layers including nitrided surface regions;

[0007] Figure 2 This is a schematic cross-sectional view of an exemplary high-voltage semiconductor device, showing a portion of the active cell structure and the edge termination of the device, and including a stack of layers for passivation over the surface topography.

[0008] Figure 3This is a schematic cross-sectional view of an exemplary high-voltage semiconductor device including a stack of layers for passivation over a surface topography.

[0009] Figure 4A This is a schematic cross-sectional partial view of an exemplary layer stack used for passivation;

[0010] Figure 4B This is a schematic cross-sectional partial view of an exemplary layer stack used for passivation;

[0011] Figures 5A to 5D This is a schematic diagram showing the degree of edge and sidewall coverage of the step morphology used for different intermediate layers in layer stacking;

[0012] Figure 6 This is a partial cross-sectional view of an exemplary high-voltage semiconductor device, showing the transition region between the active cell region and the edge termination of the exemplary high-voltage semiconductor device;

[0013] Figure 7 These are contour-tracing electron microscope images of an exemplary layer stack on top of a step morphology used for passivation. Detailed Implementation

[0014] It should be understood that, unless otherwise specifically indicated, the features of the various exemplary embodiments and examples described herein can be combined with each other.

[0015] As used in this specification, the terms "deposition," "coverage," "connection," and / or "electrical connection" do not imply that elements or layers must be in direct contact with each other; intermediate elements or layers may be provided between "deposition," "coverage," "connection," and / or "electrical connection" elements. However, according to this disclosure, the above terms may optionally also have the specific meaning of elements or layers being in direct contact with each other, i.e., no intermediate elements or layers are provided between "deposition," "coverage," "connection," and / or "electrical connection" elements.

[0016] Furthermore, the term "above" as used herein to describe a component, element, or layer of material formed, positioned, or arranged "above" a surface may be used to indicate that the component, element, or layer of material is "directly" positioned (e.g., placed, formed, arranged, deposited, etc.) on the surface in question, such as being in direct contact with the surface in question. The term "above" as used herein to describe a component, element, or layer of material formed, positioned, or arranged "above" a surface may also be used to indicate that the component, element, or layer of material is "indirectly" positioned (e.g., placed, formed, arranged, deposited, etc.) on the surface in question, wherein one or more additional components, elements, or layers are arranged between the surface in question and the component, element, or layer of material.

[0017] Specifically, high-voltage semiconductor devices can include semiconductor chips with vertical or horizontal structures. That is, the semiconductor chip of a high-voltage vertical semiconductor device (e.g., a high-voltage vertical semiconductor device) can be manufactured such that current flows in a direction perpendicular to the main surface of the semiconductor chip. Semiconductor chips with vertical structures typically have load electrodes on their two main surfaces, that is, on their top and bottom sides (the bottom side is also referred to herein as the back side). Conversely, in horizontal semiconductor devices, current flows in a direction parallel to the main surface of the semiconductor chip, and the load electrodes are typically placed on the front main surface of the semiconductor chip.

[0018] High-voltage semiconductor devices (e.g., semiconductor chips) can be configured, for example, as IGBTs (Insulated Gate Bipolar Transistors), FETs (Field Effect Transistors) (especially MOSFETs (Metal-Oxide-Semiconductor FETs), JFETs (Junction Gate FETs)), thyristors (especially GTOs (Gate-Off Thyristors), BJTs (Bipolar Junction Transistors), HEMTs (High Electron Mobility Transistors), or diodes. As an example, the source and gate electrodes of an FET or MOSFET can be located on the front-side main surface, while the drain electrode of the FET or MOSFET can be arranged on the back-side main surface.

[0019] refer to Figure 1A The step morphology 110 of the high-voltage semiconductor device 100A is shown. Figure 1A In this context, the step morphology 110 is formed, for example, by a high-voltage conductive structure 120, which is made, for example, of a metal. All kinds of metals or metal alloys can be used for the high-voltage conductive structure 120, although in many cases the metal may include aluminum or copper, or alloys of aluminum or copper, or may be composed of aluminum or copper, or alloys of aluminum or copper. Examples of the step morphology 110 and the high-voltage conductive structure 120 are further illustrated below. It should be noted that the step morphology 110 does not need to be formed directly by the high-voltage conductive structure 120; however, it can be positioned relatively close to the structure 120 to withstand a high electric field during operation of the high-voltage semiconductor device 100A.

[0020] The stepped morphology 110 and / or the high-voltage conductive structure 120 may be disposed on the semiconductor substrate 130, for example, on or above the surface 131 of the semiconductor substrate 130. The semiconductor substrate 130 may include or be composed of semiconductor materials, such as, for example, Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc. For example, the semiconductor substrate 130 may be a wafer or a chip.

[0021] The conductive structure 120 can be configured to be subjected to a high voltage equal to or greater than 0.6 kV, 1 kV, 2 kV, 3 kV, 4 kV, 5 kV, 6 kV, or 6.5 kV during operation. This voltage can be applied to the first electrode (e.g., the conductive structure 120 or another conductive structure connected to the conductive structure 120) and the second electrode (e.g., arranged in a manner similar to...). Figure 1A The back electrode (not shown) is located between the surface 131 and the surface of the semiconductor substrate 130.

[0022] exist Figure 1A Many details may be omitted in the schematic diagram. For example, a barrier layer (not shown) may be provided between the surface 131 of the semiconductor substrate 130 and the conductive structure 120. Furthermore, the semiconductor substrate 130 may be structured by including doped regions or trenches (not shown). Some of these possibilities will be described in further detail below.

[0023] The step morphology 110 is covered by a layer stack LS, which includes an insulating buffer layer 150, a SiC layer 160 disposed on the electrically insulating buffer layer 150, and a silicon nitride layer 170 disposed on the SiC layer 160.

[0024] Typically, the SiC layer 160 can be, for example, a crystalline, polycrystalline, or amorphous SiC layer. Without loss of generality, the SiC layer will be illustrated below by way of a hydrogen-containing amorphous SiC layer. This hydrogen-containing amorphous SiC layer is referred to as a-SiC:H layer 160. a-SiC:H layer 160 can be generalized to represent a SiC layer anywhere in this disclosure.

[0025] Figure 1B A partial view of a high-voltage semiconductor device 100B is shown, illustrating another layer stack LS disposed above a stepped topography 110. The layer stack LS of the high-voltage semiconductor device 100B includes an insulating buffer layer 150 and (exemplary) an a-SiC:H layer 160. However, instead of a silicon nitride layer 170, the a-SiC:H layer 160 (typically a SiC layer) includes a nitride surface region 180 at the top surface 160_1 of the a-SiC:H layer 160. All other features and characteristics of the high-voltage semiconductor device 100B may be similar to or identical to those of the high-voltage semiconductor device 100A, and for the sake of brevity, repetition of identical features or characteristics is avoided.

[0026] refer to Figure 2An exemplary surface morphology of a high-voltage semiconductor device 200 is shown. The surface morphology may include multiple step morphologies, including, for example, active metal electrodes 210 and / or metal field plates 220 disposed on a semiconductor substrate 130. A doped field ring (also referred to as a p-ring) 230 may be disposed in the substrate 130 and electrically connected to the metal field plate 220. An insulating layer 240 may be disposed on the semiconductor substrate 130 between the field ring 230 and the metal field plate 220. Another step morphology of the high-voltage semiconductor device 200 may be formed by a peripheral conductive structure 250 disposed at the edge termination of the semiconductor substrate 130 (e.g., a semiconductor chip). The peripheral conductive structure 250, which may be formed of, for example, metal or polysilicon, may be connected to, for example, the n-ring of the semiconductor substrate 130. ++ A channel stopper 260 is formed by the doped region. For example, a high voltage can be applied between the active metal electrode 210 and / or the field plate 220 and the peripheral conductive structure 250.

[0027] The active metal electrode 210 may, for example, form the load electrode (e.g., source electrode or drain electrode) or so-called gate channel of the high voltage semiconductor device 200.

[0028] The active metal electrode 210, the metal field plate 220, and the peripheral conductive structure 250 can all be made of the same metal, such as aluminum or copper or an aluminum or copper alloy (e.g., an aluminum alloy AlSiCu with about 1.0 wt% Si and about 0.5 wt% Cu, with the balance being aluminum).

[0029] Figure 2 The portion of the high-voltage semiconductor device 200 depicted, including, for example, active metal electrode 210 and / or metal field plate 220 and / or peripheral conductive structure 250, can represent the high-voltage edge termination region of the high-voltage semiconductor device 200, which surrounds the internal active region of the high-voltage semiconductor device 200, which is not (or only extends to a small area of ​​the active metal electrode 210) in Figure 2 The high-voltage semiconductor device 200 can be formed from a high-voltage semiconductor chip, as depicted in the text. Figure 2 The diagram can depict a cross-sectional view of the edge termination region of a high-voltage semiconductor chip.

[0030] On the back side of the semiconductor substrate 130, a semiconductor contact region 270 may be formed to provide electrical contact to the back-side metallization layer 280. The semiconductor contact region 270 may be composed of a ratio (e.g., n...) - The semiconductor substrate 130 is formed by further doping (e.g., n-doping) of the substrate region.

[0031] Step morphology (its in) Figure 2In the example, at least one of the following (formed by an active metal electrode 210, a metal field plate 220, and a peripheral conductive structure 250) is covered by a layer stack LS. The layer stack LS can have, for example, Figure 1A or Figure 1B The design shown.

[0032] Furthermore, the imide layer 290 can be disposed on the layer stack LS, and can, for example, completely cover the layer stack LS. The imide layer 290 can be a conformal layer (not shown) or a non-conformal layer, i.e., in the latter case, it flattens the step topography above the semiconductor substrate 130.

[0033] Figure 3 Another example of a high-voltage semiconductor device 300, or more specifically, its edge-terminating region, is shown. Here, the semiconductor substrate 130 includes a so-called VLD (laterally doped variant) structure 310 in its edge-terminating region or high-voltage peripheral region. The VLD structure 310 is doped more weakly than the laterally adjacent well 320 located at the boundary of the internal active region of the high-voltage semiconductor device 300. The VLD structure 310 has a doping concentration that decreases in the lateral direction toward the edge of the semiconductor substrate 130 (e.g., toward the channel cutoff 260 located at the edge of the semiconductor substrate 130).

[0034] like Figure 3 As shown, the layer stacking LS covers Figure 3 At least one of the step morphologies shown, such as a step morphology formed by the active metal electrode 210, a step morphology formed by the insulating layer 240 near the active metal electrode 210, a step morphology formed by the insulating layer 240 near the peripheral conductive structure 250, and / or a step morphology formed by the peripheral conductive structure 250. Furthermore, the layer stack LS may, for example, have the following characteristics: Figure 1A or Figure 1B The design shown is for reference only, and to avoid repetition, you can refer to [other sources]. Figure 1A , 1B The above description of 2.

[0035] Figure 4A It shows Figure 1A The layers are stacked as LS. The thickness T1 of the insulating buffer layer 150 (e.g., a silicon oxide layer) can be equal to or greater than 100 nm and equal to or less than 5 μm. In particular, the thickness T1 can range from 1 μm to 3 μm.

[0036] The insulating buffer layer 150 can be formed using a plasma process employing, for example, N₂O and silane as process gases. Another possibility is to provide a high-purity oxide, which can be produced in a plasma process using silane and O₂ as process gases. A sputtering process (e.g., using Ar as the sputtering gas) can be added for edge rounding.

[0037] Optionally, the surface region of the insulating buffer layer (e.g., an insulating oxide layer) 150 may be nitrided. Nitriding of the surface region can be achieved by introducing NH3 and N2 into a plasma process. The nitrided surface region of the insulating buffer layer 150 is indicated by reference numeral 155. The nitrided surface region 155 of the insulating buffer layer 150 may have a depth of only a few nm.

[0038] The nitrided surface region 155 of the insulating oxide layer, which serves as the insulating buffer layer 150, provides an oxygen-depleted top surface for the insulating oxide layer 150. This significantly improves the adhesion strength of the a-SiC:H layer 160 (or typically a SiC layer) to the underlying insulating oxide layer 150 by preventing the C atoms of the a-SiC:H layer 160 from bonding with the O atoms of the underlying insulating oxide layer 150.

[0039] a-SiC:H layer 160 (or more generally, SiC layer) is a key layer in layer-stacked LS, taking into account the improved functionality of layer-stacked LS in terms of impermeability and stability against humidity and ion transfer. As will be explained in more detail below, a-SiC:H layer 160 can be fabricated to completely cover the vertical sidewalls and edge structures of the stepped morphology with high conformity and without any growth gaps (also known as seam lines).

[0040] The a-SiC:H layer 160 can have a thickness T2 between 50 nm and 1 μm, more specifically between 100 nm and 0.5 μm. The maximum thickness of about 1 μm is due to the mechanical strain introduced by the a-SiC:H layer 160.

[0041] The a-SiC:H layer 160 can be applied via a plasma process (e.g., a plasma process performed in the same plasma chamber as the plasma process used to form the insulating buffer layer 150). CH4 and / or C2H2 can be used as process gases, for example, silane. Since the a-SiC:H layer 160 is not etched during the plasma deposition process, the vertical sidewalls and edges of any step morphology are fully and tightly passivated by the a-SiC:H layer 160. Therefore, any edge termination concept configured to have a step morphology at or near a high-voltage conductive structure (e.g., ...) Figure 2 and 3 (As illustrated in the example) can be effectively shielded from environmental influences by using an a-SiC:H layer 160 in a layer stack LS.

[0042] Furthermore, a silicon nitride layer 170 can be deposited on top of the a-SiC:H layer 160. The thickness T3 of the silicon nitride layer 170 can range from 10 nm to 2 μm, particularly from 200 nm to 1 μm. The silicon nitride layer 170 can be applied by, for example, another plasma process performed in the same plasma chamber as the two other layer stack LS deposition processes used to generate the insulating oxide layer 150 and the a-SiC:H layer 160. On the one hand, the silicon nitride layer 170 provides good adhesion to the next layer (e.g., the imide layer 290) (see...). Figure 2 , 3 Or 6). In addition, the silicon nitride layer 170 can be used as an additional humidity barrier and thus as a protective layer against the a-SiC:H layer 160.

[0043] like Figure 4B As shown, the silicon nitride layer 170 can also be omitted and replaced by the nitride surface region 180 of the a-SiC:H layer 160. This nitride surface region 180 (which is not a separate layer and therefore does not increase the total layer thickness of the layer stack LS) can have a depth of only a few nm from the top surface 160_1 of the a-SiC:H layer 160. The nitride surface region 180 of the a-SiC:H layer 160 also provides good adhesion to the next layer (e.g., the imide layer 290) (see...). Figure 2 , 3 Or 6).

[0044] Figures 5A to 5D The effect of different types of "intermediate" layers in layer-stacked LS, which have been tested in light of their ability to provide efficient passivation for layer-stacked LS, is illustrated schematically.

[0045] If a hard aC:H layer is formed instead of an a-SiC:H layer 160 (e.g., by using CH4 as the plasma treatment gas), the vertical sidewalls of the stepped morphology are not covered, see [reference]. Figure 5A If C2H2 is used as the plasma processing gas, a soft aC:H layer can be generated, which provides only about 50% sidewall coverage (see [link to relevant documentation]). Figure 5B (the left side), or a hard aC:H layer can be generated, which is not dense or has a reduced barrier function at the step morphology (see the left side). Figure 5B (The right side). For example... Figure 5C As shown, even hard SiN layers cannot provide sufficient coverage and compactness at stepped morphological structures. Only a-SiC:H layers 160 were found to provide high compactness and complete sidewall and edge coverage for stepped morphological structures, and are applicable to low-temperature plasma processing. (See [link to relevant documentation]). Figure 5D .

[0046] It should be noted that the insulating buffer layer 150 (e.g., an insulating oxide layer) allows the a-SiC:H layer 160 to remain electrically floating. This avoids any electrochemical interactions of the a-SiC:H layer 160. Furthermore, the insulating buffer layer 150 (e.g., an insulating oxide layer) facilitates the process integration for forming the a-SiC:H layer 160, as anisotropic etching of the a-SiC:H layer 160 would be more difficult in the presence of exposed metal (because anisotropic etching would sputter the exposed metal).

[0047] Figure 6 This is a partial cross-sectional view of an exemplary high-voltage semiconductor device 600, showing the transition region between the active cell region 600A and the transition region 600B leading to the edge termination region of the high-voltage semiconductor device 600 (e.g., a semiconductor chip). In this example, 610 represents a p-doped region of the semiconductor (e.g., silicon) substrate 130, 620 represents a LOCOS (Local Oxidation of Silicon) oxide layer, 630 represents a polysilicon layer, and 640 represents an intermediate oxide layer. Surrounding this is a stepped-top (ST) structure effectively protected by a conformal layer stack LS. In this example, the imide layer 290 is, for example, a conformal layer.

[0048] Figure 7 This is a contour-tracing electron microscope image of an exemplary layer stack LS on a surface step topography 110 used for passivation. The step topography 110 includes a horizontal substrate and vertical sidewalls.

[0049] Typically, the vertical sidewalls can have a height H, for example, equal to or greater than or less than 0.5 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm, or 10 μm. Figure 7 In the exemplary layer stack LS, the height H is approximately 4 μm. As previously described, the step morphology 110 can be formed, for example, by a conductive structure. Figure 7 It is to true scale, thus exposing exemplary relative and / or absolute dimensions.

[0050] Figure 7 An exemplary layer stack LS includes or comprises an insulating oxide layer 150 with a thickness T1 = 2700 nm, an a-SiC:H layer 160 with a thickness T2 = 300 nm, and a silicon nitride layer 170 with a thickness T3 = 800 nm. Figure 7 The step morphology 110 (exemplarily) is formed by a conductive structure 120 with a height of about 3.2 μm.

[0051] Figure 7The integration and integrity of the layer stack LS, including insulating oxide layer 150, silicon nitride layer 170, and intermediate a-SiC:H layer 160, are shown. Specifically, complete coverage of the vertical sidewalls of the step morphology 110, as well as complete coverage of the edge or corner regions between the horizontal substrate and the vertical sidewalls of the step morphology 110, is achieved. No weak regions or areas are obtained that would reduce the thickness or integrity of the layer stack LS, and particularly the a-SiC:H layer 160.

[0052] The following examples relate to other aspects of this disclosure:

[0053] Example 1 is a high-voltage semiconductor device including a high-voltage conductive structure; a step morphology at or near the high-voltage conductive structure; and a layer stack covering the step morphology, the layer stack including: an electrically insulating buffer layer; a SiC layer above the electrically insulating buffer layer; and a silicon nitride layer above the SiC layer or a nitrided surface region of the SiC layer.

[0054] In Example 2, the subject matter of Example 1 may optionally include, wherein the stepped morphology is formed by the edge of the high-voltage conductive structure.

[0055] In Example 3, the subject matter of Example 1 or 2 may optionally include, wherein the step morphology is formed by the edge of the gate channel or p-ring or field plate or the edge of the variable lateral doped region of the high voltage transistor.

[0056] In Example 4, the subject matter of any of the foregoing examples may optionally include, wherein the SiC layer is an a-SiC:H layer.

[0057] In Example 5, the subject matter of any of the foregoing examples may optionally include, wherein the electrically insulating buffer layer comprises a nitrided top surface region.

[0058] In Example 6, the subject matter of any of the foregoing examples may optionally include, wherein the electrically insulating buffer layer is an oxide layer.

[0059] In Example 7, the subject matter of any of the foregoing examples may optionally include, wherein the high-voltage conductive structure comprises aluminum or copper.

[0060] In Example 8, the subject matter of any of the foregoing examples may optionally also include an imide layer over the silicon nitride layer or over the nitride surface region of the SiC layer.

[0061] In Example 9, the subject matter of any of the foregoing examples may optionally include, wherein the step morphology comprises a horizontal base and vertical sidewalls, and the vertical sidewalls have a height equal to or greater than 0.5 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm, or 10 μm.

[0062] In Example 10, the subject matter of any of the foregoing examples may optionally include, wherein the stepped topography comprises a horizontal base and vertical sidewalls, and the SiC layer completely covers the corner region between the horizontal base and the vertical sidewalls.

[0063] In Example 11, the subject of Example 10 may optionally include, wherein the SiC layer also completely covers the vertical sidewall.

[0064] In Example 12, the subject matter of any of the foregoing examples may optionally include, wherein the SiC layer is a conformal layer that follows the stepped topography.

[0065] In Example 13, the subject matter of any of the foregoing examples may optionally include, wherein the electrically insulating buffer layer is a conformal layer that follows the stepped morphology.

[0066] In Example 14, the subject matter of any of the foregoing examples may optionally include, wherein the silicon nitride layer is a conformal layer that follows the stepped morphology.

[0067] In Example 15, the subject of any of the foregoing examples can optionally be configured such that the SiC layer is electrically levitated.

[0068] In Embodiment 16, the subject matter of any of the foregoing examples may optionally be configured to operate at a voltage equal to or greater than 0.6 kV, 1 kV, 2 kV, 3 kV, 4 kV, 5 kV, 6 kV, or 6.5 kV.

[0069] In Example 17, the subject matter of any of the foregoing examples may optionally include, wherein the high-voltage semiconductor device is one of IGBT, FET, diode, thyristor, GTO, JFET, MOSFET, BJT, and HEMT.

[0070] Although specific embodiments have been shown and described herein, it will be understood by those skilled in the art that various alternatives and / or equivalent implementations may be used instead of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. A high-voltage semiconductor device, comprising: High-voltage conductive structure; Step morphology at or near the high-voltage conductive structure; as well as A layer stack covering the stepped topography, the layer stack comprising: Electrically insulating buffer layer; The SiC layer above the electrically insulating buffer layer; and The silicon nitride layer above the SiC layer or the nitride surface region of the SiC layer, The electrically insulating buffer layer includes a nitrided top surface region.

2. The high-voltage semiconductor device according to claim 1, wherein, The stepped morphology is formed by the edge of the high-voltage conductive structure.

3. The high-voltage semiconductor device according to claim 1 or 2, wherein, The stepped morphology is formed by the edge of the gate channel, the edge of the p-ring, the edge of the field plate, or the edge of the variable lateral doped region of the high-voltage transistor.

4. The high-voltage semiconductor device according to claim 1 or 2, wherein, The SiC layer is an a-SiC:H layer.

5. The high-voltage semiconductor device according to claim 1 or 2, wherein, The electrically insulating buffer layer is an oxide layer.

6. The high-voltage semiconductor device according to claim 1 or 2, wherein, The high-voltage conductive structure includes aluminum or copper.

7. The high-voltage semiconductor device according to claim 1 or 2, further comprising: An imide layer, said imide layer being on the silicon nitride layer or on the nitride surface region of the SiC layer.

8. The high-voltage semiconductor device according to claim 1 or 2, wherein, The stepped morphology includes a horizontal base and vertical sidewalls, and The vertical sidewall has a height equal to or greater than 0.5 μm.

9. The high-voltage semiconductor device according to claim 1 or 2, wherein, The stepped morphology includes a horizontal base and vertical sidewalls, and The SiC layer completely covers the corner area between the horizontal substrate and the vertical sidewall.

10. The high-voltage semiconductor device according to claim 9, wherein, The SiC layer also completely covers the vertical sidewall.

11. The high-voltage semiconductor device according to claim 1 or 2, wherein, The SiC layer is a conformal layer that follows the stepped morphology.

12. The high-voltage semiconductor device according to claim 1 or 2, wherein, The electrically insulating buffer layer is a conformal layer that follows the stepped morphology.

13. The high-voltage semiconductor device according to claim 1 or 2, wherein, The silicon nitride layer is a conformal layer that follows the stepped morphology.

14. The high-voltage semiconductor device according to claim 1 or 2, configured such that the SiC layer is electrically floating.

15. The high-voltage semiconductor device according to claim 1 or 2, configured to operate at a voltage equal to or greater than 0.6 kV.

16. The high-voltage semiconductor device according to claim 1 or 2, wherein, The high-voltage semiconductor device is one of IGBT, FET, diode, thyristor, GTO, and BJT.

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